No 2 Power Dissipation

8/10/2019 No 2 Power Dissipation

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VLSI CIRCUIT DESIGN

Power Diss ipation (WH-4.4)

Cross talk (WH-4.5.4)

Reliab il i ty (WH-4.7)

Mohammad

Shafquatul Islam


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POWERDISSIPATION

Static CMOS are very power efficient as theydissipate nearly 0 power while idle.

As transistor counts and clock frequencies haveincreased, power consumption has greatlyincreased and now is a primary design constraint.

Instantaneous power P(t) drawn from powersupply is proportional to the supply current i

DD(t)

and the supply voltage VDD

.


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POWERDISSIPATION

The energy consumed over some time intervalT is the integral of the instantaneous power,

Average power over this interval is

PD=PStatic+PDynamic

dt.VtiE DDT

DD

0

dt.VtiTT

EP

DD

T

DDavg

0

1


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POWERDISSIPATION

Static Power Dissipation is due to1. Subthreshold Conduction through OFF transistors.

2. Tunneling current through gate oxide.

3. Leakage through reverse-biased diodes.


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POWERDISSIPATION

Dynamic Power Dissipation is due to1. Charging and discharging of load capacitors.

2.Short-circuit current while both pMOS and nMOSnetworks are partially ON.

Ptotal=PStatic+PDynamic


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STATICPOWERDISSIPATION

Consider an inverter. One transistor is always OFF.Ideally no current flows through the OFF transistor.

Power dissipation is 0 when the circuit is quiescent,i.e., when no transistors are switching. Zeroquiescent power dissipation is a principle advantageof CMOS over competing transistor technologies.


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STATICPOWERDISSIPATION

However, secondary effects subthresholdconduction, tunneling, small amounts of leakagecurrent flowing through the OFF transistor.

Assuming the leakage current is constant,instanteneous and average power are same, so staticpower dissipation is the product of total leakagecurrent and supply voltage,

Pstatic=IStatic.VDD


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DYNAMICPOWERDISSIPATION

Primary dynamic dissipation component is charging

the load capacitance. Suppose a load CLis switched between GND and VDD

at an average frequency of fSW, over any giveninterval of time T, the load will be charged and

discharged T.fSWtimes. Current flows from VDD to the load to charge it and

from load to GND to discharge it. In one completecharge/discharge cycle, a total charge of Q=CL.VDDisthus transferred from VDDto GND.


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Average Dynamic Power Dissipation

Taking the integral of the current over same intervalT as the total charge delivered during that time, we

simplify to

dttiT

Vdt.VtiT

PT

DDDD

DD

T

DDDynamic 001

DLDDLSWDD

DynamicCVCTf

T

V 2


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Average dynamic power dissipation Pddissipated

during switching for a square-wave input Vinhavingfrequency fp=1/tpis given by -

dtVV.titdt.VtitP outDDt

t pp

out

t

np

d

p

p

p

2/

2/

0

11

dtVV.dt

VVdC

tdt.V

dt

dVC

t outDD

V

V

outDDL

p

out

V

V

outL

p

DD

SS

SS

DD

11

outDDV

V outDD

p

Lout

V

V out

p

L VVdVVt

CdVV

t

C DD

SS

SS

DD

..

in= nMOS transient cur rent

ip= pMOS transient cur rent


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SS

DD ouDDp

LV

Voutp

L

VVt

C

Vt

C 22

)(22

222 ()(22 DDDDD

p

LDDSS

p

L VVVt

CVV

t

C

22.

2.

2 D

p

LDD

p

L Vt

CVt

C

22

. DDpLDDp

L

VfCVt

C


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POWER-DELAYCONTRADICTION

Inverter delay -

Dynamic Power Dissipation,

If we increase VDD, delay reduces but PDincreases.

Modern trend is reducing VDDto reduce power

dissipation.

So,

increase to reduce delay.

reduce VDDto decrease power dissipation

DD

Lrf

V

kCtt

2

DDpLD VfCP


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POWER-DELAYCONTRADICTION

Since most gates do not switch every clock cycle, it is

often most convenient to express switching frequencyfswas an activity factor times the clock frequency f.

Dynamic power dissipation can be rewritten as,

fVCP DDLDynamic2


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Q1. A digital system in a 1.2 V 100 nm process [PariharOl] has 200 million transistors, of which 20

million are in logic gates and the remainder in memory arrays. The average logic transistor width is

12 and the average memory transistor width is 4 ,. The process has two threshold voltages and

two oxide thicknesses. Subthreshold leakage for OFF devices is 20 nA/um for low-threshold

devices and 0.02 nA/ urn for high-threshold devices. Gate leakage is 3 nA/um for thin oxides and

0.002 nA/um for thick oxides. Memories use low-leakage devices everywhere. Logic uses low-leakage devices in all but 20% of the paths that are most critical for performance. Diode leakage

is negligible. Estimate the static power consumption. How would the power consumption change if

the low-leakage devices were not available?

Solution:

There are (20 106logic transistors) (0.2) (12 (0.05 um/) = 2.4 106um of high-leakage devices

and

[(20 106

logic transistors) (0.8) (12 ) + (180 106

memory transistors) (4 )] (0.05 um/) = 45.6 106urn of low-leakage devices.

All devices exhibit gate leakage. On average, half the transistors are OFF and contribute subthreshold

leakage. Therefore, the total static current is (2.4 106 um) [(20 nA/um)/2 + (3 nA/um)] + (45.6

106um) [(0.02 nA/um)/2 + (0.002 nA/um)] = 32 mA.

Static power consumption is (32 mA) (1.2 V) = 38 mW. This is likely to be small compared to

dynamic power consumption, yet large enough to limit the battery life of battery-powered systems

on standby.

If low-leakage devices were not available, the total static current would be (2.4 106um + 45.6 106)

[(20 nA/um)/2 + (3 nA/um)] = 624 mA, for standby power of (624 mA) (1.2 V) = 749 mW.


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Q2. Our 200M transistor digital system from the example on page 99 uses static CMOS

for the logic gates with an average activity factor of 0.1 The memory arrays are

divided into banks and only the necessary bank is activated so the effective memory

activity factor is 0.05. Assume transistors have a gate capacitance of about 2 fF/um.

Neglecting wire capacitance, estimate the dynamic power consumption per MHz of

the system.

Solution:

There are (20 106 logic transistors) (12) (0.05 um/A,) (2 fF/um) = 24 nF of logic transistors and

(180 106 memory transistors) (4) (0.05 um/A,) 2 fF/um = 72 nF of memory transistors.

The power consumption is [(0.1) (24 KT9) + (0.05) (72 10-9) ] (1.2)2 = 8.6 mW/MHz, or 8.6 W

at 1 GHz.


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CROSSTALK

As reviewed in Figure 4.41, wires have capacitance to their adjacent neighbors aswell as

to ground. When wire A switches, it tends to bring its neighbor B along with it on

account of capacitive coupling, also called crosstalk. If B is supposed to switch

simultaneously, this may increase or decrease the switching delay. If B is not

supposed to switch, crosstalk causes noise on B.

We will see that the impact of crosstalk depends on the ratio of Cadj to the total

capacitance. Note that the load capacitance is included in the total, so for short wires

and large loads, the load capacitance dominates and crosstalk is unimportant.

Conversely, for long wires crosstalk is very important.


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CROSSTALKDELAYEFFECTS

If both a wire and its neighbor are switching, the direction of the switching affects the amount of

charge that must be delivered and the delay of :he switching. Table 4.10 summarizes this effect.

The charge delivered to the coupling capacitor is Q = C^AV, where AFis the change in voltage

between^ and B. If A switches but B does not, A V = VDD. The total capacitance effectively seen

by A is just the capacitance to ground and to B. If both A and B switch in the same direction, A V=

0. Hence, no charge is required and Cadj is effectively absent for delay purposes. If A and B

switch in the pposite direction, AV = 2VDD. Twice as much charge is required. Equivalently, the

capacitor can be treated as being effectively twice as large switching through VDJ> This is analo-

tdus to the Miller effect discussed in Section 4.2.5.4. The Miller Coupling Factor (MCF) describeshow the capacitance to adjacent wires is multiplied to find the effective capacitance. Some

designers use MCF = 1.5 as a statistical compromise when estimating propagation delays before

layout information is available.


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Each wire in a pair of 1 mm lines has capacitance of 0.1 fF/u.m to ground and 0.1

fF/u.m to its neighbor. Each line is driven by an inverter with a 1 k effective

resistance. Estimate the contamination and propagation delays of the path. Neglect

parasitic capacitance of the inverter and resistance of the wires.

Solution:

We find Cgnd = Cadj = (0.1 fF/um) (1000 urn) = 0.1 pF. The delay is Ceff. The contamination delay is

the minimum possible delay, which occurs when both wires switch in the same direction.

In that case, Ceff = Cgnd and the delay is tcd = (lk) (0.1 pF) = 100 ps. The propagation delay is the

maximum possible delay, which occurs when both wires switch in opposite directions.

In this case, Ceff = Cgnd + 2Cadj and

the delay is tpd = (lk) (0.3 pF) = 300 ps.


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RELIABILITY

Designing reliable CMOS chips involves understanding and addressing the potential

failure modes [Greenhill02, Bernstein99]. This section addresses reliability problems

(hard errors) that cause integrated circuits to fail permanently, including:

Electromigration

Self-heating Hot carriers

Latchup

Overvoltage failure

This section also considers transient failures (soft errors) that cause the system to crash

or lose data.


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ELECTROMIGRATION

Electromigration causes wearout of metal interconnect through the formation of voids

[Hu95]. High current densities lead to an "electron wind" that causes metal atoms to

migrate over time. Remarkable videos taken under a scanning electron microscope show

void formation and migration and wire failure [Meier99]. The problem is especially severe

for aluminum wires; it is commonly alleviated with an Al-Cu or Al-Si alloy and is much

less important for pure copper wires because of the different grain transport properties.

The electromigration properties also depend on the grain structure of the metal film.

Electromigration depends on the current density/ = I/wt. It is more likely to occur for

wires carrying a DC current where the electron wind blows in a constant direction than for

those with bidirectional currents [Liew90]. Electromigration current limits are usually

expressed as a maximum Jdc. The mean time to failure (MTTF) also is highly s(

operating temperature as given by Black's Equation [Black69]:

where Ea is the activation energy that can be experimentally determined by stress testing at

high temperatures and n is typically 2. The electromigration DC current limits vary with

materials, processing, and desired MTTF and should be obtained from the fabrication

vendor. In the absence of better information, a maximum JA of 1-2 mA/urn2 is a

conservative limit for aluminum wires at 110C [Rzepka98], although 10 mA/|im2 or better may

be achievable for copper wires [YoungOO]. Current density may be even more limited in contact cuts.


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SELF-HEATING

While bidirectional wires are less prone to electromigration, their current density is still

limited by self-heating. High currents dissipate power in the wire, which raises its ambient

temperature. Hot wires exhibit greater resistance and delay. Electromigration is also highlysensitive to temperature, so self-heating may cause temperature-induced electromigration

problems in the bidirectional wires. Brief pulses of high peak currents may even melt the

interconnect. Self-heating is dependent on the RMS current density. This can be

measured with a circuit simulator or calculated as

A reasonable rule to control reliability problems with self-heating is to keep Jrmi < 15 mA/u,m2 for

bidirectional aluminum wires [Rzepka98] on a silicon substrate. Self-heating is especially

significant for SOI processes because of the poor thermal conductivity of Si02. In summary,electromigration from high DC current densities is primarily a problem in power and ground lines.

Self-heating limits the RMS current density in bidirectional signal lines. However, do

not overlook the significant unidirectional currents that flow through the wires contacting nMOS andpMOS transistors. For example, Figure 4.62 shows which lines in an inverter are limited by DC

and RMS currents. Both problems can be addressed by widening the lines or reducing the

transistor sizes (and hence the current).


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HOTCARRIERS

As transistors switch, some high-energy ("hot") carriers may be injected into the gate

oxide and become trapped there. The damaged oxide changes the I-V characteristics of the

device, reducing current in nMOS transistors and increasing current in pMOS transistors.

Damage is maximized when the substrate current 7sub is large, which typically occurs when

nMOS transistors are in saturation while the input rises. Therefore, the problem is worst

for inverters and NOR gates with fast rising inputs and heavily loaded outputs

[Sakurai86], and for high power supply voltages.

Hot carriers cause circuit wearout as nMOS transistors become too slow. They can

also cause failures of sense amplifiers and other matched circuits if matched components

degrade differently [Huh98]. Hot electron degradation can be analyzed with simulators

[Hu92, Hsu91, Quader94]. The wear is limited by setting maximum values on input rise-

time and stage electrical effort [Leblebici96]. These maximum values depend on the

process and operating voltage.

A related aging mechanism is negative bias temperature instability (NBTI), which lead

to a decrease in pMOS transistor current as transistors wear at high temperature

[Doyle91]. NBTI results from trapped holes in the oxide coupled with the creation of

interface states. Like hot carriers, it leads to circuit failures from increased delay and

poorer matching [Reddy02]. NBTI shifts depend on the electric field seen by the device

and can be locked in to the device by high-voltage stress during burn-in; this is good

because it allows testing with full NBTI degradation.


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LATCHUP

Early adoption of CMOS processes was slowed by a curious tendency of CMOS chips to develop low-

resistance paths between VDD and GND, causing catastrophic meltdown. The phenomenon,called latchup, occurs when parasitic bipolar transistors formed by the substrate, well, and

diffusion turn ON. With process advances and proper layout procedures, latchup problems can be

easily avoided.

The cause of the latchup effect [Estreich82, Troutman86] can be understood by examining the process

cross-section of a CMOS inverter, shown in Figure 4.63(a), over which is overlaid an equivalent

circuit. In addition to the expected nMOS and pMOS transistors, the schematic depicts a circuit

composed of an npn-transistor, a pnp-transistor, and two resistors connected between the power

and ground rails (Figure 4.63(b)). The npn-transistor is formed between the grounded n-diffusionsource of the nMOS transistor, the p-type substrate, and the n-well. The resistors are due to the

resistance through the substrate or well to the nearest substrate and well taps. The cross-coupled

transistors form a bistable silicon-controlled rectifier (SCR). Ordinarily, both parasitic bipolar

transistors are OFF. Latchup can be triggered when transient currents flow through the substrate

during normal chip power-up or when external voltages outside the normal operating range are

applied. If substantial current flows in the substrate, Fsub will rise, turning ON the npn-transistor.

This pulls current through the well resistor, bringing down Ve]1 and turning ON the pnp-transistor.

The pnp-transistor current in turn raises V^ initiating a positive feedback loop with a large current

flowing between VDD and GND that persists until the power supply is turned off or the power wires

melt.


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Fortunately, latchup prevention is easily accomplished by minimizing Rsub and Rwell. Some processes use a

thin epitaxial layer of lightly doped silicon on top of a heavily doped substrate that offers a low substrate

resistance. Most importantly, the designer should place substrate and well taps close to each transistor, as

described in Section 1.5.1. A conservative guideline is to place a tap adjacent to every source connected

to VDD or GND. If this is not practical, you can obtain more detailed information from the process vendor

(they will normally specify a maximum distance for diffusion to substrate/well tap) or try the following

guidelines:

'Every well should have at least one tap.

All substrate and well taps should connect directly to the appropriate supply in metal.

A tap should be placed for every 5-10 transistors or every 25-100 |im (this distance is process-dependent).

nMOS transistors should be clustered together near GND and pMOS transistors should be clustered

together near VDD, avoiding convoluted structures that intertwine nMOS and pMOS transistors in

checkerboard patterns.


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I/O pads are especially susceptible to latchup because external voltages can ring below GND orabove VDD, forward biasing the junction between the drain and substrate or well and injecting

current into the substrate. In such cases, guard rings should be used to collect the current, as

shown in Figure 4.64. Guard rings are simply substrate or well taps tied to the proper supply that

completely surround the transistor of concern. For example, the n+ diffusion in Figure 4.64(b) can

inject electrons into the substrate if it falls a diode drop below 0 volts. The p+ guard ring tied to

ground provides a low-resistance path to collect these electrons before they interfere with the

operation of other circuits outside the guard ring. All diffusion structures in any circuit connected to

the external world must be guard ringed, i.e., n+ diffusion by p+ connected to GND or p+ diffusionby n+ connected to VDD. For the ultra-paranoid, double guard rings may be employed, i.e., n+

ringed by p+ to GND, then n+ to VDD or p+ ringed by n+ to VDD, then p+ to GND. SOI processes

avoid latchup entirely because they have no parasitic bipolar structures. Also, processes with VDD

< 0.7 are immune to latchup because the parasitic transistors will never have a large enough

base-to-emitter voltage to turn on. In general, low-voltage processes are much less susceptible to

latchup problems.


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No 2 Power Dissipation