No Slide Title - moodle.fel.cvut.cz · Resolution Enhancement Techniques Resolution Enhancement Techniques OPC GDSII MDP OPC Mask Manufacturing OPC – Optical proximity correction

Electronics and Microelectronics AE4B34EM

10. lecture

• IC processing technology

• Lithography

• Oxidation

• Ion Implantation

• Deposition

Jiří Jakovenko – Electronics and Microelectronics - Department of Microelectronics – CTU

How to get

1 000 000 000

Components to 1 cm2


Oxidation

Optical mask

Next technology step

Photoresist coating

Washing, drying Etching

Photoresist processing

Exposition

Typical operation steps in one photolithographic cycle

Photolithography

Removal

photoresist


Transfer of the design on a chip

Stepwise Exposure: Focus, deposition, exposure, step and over again

UV light source

Optical Mask - contains

one or more chip layouts

Aperture

Control of wafers shift

in X, Y, Z, q

Projection Optics

The aperture is closed during focusing and

splicing. Opened during the exposure

Composing laser


Negative Photoresist

Projection System

UV light source (lamp)

Fotolitografic mask

Developer

Washing

Photolithography - projection method

Silicon wafer with a layer of thermal oxide.

The wafer is coated by sensitive layer to light - photoresist. During the application of the photoresist coated plate reaches fast rotation which makes steady stratification throughout the area.

Chip (layer) topology is transferred throughout the mask on the top of the board - the plate is irradiated by ultraviolet light.

Developer removes illuminated photoresist from the wafer plate.

Oxide

Substrate


Photolithography and etching

The board is immersed into etching substance It removes the exposed oxide down to the silicon surface - wet etching

Etching substance


Photolithography

Today we use UV light sources of 248, 195nm

Very expensive equipment 40 000 000 USD

Resolution Enhancement Techniques

Resolution Enhancement Techniques

GDSII

MDP

Mask

Manufacturing

OPC – Optical proximity correction


90nm and Below 130nm 180nm

OPC

Design

Mask

Wafer

OPC

0°

180°

0°

180°

PSM

Resolution enhancement techniques

diffraction

feature sizes light wave length


OPC – Optical proximity correction

PSM – Phase shift margin Source: IDESA

Optical Proximity Correction

Predistortion of the mask layout is needed when scaling down the technology

Needed for 90nm and below

No OPC OPC Corrections

With OPC

Original Layout


Source: IDESA


Increasing percent of mask layers

are using OPC/RET technologies

180 150 130 90 0

10

20

30

40

50

60

70

% of RET

Technology Node (nm)


Source: IDESA


Comparison by difference of OPC method

Original Moderate Aggressive


Source: IDESA

Optical Proximity Correction: Mask Writing Time

Number of Shots by E-beam used in electron lithography (Giga)

90nm Logic 65nm Logic 45nm Logic Generation

Chip area 120mm2

45

0

135

90

180


Source: IDESA

RET : OPC: Mask Writing Time

Time (hours)

90nm Logic 65nm Logic 45nm Logic Generation

Chip area 120mm2

Shot Time Stage Time

4

0

12

8

20

16

28

24


Source: IDESA

90nm and Below 130nm 180nm

OPC

Design

Mask

Wafer

OPC

0°

180°

0°

180°

PSM

Phase shift mask

Wavelength: 193nm


Source: IDESA

Phase shift mask

Design

Cross Section

Electric Field

Sum

Intensity

Conventional Mask Alternating PSM

Shifter

+ 0 -

+ 0 -

+ 0 -

Source: DNP

phase shift glass Expensive

light beam interference

light phase shifting


Source: IDESA

Immersion photolithography

Technique which improves resolution photolithography resulution (30-40%)

DUVi – use liquid between the lens system and wafer

This will increase the depth of field (DOF)

NA value is significantly greater than 1.0

Use absolutely clean water

Necessary for technology node 45 nm (ASML, Canon and Nikon)

There are solution for 14 nm technology (Intel Ivy Bridge)

Jiří Jakovenko – Návrh Integrovaných Systémů - A2M34NIS

Source: Cymer

Jiří Jakovenko – Struktury Integrovaných Systémů - A2M34SIS

EUV Extreme ultraviolet lithography

Radiation source 13.5 nm

Requires vacuum

All optics (mirrors) including masks must be made of multilayer Mo / Si without fault

zdroj: SPIE

Jiří Jakovenko – Struktury Integrovaných Systémů - A2M34SIS Jiří Jakovenko – Electronics and Microelectronics - Department of Microelectronics – CTU

Etching process - basic types

Wafer

Photorezist

Oxide

SiO2

Wafer

Photorezist

Oxide

SiO2

Wafer

Photorezist

Oxid

SiO2 SiO2

Wet chemical etching

Plasma etching

Reactive ion etching

Oxide


Anisotropic and isotropic etching

Isotropic etching Anisotropic etching

Wafer Wafer

Photorezist

Oxide

Pgotorezist

Oxide

Anisotropy coefficient Af = 1 – VH / VV

The isotropic etching is coefficient Af = 0

Selectivity to resistSFM = VF / VM VF >> VM

Selectivity to wafer SFS = VF / VS


Anisotropic etching of silicon


Plasma etching

Rotary vacuum pump

Working chamber

RF generator

Distribution of working gases

Holder with wafers Cover

Decontamination of waste gases

N2 O2 CF4 100 Pa

Used for silicon-nitride layers and photoresist removal

The process use a high reactive fluorine atoms which is generated by the decay of Freon CF4 molecules at very high

temperature and mixed with oxygen are used


Thermal oxidation

44%

56%

Original surface

Si Si Si Si Si Si Si




O O

O O O O

O O

O

O

O

O O Si

Si Si

Si

Si

Si O

O

O

O O

O O O O

O O O H

O H

300 600

500

1000

Time [min]

Thic

kness

[nm

]

Oxygen Water

1000°C 1100°C

Si

1000°C

SiO2

Dependence of thickness on oxidation time.

The thin layer of oxide are created on air (1 - 2 nm) At higher temperature (800°C - 1200°C) oxygen molecules are able to diffuse through oxide layer. 44% thickness is below the original surface of silicon and 56% above.


Oxidation (diffusion) chamber

Asanace odpadních plynů

Asanace odpadních plynů

Asanace plynů

Gas inlet



Temperature inside the chamber is 400 - 1200°C

The tube is made of quartz glass

Local oxidation masked by Silicon-Nitride

Limiting oxidation factors: - Bird heads forming - grow up – uneven surface

Forming of „Bird heads!“

Nitride Oxide

a) Nitride deposition

It serves as an oxidation mask b) Transferred on masks :

Nitride is etched

c ) Local oxidation


Shallow (Silicone) trench isolation - STI

Si

Si3N4

SiO2

Oxide and nitride Si3N4 deposition

STI - Shallow Trench Isolation

Si SiO2

Si3N4

Etching Si

Masked etching Si3N4 and SiO2

Si3N4

Si

SiO2

Si3N4

Si3N4

Si

SiO2

SiO2

Oxide deposition fills the trench etched

Si SiO2

Si3N4

CMP grinding of carbon nitride layer

Si SiO2

Removal of nitride by (H3PO4)

(It's thermal oxide!)

SiO2 deep = ~ 350 nm; “shallow”

Jiří Jakovenko – Electronics and Microelectronics - Department of Microelectronics – CTU Jiří Jakovenko – Electronics and Microelectronics - Department of Microelectronics – CTU

Diffusion - the principle

Diffusion is one of the most common processes in nature Diffusion rate is strongly dependent on temperature

Blue vitriol dissolves in water


Diffusion - the principle

H2O

H2O

H2O

H2O H2O

H2O

H2O

H2O

CuSO4 CuSO4

H2O

H2O

H2O H2O

H2O

H2O

H2O

H2O

H2O

H2O

H2O

H2O

H2O

H2O

H2O H2O

H2O

H2O

H2O H2O

H2O H2O

H2O H2O H2O

H2O H2O

H2O

H2O H2O

H2O

H2O

H2O

H2O

H2O

H2O H2O

H2O

H2O

H2O

H2O

H2O

H2O H2O

H2O

H2O

H2O

CuSO4

H2O H2O

CuSO4

CuSO4

CuSO4

CuSO4

CuSO4

CuSO4 CuSO4 Diffusion source

Diffusion rate is strongly dependent on temperature. In

the solids is almost immeasurable at room temperature . Diffusion at high temperatures is used in semiconductor

process for local subsidizing.


Diffusion in semiconductor process

P P

P

P P

P P

P

P

1000°C

P P

P

P

P P

P

P

P

P

P P

P

P

P

P

P P

P

P P P

P

P P

P

P

P

P

P

P P

P

P

It this process dopant atoms penetrate below the silicon surface in selected areas Temperature and time adjust layer depth and dopant concentration on the surface

Annealing is the mechanism by which the dopant atoms in silicon move around without diffusion source. It positively forms dopant profile. Oxide on the surface of the silicon wafer must be sufficiently thick (about 500 nm) to stop atoms of phosphorus penetrate through it.


Ion implantation

P

P

P P

P

P P

P

P

P P

P

P P

P

P P

P

P P

P

P P

P

P

P P

P

P P

P

P

1000°C

Ion implantation is a process in which a dopant atoms are implanted below the surface of the silicon wafer. Dopant ions are accelerated by electric field and focused to the wafer surface where penetrate to a certain depth beneath the surface of silicon

Dopant profile changes during

annealing. The quantity of dopants is an

important parameter called the dose.


An Ion implantation system

PCl3

P

Ion source

Magnet

Separating slit

Accelerator

P P

P

P

P

P P P P P

P

P

P

P

40 - 160 kV

Vacuum Vertical and horizontal deflection

system

Si wafer

Phosphorus (P) Si wafer doped by Phosphorus has a N type

conductivity

- +

Cl P P Cl

Cl P Cl

Cl

PCl3

P Cl

Cl Cl

-

+

40 k

iV

Cl

Cl

Cl P

P

Positive ions of P and Cl

Phosphor Chloride molecule Cl P Cl

Cl

Heavy Ions Cl

Lighter ions

Cl

Cl

The ions are accelerated

by the accelerator.

electric discharge source break the molecules into Phosphor

and Chloride atoms or clusters of atoms with an electric charge - ions.


Ion implantation – Magnet system

Graphit

Ion source

Magnet

Ion beam

Iris

Lighter ions

Heavy ions

Neutral ions


Accelerator system

100 MW 100 MW 100 MW 100 MW 100 MW

0 kV +100 kV +80 kV +20 kV +40 kV +60 kV

+100 kV

Ion beam

Ion beam

Into deflection system

Electrodes

Input from magnet


Linear accelerator system

Source

Magnet End deflection

magnet

Scan disc

Substrate


Electron shower system

+

+ +

+ +

+

+

+

+ +

+

+

+

+

Iris

Electron gun

Secondary electron target

Secondary electrons

Recombination +ion - electron

Wafer

Helps us to eliminate substrate charging


Epitaxy is the accretion of layers of silicon on the surface of the silicon wafer. The layer has the same crystallographic characteristics as a substrate but may

have a different concentration of additives or other ingredients.

Epitaxial growth

P

H

H H

P Si

Si Si

Si Si

The process takes place at high temperature - 1200 ° C. Around the incandescent panels flows hydrogen. When you add hydrogen chloride HCl it starts to react with the silicon surface and etches boards. It is important to

remove any dirt or surface inequality of the wafer.

After surface etching the silicon tetrachloride vapor SiCl4 reacts with present hydrogen at high temperature. The result of the

reactions are free silicon atoms deposited on the surface of the silicon wafer according its crystal structure.

In case of presence of phosphine molecules PH3, phosphorus atoms cause epitaxial layer growth. Similarly, boron compounds can be

used for doping.

H H

H H

H H

H H

H H

H Cl

H Cl

H Cl

The result is a thick epitaxial

layer of a few micrometers to tens of micrometers.

Cl

Cl

Cl

Si Cl

Cl

Cl

Cl

Si Cl

Cl

Cl

Cl

Si Cl


Sputtering

Al Al Al Al Al Al Al Al Al Al Al Al Al Al

Al Al Al Al Al Al Al Al Al Al Al Al Al Al Al Al

Al Al Al Al Al Al Al Al Al Al Al Al Al Al Al

Al

Al Al Al Al Al Al Al Al Al Al Al Al Al Al

Al

Al Al Al Al Al Al Al Al Al Al Al Al

Al Al

Al Al

Ar

Argon atom (Ar) faces at high speed (tens of km/s) on the surface of aluminium

plate and scatters a few aluminium atoms. Sprayed aluminium is deposited on nearby objects. The semiconductor industry uses aluminium, silver, gold,

titanium, nickel or aluminium alloy with copper and silicon (AlCuSi) materials.


Sputtering system

Argon

Vacuum pump

High voltage source 1000 V

Anode

Al plate - target

Magnet

Si wafers

The target is connected to the negative pole of the high voltage source and the auxiliary electrode-anode – to the positive pole. Argon atoms are ionized and discharged and accelerated by an electric field and directed at the target. Sprayed aluminium target is deposited on the plates, creating a layer of aluminium. The magnetic field located behind the target increases the efficiency of sputtering

process.


Chemical Vapor Deposition CVD

Continuous gas flow

Deposited film

Si substrate

Border layer

Reactant difusion

SiH4(gas) + O2(gas) SiO2 (solid) + 2H2 (gas)

SiH4(gas) + H2(gas) +SiH2(gas) 2H2(gas) + PolySilicon (solid)


Metalization – conductive couplings

Today Al is substituted by Cu – 40% less resistivity

Maximum 11 metal layers

CMP – Chemical-mechanical planarization

Chemical-mechanical planarization / Polishing

Mechanically with chemical etching, or chemically with mechanical grinding … … why? – surface planarization with removal of excess material

Chemical reaction etches surface and makes the deposited material soft, then the mechanical grinding flattens the surface .

without with CMP CMP



Wafer

Suspension

Downforce

c

p

Wafer holder

Abrasive particles film

Rotating plate

wafer Clamping plate

shift

Suspension = chemicals + particles





IC testing process

Optical control

Measurements of test structures


Packaging

Package requirements:

Electrical – small parasitic capacitances, inductance

Mechanical – reliable and solid

Thermal – good heat dissipation

Economical - cheap


Packaging

Diamond saw cuts the silicon wafer with chips into individual chips. Good chips are

soldered or glued into the case. Leads are connected to contacts on the chip with a thin copper wire (0.15 mm).


Board mounting

(a) Through-Hole Mounting (b) Surface Mount


Package types


Package parameters


Multi-chip modules

Documents

No Slide Title - moodle.fel.cvut.cz · Resolution Enhancement Techniques Resolution Enhancement Techniques OPC GDSII MDP OPC Mask Manufacturing OPC – Optical proximity correction