Noise Canceling in 1-D Data: Presentation #5

Seri Rahayu Abd RaufFatima BoujarwahJuan ChenLiyana Mohd SharippArti Thumar

M2

Feb 21st, 2005Component Layout

Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware

Project Manager: Bobby Colyer

Status

• Design proposal (Done)

• Architecture proposal (Done)

• Size Estimates and Floorplan (Done)

• Gate Level Design

- Schematics ( almost Done)

• To be done:– Layout (20%)– Spice simulation

Top Level Schematics

Revised Floorplan

Aspect Ratio = 1:1

Component LayoutSine ROM Table/Cosine (Similar)

Dimension : 7.8 x 62

ROM Controller

Mux 2-1

Half Adder

Full Adder

16 bit 2-1 Mux

Last week’s challenges…

• Completing and Testing Top level Schematic (98% done)

• Creating Layouts for Floating Point Multipliers and Adders with different shapes.– For Wallace Tree, decided to split it into two

trees, incorporating Booth encoding.

• Clock Skew and other Timing issues– Don’t have to worry about it

• Transistor count .. again.. – Ok..

This week’s challenges…

• Completing and Testing Top level Schematic – Power Saving options??

• Wallace Tree Layout– Is Booth encoding only for 2’s

complement numbers??

• Functional Blocks Layout– Follow the Floorplan

Questions?