Noise Minimization for Low Power Bandgap Reference and ......Email: [email protected] related with each other.Power Supply Rejection (PSR) is a measure of how well

Copyright © 2009 American Scientific PublishersAll rights reservedPrinted in the United States of America

Journal ofLow Power Electronics

Vol. 5, 1–17, 2009

Noise Minimization for Low Power Bandgap Referenceand Low Dropout Regulator Cores

Angelo Monteiro1, Marcelino Santos1�2�∗, Alexandre Neves1, and Nuno Dias11Inst. de Engenharia de Sistemas e Computadores, I&D, INESC-ID,

Inst. Superior Técnico, IST, 1000-029 Lisboa, Portugal2SiliconGate, Portugal

(Received: 21 February 2009; Accepted: 12 June 2009)

This paper describes the techniques to design low power series low dropout regulators (LDO)with low output noise and high power supply rejection (PSR). The noise analysis of the bandgapreference is critical to the linear regulator’s output noise, since it represents the main source ofnoise. The necessary trade-offs that a designer faces are discussed according to the demands ofmodern IP cores. A precise theoretical noise analysis of a typical bandgap and LDO topology ispresented, allowing the analogue designer to identify which are the trade-offs between power andnoise, and decide the architecture and design criteria based on these constraints. A LDO and abandgap with low noise, low power and high PSR are designed in a 0.35 �m CMOS technologyand integrated in a Power Management Unit (PMU). No decoupling capacitor is considered in thereference’s output.

Keywords: CMOS Low Dropout Regulator, Bandgap Reference, Low Power, Low Noise,High PSR.

1. INTRODUCTION

A power management system contains several subsystemsincluding linear regulators, switching regulators, and con-trol logic that reconfigures each subsystem;1 turning theoutputs on and off as well as changing the output voltagelevels, to optimize the power consumption of the device.Low dropout regulators have the advantages of a “quiet”operation when compared to a switching circuit such as aDC–DC converter, so they are usually employed in sys-tems that require a low noise power source, meaning thatthey occupy a place of choice in multi-domain (analog,digital and RF) cores. LDOs are also used in applica-tions where the input and output voltages have a smalldifference, such as battery-powered systems. Power dis-sipation, and thereby efficiency, can be improved as thedropout voltage decreases. Their low current consumptionand low dropout voltage make LDOs a common solutionin portable and RF applications.2–3

Modern LDOs are characterized by their ability toprevent fluctuations in the regulated output voltage dueto input voltage variations, output noise and quiescentcurrent.4–6 These three operational factors are intimately

∗Author to whom correspondence should be addressed.Email: [email protected]

related with each other. Power Supply Rejection (PSR)is a measure of how well the circuit rejects small-signalac ripples coming from the input power supply over thefrequency spectrum.7 Thus, PSR represents a very impor-tant specification when the LDO is supplied by a noisypower supply and/or when switched circuits are presentin the same die as the linear regulator. Some examplescould be digital circuits, RF circuits, DC–DC convert-ers, Charge Pumps, etc., PSR is strongly dependent onthe gain-bandwidth (GBW) of the system. If the GBWincreases, then the PSR increases. Moreover, PSR at dcis strongly proportional to 1/A0 and to the transconduc-tance of the pass device, where A0 is the open-loop gainof the error amplifier. The output noise of a system ismainly given by flicker, thermal and shot noise, and feed-back loops used in the design.8

Based on the relevant types of noise in an electri-cal circuit, this paper presents a noise analysis of a lowdropout voltage regulator and a bandgap voltage referencewhich allows the designer to quickly impose the trade-offsbetween power consumption and noise, along with PSR.

This paper is organized as follows: Section 2 presentsthe types of noise and how feedback impacts on thenoise propagation, Section 3 presents a precise theoreticalnoise analysis of a typical bandgap and LDO topologies,and presents the corresponding optimization strategies,

J. Low Power Electronics 2009, Vol. 5, No. 2 1546-1998/2009/5/001/017 doi:10.1166/jolpe.2009.1021 1

Noise Minimization for Low Power Bandgap Reference and Low Dropout Regulator Cores Monteiro et al.

Section 4 describes the LDO and bandgap designed in0.35 �m CMOS technology and integrated in a PowerManagement Unit (PMU). Finally, Section 5 presents theconclusions of this work.

2. BACKGROUND

2.1. Types of Noise

Flicker noise is present in all active devices. It has vari-ous origins and it is always associated with a dc current.9

The average power of flicker noise cannot be predictedeasily. Depending on the “cleanness” of the oxide-siliconinterface, flicker noise may assume considerably differ-ent values and such varies from one CMOS technology toanother. Flicker noise is more easily modelled as a voltagesource in series with the gate and is given by (1).10

E2 =∫ f2

f1

�

fdf (1)

� denotes the appropriate device constants, and f1 andf2 are the lower and upper frequencies of the equivalentnoise bandwidth. For a MOSFET transistor, the root-mean-square flicker noise produced by the drain noise current isgiven by (2).

I1/f mos rms =√∫ f2

f1

Kx ·g2m

COX ·WL · f df (2)

W , L, Cox, gm, and Kx denote the transistor’s width, length,gate capacitance per unit area, transconductance, andflicker noise process-dependent constant for a xMOS tran-sistor, respectively. The inverse dependence of (2) on WLsuggests that to decrease flicker noise, the device area mustbe increased. Flicker noise is also called 1/f noise becauseof the inverse dependence with frequency. It is believedthat PMOS devices exhibit less 1/f noise than NMOStransistors because the former carry the holes in a “buriedchannel”, i.e., at some distance from the oxide-siliconinterface. Nonetheless, this difference between PMOS andNMOS transistors is not consistently observed.11 More-over, if the current consumption of a circuit is kept lowenough, thermal noise will predominate over flicker, sinceflicker noise is proportional to the dc current in the device.

Thermal noise results from the random motion of chargecarriers (electrons or holes) in a conductor, which intro-duces small fluctuations in the voltage measured acrossthe conductor even if the average current is zero.10 Ther-mal noise is one type of white noise and is proportional tothe absolute temperature, although is independent of cur-rent flow. It can be modelled as a voltage placed in serieswith a noiseless resistor, and the root-mean-square valueof the voltage noise source is shown in (3), where k isBoltzmann’s constant, T is absolute temperature in Kelvin,and R is the resistance of the conductor in Ohms.

ERrms =√∫ f2

f1

4kTRdf (3)

Fig. 1. Inverting op amp circuit with noise sources.

Finally, shot noise is always associated with currentflow and it is also spectrally flat like thermal noise.12 It iscaused by electrons or holes that, randomly, cross a poten-tial barrier like a pn junction. Since the charges arrivein quanta, one electron at a time, the current flow is notcontinuous, but limited by the quantum of the charge car-riers. Thus the instantaneous current, In, is composed of alarge number of random, independent current pulses withan average value, ID. Shot noise is generally specified interms of its mean-square variation about the average value,as in (4), where q denotes the electron charge.

I 2n = �I − ID�

2 =∫ f2

f1

2qID df (4)

2.2. Feedback

Feedback loops can be problematic to the noise perfor-mance of a circuit if the closed-loop gain is high, whichmeans a low feedback factor, �. In fact, the noise presentat the input is amplified, approximately, by 1/�. Consid-ering an inverting op amp circuit, as shown in Figure 1,the output rms noise voltage due to the thermal noise ofthe resistors is expressed in (5).

Vnout rms =√∫ f2

f1

[4kT

(R2 +R1

(1�

)2)]df

�= R1

R2

(5)

It is shown by (5) that if increases, � then the output rmsnoise voltage decreases. If � is composed of resistors, thenthere will always be a compromise between noise, area andcurrent consumption. If the resistor value increases, powerconsumption goes down but noise and area increase. Thus,if one wishes a low-noise solution, the resistor value mustbe low and consequently its current will increase, addingmore power consumption to the system.

3. NOISE ANALYSIS

3.1. Low Dropout Regulator

A LDO is a closed-loop system which is commonly consti-tuted by a voltage reference (Vref ), an error amplifier (A0)

2 J. Low Power Electronics 5, 1–17, 2009

Monteiro et al. Noise Minimization for Low Power Bandgap Reference and Low Dropout Regulator Cores

Fig. 2. Low dropout voltage regulator: typical architecture with noisesources.

that controls the gate of a PMOS pass transistor (MPD),and a resistive feedback network (R1 and R2). The totaloutput noise of the linear regulator is given by differentnoise sources as illustrated in Figure 2, where ER1 andER2 are the thermal noise voltage sources of R1 and R2

resistors respectively, Ebg and Ein are the noise voltagesources of the reference voltage and of the error amplifier,respectively, seen at the input of the regulator, and Imos isthe noise current source that models thermal and flickernoise of the pass transistor. Capacitors do not generateany noise, but they accumulate noise generated by othernoise sources. When connected to an arbitrary resistor, it ispossible to define the capacitor noise mean-squared value,E2extcap.Superposition method is used in all noise analysis to

determine the output root-mean-square noise voltage ofthe LDO and bandgap. Hence, starting with the LDO, thefeedback resistors contribute with thermal noise which isgiven by (6) and (7), where * denotes the feedback factorgiven by R2/�R1 +R2�.

V 2R1

= E2R1

=∫ f2

f1

4kTR1 df (6)

V 2R2

=∫ f2

f1

(R1 +R2

R2

)2

E2R2df =

∫ f2

f1

(1*

)2

·4kTR2 df

(7)

The reference voltage used by the LDO is provided bya bandgap that may contain all types of noise. The con-tribution of this noise to the output voltage of the LDOis presented in (8) and strongly depends on the feedbackfactor.

V 2ref =

∫ f2

f1

(1+ R1

R2

)2

E2bg df =

∫ f2

f1

(1*

)2

E2bg df (8)

The noise seen at the output that is generated by theerror amplifier can be referred to its input using a voltagesource (Einamp�, and so the root-mean-square noise pro-duced by the error amplifier is given by (9).

V 2in =

∫ f2

f1

(1*

)2

E2inamp df (9)

The pass device introduces thermal and flicker noise, asdescribed in (10), where rds is its drain-source resistance,KP is the flicker noise parameter of the PMOS transistor,gm is the transconductance.

V 2mos=

∫ f2

f1

I 2mos�R1�rds�RL�

2 · df

1+�R1�rds�RL�2C2

L�2+f �2

=∫ f2

f1

(I 2th+I 2

1/f

)�R1�rds�RL�

2 · df

1+ �R1�rds�RL�2C2

L�2+f �2

=∫ f2

f1

(4kT �2/3�gm+

KP ·g2m

CoxWL·f)�R1�rds�RL�

2 · df


L�2+f �2

(10)

To calculate the noise generated by the off-chip capaci-tor, a load resistor is considered in parallel with the capac-itor. The output voltage across the capacitor is simply afirst-order low pass filter where the thermal noise voltagesource of the resistor is the input. Since the noise band-width is given by (+/2�f0, the power spectral density ofthe capacitor is given by (11), where CL denotes the capac-itance value.

V 2extcap = �4kTRL�

(+2

)( 12+RLCL

)= kT

CL

(11)

Hence, since all noise sources are uncorrelated andusing (6)–(11), the output mean-square noise voltage isgiven by (12).

V 2nout = V 2

R1+V 2

R2+V 2

ref +V 2in+V 2

mos +V 2extcap

=∫ f2

f1

4kT[R1 +R2

(1*

)2

+ 23gm�R1�rds�RL�

2

· 1


L�2+f �2

]df

+∫ f2

f1

KP ·g2m�R1�rds�RL�

2

Cox ·WL · f· df


L�2+f �2

+∫ f2

f1

(1*

)2

·(E2bg +E2

inamp

)df

+kT

CL

(12)

In this case, a very large output capacitor assumes apreponderant role because it allows the system to be stable,and it filters the output from noise that is generated in thecircuit. Therefore, an ultra-low noise LDO with externalcapacitor can be easily achieved if:• the closed-loop gain is low enough (it is rather diffi-cult to change this specification because if the reference isalready designed to a certain value, then the output voltagewill change according to the new closed-loop gain);

J. Low Power Electronics 5, 1–17, 2009 3


• a low noise bandgap reference is used, which is a sig-nificant challenge—the reference rms noise voltage can beeasily 200 to 300 �V in a equivalent noise bandwidth from10 Hz to 100 kHz if the design does not care about noiseconsiderations;• a large pass device (usually necessary to accomplish acertain dropout value) is used to improve flicker noise dueto the increase in area (WL);• the transistors used in the error amplifier are carefullydesigned so that current mirrors present low voltage gain(overdrive voltages around 200 mV, and good area) and thegain transistors, like the input differential pair, present hightransconductances (very high width, sub-threshold opera-tion for the input differential pair);• the use of resistors, normally to compensation and PSR,in the error amplifier is avoided. The best solution as faras noise is concerned is to only use decoupling transistorsthat push the dominant pole to lower frequencies, helpingPSR, noise and stability performances;• the values of the feedback resistors is reduced, espe-cially R1 (but the same ratio to keep unchanged the out-put voltage value), however power consumption increases.One practical solution that overcomes this limitation is theuse of diode-connected PMOS transistors, where the samevalue of resistance can be achieved, but the current drainof both transistors is greatly lower than compared to theresistor solution.

3.2. Bandgap Voltage Reference

A bandgap voltage reference is based on subtracting thevoltage of a forward-biased diode (or base-emitter junc-tion) having a negative temperature coefficient from aproportional-to-absolute-temperature (PTAT) voltage. ThisPTAT voltage results from the amplification of the voltagedifference between base-emitter junctions with differentsizes. Figure 3 shows a typical bandgap reference archi-tecture that is used in the noise analysis.

The output voltage, Vref , is given by (13), where mdenotes the current ratio; n represents the bipolar tran-sistors area ratio; - is the voltage gain (a ratio of resis-tors); and VT denotes the thermal voltage of the bipolartransistors.

Vref = VEB1 +- ·m ·/VEB= VEB1 +

R1

R3

·m ·VT ln�n ·m�

= VEB1 +R1

R3

· I1

I2

·VT ln(A4

A3

· I3

I4

)(13)

The most common ratios are m = 1 and n = 8, whichresults in the same current through the feedback branchesand a good layout matching for the bipolar transistors(using common centroid). However, to achieve a low noisebandgap solution these parameters shall be revised, as it

Fig. 3. The block diagram of the bandgap voltage reference.

will be seen further in this work. The - factor is usedto trim the temperature curvature of the output bandgapvoltage, and the resistor ratio must satisfy (14), so thatthe output reference voltage presents a zero temperaturecoefficient (ideally).

0

(R1

R3

· I1

I2

·VT ln(A4

A3

· I3

I4

))0T

+ 0VEB1

0T= 0

⇒ R1

R3

· I1

I2

· kq· ln(A4

A3

· I3

I4

)=∣∣∣∣dVEBdT

∣∣∣∣ 212×10−3

⇔ R1

R3

212×10−3

I1

I2

· kq· ln(A4

A3

· I3

I4

) (14)

The reference circuit shown in Figure 3 has two feed-backs: the positive feedback factor is constituted by R2,R3, Q4 and M2, and the negative feedback factor is formedby R1, Q3 and M1. The negative feedback must be greaterthan the positive feedback, because the system’s transientresponse is dependent on the difference between the nega-tive and positive feedbacks when large capacitive loads areused. Thus, an overall negative feedback has to be guar-anteed, to keep the system stable and well-behaved in atransient response. The negative and positive feedbacks aregiven by (15) and (16), respectively.

*N =−gmM1

(1/gmQ3

1/gmQ3+R1

)[rds1��1/gmQ3

+R1�]

(15)



*P =−gmM2

(1/gmQ4

+R3

1/gmQ4+R1+R3

)[rds2��1/gmQ4

+R1+R3�]

(16)

Noise reduction effort must target specially the bandgapcore. In the remaining blocks it is important to use largetransistors and minimize the use of resistors in order toreduce flicker and thermal noise. Therefore, in the masterbias cell that generates biasing voltages and currents, inthe internal regulator that possibly is used in State-of-the-Art voltage references, in the output buffer that provideslow output impedance to the circuit, and in the start-upand power-on-reset circuits noise follows the models pre-sented in Section 2 and can easily be analysed. Thus, thenoise analysis of the bandgap will focus the bandgap corepresented in Figure 4.

In terms of noise, the bandgap reference is a more com-plex structure than the LDO. Once again, the superpositionmethod is used to analyse the bandgap’s generated noise.Not only thermal and flicker noise is present in resistorsand MOSFET transistors, but the bipolar transistors alsointroduce shot noise due to their potential barriers, alongwith thermal noise.

Now let us re-write (15) and (16) to facilitate furtherexpressions, as shown in (17) and (18).

*N = AMOS1

(1/gmQ3

1/gmQ3+R1

)(17)

*P = AMOS2

(1/gmQ4

+R3

1/gmQ4+R1 +R3

)(18)

Fig. 4. Noise sources considered in the noise analysis of the bandgapreference.

Starting from the thermal noise produced by the feed-back resistors, then thermal noise generated by R1, R2 andR3 is given by (19), (20) and (21), respectively.

V 2R1

=∫ f2

f1

E2R1df =

∫ f2

f1

4kTR1 df (19)

V 2R2

=∫ f2

f1

E2R2·(AMOS1

*N

)2

df

=∫ f2

f1

4kTR2 ·(AMOS1

*N

)2

df (20)

V 2R3

=∫ f2

f1

E2R3·(AMOS1

*N

)2

df

=∫ f2

f1

4kTR3 ·(AMOS1

*N

)2

df (21)

MOSFET transistors, M1 and M2, introduce flicker andthermal noise, as shown in (22) and (23), where rdsMx

is the drain-source resistance of transistor Mx; gmMx isthe transconductance of transistor Mx; KPMx is the flickernoise parameter of the PMOS Mx transistor (given by thetechnology); COXMx is the gate capacitance per unit areaof transistor Mx; and WMx and LMx are the width andlength of transistor Mx, respectively.

V 2nM1

=∫ f2

f1

I2nM1

·(rdsM1

∥∥∥∥(R1+1/gmM1

))2

df

=∫ f2

f1

[4kT

(23

)gmM1

+ KPM1·g2

mM1

COXM1·WM1

LM1· f]

·[rdsM1

∥∥∥∥(R1 +

1gmM1

)]2

df (22)

V 2nM2

=∫ f2

f1

I2nM2

·(AMOS1 ·AMOS2

*N ·*P

·rdsM2

)2

df

=∫ f2

f1

[4kT

(23

)gmM2

+ KPM2·g2

mM2

COXM2·WM2

LM2· f]

·(AMOS1 ·AMOS2

*N ·*P

· rdsM2

)2

df (23)

Referring the noise of the error amplifier to its input, theoutput mean-square noise voltage produced by the erroramplifier is given by (24).

V 2in =

∫ f2

f1

E2in ·(AMOS1

*N

)2

df (24)

The bipolar transistors introduce thermal and shot noise.Their noise model is described as: two voltage sourcesthat model thermal noise of the emitter and base contactresistances, and two current sources that model base and



collector shot noise caused by current flowing through thejunctions. In this work, it will only be studied the emitterthermal noise and the collector shot noise of both bipolartransistors. Therefore, the output mean-square noise volt-ages produced by the emitter contact resistance of Q1 andQ2 are given by (25) and (26), respectively.

V 2ne3 =

∫ f2

f1

E2ne3

(AMOS2

*P

)2

df =∫ f2

f1

4kT ·re3 ·(AMOS2

*P

)2

df (25)

V 2n e4 =

∫ f2

fE2n e4

(R2

*NAMOS1

·R2 −R3 − re4

)2

df

=∫ f2

f1

4kT · re4 ·(

R2*N

AMOS1·R2 −R3 − re4

)2

df (26)

The collector shot noise that Q3 and Q4 bipolars intro-duce at the output is given by (27) and (30); rb′bx andrb′ex are the base and base-to-emitter resistances of Qxbipolar transistor; Cb′e3 is the base-to-emitter capacitanceof Q3 bipolar; Zb′e4 is the impedance between the baseand emitter junctions of Q4 bipolar and it is equal to theparallel of the base-to-emitter resistance and the base-to-emitter capacitance; gmQx denotes the transconductance ofQx bipolar transistor; rex is the emitter contact resistanceof Qx bipolar transistor; ICx is the collector current of Qxbipolar transistor.

V 2nshotc3 =

∫ f2

f1

[K1 ·K2 ·R1�R3gmQ4

+1−gmQ4�

�K2+re3�

]2

·I 2nc3 df

=∫ f2

f1

[K1 ·K2 ·R1�R3gmQ4

+1−gmQ4�

�K2+re3�

]2

·�2qIC3�df (27)

K1 and K2 constants are given by (28) and (29).

K1 =gmQ4

�R3 +R1�+1

R1�R3gmQ4+1�

(28)

K2 =�rb′e3 �1/sCb′e3 �+ rb′b3

1+gmQ3�rb′e3 �1/sCb′e3 �

(29)

V 2nshotc4 =

∫ f2

f1

�1/gmQ3

+R1��Zb′e4+rb′b4�

Zb′e4+rb′b4+R3+re4−gmQ4

Zbe4

gm1�Zb′e4+rb′b4+R3+re4�−1/gmQ3

2

· I 2nc4 df

=∫ f2

f1

�1/gmQ3

+R1��Zb′e4+rb′b4�


Zbe4

gm3�Zb′e4+rb′b4+R3+re4�−1/gmQ3

2

·2qIc4 df(30)

From (19)–(27) and (30), it is now possible to definethe output mean-squared noise voltage of the core of thebandgap, as shown in (31).

V 2nref = V 2

R1+V 2R2+V 2

R3+V 2nM1+V 2

nM2

+V 2in+V 2

ne3+V 2ne4+V 2

nshotc3+V 2nshotc4

=∫ f2

f1

4kT

[R1+�R2+R3�·

(AMOS1

*N

)2]2

df

+∫ f

f1

4kT(

23

)·[(

rdsM1

∥∥∥∥(R1+

1gmM1

))2

·gmM1+(AMOS1 ·AMOS2

*N ·*P

·rdsM2

)2

·gmM2

]df

+∫ f2

f1

4kT ·

re3 ·

(AMOS2

*P

)2

+re4 ·

R2

*N

AMOS1

·R2−R3−re4

2df

+∫ f2

f1

(KPM1 ·g2

mM1

COXM1 ·WM1LM1 ·f)·[rdsM1

∥∥∥∥(R1+

1gmM1

)]2

df

+∫ f2

f1

(KPM2 ·g2

mM2

COXM2 ·WM2LM2 ·f)·(AMOS1 ·AMOS2

*N ·*P

·rdsM2

)2

df

+∫ f2

f1

E2in ·(AMOS1

*N

)2

df

+∫ f2

f1

[K1 ·K2 ·R1

(R3gmQ4

+1−gmQ4

)�K2+re3�

]2

·�2qIC3�df

+∫ f2

f1

(1/gmQ3

+R1

)�Zb′e4+rb′b4�


Zb′e4

gmQ3�Zb′e4+rb′b4+R3+re4�

−1/gmQ3

2

·�2qIC4�df (31)

Despite the complexity of (31), thermal noise resultsfrom the use of the feedback resistors, R1, R2 and R3,MOSFET and bipolar transistors. Flicker noise is exclu-sively introduced by the MOSFET transistors, where it isdirectly proportional to their transconductance and to thesquared closed-loop gain. Shot noise results from the useof bipolar transistors to generate the output bandgap volt-age reference, and increases proportionally to the numberof charges passing through the junctions. In this work, shotnoise can be negligible when compared to thermal andflicker noise values.

The total rms noise at the output node of the bandgapcan be reduced if:• the feedback resistors R1, R2 and R3 present low resis-tance in order to minimize thermal noise;• the area of the current sources, M1 and M2, is quite largeand their transconductance the minimum possible;• the feedback factors (positive and negative) are as highas possible since they always appear in the denominatorof (31);



• the input-referred noise of the error amplifier presentsvery low noise;• the emitter contact resistance is as low as possible inorder decrease thermal noise in the emitter of the bipolartransistors;• an additional internal or external bypass capacitor isadded at the output of the bandgap.

Unfortunately, some of these topics lead the designer tohigher levels of current consumption, so they have to becarefully considered.

4. LDO AND BANDGAP DESIGN

4.1. Circuit Design

The linear regulator is a positive low dropout voltage reg-ulator capable of supplying up to 50 mA with the blockdiagram shown in Figure 5.

The main features of this LDO are low power, low noiseand high power supply rejection ratio (PSR) over the fre-quency spectrum. A series topology is used to regulate thesupply voltage (VIN �, where the error amplifier is suppliedby the regulated voltage instead of VIN , because it con-ceives better immunity to power supply fluctuations. Theregulated voltage is sampled, scaled and compared to areference voltage (VBG�, generated by a bandgap referencecore. The error amplifier is a single-ended differential pairwith an active load followed by a common-source outputstage that generates an output current depending on thedifference between the inputs. The schematic of the erroramplifier is presented in Figure 6. The negative feedbackloop formed by the error amplifier and the sampling circuit(R1 and R2� ensures that the regulated voltage is main-tained at the desired level. The control method used in thepass transistor (MPD� is current based, meaning that thegate voltage of the pass transistor depends on the erroramplifier’s output current (I3�, since I2 changes (and, con-sequently, VG� according to the difference between cur-rents IBIASN and I3. Supposing that the output voltage isstable at the desired voltage and that for some reason

Fig. 5. The block diagram of the designed LDO.

Fig. 6. Schematic of the LDO’s error amplifier.

its value increases, then the error amplifier detects it bythe feedback network and I3 increases; consequently, I2

decreases to maintain the same value of IBIASN . Thus, thegate voltage of the pass transistor increases and the outputvoltage returns to the desired value again.

During the power-up of the LDO, the off-chip capacitorrequests a large amount of current due to the fact that itis completely discharged. In order to ensure a fast turn-on time, the current flowing through the pass transistor tothe output capacitor could reach about 1 A. Hence, a cur-rent limiter was introduced that senses the gate voltage ofthe pass transistor and restricts the range of I2, meaningthat the VSG of the pass transistor is such that the outputcurrent does not go above 200 mA (worst corner simula-tion). In the end, the settling time is increased by a cou-ple of micro-seconds, but the output current is effectivelylimited.

This LDO also includes a shunt regulator transistor(MST ) to improve load transients. This shunt regulator isparticularly important in order to limit the over-shoot pro-duced by a load change (from maximum to minimumcurrent load). This is possible due to a fast current pathfrom the output node to ground, discharging the externalcapacitor. The shunt regulator is also used during power-up, because the gate voltage of the pass transistor is lowfor an extra period of time allowing the output voltageto go above its desired value. This happens because theerror amplifier has an inherent delay. Thereby, the shuntregulator rapidly decreases the output voltage, discharg-ing the extra charge accumulated in the off-chip capacitorand leading the output voltage to its final and stable value(3.1 mA of current flowing to ground), thus avoiding a



high over-shoot. In a load transition from maximum tominimum current, the current flowing through the shuntregulator reaches 2.9 mA (typical) and 6 mA (worst cornersimulation). Fortunately, this only happens in a very shortperiod of time and under load transients.

The top specifications for the LDO were previouslydefined as an output rms noise voltage of 30 �V inte-grated between 10 Hz and 100 kHz, power consumptionaround 50 �A when load requests 50 mA and a PSR of80 dB @ 100 kHz. Some considerations are taken in orderto reduce the LDO’s output rms noise voltage, but alsofocusing the design to a low power and high PSR solu-tion. The external capacitor (it can be seen as a bypasscapacitor as far as noise is concerned) provides a quitesignificant improve in the overall generated noise, becauseits large capacitance value reduces the bandwidth of thesystem, improving noise performance. Even if the rmsnoise voltage that results from the feedback resistors, erroramplifier, closed-loop gain and pass device is 30 �V, itis sure that the output rms noise is lower. The first stageof the error amplifier consumes 8 �A and although itcould be reduced, the load regulation performance wouldbe degraded due to the decrease of slew-rate of the ampli-fier. The voltage gain of the error amplifier’s first stageis 40 dB where the input differential pair is working insub-threshold region. The consequent input voltage erroris 1 mV. The current of the feedback resistors representsa strong trade-off between current consumption and noise,as showed in (12). Thus, to maintain a relatively low noisein the resistors, their current is set to 12 �A instead ofa lower value, contributing to an overall noise that meetstop specifications. The size of the transistors of the erroramplifier is quite large (80 �m2 for the input pair) toreduce low frequency (flicker) noise. The current controlof the pass device also uses large transistors to contributeto a low noise LDO. The most critical parts of the circuit,as far as low power is concerned, are IBIASN (shown inFig. 5) and the current limiter because they have a staticcurrent consumption of 16 and 14 �A, respectively.

Since the linear regulator needs a reference voltage,a bandgap voltage reference was also designed. Bothcores were integrated in a PMU with a DCDC, a chargepump, with trimming, configuration and design-for-debugcircuitry.13 The bandgap core has several current referenceoutputs to bias the different PMU’s blocks. The block dia-gram of the bandgap reference is presented in Figure 7.The design of the reference was intended to be portable,meaning that it presents high performance specifications,and the necessary modifications to either a low noise orlow power application are quite small based on the analy-sis made in Chapter 3. Top specifications for the bandgapwere a PSR of 100 dB @ 10 Hz and 50 dB @ 1 MHz,supply voltage between 3.1 V and 5.5 V, driving capability,low noise using no external and/or internal large capacitorand a current consumption of about 15 �A.

Fig. 7. The block diagram of the designed bandgap reference.

Based on the design experience of low dropout regula-tors and their performance in terms of power supply noiseimmunity, the bandgap reference uses a regulated voltageto supply both the amplifier of the bandgap’s core andthe output buffer. This approach has the advantage of highPSR, although the design is much more complex due tothe feedback loops involved in the circuit. The power-upof the bandgap can be summarized as: the biasing block(which is not presented in Fig. 7) generates temporaryvoltages (VCASCN , VBIASP and IBIASN � that are used to biasthe pass transistor (MPASS� with a low voltage, allowingVINREG to increase; by the time, VBGAUX is equal to thebandgap voltage value, the biasing block generates bias-ing voltages based on VINREG and, therefore, the temporaryvoltages can be turned-off. After this change, the circuitwill be supplied by VINREG instead of VIN , resulting ina higher PSR.14 VBGAUX is, in fact, the bandgap voltage,although a buffer is needed because the core has to drivecurrent (approximately, 10 �A) to the next cores of thePMU. VINREG is given by the VBGAUX voltage plus the gate-to-source voltage of transistor MS and its value is set to2.2 V. The error amplifier is a folded cascode topology andthe buffer is a single-ended differential pair with activeload to minimize area and current consumption.

Current consumption is set to the minimum required bythe blocks to satisfy top specifications such as quiescentcurrent and power-up time. Nevertheless, the core circuitof the bandgap is consuming 8.5 �A which is not a goodvalue if one needs an ultra-low power reference. In fact,it could be designed to consume much less current fromthe supply, but that would imply more noise at the out-put. Using the architecture of Figure 7, and assuming atotal quiescent current of 9 �A, the simulated output rmsnoise voltage of the bandgap would be 240 �V. Makinguse of this quiescent current value as first step, one canfirst try to increase the bipolar transistors ratio, in orderto decrease the overall noise, as (31) suggests. If the ratiodoubles (A4/A3 = 16), using (14) it is evident that theresistor value of R1 and its generated noise decreases by



25%. It is also useful to increase the current ratio fromI1/I2 = 1 to I1/I2 = 2, because, from (14), the resistorratio, R1/R3, decreases, allowing R1 to have an even lowervalue. Moreover, the area of M1 and M2 can be increased,conceiving better matching when running Montecarlo sim-ulations and less flicker noise. However, their drain currentmust be kept as low as possible so that the transconduc-tance is not compared to the area, resulting in an areacost with no improve in noise. Hence, the quiescent cur-rent of the bandgap’s core was left to 8.5 �A, where M1

and M2 drain currents are 3 �A and 1.5 �A, respectively.Moreover, if the area of Q4 is increased, it results that thecurrent density ratio between I1 and I2 increases, and also

(a)

(b)

Fig. 8. Layout of the: (a) Bandgap voltage reference. (b) Low dropout voltage regulator.

the delta between the emitter-base voltages of the bipo-lar. This assumption imposes an additional area cost dueto the fact that bipolar transistors occupy a large area,although the overall result is a decrease in the noise gen-erated by the bandgap’s core. Another useful tip is /VEBmultiplication,15 where a Darlington configuration is usedfor the bipolar transistors and the resistors values can begreatly decreased, resulting in a minimum thermal noisefrom the resistors and bipolars. A major disadvantage ofthis solution is the increase in power consumption andthe requirement of a higher supply voltage because thebandgap voltage value will increase. It is particularly diffi-cult to limit noise in the design of ultra-low power bandgap



Fig. 9. Power-on and load transient response of the proposed LDO. It focus the typical over and under-shoots in the output regulated voltage.

reference (below 5 �A of quiescent current). The resultantcurrent consumption of the designed bandgap is 16 �A(8.5 �A for the core), and the output rms noise voltageis 120 �V. This is a major improvement when comparedto the initial value of 240 �V (IQ = 9 �A) with I1/I2 = 1and A4/A3 = 8.

Once again, the output rms noise voltage can be fur-ther decreased by introducing an off-chip capacitor of afew nano-Farads or using an on-chip RC low pass filter(area cost). This solution clearly has some drawbacks: ifthe bandgap uses an output buffer in order to conceive lowoutput impedance, then an ac open-loop must be revised

Fig. 10. Line transient response of the LDO using an output current of 50 mA.

to ensure that phase margin is not degraded, further caus-ing instability; power-up time is increased if the designerdoes not guarantee an increase in the output current; boardspace is diminished resulting in an extra connection to thepcb ground.

Moreover, the bandgap reference core adds a trimmingcircuit that is used to guarantee the typical temperaturecurvature, whatever is the battery-supply voltage, the typeof transistors, resistors and bipolar transistors which resultfrom the fabrication process. The trimming circuit is com-posed by a 3-bit decoder, resistors and switches. The cur-rent flows through the resistors selected by the digital word



Fig. 11. Quiescent current and output current transient of the LDO showing current limitation circuit operation and the maximum current flowingthrough the ground pin. The transient simulation imposes a load change.

Fig. 12. Typical PSR performance of the LDO considering an output current of 50 mA and 5 �A.



Fig. 13. PSR performance of the LDO considering an output current of 50 mA and 96 corners.

Fig. 14. Output noise performance of the LDO considering an output current of 50 mA and 96 corners.



at the decoder input. The decoder ensures that only oneswitch is enabled at a time, reducing the influence of theswitches’ drain-to-source resistance to the minimum.

Figure 8 presents the layout of both cores implementedwith a standard CMOS, single well, 0.35 �m technology.

4.2. Simulation Results

The simulation conditions used to characterize both coresare a supply voltage ranging from 3.1 to 5.5 V (typi-cal is 4.3 V), an operating junction temperature range of[−40; 125] �C (typical is 25 �C), a 4.7 �F output ceramiccapacitor with an ESR of 8 m8 and ESL of 1.55 nH forthe LDO core, and process variations considering 4 typesof mosfet transistors (worst-power, worst-speed, worst-oneand worst-zero), 3 types of bipolar transistors (high-speed,high-beta and low-beta), and 2 types of resistors (worst-power and worst-speed).

The bandgap and LDO cores are separately simulated inorder to characterize each one and to ensure that there is noinfluence from one to each other. The difference of resultswhen both cores are connected is felt in terms of noise,because the noise voltage seen at the output of the LDO

Fig. 15. Transient response and quiescent current of the bandgap reference.

results from its own generated noise and the one generatedby the bandgap. Thus, intended for use in battery-poweredapplications, post-layout simulations show that the lowpower LDO presents a dropout voltage of 170 mV (typi-cal) at 50 mA of load current. Figure 9 presents a transientresponse of the proposed LDO in respect to its power-onand load transient response. The use of an external capaci-tor helps reducing the over-shoot when load changes from50 mA to 0 mA, and also the under-shoot experiencedwhen load changes in the opposite way. The shunt regu-lator transistor does also provide an extra improvement inan over-shoot situation. Considering a load change of 0 to50 mA and typical supply voltage, the regulated voltagesuffers an under-shoot of 21.3 mV (typical); and from 50 to0 mA the over-shoot is 20.9 mV (typical). A line transientwas simulated and it can be observed in Figure 10. Overand under-shoots are smaller when compared to a loadtransient, which demonstrates that load changes does affectmore the response of the regulator, due to pole movementin its frequency response. Considering a line change of3.1 to 5.5 V with an output current of 50 mA, the regu-lated voltage suffers an under-shoot of 2.9 mV. In termsof current consumption, Figure 11 shows the quiescent



Fig. 16. PSR performance seen at the output of the bandgap reference considering 96 corners.

and output currents transient of the proposed LDO. Thefunctionality of the current limiter is well identified inthe quiescent current response. As soon as enable goeshigh, the pass device allows a 200 mA maximum cur-rent flowing from the supply to the external capacitor, and

Fig. 17. Spectral density seen at the output of the bandgap reference core considering 96 corners.

consequently, the output voltage increases. Moreover, it isalso clear that the shunt regulator transistor avoids an evenhigher over-shoot in the output voltage when it finishesthe ramp up to the final and desired value. The limita-tion is set to 100 mV above 2.4 V and at this point the



current flowing to ground reaches 3.1 mA (typical). Like-wise, when load changes from 50 to 0 mA, the shunt reg-ulator allows a fast ground path that discharges the outputcapacitor and avoids a higher over-shoot in the output ofthe LDO. In this case, the ground current reaches 2.9 mA(typical). The quiescent current is 50 and 54 �A whenthe output current is 0 and 50 mA (typical), respectively.Figure 12 denotes the typical PSR performance obtainedwith the architecture proposed in this work when the out-put current is 50 mA and 5 �A. In the first case, the PSRof the LDO is 120 dB @10 Hz and 90 dB @ 100 kHz(typical). One can also conclude that the PSR of the sec-ond case is comparable to the first one, despite the regionfrom 100 kHz to 2 MHz where the slope of the curve givesaround 120 dB @ 2 MHz. Obviously this condition meansthat the next system supplied by the LDO is in idle orsleep mode, because typically LDOs are used to provide alarge amount of output current but also a constant and sta-ble voltage. Figure 13 shows a 96 corner simulation of thePSR performance of the LDO. The low frequency accu-racy greatly depends on the open-loop gain of the system,thereby the curves present that spread which is the typicalbehaviour of a PSR simulation over corners. The observedhigh immunity to fluctuations on the supply voltage makes

Fig. 18. Temperature sweep applied to the output voltage of the bandgap and trimming of its typical value.

this LDO a good solution to noisy-applications. The out-put noise of the LDO is shown in Figure 14, where it isconsidered an ideal voltage reference in order to clearlyidentify the noise generated by the LDO, isolated from thebandgap reference. The total output rms noise voltage inte-grated between 10 Hz and 100 kHz is 21 �V, where flickernoise represents the bottleneck to a better overall noiseperformance. The area occupied by the LDO is 0.09 mm2

which is mainly due to the width of the pass device.With respect to the bandgap reference, Figure 15 shows

the power-on and its quiescent current transients. Despitethe over-shoot experienced in the power-up, the output ref-erence is a stable and constant 1.21 V voltage. The sim-ulated quiescent current is 16 �A (typical). Simulationresults presented in Figure 16 show that the bandgap hasa high PSR all over the frequency spectrum, 130 dB @10 Hz and 70 dB @ 100 kHz. In terms of PSR, bothbandgap and LDO present high performance. However, ifthe difference between them would be higher, the over-all PSR performance would be degraded, assuming thatthe cores are connected as they should be in an IP/ICLDO product. The output noise voltage can be observed inFigure 17 and is equal to 120 �V when integrated between10 Hz and 100 kHz. It is clear that flicker noise is the



preponderant noise source in the circuit, although, thermaland shot noise (both spectrally flat) also introduce a sub-stantial positive “offset” in the spectral density. Figure 18shows the functionality of the trimming circuit, where itis possible to change the output voltage depending on thedigital code (bgtrim). Thus it is possible to adjust it tothe temperature of operation. The bandgap reference has atemperature coefficient of 15 ppm/�C considering the tem-perature range of [−40; 125] �C, which is a typical valueto a first-order temperature compensated bandgap circuit.

Table I presents a comparison between the LDOimplemented and other recently published works.16–19 Byanalysing Table I, we can conclude that line and load tran-sients are within the common specifications of the LDOs.Ref. [16] presents a low power LDO with an output noise87% above and half the current consumption of the pro-posed implementation. The noise reported for the LDO inRef. [17] is a good result, but the current consumptionstated is defined for a current load of 0 mA instead of fullload, making a comparison impossible. The current con-sumption reported by Refs. [18–19] is high above the onein the proposed linear regulator, which allows a better out-put noise value when integrated in the same bandwidth.Moreover, the specifications table of Ref. [18] presents anoutput rms noise voltage of 6.5 �V, considering a fre-quency range from 0.01 to 100 kHz; although the corre-sponding graphical simulation shows a different frequencyrange of 0.1 to 100 kHz. This leads to inconsistence inthe results because flicker noise located between 10 and100 Hz is quite relevant to the overall output noise. Typi-cal simulations show that at 100 Hz, the output rms noisevoltage of the LDO in Ref. [18] is 50 nV above the sim-ulated results of the proposed LDO. An external bypasscapacitor of 10 nF is also added in Ref. [19] in order toimprove the output noise voltage. Simulation results showthat the proposed topology can present a total output rmsnoise of 40 �V if the current consumption of the bandgapreference changes from 16 �A to 66 �A and the LDO iskept unchanged.

The PSR of the proposed work is high above the pub-lished works: PSR@100 kHz in this work is above or

Table I. Comparision of LDO’s Specifications used in industry.

Parameter [16] [17] [18] [19] This work

VIN (V) 2.7–6.5 1.7–5.5 2.5–5.5 1.8–20 3.1–5.5VOUT (V) 1.2–6.3 0.6–5.3 1.5–3.3 1.2–5 2.4IOUT (mA) 250 500 150 100 50IQ (�A) 45 80a 160 2200 16+54c

VNOUT rms (�V) 266 16 6.5 20 120+21c

COUT (�F) 2.2 10 0.47 10 4.7PSR (10 Hz) (dB) 60 92 85 65 120PSR (100 kHz) (dB) 28 62 40 — 90/VOUT //VIN (%) 0.08 0.04 0.06 0.04b 0.12/VOUT //IOUT (%) 1.25 0.02 3.4 3.2 0.89

aIOUT = 0 mA. bIOUT = 1 mA. cBandgap+LDO.

comparable with the value obtained @10 Hz of compara-ble LDOs.18–19

5. CONCLUSION

A precise theoretical noise analysis of a typical bandgapand LDO topology was presented, allowing the analoguedesigner to identify which are the trade-offs betweenpower and noise, and decide the architecture and designcriteria based on these constraints. Not only does the pro-posed regulator is low power, but it provides high PSR.

The proposed LDO is capable of supplying 50 mA ofload current; it exhibits an output root-mean-square noisevoltage of 21 �V and consumes 54 �A. The PSR is120 dB @ 10 Hz and 90 dB @ 100 kHz. The bandgapreference was chosen as a compromise between quiescentcurrent and noise for this low power PMU: for a quiescentcurrent of 16 �A, the output rms noise voltage achieved,with no bypass capacitor, is 120 �V.

The noise performance of the LDO is greatly affectedby the noise in the voltage reference used—the bandgapoutput. Therefore, a major constrain when designing a lownoise LDO is the power budget for the bandgap whichseverely limits the noise performance of the reference volt-age. Lower output voltage values lead to lower output rmsnoise in the LDO, since the thermal noise of the feedbackresistors decreases, while the power consumption remainsthe same.

The architectural approach of adding a dedicated seriesregulator in the supply of the bandgap proved to be a veryeffective solution, leading to significantly higher PSR thanrecently published works.

Simulation results show that a total rms noise reduc-tion to 40 �V can be achieved if the power consump-tion of the linear regulator plus reference changes to120 �A (increasing only the bandgap current). Exercis-ing this design flexibility clearly shows the advantages ofthe presented solution when compared to recently publishsimilar LDOs.

References

1. G. Patounakis, Y. W. Li, and K. Shepard, A fully integrated on-chipDC–DC conversion and power management system. IEEE J. Solid-State Circuits 39, 443 (2004).

2. R. J. Milliken, J. Silva-Martínez, and E. Sánchez-Sinencio, Full on-chip CMOS low-dropout voltage regulator. IEEE Trans. on Circuitsand Systems 54, 1879 (2007).

3. S. Yuan and B. C. Kim, Low dropout voltage regulator for wirelessapplications. 33rd Annual Power Electronics Specialists Conference,November (2002), Vol. 2, pp. 421–424.

4. V. Gupta, G. Rincon-Mora, and P. Raha, Analysis and design ofmonolithic, high PSR, linear regulators for SoC applications. Proc.IEEE Int. Syst. Chip Conf., Santa Clara, CA, September (2004),pp. 311–315.

5. V. Mannama, R. Sabolotny, and V. Strik, “Ultra low noise low powerLDO design. Baltic Electronics Conference, October (2006), pp. 1–4.

6. G. Rincon-Mora and P. Allen, A low-voltage, low quiescent current,low drop-out regulator. IEEE J. Solid-State Circuits 33, 36 (1998).



7. Analog Devices, Op Amp Power Supply Rejection Ratio (PSRR)and Supply Voltages, [Online], Available: www.analog.com/static/imported-files/tutorials/MT-043.pdf.

8. K. Lundberg, Noise Sources in Bulk CMOS, [Online], Available:web.mit.edu/klund/www/CMOSnoise.pdf.

9. A. v. d. Ziel, Noise, Prentice Hall (1954).10. B. Razavi, Design of Analog CMOS Integrated Circuits, 1st edn.,

McGraw-Hill Science/Engineering/Math, NY, USA (2000), Chap. 7,pp. 209–216.

11. Y. Tsividis, Operation and Modeling of the MOS Transistor, 2ndedn., McGraw-Hill, Boston (1999).

12. Johns & Martin, Analog Integrated Circuit Design, 1st edn., JohnWiley & Sons Inc, Chap. 4, pp. 181–216.

13. J. Rocha, N. Dias, A. Neves, G. Santos, A. Monteiro, M. Santos,and J. Teixeira, Controllability and observability in mixed signalcores. Submitted to IOLTS’2009 IEEE International On-Line TestingSymposium, Sesimbra-Lisbon, Portugal, June (2009).

14. A. Monteiro, M. Santos, B. Borges, and F. Lima, High PSRR,low power bandgap. DCIS’2008 XXIII Conference on Designof Circuits and Integrated Systems, Grenoble, France, November(2008).

15. P. Brokaw, M. Kayal, and T. Szepesi, Electronics Laborato-ries Advanced Engineering Course on POWER MANAGEMENT,September (2006).

16. 250 mA, Low Quiescent Current, Ultra-Low Noise, High PSRR LowDropout Linear Reg (Rev. F). Texas Instruments, Texas InstrumentsDatasheet, TPS73433 (2009).

17. Low-Noise 500 mA LDO Regulators in a 2 mm × 2 mm TDFNPackage, Maxim, Maxim Datasheet, MAX8902A (2008).

18. Ultra Low Noise, 150 mA Linear Regulator for RF/Analog CircuitsRequires No Bypass Capacitor, National Semiconductor, NationalSemiconductor Datasheet, LP5900 (2008).

19. 100 mA, Low Noise, LDO Micropower Regulators in SOT-23, Lin-ear Technology, Linear Technology Datasheet, LT1761 Series.

Angelo MonteiroAngelo Monteiro was born in Barreiro, Portugal, in 1984. He received the M.Sc. degree in electrical and computer engineeringfrom Instituto Superior Técnico, Technical University of Lisbon, Lisbon, Portugal, in 2008. In summer 2007, he joined MIPS® ABGChipidea, Portugal, where he developed his M.Sc. thesis and worked as a trainee in Audio and Power Solutions division. In 2008,he joined INESC-ID, Portugal, where he is currently a researcher in the area of power management ICs and a Ph.D. candidate fromInstituto Superior Técnico, Technical University of Lisbon, Lisbon, Portugal. His areas of interest include power management anddata conversion systems design.

Marcelino Bicho dos SantosMarcelino Bicho dos Santos was born in Beja, Portugal, in 1967. He received the M.Sc. and Ph.D. degrees in electrical engineeringfrom the Instituto Superior Técnico, Technical University of Lisbon, Lisbon, Portugal, in 1994 and 2001, respectively. He has beena Professor at Instituto Superior Técnico, form the Technical University of Lisbon, since 1990. His research interests include powermanagement, testability, and educational issues on microelectronics.

Alexandre NevesAlexandre Neves was born in Lisbon, Portugal, in 1983. He received the M.Sc. degrees in electronics engineering from InstitutoSuperior Tecnico, Portugal, in 2007. In 2007, he joined the MIPS ABG Chipidea as power management engineer. In 2008 he joinedINESC-ID as a researcher/Ph.D. student in data conversion systems. His current interest is in the development of low-power delta-sigma A/D and D/A converters for digital audio.

Nuno DiasNuno Dias was born in Tavira, Portugal, on the 14th April 1983. He has received his M.Sc. degree in Electrical and ComputerEngineering from Instituto Superior Técnico, Portugal, in 2008. His M.Sc. thesis has been developed at Chipidea® MIPSABG, with thefocus on low power DC–DC conversion. In 2008 he joined INESC-ID as researcher/Ph.D. student in low power integrated DC–DCconversion.


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Noise Minimization for Low Power Bandgap Reference and ......Email: [email protected] related with each other.Power Supply Rejection (PSR) is a measure of how well