.................................................................................................................................................................................................................

NONVOLATILE PROCESSORARCHITECTURES: EFFICIENT, RELIABLEPROGRESS WITH UNSTABLE POWER

.................................................................................................................................................................................................................

NONVOLATILE PROCESSORS (NVPS) ARE A PROMISING SOLUTION FOR ENERGY-

HARVESTING SCENARIOS IN WHICH THE AVAILABLE POWER SUPPLY IS UNSTABLE AND

INTERMITTENT. THIS ARTICLE EXPLORES THE DESIGN SPACE FOR AN NVP ACROSS

DIFFERENT ARCHITECTURES, INPUT POWER SOURCES, AND POLICIES FOR MAXIMIZING

FORWARD PROGRESS IN A FRAMEWORK CALIBRATED USING MEASURED RESULTS FROM A

FABRICATED NVP. THE AUTHORS PROPOSE A HETEROGENEOUS MICROARCHITECTURE

SOLUTION THAT EFFICIENTLY CAPITALIZES ON EPHEMERAL POWER SURPLUSES.

......To handle unstable power condi-tions, such as power from ambient Wi-Fi sig-nals, solar panels, and human movementpiezo-electronic energy harvesters (see the“Energy-Harvesting Systems” sidebar), tradi-tional processors need a large energy-storagedevice such as a supercapacitor to conserva-tively accumulate sufficient energy for taskcompletion before that task starts. Otherwise,a task failure could occur at every power-supply emergency. Although this approach isviable for certain deployments, both formfactor (the energy-storage device’s mass and/or size) and conversion efficiency can pre-clude fully conservative solutions. Existingsolutions to power instability mainly consistof checkpointing techniques to store theintermediate task computation states toexternal nonvolatile memory (NVM) stor-age, such as flash, before power failures occur.However, reset and rollbacks with communi-

cation to external data storage result in highperformance and power costs.1,2

Unlike traditional processors, nonvolatileprocessors (NVPs) can leverage their nonvo-latility feature to ensure forward progresswithout relying on additional durable storageto preserve processor state.1–4 An NVP is aprocessor with built-in NVM and the facili-ties to back up all state on the chip to thesememories when a power failure occurs and torestore the processor state when powerreturns. Importantly, an NVP’s instruction-level backup and recovery operations can bebuilt transparent to programmers and com-pilers, making it compatible with manydesign automation techniques and moreenergy efficient than existing solutions.Although NVPs intuitively offer simplerminimum forward progress guarantees,recent works3–5 have shown that NVPs offersuperior overall forward progress—that is,

Kaisheng MaXueqing Li

Pennsylvania State University

Karthik SwaminathanIBM T.J. Watson Research Center

Yang ZhengPennsylvania State University

Shuangchen LiUniversity of California,

Santa Barbara

Yongpan LiuTsinghua University

Yuan XieUniversity of California,

Santa Barbara

John (Jack) SampsonVijaykrishnan Narayanan

Pennsylvania State University

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72 Published by the IEEE Computer Society 0272-1732/16/$33.00�c 2016 IEEE

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Energy-Harvesting SystemsRecent developments in body-area networks and the Internet of

Things (IoT) markets have led to a profound proliferation of power-

constrained and form-factor-constrained devices. For many of these

devices, their intended deployment conditions or durations make bat-

tery-powered operation difficult or impractical. With technological

improvements in both material types and computation efficiency,

energy-harvesting systems1–6 have become a plausible alternative to

battery-powered operation, in that the average power available for

harvesting-powered devices is now sufficient to perform meaningful

computation. Figure A shows a sampling of such energy-harvesting

IoT devices7,8 and highlights their diversity in energy source (RF, pie-

zoelectric,9,10 thermal,11 and solar12), form factor, application space,

and power needs. Although such devices are well-suited for certain

niche applications, they do not present a competitive alternative for

the complex computations required by more mainstream applications.

This is because of the difficulty in using a short-term power budget

that is both highly variable and deeply unpredictable.

Figure B shows the power traces for four typical ambient energy

sources that could be harvested to power an embedded system:

namely, solar energy and energy due to RF radiation, piezoelectric

Temporomandibular joint(jaw joint)

Ear canaldeformation Jaw joint

movement

(1)

(2) (3)

(4)

Figure A. A sampling of energy-harvesting Internet of Things devices. (1) A Wi-Fi-powered camera, with demonstration

system mounted on an industrial gas cylinder, monitoring a pressure gauge.7,8 (2) In-shoe piezoelectric devices9 and a

piezoelectric ear canal motion energy harvester.10 (3) Thermoelectric generator.11 (4) Solar leaves.12

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MAY/JUNE 2016 73

effect, and thermal gradients. The RF energy is obtained by measur-

ing the power of the frequency spectrum from a TV station, the piezo-

electric energy is measured through devices fixed on a bike, the

thermal energy is generated from characterizations described by

Romain Grezaud and Jerome Willemin,13 and the solar trace is

obtained using data from the Measurement and Instrumentation

Data Center (www.nrel.gov/midc). Although all of these sources are

nearly ubiquitously available, there are several drawbacks in relying

on ambient sources of energy for computing purposes. Most harvest-

ers of these energy sources operate at relatively low conversion effi-

ciencies, because only a small fraction of the total transmitted power

can be tapped. In addition, a common issue across harvesting sys-

tems is unstable input power, because external factors could cause a

supply disruption. For instance, ambient RF or Wi-Fi power can vary

arbitrarily, according to power source, frequency, distance from the

transmitter, height, obstacles, external electromagnetic signals, and

other factors3; Figure B1 showcases this phenomenon, with instanta-

neous power levels that can vary by orders of magnitude over even

very short timescales. To understand how these sources’ properties

will enable and limit various aspects of energy-harvesting systems,

we classify power sources according to three primary characteristics:

signal magnitude, signal strength variability, and power drop-out fre-

quency (intermittency).

With respect to signal variability, we observe substantial variation

in power, even over a few milliseconds, for RF in Figure B1 with the

ratio between the maximum and minimum power over this period

around 250 times. The piezoelectric power is more stable than RF

with just some short power loss in Figure B2. The thermal power,

shown in Figure B3, is even more stable, because of the gradual

nature of temperature variation. Variation in solar power, seen in Fig-

ure B4, depends on the weather conditions and orientation of the

solar cell.

Another feature is the intermittency frequency, which influences

how soon the power drops below a viable threshold, as indicated by

the annotations in Figure B1. The intermittency frequency strongly

influences backup and recovery overheads. Sources with periodic

behavior, as in Figure B2, favor prediction of power loss and enable

efficient scheduling of tasks, whereas less predictable sources similar

to Figure B1 must consider more conservative approaches or minimize

the cost of mispredictions.

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Figure B. Power traces. (1) TV station RF, (2) piezoelectric, (3) thermal, and (4) solar. Sample time for each figure is 0.33 ls.

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74 IEEE MICRO

conversion of incoming energy into usefulwork—than other approaches.

The concept of a processor or microcon-troller with integrated nonvolatility is notnew. Commercial products from Texas Instru-ments6 and chips from academic sources2

have been produced with nonvolatile reten-tion features. However, our previous work3

and its extensions4 represent the first explora-tion into the architectural design space ofNVPs; the interactions among microarchitec-tures, backup policies, and harvesting technol-ogies; and the design and management of anenergy-harvesting system that maximizes con-version of incoming ambient energy into use-ful work in an environment where poweremergencies can occur with frequencies in thetens of instructions. Our work aims to provideforward guidance for an increasingly battery-less Internet-of-Things future, and we havehighlighted key differences between designoptimizations for harvesting and battery-powered systems.

Our models have been validated againstfabricated NVP hardware, taking into accountsystem-level effects of power instabilitybeyond the processor itself. NVP research isfundamentally cross-layer in nature, becausepower instability affects every aspect of the sys-

tem, from application quality of service todelays in phase-locked-loop stabilization tothe interaction of capacitor sizing, rectifier effi-ciency, and the ability to make predictionsregarding whether continued execution duringa power emergency is likely to improve ordegrade the rate of progress. We show how,even in this extremely power-limited environ-ment, aggressive architectures operatingbeyond the maximum efficiency point canactually be beneficial in scenarios where peakpower can be vastly higher than average, andwe show the potential of predictive mecha-nisms to more aggressively exploit whateverincoming energy does still arrive during apower emergency and to select among micro-architectures in a heterogeneous design tomaximize forward progress. In this article, wesummarize our key findings and approachesto exploring the tradeoffs in the design spaceof NVP architectures and policies.

Architectural and Backup Policy CodesignSpaceEven the simplest processor microarchitec-ture has multiple possible policies for whatstate to back up and when. Here, we outlinethe space of microarchitectures and

References1. K. Ma et al., “Architecture Exploration for Ambient Energy

Harvesting Nonvolatile Processors,” Proc. Int’l Symp. High-

Performance Computer Architecture, 2015. pp. 526–537.

2. K. Ma et al., “Nonvolatile Processor Architecture Exploration

for Energy-Harvesting Applications,” IEEE Micro, vol. 35, no.

5, 2015, pp. 32–40.

3. Y. Liu et al., “Ambient Energy Harvesting Nonvolatile Pro-

cessors: From Circuit to System,” Proc. 52nd Ann. Design

Automation Conf., 2015, article 150.

4. Y. Liu et al., “A 65nm ReRAM-Enabled Nonvolatile Processor

with 6X Reduction in Restore Time and 4X Higher Clock Fre-

quency Using Adaptive Data Retention and Self-Write-Termi-

nation Nonvolatile Logic,” Proc. IEEE Int’l Solid-State Circuits

Conf., 2016, pp. 84–85.

5. X. Li et al., “RF-Powered Systems Using Steep-Slope

Devices,” Proc. IEEE 12th Int’l New Circuits and Systems

Conf., 2014, pp. 73–76.

6. H. Liu et al., “Tunnel FET RF Rectifier Design for Energy Har-

vesting Applications,” IEEE J. Emerging and Selected Topics

in Circuits and Systems, vol. 4, no. 4, 2014, pp. 400–411.

7. V. Talla et al., “Powering the Next Billion Devices with Wi-

Fi,” arXiv preprint, 2015; arXiv:1505.06815.

8. S. Naderiparizi et al., “WISPCam: A Battery-Free RFID Cam-

era,” Proc. IEEE Int’l Conf. RFID, 2015, pp. 166–173.

9. N.S. Shenck et al., “Energy Scavenging with Shoe-Mounted

Piezoelectrics,” IEEE Micro, vol. 21, no. 3, 2001, pp. 30–42.

10. A. Delnavaz and J. Voix, “Energy Harvesting for In-Ear Devi-

ces Using Ear Canal Dynamic Motion,” IEEE Trans. Industrial

Electronics, vol. 61, no. 1, 2014, pp. 583–590.

11. S.J. Kim et al., “A Wearable Thermoelectric Generator Fabri-

cated on a Glass Fabric,” Energy & Environmental Science,

vol. 7, no. 6, 2014, pp. 1959–1965.

12. “Solar Power from Energy-Harvesting Trees,” video, 16 Feb.

2015; http://youtu.be/ QswunfBC8U.

13. R. Grezaud and J. Willemin, “A Self-Starting Fully Integrated

Auto-Adaptive Converter for Battery-Less Thermal Energy

Harvesting,” Proc. IEEE 11th Int’l New Circuits and Systems

Conf., 2013; doi:10.1109/NEWCAS.2013.6573612.

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MAY/JUNE 2016 75

associated policies we considered. We focusedon determining which architectural configu-rations were best suited to optimally use theavailable power and energy by maximizingprocessor performance under different energyconstraints. Hence, depending on the energyharvested, we analyzed various parameters,such as the number of pipeline stages, data tobe backed up, and frequency of backups.

Nonpipelined ConfigurationIn the absence of any pipeline stages, theentire processor state can be characterized bya single instruction state. In addition to thearchitecture, there are also tradeoffs betweenthe energy consumed in backing up andrecovering the data and the overall perform-ance. We explore these tradeoffs by choosingwhich data to save and where and when tosave them for three architectures of gradientcomplexity.

The first policy, backup every cycle (BEC),employs an NVM register file, or else boththe contents of a volatile Regfile and its coun-terpart nonvolatile location need to updatedevery cycle. As Figure 1 shows, only the pro-gram counter (PC) and a few registers arewritten into the Regfile every cycle. Someinstructions, such as StoreWord and Jump,do not require any further Regfile write.

The second policy, on-demand all backup(ODAB), differs from the previous solutionin that all RegFile entries must be backed uponly in the event of a reduced power state. Inthe last policy, on-demand selective backup

(ODSB), only data that has changed sincethe last backup is updated in NVM.

N-Stage Pipeline (In Order)Owing to the increase in processor circuitcomplexity and activity factor in an n-stagepipeline processor, the power threshold of thisdesign in energy-harvesting systems is higherthan that of the nonpipelined (NP) case.

We consider two strategies for backup inthe pipelined design (see Figure 2). In thefirst scheme, shifted PC and volatile flip-flop(SPC/VFF), a shifter buffer is designed toremember the PC value in each pipelinestage. The unfinished PC to be backed upwould then be in the data memory stage. Inthe second scheme, nonvolatile flip-flops(NVFF), the PC and RegFile are automati-cally backed up through NVM flip-flops inthe instruction fetch/instruction decode (IF/ID) pipeline stages.

Out-of-Order ProcessorsAlthough OoO processors are less frequentlyconsidered for low-power deploymentsbecause of their lower efficiency, the need ofbatteryless harvesting systems to greedily con-sume power when it is present can still makethem a competitive option. Because of itshigher activation requirements, an OoO pro-cessor will be less frequently active than theother two datapath designs, and it also con-tains more state to consider saving duringpower emergencies. We considered severalpolicies for an OoO processor.

TimeInput

power

ComputeODSB

PC or PC+4 Backup only Changed RegFile

Off

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Recovery PC or PC+4

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last inst

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...

Backup or skip the Reg

Compute one inst

Off

Recovery Compute

...

Backup PCBackup the changed Reg

Inst like SW, J do not change Reg

BEC

on off on

Figure 1. Runtime components for nonpipelined (NP) configuration schemes.

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Minimum-state resource backup solution (Mi-nR). MinR backs up the minimal number ofbits required to preserve functionality acrosspower interruptions, including first uncom-mitted PC at the head of the reorder buffer(ROB), architectural RegFile, and map table.However, before backing up, some extra oper-ations are needed to achieve a consistent state.

Low-latency backup solution (LLB). Ratherthan back up only the first uncommitted PC,this solution backs up the entire ROB, theinstruction queue (IQ), ARegFile, map table,and PRegFile. Although LLB has more struc-tures to be backed up than MinR, it cansometimes be more energy efficient becauseof the extra work required in MinR both pre-backup and post recovery.

Middle-level backup solution (MLB). Insteadofusing extra recovery time andenergy to restorethe ready table and free list in the LLB, MLBbacks up the ready table and free list as well.

Min-state-lost backup solution. In this solu-tion, all the structures are backed up, includ-ing the branch history buffer (BHT) andbranch target buffer (BTB).

Incremental backup. This scheme combinestwo key insights. During power emergencies,power income often is still greater than zero,and if substantial capacitor energy remainsafter the minimum amount of state has beenpreserved, the system can continue backing upprogressively less-essential microarchitectural

state to preserve performance after recovery,despite having a capacitor provisioned onlyfor minimal backup margins. This could delayrecovery from shorter power emergencies,because the capacitor might be more drainedthan it otherwise would have been.

Architecture SelectionWhich nonvolatile architecture provides thebest forward progress for a particular applica-tion scenario depends on various factors. Theinput power and the stability of the powersupply are two key elements that impact thechoice. In addition, the application’s compu-tational complexity and performance require-ments are also important.

To evaluate our different design strategies,we developed a simulation framework formodeling both execution and power emer-gencies. We validated this framework, espe-cially the system-level effects of poweremergencies, against a fabricated NVP.7 Ourframework models energy consumptionbased on synthesized versions of all threepipelines (including an OoO design fromFabscalar8) in Synopsys Design Compilerwith a 45-nm TSMC low-power library.

The input signal characteristics play amajor role in determining the optimal design,as our experiments with Wi-Fi power trailsunder different environmental conditionsmade clear. Figure 3 demonstrates the per-formance of the various backup schemeswhen home and office Wi-Fi sources are usedfor harvesting energy. For the home environ-ment, a nonpipelined ODSB architecture

Time

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Pipeline FF in each stage Flag

Clear Atomic flag PC

Figure 2. Runtime components for five-stage pipelined (5-SP) schemes. (SPC: shifted PC; NVFF: nonvolatile flip-flops; VFF:

volatile flip-flops.)

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MAY/JUNE 2016 77

performs best, whereas in the office environ-ment, the more complex OoO processor isdesirable. This is because the home Wi-Fi sig-nal typically comprises a single router, whereasthe office environment usually comprises sig-nals from more routers. A disturbance in thesignal would result in input power going toalmost zero in the home environment; thus,

the simplest design with the lowest powerthreshold is preferred. In contrast, in the officeenvironment, the additional routers continueto supply input power at a relatively similarstrength in an uninterrupted fashion, allowingfor more complex architectures.

Here, we briefly summarize our findingswhen comparing architecture and policy pairs.

BEC ODAB ODSB SPC/VFF NVFF MinR LLB MPL0

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Office string search stringsearch inst no. = 159 KImage recognition susan.corners inst no. = 1.1 MImage recognition susan.edges inst no. = 1.8 M Image decoder jpeg.decode inst no. = 6.7 MExchange of crypto-graphic keys sha inst no. = 13.5 MVoice decoding gsm.decode inst no. = 23.9 M

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Figure 3. Execution time when harvesting Wi-Fi energy. (a) Home environment (with one

router as the strongest and the others with relatively weak signals). (b) Office environment

(with multiple routers of similar signal strength).

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Of the NP policies, ODSB is the most energy-efficient strategy when the source is relativelystable (for example, solar energy). Comparedto ODAB, ODSB can reduce the backupenergy penalty by 69 percent with only 0.002percent area overhead. Although BEC is notthe most energy efficient, with very weak sour-ces such as Wi-Fi, it does not require the timeto accumulate energy in the capacitor toensure sufficient backup energy is available.Thus, it is viable when the power failures areextremely frequent (less than 1 in 10 cycles),which rarely happens even in Wi-Fi sources.

For pipelined processors, we find thatSPC/VFF requires 11 percent less time and57 percent less energy than NVFF. An extrafour clock cycles are needed to reexecute thelast four instructions that are lost from thelatter pipeline stages after recovery (we regardthis as part of the recovery time penalty).However, only backing up one PC with asmall shifter allows a smaller backup capaci-tor with lower leakage to be sufficient forSPC/VFF, which in turn affects the powerthreshold. In this case, SPC/VFF will also beable to outperform NVFF after severalrepeated instructions.

The OoO processor’s viability and backuppreference depend highly on the power pro-file, offering both substantial speedups andlarge slowdowns for different power inputtraces. In particular, the OoO processorbackup policies are sensitive to the frequencyof power emergencies. For the traces exam-ined, the incremental backup approach washighly promising.

Smart Matching ArchitectureThe results of the previous section highlighthow different architectures can achieve supe-rior progress depending on the applicationand power profile features. This variableaffinity also exists at finer temporal granular-ity within a power profile. To exploit this, wepropose using a dynamic heterogeneousarchitecture with NP, n-stage pipelined, andOoO microarchitecture cores to fit differentscenarios (see Figure 4).9 The NP datapathhas the lowest energy per instruction at ourminimum considered frequency, giving it thelowest turn-on threshold and making it suit-able for periods with minimally viable powerincomes. For our NSP design, we employpipelining not to achieve a higher frequency,but to achieve the same frequency as the NPdesign at a lower voltage. Finally, the OoOprocessor’s greater performance can lead togreater overall progress despite less-frequentactivation opportunities, making all threedesigns plausible selections for being themost suitable core for executing a portion ofa program given varying input power.

At one time, only one microarchitecture isactive, and a dynamic matching architecturecontroller selects the active core. The control-ler comprises two primary components: a fea-ture extractor that accumulates the recenthistory of input power and power emergen-cies into a signature, and a prediction modulethat maps this signature to a selection.Because of the predictor’s relatively highcomplexity compared to the simple NP andNSP datapaths, this controller is activated to

PC ALU Writeback

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Figure 4. Dynamic matching architecture diagram with a machine-learning-based controller in the control path.

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MAY/JUNE 2016 79

perform a prediction only once every 200ms, thus limiting prediction overhead. Thecontroller predicts if and when the micro-architecture should be switched, for example,from NP to OoO due to underexploitationof incoming power, or from OoO to NP dueto excessive frequency of backup events. Ifthe nonvolatile storage is augmented withdouble buffering, the same controller canalso be used to make predictions on whetherpower emergencies will resolve before storedenergy is depleted, eliding a backup opera-tion. If the controller changes the currentmicroarchitecture setting, it will need to takeseveral steps to finish such a switching opera-tion, and the transition overheads varydepending on which transition is occurring.

Switching among architectures requiresseveral steps to be carried out under the con-trol of the dynamic matching architecturecontroller. The complexity of the switchvaries depending on which transition isoccurring. For example, the NP to NSP orOoO transition proceeds through the follow-ing steps:

1. The controller ensures that there isenough energy storage to guaranteesuccessful microarchitecture switching.

2. The controller gates the clock signaland waits for longer than one normalclock cycle to make sure that oneinstruction is finished for NP.

3. The PC indicating the next instruc-tion address in instruction memoryis shared from NP to NSP or OoO.

4. The register file is volatile and hasalready been updated by NP. Thecontrol signals of register files arenow handed over from NP to NSPor OoO.

5. The data memory is nonvolatile andhanded over from NP to NSP orOoO.

6. The PC part for NP, the arithmeticlogic unit part for NP, and the write-back part for NP are all supply gatedto avoid leakage.

The process of switching from NSP toNP or OoO is similar, albeit with a higherinitial energy threshold. Key differencesinclude potential reexecution of software if itis the oldest incomplete instruction and slight

differences in PC backup. The NSP PCtracking hardware (SPC/VFF) can be inte-grated into both the NP and NSP pipelinesto simplify transitions between the twodatapaths.

Switching from OoO is more compli-cated. The minimum energy required for aswitch is much higher than that of NP andNSP, because OoO needs to restore the origi-nal states changed by the uncommittedinstructions. We resume on uncommittedthe PC at the head of ROB and squash allother instructions regardless of status, lever-aging existing branch misprediction path-ways. When returning to OoO from NP orNSP, performance could initially be substan-tially lower than that observed during thepreceding OoO execution period. This isbecause some metadata related to perform-ance rather than correctness (for example,BHTand/or BTB) is lost.

Result and DiscussionFigure 5 compares a baseline execution of theNP core at 32 KHz against the dynamicmatching architecture. For the same powerprofile, the forward progress of NSP is 1.08times that of NP, and the forward progress ofOoO is 1.32 times that of NP. We also testother power profiles and observe that the for-ward progress ratio of OoO to NP variesfrom 2.55 to 0.14 times. Because OoOrequires a higher power and energy threshold,this ratio is highly dependent on the powersources and profiles. The power profileshown in Figure 5a is the power inputsampled every 0.2 seconds per point in theambient Wi-Fi environment. The Wi-Fi’svariation is large because of the multiplechannel effect, data transformation, obstaclemovement, signal refraction, and reflections.The maximum temporal power can be 300times larger than the minimum power. Wealso compare with a fixed OoO core, but weshow only the NP baseline for clarity. TheNP baseline shows continuous forward prog-ress due to a lack of backup events for thisparticular power trace. Note, however, thatsystem execution does not begin until there issufficient stored energy for a successfulbackup.

Figures 5b and 5c show the stored energy,backup operations, and current processor

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mode. For this power profile and trainingresult, and the input power profile, NSP isnot selected, and there are numerous switchesbetween NP and OoO. As Figure 5b shows,the stored energy level is consumed moreaggressively in the dynamic architecture thanthe baseline. This reduces the percentage oftime when the capacitor saturates, whichavoids energy losses due to insufficientenergy-storage capacity. More aggressive con-sumption does come with a cost: Comparedto the baseline with no backup operation,this dynamic matching architecture needs 13backup operations. However, the net effect ofconsumption increase is strongly positive,turning more incoming energy into compu-tation. This significantly increases the for-ward progress, achieving 2.4 and 1.82 times

the progress of the baseline NP and OoOarchitectures, respectively.

N onvolatile-processor-based platformscan be an ideal enabler for the IoTand

wearable devices. Some of the explored archi-tectures have been adopted and verifiedthrough fabrication: for example, the pro-posed ODSB solution is applied in second-generation NVP.2

In the near future, we will explore how tra-ditional techniques such as dynamic voltageand frequency scaling can be applied to NVPand how should it be adjusted. A hybrid archi-tecture with dynamic resources could also beuseful to adapt to variable power profiles.Rather than traditional architecture methods,a machine-learning-based controller proves to

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Figure 5. Baseline: a nonvolatile processor with only one NP microarchitecture core simulation result. (a) An example 1-

minute power profile in an ambient Wi-Fi environment. (b) Scaled stored energy level in a 470 uF energy storage capacitor. (c)

Scaled forward progress simulation results for dynamic matching architecture with nonpipelined (NP), n-stage pipelined

(NSP), and out of order; the neural network comprises four hidden layers with 30, 10, 10, and 10 neurons in each hidden layer.

(d) Stored energy level as inputs and backup number count. (e) Neural network outputs for the microarchitecture core

selection. (f) Forward progress result for the dynamic matching architecture.

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predict in high quality in control path design.Accelerators for machine learning application-level algorithms based on software implemen-tation or hardware implementation can evenbe merged for both the application and con-troller. New devices like the Tunnel-FET canalso be applied to further reduce the powerconsumption for NVPs.10,11 Novel distrib-uted circuits merging both the computationand backup operations can further reduce thebackup time and energy.12

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AcknowledgmentsThis work was supported in part by the Cen-ter for Low Energy Systems Technology(LEAST); MARCO and DARPA; NSFawards 1160483 (ASSIST), 1205618,1213052, 1461698, and 1500848; ShannonLab Huawei Technologies; High-TechResearch and Development (863) Programunder contract 2013AA01320; and theImportation and Development of High-Caliber Talents Project of Beijing MunicipalInstitutions under contract YETP0102.Xueqing Li and Vijaykrishnan Narayananare the contact authors.

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8. N.K. Choudhary et al., “FabScalar: Compos-

ing Synthesizable RTL Designs of Arbitrary

Cores Within a Canonical Superscalar

Template,” Proc. 38th Ann. Int’l Symp.

Computer Architecture, 2011, pp. 11–22.

9. K. Ma et al., “Dynamic Machine Learning

Based Matching of Nonvolatile Processor

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puter-Aided Design, 2015, pp. 670–675.

10. X. Li et al., “RF-Powered Systems Using

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11. H. Liu et al., “Tunnel FET RF Rectifier Design

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12. G. Sumitha et al., “Nonvolatile Memory

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Kaisheng Ma is a PhD student in theDepartment of Computer Science andEngineering at Pennsylvania State Univer-sity. His research interests include energy-harvesting architectures, machine learning,and neuromorphic computing. Ma receivedan ME in microelectronics from PekingUniversity. Contact him at kxm505@cse.psu.edu.

Xueqing Li is a postdoctoral researcher inthe Department of Computer Science andEngineering at Pennsylvania State Univer-sity. His research interests include high-per-formance data converters, wireless trans-ceivers, self-powered nonvolatile systems,and circuits and systems using emergingdevices. Li received a PhD in electronics

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engineering from Tsinghua University. He isa member of IEEE. Contact him at lixueq@cse.psu.edu.

Karthik Swaminathan is a researcher at theReliability and Power-Aware Microarchitec-ture Group at the IBM T.J. WatsonResearch Center. His research interestsinclude power-efficient and resilient sys-tems, approximate computing, and cogni-tive architectures. Swaminathan received aPhD in computer science and engineeringfrom Pennsylvania State University. Contacthim at kvswamin@us.ibm.com.

Yang Zheng is a software engineer at Goo-gle. His research interests include computerarchitecture design and nonvolatile memory.Zheng received an MS in computer scienceand engineering from Pennsylvania StateUniversity, where he completed the work forthis article. Contact him at yxz184@cse.psu.edu.

Shuangchen Li is a PhD student in theDepartment of Electrical and ComputerEngineering at the University of California,Santa Barbara. His research interests includecomputer architecture, especially emergingnonvolatile memory. Li received an MS inelectronic engineering from Tsinghua Uni-versity. Contact him at shuangchenli@ece.ucsb.edu.

Yongpan Liu is an associate professor in theDepartment of Electronic Engineering atTsinghua University. His research interestsinclude nonvolatile computation, low-powerVLSI design, emerging circuits and systems,and design automation. Liu received a PhD inelectronics engineering from Tsinghua Uni-versity. He is a member of IEEE; ACM; andthe Institute of Electronics, Information, andCommunication Engineers. Contact him atypliu@tsinghua.edu.cn.

Yuan Xie is a professor in the Departmentof Electrical and Computer Engineering atthe University of California, Santa Barbara.His research interests include computerarchitecture, electronic design automation,and VLSI design. Xie received a PhD inelectrical engineering from Princeton

University. He is a Fellow of IEEE. Contacthim at yuanxie@ece.ucsb.edu.

John (Jack) Sampson is an assistant profes-sor in the Department of Computer Scienceand Engineering at Pennsylvania State Uni-versity. His research interests includeenergy-efficient computing, architecturaladaptations to exploit emerging technolo-gies, and mitigating the impact of dark sili-con. Sampson received a PhD in computerengineering from the University of Califor-nia, San Diego. He is a member of IEEE.Contact him at sampson@cse.psu.edu.

Vijaykrishnan Narayanan is a distin-guished professor of computer science andengineering and electrical engineering atPennsylvania State University. His researchfocuses on energy-efficient computing. Nar-ayanan received a PhD in computer sciencefrom the University of South Florida. He isa Fellow of IEEE and ACM. Contact him atvijay@cse.psu.edu.

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