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Department of Electrical and Computer Engineering
Center for High Performance Power Electronics
Normally-Off GaN Field Effect Power Transistors:
Device Design and Process Technology Development
Sept 19th , 2014
Dr. Wu Lu (614-292-3462, [email protected])
Dr. Siddharth Rajan (614-247-7922, [email protected])
Leading Faculties
2
Dr. Wu Lu
Professor
• Semiconductor device physics and
design
• Advanced semiconductor
processing technologies
• Device characterization and
modeling
• Energy storage devices
Dr. Siddharth Rajan
Associate Professor
• Nano-scale semiconductor
devices
• Molecular beam epitaxy
• III-nitride semiconductors.
Research Programs on Nitride Semiconductor Materials and Devices
Crystal growth and epitaxy (Rajan, Myers)
Process science and advanced device fabrication technologies
(Lu, Rajan)
• Metal contacts
• Process-induced defects
• Nanoscale,e-beam lithography; deep UV; ICP RIE plasma etching
• High frequency, high power, low noise GaN HEMTs
Material characterization (Ringel, Brillson, Arehart)
• Structural, electronic, optical, chemical, in-situ & ex-situ measurements
• Development of new techniques at nanometer resolution
• Interface physics (metal-ceramic, dielectric-semiconductor)
Device modeling, testing and circuit design (Lu, Roblin, Wang)
• Small and large signal RF testing/modeling
• Pulsed IV, RF measurements; nonlinear mwave; thermal modeling
3
Normally-off GaN-based Power FETs
Two strategies for normally-off GaN-FETs
1 Design of new Ga-faced or N-faced heterostructures for normally-off channel
2 Development of key process technologies for GaN power transistors
Key requirements of solid-state power devices
- Higher breakdown voltage
- Lower on-resistance
- Higher operation current
- Normally-off channel
- Higher switching speed
Therefore, normally-off GaN-based FETs
4
5
Frontend Processing Technologies
6
Manufacturable Ohmic Contacts for GaN Power Transistors
Metal GaN
2DEG
﹋﹋ e-
Ef
Ec
Ev
AlGaN
Plasma processing to generate a thin layer of n+
region to promote carrier tunneling
Requirements for Gate Recess
1. Controllability
Slow etch rate
High selectivity (some applications)
2. Minimal damage
3. Smooth surface morphology
4. Uniformity
7
Excellent Etch Rate Control, Selectivity, Smoothness
0 1 2 3 4 5 9 100
2
4
6
8
10
12
Etc
h d
epth
(nm
)
Etch time (min)
GaN cap
thickness4-5 nm/min
[6] M. Schuette et al., J. Vac. Sci. Technol. B. 25 p. 1870 (2010).
8
Diode C-V
2DEG shifted 11 nm toward surface Cap layer precisely removed after 70% overetch
n+-GaN cap fully depleted
Sch
ottk
y in
terface
0 10 20 30 40 50 6010
16
1017
1018
1019
1020
1021
recessed
non-recessed
Ele
ctro
n d
ensi
ty (
cm-3)
Depletion width (nm)
11.0 nm
Vmax
= +3 V
9
Diode C-V, I-V
0 2 4 6 8 10 12 14 16 182
3
4
5
6
7
8
9
0
2
4
6
8
10
-Pin
cho
ff vo
ltage (V
)
2D
EG
den
sity
(1
01
2 c
m-2)
Plasma exposure time (min)
C-V extractions
• Threshold voltage control
-5 -4 -3 -2 -1 0 1 2 3 410
-6
10-5
10-4
10-3
10-2
10-1
100
101
102
103
reference
6 min
18 min
Cu
rren
t d
ensi
ty (
A/c
m2)
Applied bias (V)
• Reduced leakage current
Etched
Not etched
10
10-3
10-2
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
Gm
,max
(mS/m
m)
Threshold voltage & Gm,max
vs ID at V
DS = 10 V
VT (V
)
ID (A) at V
DS 10 V
0
100
200
300
400
500
102
103
104
105
106
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
Threshold voltage & Gm,max
vs Resistance at VDS
= 0 V
Gm
,max
(mS/m
m)
VT (V
)
R () at VDS
= 0 V
0
100
200
300
400
500
-2 -1 0 1 2 30
100
200
300
400
500
VGS
(V)
Gm (m
S/mm
)
I D (m
A/m
m)
0
40
80
120
160
-2 -1 0 1 2 30
100
200
300
400
500
600
700
Gm (m
S/mm
)I D
(mA/
mm
)
VGS
(V)
0
50
100
150
200
250
300
350
-1 0 1 20
50
100
150
200
250
Gm (m
S/mm
)I D (m
A/m
m)
VGS
(V)
0
40
80
120
160
VT & Gm,max distribution vs R at 0 V and ID at 10 V
Note that R at 0V and ID at 10 V were measured between source & drain after gate recess & before gate metallization
11
Why Gate dielectric is necessary in GaN Power FETs ?
• Why MIS structures?
- To reduce gate leakage current (various oxides, SiNx)
- To increase a gate voltage swing
- To improve thermal stability
- To reduce trap density (~1011 eV1cm2 with Al2O3)*
* P. Kordos et al., Appl. Phys. Lett. (2009)
• Why Al oxides?
- Large dielectric constant (8.6~ 10), large bandgap (~9 eV)
- high breakdown field (5 ~ 60 MV/cm)
- thermal & chemical stability**
Ref 1 ) Y. Q. Wu et al., App.. Phys. Lett. 90, 072105 (2007)
12
Al2O3/GaN Energy band line-up
metal Al2O3 GaN
Esposto et al., Appl. Phys. Lett. 99, 133503, 2011
Flat band voltage
Flat band in GaN is not flat-band in oxide
Conduction band offset
ΔEc = 2.12 eV
(matches theory and
other measurements)
Oxide field
Fox = 0.51 MV/cm φb = 3 eV
φs = 0.018 eV
Linear fit: VFB=0.863-0.51x106 tox(cm)
13
Al2O3/GaN interface charges
σfix = σmetal + σsp_GaN
Total fixed charge = + 1.83x1013 cm-2
σfix
σmetal σsp_GaN
metal Al2O3 GaN
Total fixed charges (σfix) induce electrical
field in the dielectric
Increase leakage current
Interface fixed charge is greater than just the
polarization charge!
• Positive charge prevents normally off
FETs by shifting threshold in the negative
direction
14
Remote Ionized Impurity Scattering
• Fixed charges (~ 1013 cm-2) cause remote ionized
impurity scattering
• Polarization charges do not act as scattering centers
• When charges are close to the 2DEG the effect is
more severe
Fixed
charges
GaN
AlGaN
Dielectric S D
G
+++++++++++++++++++++++
d
15
Remote Ionized Impurity Scattering
Remote impurity scattering:
Proportional to fixed
charge density
Increases exponentially as
distance is decreased
Fixed
charges
GaN
AlGaN
Dielectric S D
G
+++++++++++++++++++++++
d
• Fixed charges (~ 1013 cm-2) cause remote ionized
impurity scattering
• Polarization charges do not act as scattering centers
• When charges are close to the 2DEG the effect is
more severe
16
Remote impurity scattering
Interfacial charge scattering reduces electron mobility significantly
Remote impurity scattering becomes dominant as
• 2DEG density < 5x1012 cm-2
• Fixed charge density > 5x1012 cm-2
• Distance is lower than 10 nm
Hung et al., Appl. Phys. Lett. 99, 162104
n2D = 1 x 1012 cm-2
n2D = 5 x 1012 cm-2
n2D = 1 x 1013 cm-2
The regime of the interface charge density we expect
nfix = 4 x 1013 cm-2
17
Interface charge effects on devices
• Interfacial charge scattering reduces electron mobility
significantly
• Interface charge increases reverse gate leakage
• Interface charge prevents normally off operation
Hung et al., Appl. Phys. Lett. 99, 162104
nfix = 4 x 1013 cm-2
It is important to reduce the positive charge density in oxide/III-nitride interfaces
18
Oxygen Plasma Treatment – Recessed MISHEMT
9 nm recesed AlGaN/AlN cap layer
Both oxygen plasma and PMA were applied.
Interface fixed charges were reduced to 8x1012 cm-2 after O2 plasma and PMA.
Mobility rises after PMA, close to theory.
-9 -6 -3 0
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
Cap
acita
nce
(F/
cm2
)
Vg (V)
(nfix= 8x1012
cm-2
)
O2 Plasma
and PMA
O2 Plasma (nfix= 1.6 x1013
cm-2
)
5x1012
1013
0
200
400
600
800
1000
No PMA
2DEG density (cm-2
)M
obili
ty
(cm
2V
-1s-1
)
400C PMA
Theory (nfix
= 8x1012
cm-2
)
(b)
(a)
GaN
AlN
Al0.3Ga0.7N
20 nm Al2O3
9nm
19
- Normally-off MISHEMT
- Vth = +1.5 V (at Vds = 10 uA/mm)
- Saturation Ids >140 mA/mm
- Maximum gm = 40 mS/mm
Oxygen plasma treatment – Normally-off MISHEMT
- Thin AlN left after recess etch
- O2 plasma + PMA treatments
- 20 nm ALD Al2O3
Al0.3Ga0.7N
20 nm Al2O3
S D
G
AlN
native oxide
GaN
0.4 um 2 um
6 um
0.4 um
0 2 4 6
20
40
60
80
100
120
140
I d
(m
A/m
m)
Vd (V)
Vg = 0V ~ 10V
V = +2V
0 2 4 6 8 10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
10-2
10-1
Igs
C
urre
nt d
ensit
y (A
/mm
)
Vg (V)
Ids
-1 0 1 2 3 4 5 6 7 8
0
20
40
60
80
100
120
140
g m (
mS/
mm
)
I d (
mA
/mm
)
Vg (V)
0
10
20
30
40
50
over recessed
Vds
= 7 V
0 1 2 3 40.0
0.1
0.2
0.3
0.4
C
apac
itanc
e (u
F/cm
2)
Vg (V)
V~0.25V
(d)(c)
(b)
(a)
Hung, Ting-Hsiang, et al. Applied Physics
Letters 102.7 (2013): 072105.
20
21
Backend Processing Technologies
Deep Etching of Si Structures
F-based chemistry;
High etch rate (2~3 um/min)
A clean process;
Aspect ratio is temperature
dependent.
Cryo-Process
22
High Aspect Ratio Si trench and Via Etch
Etch rate 2.2mm/min,
100mm etch depth,
20:1 aspect ratio,
90º +/- 0.25º sidewall angle.
Etch Rate 2µm/min
200µm etch depth
40:1 aspect ratio
>75:1 selectivity to photoresist
>200:1 selectivity to oxide
23
Backside SiC Via Etching
SiC via hole etched by ICP-RIE
F- or Cl- Based chemistries
High etch rate
Hard mask required
24
Deep Dry Etching of III-Nitrides
Etch profile obtained in
AlGaN/GaN double heterostructure
layer by ICP-RIE.
Etch profile obtained in
AlGaN/GaN double heterostructure
layer by CAIBE.
25
Summary
Normally-off GaN HEMTs can be designed for
high frequency power switching applications with
several critical issues being taken care.
GaN transistors have great potential for power
electronics but significant developments are still
required.
26
Department of Electrical and Computer Engineering
Center for High Performance Power Electronics
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