Novel Circuit Topologies for Active Distributed Frequency … · 2015-04-25 · The demultiplexer conﬁguration designed and fabri-cated in this article, was originally devised for

Novel Circuit Topologies for Active DistributedFrequency Multiplexers and Demultiplexers

Homayoon Oraizi, Ebrahim Forati

Iran University of Science and Technology, Narmak, Tehran 1684613114, Iran

Received 6 April 2010; accepted 26 July 2010

ABSTRACT: In this work, a novel circuit topology is introduced for the implementation of

multiplexers and demultiplexers, called ‘‘active distributed (de)multiplexers.’’ The desired

characteristics of active distributed (de)multiplexers as being wideband, planar and active

are realized by the proposed microwave circuit. A numerical methodology is presented

for its design. An active distributed detriplexer is designed, simulated, fabricated, and

measured by the proposed numerical procedure. Computer simulation and measurement

results show the effectiveness and suitability of the proposed topology as a detriplexer.

VC 2010 Wiley Periodicals, Inc. Int J RF and Microwave CAE 21:67–76, 2011.

Keywords: demultiplexer; detriplexer; diplexer; distributed amplifier; multiplexer; optimization;

triplexer

INTRODUCTION

Multiplexers (MUX), particularly diplexers and triplexers

are among key devices in microwave circuits. Several pas-

sive circuits are devised for the realization of MUX, such

as circulator coupled MUX, manifold coupled MUX,

directional coupled MUX and hybrid coupled MUX [1–4].

The main required characteristics of MUXs are low vol-

ume, capability of integration, desired in-band and out-of-

band frequency response and in some cases ultra wide-

band performance. It has not been feasible to achieve all

of these characteristics simultaneously and the circuit de-

signer is forced to adopt some trade-offs among them.

In this study, we propose an active multiplexer circuit,

which not only possesses the aforementioned desired char-

acteristics, but also has some other unique features. Spe-

cifically, each port may have a gain greater than unity (in-

dependent of the other ports) and also a wide frequency

bandwidth (above 40%). Furthermore, active distributed

MUX similar to active circuits may be designed as low

noise and/or high power devices.

In [5] an active detriplexer is designed by the use of

distributed amplifiers but the active distributed detriplexer

presented in this article is different in several aspects

from that discussed in [5]. The detriplexer introduced in

[5] is for a special application and is designed by com-

puter simulations. Consequently, the gain of ports may not

be controlled independently and adjusted separately, the

bandwidths of ports may not be specified independently

and the rejectbands of ports may not be controlled sepa-

rately. That is, all the three input ports transmit the input

signal to the output port from DC to the cut-off frequency

limit. However, in this article we propose a comprehen-

sive design procedure for the active distributed MUX.

To keep the design development relatively straightfor-

ward and the presentation of results simple, we introduce

an active distributed detriplexer. The generalization of the

proposed circuit and extension of the design procedure to

MUX and demultiplexers will be provided at the end of

the article. In ‘‘The Distributed Detriplexer’’ section, we

describe the proposed distributed detriplexer. In ‘‘The Op-

timum Design Procedure’’ section, the proposed design

procedure and its related algorithm and computer program

are presented. In ‘‘Design Example of a Detriplexer’’ sec-

tion, the computer simulation results, fabrication and

measurements of a sample detriplexer circuit are presented

and discussed.

THE DISTRIBUTED DETRIPLEXER

The performance of the proposed detriplexer is similar to

distributed amplifiers which are described in several refer-

ences [6–10].

Figure 1 shows the simplified block diagram of the

proposed detriplexer, which consists of three gate and one

drain transmission lines. The input signals to gate lines

are sampled by some sampling and injecting elements and

are injected into the drain line. By the proper design of

Correspondence to: H. Oraizi; e-mail: [email protected]

VC 2010 Wiley Periodicals, Inc.

DOI 10.1002/mmce.20488Published online 29 November 2010 in Wiley Online Library

(wileyonlinelibrary.com).

67

gate and drain lines, the signals injected into the drain

line will travel towards the output efficiently.

The more detailed schematic diagram of the proposed

detriplexer is shown in Figure 2, which is to be necessar-

ily fabricated as a two layer microstrip circuit. The por-

tions of the circuit which are drawn by gray traces are

etched on one layer and the remaining parts are built on

the other layer. The cross section of the two microstrip

layers is shown in Figure 3, where interconnections

between them are made through vias as denoted by V1,

V2, and V3 in Figure 2.

This detriplexer has ‘‘n’’ blocks, which is usually equal

to 2 or 3. Its circuit operation is similar to the distributed

amplifier, except that it has three gate lines as shown in

Figure 2, instead of one gate line. The main requirement

for its correct operation is that the phase velocity of

waves on the gate and drain lines be equal. At the point

where a transistor gate is connected to the gate line, its

gate capacitance (Cgs) is injected into the gate line. Con-

sequently, to make the phase velocities equal on all the

three gate lines, some stubs are added to the other two

gate lines at the corresponding points of connection of the

transistor’s gate to the gate line. For example, in Figure 3

stubs S1 and S2 are added to the circuit because of the

connection of the transistor’s gate to the V1 point. The

input impedance of the stub is adjusted to be equal to that

of the transistor Cgs. Similarly, at the point of connection

of transistor drain to the drain line, the drain capacitor Cds

is injected into the drain line. Therefore, to make all the

phase velocities equal on the three gate lines and drain

line, a stub is connected to the drain of the transistor. The

input impedance of this stub is adjusted to be equal to

that of the difference between Cgs and Cds of the transis-

tor, since in general Cds < Cgs.

In common design methods for MUX, common filters

are used to realize the required passband and rejectband

characteristics in the desired signal paths. Although the

passive filters have the advantages of the simple design

procedure and easy fabrication process, but they have the

disadvantage of dependency between scattering parameters

of S11 and S21 and cannot produce sharp skirt in the tran-

sition between passband and rejectband.

The active distributed detriplexer proposed in this arti-

cle, makes S11 and S21 independent of each other. This is

a unique advantage for several applications. For example,

in a passive diplexer designed for two consecutive fre-

quency bands, the value of S21 is almost �3dB at the

boundary between two bands, but for the active MUX pre-

sented in this article, the value of S21 may be equal to or

greater than 0 dB at a single frequency for several signal

paths.

Active distributed MUX are suitable for wideband

applications, since their designs are based on distributed

amplifiers, which are inherently wideband.

The proposed circuit topology of detriplexer has sev-

eral advantages, which are among others as follows:

1. It provides a wide range of design possibilities. Differ-

ent frequency ranges may be specified for different

inputs, which may even overlap. If the frequency bands

are identical, the device forms a combiner.

2. Since the detriplexer is an active device, the gain of

each path may be designed to be greater than one. The

Figure 1 Block diagram of the proposed active detriplexer.

[Color figure can be viewed in the online issue, which is avail-

able at wileyonlinelibrary.com.]

Figure 2 Active distributed detriplexer.

Figure 3 Layers of active distributed detriplexer.

68 Oraizi and Forati

International Journal of RF and Microwave Computer-Aided Engineering/Vol. 21, No. 1, January 2011

unique property of the proposed topology is that the

gain of each input–output path may be specified

independently.

3. Although the proposed topology is presented as a detri-

plexer, it may be readily converted to MUX or DEMUX

Since the proposed detriplexer is small in size, it may

be integrated in MMIC. It may be designed as a low noise

and/or high power device compared with the common

detriplexers.

One of the shortcomings of distributed amplifiers is

their high noise figure, which is carried over to the active

distributed demultiplexers. Several methods are available

for the design of low noise distributed amplifiers, which

may be equally carried out for the distributed demulti-

plexers. Evidently, with lower number of cascaded blocks

and series transistors, the noise figure of demultiplexer

will decrease.

THE OPTIMUM DESIGN PROCEDURE

The design objectives of the detriplexer are the determina-

tion of widths and lengths of its various transmission

lines. A numerical procedure is developed here for its

design and optimization, because the number of variables

is too numerous to make the derivation of closed form

formulas feasible. Consider the circuit diagram of the pro-

posed active distributed detriplexer, composed of 10 sec-

tions, as shown in Figure 4. We would like to obtain the

S-parameters of the whole eight-port network in Figure 4.

Initially the S-parameters of each section are obtained

(see Appendix A). Then the S matrix of the whole eight-

port network is determined.

½b� ¼ S½ �½a� (1)

where

½a� ¼ ½ a1 a2 a3 a4 a5 a6 a7 a8 � (2)

½b� ¼ ½ b1 b2 b3 b4 b5 b6 b7 b8 � (3)

and an, bn are the incident and reflected wave amplitudes,

respectively [11]. To obtain the S-parameters of the eight-

port detriplexer from the S-parameters of 10 sections, ma-

trix [P] is needed to be defined similar to the ABCD

wave transmission matrix as

½c� ¼ P½ �½d� (4)

where

½c� ¼ ½ a1 b1 a2 b2 a3 b3 a4 b4 � (5)

½d� ¼ ½ b5 a5 b6 a6 b7 a7 b8 a8 � (6)

Therefore, the overall [P] matrix of the circuit is equal

to the product of those of each section, namely

½P� ¼Y10i¼1

½P�i (7)

The relationships among S-parameters and P-parame-

ters are given in Appendix B. Note that the computation

of S-matrix of two adjacent sections should assume identi-

cal impedances (or equivalently normalized S-parameters

and normalized wave amplitudes). Consequently, the S-pa-

rameters of the detriplexer will be obtained as a function

of the widths and lengths of line sections and termination

impedances.

Now we construct an error function as

err ¼ W1e1 þW2e2 þW3e3 þW4e11 þW5e22 þW6e33 (8)

where

exx ¼XNn¼1

½S0xxðnÞ�2 ; x ¼ 1; 2; 3; 4 (9)

Figure 4 Sections of an active distributed detriplexer.

Active Distributed Multiplexers 69

International Journal of RF and Microwave Computer-Aided Engineering DOI 10.1002/mmce

e1 ¼XNn¼1

½S41ðnÞ � S41gdB�2 (10)

e2 ¼XNn¼1

½S42ðnÞ � S42gdB�2 (11)

e3 ¼XNn¼1

½S43ðnÞ � S43gdB�2 (12)

and S41g, S42g, and S43g are the specified design goals, and

S41(n), S42(n), S43(n) are the scattering parameters of detri-

plexer as obtained in ‘‘The Distributed Detriplexer’’ sec-

tion and

S0xxðnÞ ¼SxxðnÞ þ 10 dB

0

if

if

�SxxðnÞ � �10 dB

SxxðnÞ � �10 dB

x ¼ 1; 2; 3; 4

(13)

and W1, W2,… are weighting functions. The frequency

bandwidth is divided into N discrete frequencies, where

each frequency is denoted by ‘‘n’’.

The demultiplexer configuration designed and fabri-

cated in this article, was originally devised for the realiza-

tion of an active antenna [12]. Every input port of the det-

riplexer is connected to an antenna, which is designed for

a specified frequency band. Consequently, the bandwidths

of the three receive antennas are combined. As a result,

the isolation among the ports and their rejectband

responses are not crucial for us. These parameters were

not included in the expression of the error function. How-

ever, for a common detriplexer, the above considerations

should also be included in the error function for the ensu-

ing optimization.

We use the hybrid method of genetic algorithm (GA)

and conjugate gradient method (CG) for the minimization

of error function. This method of optimization may be

implemented by a toolbox in MATLAB software package.

Besides, the initial values of variables can be generated

by its toolbox automatically.

DESIGN EXAMPLE OF A DETRIPLEXER

Consider the block diagram of a detriplexer as shown in

Figure 5. The design goals are specified as follows:

4 � f ðGHzÞ � 5:5 ) S11 � �10 dB; S41g ¼ 4 dB (14)

6 � f ðGHzÞ � 8 ) S22 � �10 dB; S42g ¼ 3 dB (15)

8:5 � f ðGHzÞ�11 ) S33� �10 dB; S43g ¼ 4 dB (16)

The frequency ranges and related gains are intention-

ally selected unequal, to demonstrate the flexibility of the

proposed circuit topology and design procedure for the tri-

plexer. We select a two block distributed detriplexer,

where ports 1,4,6,8 are terminated by 50 X impedances.

For the practical design configuration we have to add

three more stubs to Figure 4 to achieve the design

Figure 6 Designed active distributed detriplexer.

Figure 5 Desired detriplexer goals.



specifications, as shown in Figure 6. This is required,

because contrary to our original assumption, the gate and

drain lines for different transistors are not identical for

different input frequency ranges.

Consequently, due to the different loading the gate of

each transistor, a microstrip stub is added to gate of each

transistor as shown in Figure 6. Observe that in Figure 6

there are 68 transmission lines of which the lengths and

widths should be determined.

Altogether there are 136 unknown. Note that the gray

traces in Figure 6 should be etched on one layer and the

other traces on another layer as illustrated in Figure 3.

We have selected transistor type NE4210S01 with the

following bias conditions

Ids ¼ 10 mA; Vds ¼ 2 Volt

and Rogers RTduroid 5880 as the substrate for transmis-

sion lines with the following specifications:

er ¼ 2:2; h ¼ 31 mil

The optimum design values for widths and lengths of

line sections and for resistors (a total of 140 parameters)

are given in Table I. Note that some line sections should

be omitted, because their lengths have become zero.

The noise figure of the detriplexer designed in this arti-

cle was simulated by ADS software, which is drawn in

Figure 7.

Figure 7a shows the noise figure of input 1 to output

(nf(1)) which is below 6 dB in its frequency band (4–5.5

GHz). To simulate nf(1), the inputs 2 and 3 are loaded by

noiseless 50 X resistors. The reason for this high noise

figure in the outband frequency range is that the outband

signal gain is very low which causes low signal to noise

ratio leading to high noise figures. Figures 7b and 7c

show the noise figures of channels 2 and 3 which are

below 6 and 5 dB in their frequency bands, respectively.

Note that the noise figures are relatively high and it is

not suitable for low noise applications. Consequently, if it

is desired to use the detriplexer in the front end of the re-

ceiver, the low noise conditions should be added to the

error function for further design optimization.

The performance of the designed detriplexer is

obtained by computer simulation using the ADS software

package. The designed detriplexer is fabricated and its

performance is measured. Photographs of the two sides of

fabricated microstrip detriplexer on the RTduroid 5880

substrate are shown in Figure 8.

The computer simulation results and measurement data

are drawn in Figure 9 for the frequency response of S11,S22, S33, S41, S42, S43. The agreement between the two sets

of data are quite good. Any discrepancy between the two

sets of data are due to the simplifying assumption in the

numerical design procedure and our limited fabrication

technology. The discrepancy between the computer simu-

lation results and measurement data is more evident at

higher frequencies, which is due to the limited fabrication

technology available to us. For example, we intended to

use conical inductors, but we were forced to use common

SMD inductors, which have poor performance at high

frequencies.

Note that the results of computer simulations and

measured data show that the detriplexers responses in the

TABLE I Optimized Transmission Line Dimensions In Millimeter and Also Resistors in Ohms

T.L. No. W (mm) L (mm) T.L. no. W (mm) L (mm) T.L. No. W (mm) L (mm)

1 0.1 15 25 – 0 49 1 20.5

2 10 2 26 4 1.9 50 1 19.9

3 – 0 27 – 0 51 0.08 20

4 4.8 16.4 28 – 0 52 3.1 2.7

5 – 0 29 – 0 53 0.1 10.2

6 0.45 1.9 30 4 4.7 54 4 9

7 – 0 31 3 11.8 55 0.3 19.2

8 2.3 2.8 32 2.7 11.2 56 2.3 17.9

9 1.8 19.8 33 3.7 3.5 Td1 1.8 20

10 1.1 3.5 34 1.2 2 Td2 1 20

11 0.1 15.5 35 0.18 4.1 Td3 1.6 20

12 1 1.5 36 0.46 1.3 Td4 0.2 7.2

13 3.4 5.4 37 4 1.4 Td5 0.1 20

14 0.65 1.6 38 5 15 Td6 0.1 20

15 8.7 3 39 0.7 3.8 Tg1 0.6 18.4

16 4.5 22.7 40 5.2 9.7 Tg2 0.5 18

17 4 5.2 41 0.7 0.8 Tg3 0.35 1

18 6.8 8.6 42 0.08 2 Tg4 1.2 18.3

19 – 0 43 2.9 4.3 Tg5 0.7 16

20 0.08 5.8 44 2.4 9.3 Tg6 1.1 20

21 0.5 4.2 45 0.3 20 R1 20 X22 0.1 17.5 46 1 13.7 R2 82 X23 0.6 19.7 47 0.08 18.7 R3 27 X24 2.8 0.7 48 0.7 22 R4 100 X



rejectband are not satisfactory because the isolations

among the input ports of the detriplexer are not important

for our network design, and consequently have not been

included in our optimization design procedure by the error

function formulation.

Overall, the following results are obtained from the

fabricated detriplexer:

4:1 � f ðGHzÞ � 5:6 ) S11 � �10 dB; S41 ¼ 461 dB

(17)

Figure 7 Simulated noise figure of designed detriplexer (a) noise figure of channel 1 (b) noise figure of channel 2 (c) noise figure of

channel 3. [Color figure can be viewed in the online issue, which is available at wileyonlinelibrary.com.]

Figure 8 Fabricated detriplexer (a) front view (b) back view.



6:2 � f ðGHzÞ � 7:5 ) S22 � �10 dB; S42 ¼ 2:561 dB

(18)

8:2 � f ðGHzÞ � 9:5 ) S33 � �10 dB;S43 ¼ 2:560:5 dB

(19)

The isolations among the input ports were not impor-

tant for the present application. Therefore, the mentioned

isolations are not inserted into the error function. The

measured isolations of detriplexer are shown in Figure 10.

The extension of design procedure from the detriplexer

to demultiplexer is quite evident. The number of transis-

tors in each block is equal to the number of inputs of the

demultiplexer and is equal to the number of gate lines.

The order of matrices in the numerical procedure should

change from 8 � 8 to (2n þ 2) � (2n þ 2), where n is

the number of inputs of the demultiplexer.

To convert the demultiplexer to multiplexer, it is

merely necessary to interchange the drains and gates in

the circuit diagram. The input and output ports need to be

interchanged too. In the numerical procedure, only the

matrices S2, S5, S8, in Appendix A change. The error

function definition must change too. One of the important

parameters in multiplexer design is Isolation between out-

put ports which should be inserted to the error function

necessarily.

CONCLUSION

A new class of (de)multiplexers called ‘‘distributed active

(de)multiplexers’’ is introduced. A numerical procedure

has been developed for its design. A sample of wideband

distributed active detriplexer has been designed, fabricated

and measured. Measurement results confirm the suitability

Figure 9 Measured and simulated S parameters of the detriplexer: (a) S11 (b) S41 (c) S22 (d) S42 (e) S33 (f) S43. [Color figure can be

viewed in the online issue, which is available at wileyonlinelibrary.com.]



and effectiveness of the proposed topology. We have

tested several optimization methods to minimize the error

function and have found that the hybrid method of GA

and CG is the most effective method for our error func-

tion. The designed detriplexer in this article is a wideband

detriplexer, but it is possible to design its low-noise and/

or high-power versions. However, the determination of the

optimum number of blocks in the circuit of the proposed

(de)multiplexer may be the subject of further research.

APPENDIX A

Calculation of the S-Parameters of a Block of DetriplexerFirst, we determine the generalized S-parameters of the

two-port networks shown in Figure A1, where Z1 and Z2are the impedances of ports 1 and 2, respectively. Show

the S-parameters of Figures 11a and 11b as Ssn and Spn,respectively, then [13, 14]

½S�sn¼ Ssn11 Ssn12Ssn21 Ssn22

� �(A1)

Ssn11 ¼ZnZ2 þ jZ2

n tanðhnÞ � ZnZ�1 � jZ2Z

�1 tanðhnÞ

ZnZ2 þ jZ2n tanðhnÞ þ ZnZ1 þ jZ1Z2 tanðhnÞ (A2)

Ssn21 ¼ 2

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiReðZ1Þ

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiReðZ2Þ

p � 2ejhnZ2ðZnZ2 þ jZ2n tanðhnÞÞ

½Z2 � Zn þ e2jhnðZ2 þ ZnÞ� � Y;

Y¼½ZnZ1þjZ1Z2 tanðhnÞþZnZ2þjZ2n tanðhnÞ� ðA3Þ

where ‘‘n’’ denotes the number of transmission line in

Figure 4.

yn is the electrical length of the line and Zn is its char-

acteristic impedance.

S22 is equal to S11, but Z1 and Z2 are interchanged. S12is equal to S21, but Z1 and Z2 are interchanged.

Zp in Figure A1b is the impedance of an open circuit

stub.

Zp ¼ �jZncotðblÞ (A4)

½S�pn¼ Spn11 Spn12Spn21 Spn22

� �(A5)

Spn21 ¼ 2

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiReðZ1Þ

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiReðZ2Þ

p ZnZ2ZnZ1 þ jZ1Z2 tanðhnÞ þ ZnZ2

(A6)

Spn11 ¼ZnZ2 � ZnZ

�1 � jZ2Z

�1 tanðhnÞ

ZnZ2 þ ZnZ1 þ jZ1Z2 tanðhnÞ (A7)

S22 is equal to S11, but Z1 and Z2 are interchanged. S12is equal to S21, but Z1 and Z2 are interchanged [13, 14].

Now we write the scattering matrices [S]n of sections

n ¼ 1,2,…,10 in Figure 4.

Sections 1, 4, 7, 10. The following S-matrices are

obtained by [S]sn

½S�1 ¼½S�S12�2 0½ �2�2 0½ �2�2 0½ �2�2

0½ �2�2 ½S�S22�2 0½ �2�2 0½ �2�2

0½ �2�2 0½ �2�2 ½S�S32�2 0½ �2�2

0½ �2�2 0½ �2�2 0½ �2�2 ½S�S42�2

26664

37775 (A8)

½S�4 ¼½S�S122�2 0½ �2�2 0½ �2�2 0½ �2�2

0½ �2�2 ½S�S142�2 0½ �2�2 0½ �2�2

0½ �2�2 0½ �2�2 ½S�S162�2 0½ �2�2

0½ �2�2 0½ �2�2 0½ �2�2 ½S�S182�2

26664

37775 (A9)

Figure 10 Measured isolations between input ports (a) S12,

S13, S14 (b) S21, S23, S24 (c) S31, S32, S34. [Color figure can

be viewed in the online issue, which is available at

wileyonlinelibrary.com.]

Figure A1 (a) Series transmission line and (b) parallel open

circuit stub.



½S�7 ¼½S�S132�2 0½ �2�2 0½ �2�2 0½ �2�2

0½ �2�2 ½S�S152�2 0½ �2�2 0½ �2�2

0½ �2�2 0½ �2�2 ½S�S172�2 0½ �2�2

0½ �2�2 0½ �2�2 0½ �2�2 ½S�S192�2

26664

37775 (A10)

½S�10 ¼½S�S52�2 0½ �2�2 0½ �2�2 0½ �2�2

0½ �2�2 ½S�S62�2 0½ �2�2 0½ �2�2

0½ �2�2 0½ �2�2 ½S�S72�2 0½ �2�2

0½ �2�2 0½ �2�2 0½ �2�2 ½S�S82�2

26664

37775 (A11)

Sections 3, 6, 9. The following S-matrices are obtained

by [S]pn

½S�3 ¼

½S�p92�2 0½ �2�2 0½ �2�2 0½ �2�2

0½ �2�2 ½I0�2�2 0½ �2�2 0½ �2�2

0½ �2�2 0½ �2�2 ½S�p222�2 0½ �2�2

0½ �2�2 0½ �2�2 0½ �2�2 ½S�p242�2

266664

377775

½I0� ¼ 0 1

1 0

� �(A12)

½S�6 ¼½S�p102�2 0½ �2�2 0½ �2�2 0½ �2�2

0½ �2�2 ½S�p202�2 0½ �2�2 0½ �2�2

0½ �2�2 0½ �2�2 ½I0�2�2 0½ �2�2

0½ �2�2 0½ �2�2 0½ �2�2 ½S�p252�2

2664

3775 (A13)

½S�9 ¼½S�p112�2 0½ �2�2 0½ �2�2 0½ �2�2

0½ �2�2 ½S�p212�2 0½ �2�2 0½ �2�2

0½ �2�2 0½ �2�2 ½S�p232�2 0½ �2�2

0½ �2�2 0½ �2�2 0½ �2�2 ½I0�2�2

2664

3775 (A14)

Sections 2, 5, 8. We obtain S-parameters of transistor

from data sheets and combine them with those of the

transmission lines connected to its gate and drain, and

denote it by [S]t

½S�t¼ St11 St12St21 St22

� �(A15)

Then we determine the S-matrices of sections 2, 5, 8

½S�2 ¼

A B C CB A C CD D E FD D F E

0 0 0 0

0 0 0 0

0 0 0 0

0 0 0 00 0 0 0

0 0 0 0

0 0 0 0

0 0 0 0

0 1 0 0

1 0 0 0

0 0 0 1

0 0 1 0

266666666664

377777777775

(A16)

½S�5 ¼

A B 0 0

B A 0 0

0 0 0 1

0 0 1 0

C C 0 0

C C 0 0

0 0 0 0

0 0 0 0D D 0 0

D D 0 0

0 0 0 0

0 0 0 0

E F 0 0

F E 0 0

0 0 0 1

0 0 1 0

266666666664

377777777775

(A17)

½S�8 ¼

A B 0 0

B A 0 0

0 0 0 1

0 0 1 0

0 0 0 0

0 0 0 0

0 0 0 0

0 0 0 00 0 0 0

0 0 0 0

D D 0 0

D D 0 0

0 1 0 0

1 0 0 0

0 0 E F0 0 F E

266666666664

377777777775

(A18)

where

R ¼ St11St22 þ 3St11 þ 3St22 þ 9� St12S

t21 (A19)

A ¼ St11St22 � St11 þ 3St22 � 3� St12S

t21

R(A20)

B ¼ 2St11S

t22 þ St11 þ 3St22 þ 3� St12S

t21

R(A21)

C ¼ 4St21R

; D ¼ 4St12R

(A22)

E ¼ St11St22 þ 3St11 � St22 � 3� St12S

t21

R(A23)

F ¼ 2St11S

t22 þ 3St11 þ St22 þ 3� St12S

t21

R(A24)

APPENDIX B

Conversions Between Matrices S and PEquations (B1) and (B2) shows the conversions between

S and P matrices as follows:

½P� ¼

�S11 1 �S13 0 �S15 0 �S17 0

�S21 0 �S23 0 �S25 0 �S27 0

�S31 0 �S33 1 �S35 0 �S37 0

�S41 0 �S43 0 �S45 0 �S47 0

�S51 0 �S53 0 �S55 1 �S57 0

�S61 0 �S63 0 �S65 0 �S67 0

�S71 0 �S73 0 �S75 0 �S77 1

�S81 0 �S83 0 �S85 0 �S87 0

266666666666664

377777777777775

�1

�

0 S12 0 S14 0 S16 0 S18

�1 S22 0 S24 0 S26 0 S28

0 S32 0 S34 0 S36 0 S38

0 S42 �1 S44 0 S46 0 S48

0 S52 0 S54 0 S56 0 S58

0 S62 0 S64 �1 S66 0 S68

0 S72 0 S74 0 S76 0 S78

0 S82 0 S84 0 S86 �1 S88

266666666666664

377777777777775

(B1)



½S� ¼

0 �P11 0 �P13

1 �P21 0 �P23

0 �P31 0 �P33

0 �P41 1 �P43

0 �P15 0 �P17

0 �P25 0 �P27

0 �P35 0 �P37

0 �P45 0 �P47

0 �P51 0 �P53

0 �P61 0 �P63

0 �P71 0 �P73

0 �P81 0 �P83

0 �P55 0 �P57

1 �P65 0 �P67

0 �P75 0 �P77

0 �P85 1 �P87

266666666666664

377777777777775

�1

�

�1 P12 0 P14

0 P22 0 P24

0 P32 �1 P34

0 P42 0 P44

0 P16 0 P18

0 P26 0 P28

0 P36 0 P38

0 P46 0 P48

0 P52 0 P54

0 P62 0 P64

0 P72 0 P74

0 P82 0 P84

�1 P56 0 P58

0 P66 0 P68

0 P76 �1 P78

0 P86 0 P88

266666666666664

377777777777775

(B2)

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BIOGRAPHIES

Homayoon Oraizi received the

B.E.E. degree from American Uni-

versity of Beirut, Lebanon, in 1967,

M.Sc. and Ph.D. degrees in electrical

engineering from Syracuse Univer-

sity, Syracuse, NY, in 1969 and

1973, respectively. From 1973 to

1974, he was at Tousi University of

Technology, Tehran, Iran. From 1974 to 1985, he was

with the Communications Division, Iran Electronics

Industries, Shiraz, Iran. In 1985, he joined the Department

of Electrical Engineering, Iran University of Science and

Technology, Tehran, Iran, where he is a Full Professor of

electromagnetic engineering. He has authored and trans-

lated several textbooks in Farsi. He has authored or coau-

thored over 170 papers in International Journals and Con-

ferences. In 2006, he was elected an exemplary nation

wide university professor in Iran. He is an Invited Profes-

sor of the Electrical Engineering Group, Academy of Sci-

ences of Iran, and is listed as an elite engineer by the Ira-

nology Foundation. Dr. Oraizi is a Fellow of

Electromagnetic Academy and Japan Society for the Pro-

motion of Science.

Ebrahim Forati was born in Iran in

1983. He received the B.Sc. and

M.Sc degrees from Iran University of

Science and Technology (IUST),

Tehran, Iran, in 2006 and 2009,

respectively. He is currently continu-

ing his education towards his Ph.D.

degree at the University of Wiscon-

sin Milwaukee (UWM). He was a research assistant at

Electromagnetic Engineering Research Laboratory (EERL)

at IUST. His current areas of research interests include

microstrip antennas, high frequency active circuits, and

active antennas.



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Novel Circuit Topologies for Active Distributed Frequency … · 2015-04-25 · The demultiplexer conﬁguration designed and fabri-cated in this article, was originally devised for