NRTL US BCMTM Bus Converter - vicorpower.comv c1 1 µf in pc tm-out +out-in +in bcm pr pc vc tm il os sg prm cd +out-in +in pc tm vtm-out +out-in +in l o a d typical application bcm

Rev. 1.62/2010

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V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200

vicorpower.com

VIB0003TFJ PRELIMINARY DATASHEET

FEATURES

• 352 Vdc – 44 Vdc 325 W Bus Converter

• High efficiency (>95%) reduces system power consumption

• High power density (>1000 W/in3)

reduces power system footprint by >40%

• “Full Chip” V•I Chip package enables surface mount,low impedance interconnect to system board

• Contains built-in protection features: undervoltage, overvoltage lockout, overcurrent protection, short circuit protection, overtemperature protection.

• Provides enable/disable control, internal temperature monitoring

• ZVS/ZCS Resonant Sine Amplitude Converter topology

• Can be paralleled to create multi-kW arrays

TYPICAL APPLICATIONS

• High End Computing Systems

• Automated Test Equipment

• Telecom Base Stations

• High Density Power Supplies

• Communications Systems

DESCRIPTION

The V•I ChipTM bus converter is a high efficiency (>95%) SineAmplitude ConverterTM (SACTM) operating from a 330 to 365Vdc primary bus to deliver an isolated 41.25 – 45.63 V nominal, unregulated secondary. The SAC offers a low AC impedancebeyond the bandwidth of most downstream regulators, mean-ing that input capacitance normally located at the input of aregulator can be located at the input to the SAC. Since the Kfactor of the VIB0003TFJ is 1/8, that capacitance value can bereduced by a factor of 64x, resulting in savings of board area,materials and total system cost.

The VIB0003TFJ is provided in a V•I Chip package compatiblewith standard pick-and-place and surface mount assemblyprocesses. The V•I Chip package provides flexible thermal management through its low junction-to-case and junction-to-board thermal resistance. With high conversion efficiency theVIB0003TFJ increases overall system efficiency and lowers operating costs compared to conventional approaches.

SW1

enable / disableswitch

F1

V C1 1 µFIN

PCTM

-Out

+Out

-In

+In

BCM

PR

PC

VC

TMIL

OSSG

PRM

CD

-Out

+Out

-In

+In

VC

PCTM

VTM

-Out

+Out

-In

+In

LOAD

TYPICAL APPLICATION

BCMTM

Bus Converter

VIN = 330 – 365 V

VOUT = 41.25 – 45.63 V (NO LOAD)

POUT = 325 W(NOM)

K = 1/8

S

NRTLC US

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PRELIMINARY DATASHEET

ABSOLUTE MAXIMUM RATINGS

+IN to –IN . . . . . . . . . . . . . . . . . . . . . . . . -1.0 Vdc – +400 Vdc

PC to –IN . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 Vdc – +20 Vdc

TM to –IN . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 Vdc – +7 Vdc

+IN/-IN to +OUT/-OUT . . . . . . . . . . . . . . . . . . . 4242 V (Hi Pot)

+IN/-IN to +OUT/-OUT . . . . . . . . . . . . . . . . . . . 500 V (working)

+OUT to –OUT . . . . . . . . . . . . . . . . . . . . . . -1.0 Vdc - +60 Vdc

Temperature during reflow . . . . . . . . . . . . . . . . 245°C (MSL 6)

PACKAGE ORDERING INFORMATION

PART NUMBER DESCRIPTIONVIB0003TFJ -40°C – 125°C TJ, J lead

CONTROL PIN SPECIFICATIONS

See section 5.0 for further application details and guidelines.

PC (V•I Chip BCM Primary Control)

The PC pin can enable and disable the BCM. When held belowVPC_DIS the BCM shall be disabled. When allowed to float withan impedance to –IN of greater than 50 kΩ the module willstart. When connected to another BCM PC pin, the BCMs willstart simultaneously when enabled. The PC pin is capable ofbeing driven high by an either external logic signal or internalpull up to 5 V (operating).

TM (V•I Chip BCM Temperature Monitor)

The TM pin monitors the internal temperature of the BCMwithin an accuracy of +5/-5°C. It has a room temperature setpoint of ~3.0 V and an approximate gain of 10 mV/°C. Itcan source up to 100 µA and may also be used as a “PowerGood” flag to verify that the BCM is operating.

-In

PC

RSV

TM

+In

-Out

+Out

-Out

+Out

Bottom View

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

4 3 2 1

A

B

C

D

E

H

J

K

L

M

N

P

R

T

Signal Name Designation

+In A1-E1, A2-E2–In L1-T1, L2-T2TM H1, H2RSV J1, J2PC K1, K2

+OutA3-D3, A4-D4,J3-M3, J4-M4

–OutE3-H3, E4-H4,N3-T3, N4-T4

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ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT

Voltage range VIN 330 352 365 VdcdV/dt dVIN /dt 1 V/µsQuiescent power PQ PC connected to -IN 395 410 mW

No load power dissipation PNLVIN = 352 V 6.5 9.5

WVIN = 330 to 365 V 12

Inrush Current Peak IINR_PVIN = 365 V COUT = 100 µF, 2 4.5 APOUT = 325 W

DC Input Current IIN_DC POUT = 325 W 1 A

K Factor ( VOUT ) K 1/8VIN

Output Power (Average) POUTVIN = 352 VDC; See Figure 14 325

WVIN = 330 – 365 VDC; See Figure 14 305

Output Power (Peak) POUT_PVIN = 352 VDC 495 WAverage POUT < = 325 W, Tpeak < 5 ms

Output Voltage VOUT Section 3.0 No load 41.25 45.63 VOutput Current (Average) IOUT Pout < = 325 W 7.7 A

Efficiency (Ambient) η VIN = 352 V, POUT = 325 W 94.4 95.7 %VIN = 330 V to 365 V, POUT = 325 W 94.4

Efficiency (Hot) η VIN = 352 V, TJ = 100° C,POUT = 325 W 94.3 95.3 %Minimum Efficiency η 60 W < POUT < 325 W Max 90 %(Over Load Range)Output Resistance (Ambient) ROUT TJ = 25° C 100 140 180 mΩOutput Resistance (Hot) ROUT TJ = 125° C 150 190 230 mΩOutput Resistance (Cold) ROUT TJ = -40° C 60 115 180 mΩLoad Capacitance COUT 100 uFSwitching Frequency FSW 1.56 1.65 1.73 MHzRipple Frequency FSW_RP 3.12 3.3 3.46 MHz

Output Voltage Ripple VOUT_PPCOUT = 0 µF, POUT = 325 W, VIN = 352 V, 192 400 mV Section 8.0

VIN to VOUT (Application of VIN) TON1 VIN = 352 V, CPC = 0; See Figure 16 460 540 620 ms

PCPC Voltage (Operating) VPC 4.7 5 5.3 VPC Voltage (Enable) VPC_EN 2 2.5 3 VPC Voltage (Disable) VPC_DIS <2 VPC Source Current (Startup) IPC_EN 50 100 300 uAPC Source Current (Operating) IPC_OP 2 3.5 5 mAPC Internal Resistance RPC_SNK Internal pull down resistor 50 150 400 kΩPC Capacitance (Internal) CPC_INT Section 5.0 1000 pFPC Capacitance (External) CPC_EXT External capacitance delays PC enable time 1000 pFExternal PC Resistance RPC Connected to –VIN 50 kΩPC External Toggle Rate FPC_TOG 1 Hz

PC to VOUT with PC Released Ton2 VIN = 352 V, Pre-applied 50 100 150 µsCPC = 0, COUT = 0; See Figure 16

PC to VOUT, Disable PC TPC_DISVIN = 352 V, Pre-applied 4 10 µsCPC = 0, COUT = 0; See Figure 16

1.0 ELECTRICAL CHARACTERISTICS

Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over thetemperature range of -40°C < TJ < 125°C (T-Grade); All other specifications are at TJ = 25ºC unless otherwise noted

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1.0 ELECTRICAL CHARACTERISTICS (CONT.)

Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over thetemperature range of -40°C < TJ < 125°C (T-Grade); All other specifications are at TJ = 25ºC unless otherwise noted


TMTM accuracy ACTM -5 +5 ºCTM Gain ATM 10 mV/°CTM Source Current ITM 100 uATM Internal Resistance RTM_SNK 25 40 50 kΩExternal TM Capacitance CTM 50 pFTM Voltage Ripple VTM_PP CTM = 0µF, VIN = 365 V, POUT = 325 W 200 400 500 mV

PROTECTIONNegative going OVLO VIN_OVLO- 365 380 390 VPositive going OVLO VIN_OVLO+ 380 385 400 VNegative going UVLO VIN_UVLO- 270 285 304 VPositive going UVLO VIN_UVLO+ 285 300 325 VOutput Overcurrent Trip IOCP VIN = 352 V, 25°C 10 12 15 AShort Circuit Protection ISCP 15 ATrip CurrentShort Circuit Protection TSCP 1.2 usResponse TimeThermal Shutdown TJ_OTP 125 130 135 °CJunction setpoint

GENERAL SPECIFICATIONIsolation Voltage (Hi-Pot) VHIPOT 4242 VWorking Voltage (IN – OUT) VWORKING 500 VIsolation Capacitance CIN_OUT Unpowered unit 500 660 800 pFIsolation Resistance RIN_OUT 10 MΩMTBF MIL HDBK 217F, 25° C, GB 4.2 Mhrs

cTUVus

Agency Approvals/Standards CE MarkROHS 6 of 6

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1.1 APPLICATION CHARACTERISTICS

All specifications are at TJ = 25ºC unless otherwise noted. See associated figures for general trend data.

ATTRIBUTE SYMBOL CONDITIONS / NOTES TYP UNIT

No Load Power PNL VIN = 352 V, PC enabled; See Figure 1 6.5 WInrush Current Peak INR_P COUT = 100 µF, POUT = 325 W 2 AEfficiency (Ambient) η VIN = 352 V, POUT = 325 W 95.7 %Efficiency (Hot – 100°C) η VIN = 352 V, POUT = 325 W 95.3 %Output Resistance (-40°C) ROUT VIN = 352 V 115 mΩOutput Resistance (25°C) ROUT VIN = 352 V 140 mΩOutput Resistance (100°C) ROUT VIN = 352 V 190 mΩOutput Voltage Ripple VOUT_PP

COUT = 0 uF, POUT = 325 W @ VIN = 352, 192 mVVIN = 352 V

VOUT Transient (Positive) VOUT_TRAN+IOUT_STEP = 0 TO 7.7 A,

3.2 mVISLEW >10 A/us; See Figure 11

VOUT Transient (Negative) VOUT_TRAN-IOUT_STEP = 7.7 A to 0 A,

2.8 mVISLEW > 10 A/us; See Figure 12Undervoltage Lockout TUVLO 150 µsResponse Time ConstantOutput Overcurrent TOCP 10 < IOCP < 15 A 7.5 msResponse Time ConstantOvervoltage Lockout TOVLO 120 µsResponse Time ConstantTM Voltage (Ambient) VTM_AMB TJ ≅ 27°C 3 V

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No Load Power Dissipation vs Line

0

2

4

6

8

10

12

325 330 335 340 345 350 355 360 365 370

Input Voltage (V)

No

Lo

ad P

ow

er D

issi

pat

ion

(W

)

-40°C 25°C 100°CT :CASE

94

94.5

95

95.5

96

96.5

97

-60 -40 -20 0 20 40 60 80 100 120

Case Temperature (C)

Eff

icie

ncy

(%

)

Full Load Efficiency vs. Case Temperature

360 V 352 V 365 VV :IN

Efficiency & Power Dissipation -40°C Case

60

65

70

75

80

85

90

95

0 1 2 3 4 5 6 7 8 9

Output Load (A)

Eff

icie

ncy (

%)

8

10

12

14

16

18

20

22

Po

wer

Dis

sip

ati

on

(W

)

330 V 352 V 365 VV :IN 330 V 352 V 365 V

η

PD

80

82

84

86

88

90

92

94

96

98

0 1 2 3 4 5 6 7 8 9

5

7

9

11

13

15

17

Efficiency & Power Dissipation 25°C Case

Output Current (A)

Eff

icie

ncy

(%

)

Po

wer

Dis

sip

atio

n (

W)

330 V 352 V 365 VV :IN 330 V 352 V 365 V

η

PD

80

82

84

86

88

90

92

94

96

98

0 1 2 3 4 5 6 7 8 94

6

8

10

12

14

16

18

20

Efficiency & Power Disspiation 100°C Case

Output Current (A)

Eff

icie

ncy

(%

)

330 V 352 V 365 VV :IN 330 V 352 V 365 V

Po

wer

Dis

sip

atio

n (

W)

η

PD

100

110

120

130

140

150

160

170

180

190

200

-60 -40 -20 0 20 40 60 80 100 120

ROUT vs. Case Temperature

Case Temperature (°C)

�Ro

ut

(mΩ

)

I :OUT 0.7 A 7.7 A

Figure 1 – No load power dissipation vs. VIN; TCASE Figure 2 – Full load efficiency vs. temperature; VIN

Figure 3 – Efficiency and power dissipation at -40°C (case); VIN Figure 4 – Efficiency and power dissipation at 25°C (case); VIN

Figure 5 – Efficiency and power dissipation at 100°C (case); VIN Figure 6 – ROUT vs. temperature vs. IOUT

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0

50

100

150

200

250

0 2 4 6 8

Ripple vs. Load

Load Current (A)

Rip

ple

(m

V p

k-p

k)

Vpk-pk (mV)

Figure 7 – Vripple vs. IOUT ; 352 Vin, no external capacitance Figure 8 – PC to VOUT startup waveform

Figure 9 – VIN to VOUT startup waveform Figure 10 – Output voltage and input current ripple, 352 Vin, 325 W no COUT

Figure 11 – Positive load transient (0 – 7.7 A) Figure 12 – Negative load transient (7.7 A – 0 A)

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Length L 32.4 / 1.27 32.5 / 1.28 32.6 / 1.29 mm/inWidth W 21.7 / 0.85 22.0 / 0.87 22.3 / 0.89 mm/inHeight H 6.48 / 0.255 6.73 / 0.265 6.98 / 0.275 mm/inVolume Vol No Heatsink 4.81 / 0.295 cm3/in3

Footprint F No Heatsink 7.3 / 1.1 cm2/in2

Power Density PD No Heatsink 1100 W/in3

68 W/cm3

Weight W 0.5/14 oz/g

Lead FinishNickel (0.51-2.03 µm)Palladium (0.02-0.15 µm) µmGold (0.003-0.05 µm)

Operating Temperature TJ -40 125 °CStorage Temperature TST -40 125 °CThermal Capacity 9 Ws/°CPeak Compressive Force No J-lead support 5 6 lbsApplied to Case (Z-axis)

ESD RatingESDHBM Human Body Model[a] 1500

VDCESDMM Machine Model[b] 400

Peak Temperature During ReflowMSL 5 225 °CMSL 6 245 °C

Peak Time Above 183°C 150 sPeak Heating Rate During Reflow 1.5 3 °C/sPeak Cooling Rate Post Reflow 1.5 6 °C/sThermal Impedance ØJC Min Board Heatsinking 1.1 1.5 °CW

2.0 PACKAGE/MECHANICAL SPECIFICATIONS

All specifications are at TJ = 25ºC unless otherwise noted. See associated figures for general trend data.

Figure 13 – PC disable waveform, 352 VIN, 100 µF COUT full load

Safe Operating Area

0

100

200

300

400

500

600

40.00 41.00 42.00 43.00 44.00 45.00 46.00

Output Voltage (V)

Ou

tpu

t P

ow

er

(W)

Steady State 5 mS 325 W Ave

Figure 14 – Safe Operating Area vs. VOUT

[a] JEDEC JESD 22-A114C.01[b] JEDED JESD 22-A115-A

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TOP VIEW ( COMPONENT SIDE )

BOTTOM VIEW inchmmNOTES:

1. DIMENSIONS ARE .2. UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE: .X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005]3. PRODUCT MARKING ON TOP SURFACE

DXF and PDF files are available on vicorpower.com

2.1 MECHANICAL DRAWING

RECOMMENDED LAND PATTERN( COMPONENT SIDE SHOWN )

inchmmNOTES:

1. DIMENSIONS ARE .2. UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE: .X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005]3. PRODUCT MARKING ON TOP SURFACE

DXF and PDF files are available on vicorpower.com

2.2 RECOMMENDED LAND PATTERN

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RECOMMENDED LAND PATTERN

(NO GROUNDING CLIPS)

TOP SIDE SHOWN

RECOMMENDED LAND PATTERN

(With GROUNDING CLIPS)

TOP SIDE SHOWN

NOTES: 1. MAINTAIN 3.50 [0.138] DIA. KEEP-OUT ZONE FREE OF COPPER, ALL PCB LAYERS.

2. (A) MINIMUM RECOMMENDED PITCH IS 39.50 [1.555], THIS PROVIDES 7.00 [0.275] COMPONENT EDGE-TO-EDGE SPACING, AND 0.50 [0.020] CLEARANCE BETWEEN VICOR HEAT SINKS.

(B) MINIMUM RECOMMENDED PITCH IS 41.00 [1.614], THIS PROVIDES 8.50 [0.334] COMPONENT EDGE-TO-EDGE SPACING, AND 2.00 [0.079] CLEARANCE BETWEEN VICOR HEAT SINKS.

3. V•I CHIP LAND PATTERN SHOWN FOR REFERENCE ONLY; ACTUAL LAND PATTERN MAY DIFFER. DIMENSIONS FROM EDGES OF LAND PATTERN TO PUSH-PIN HOLES WILL BE THE SAME FOR ALL FULL SIZE V•ICHIP PRODUCTS.

4. RoHS COMPLIANT PER CST-0001 LATEST REVISION.

5. UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE MM [INCH]. TOLERANCES ARE: X.X [X.XX] = ±0.3 [0.01] X.XX [X.XXX] = ±0.13 [0.005]

6. PLATED THROUGH HOLES FOR GROUNDING CLIPS (33855) SHOWN FOR REFERENCE. HEATSINK ORIENTATION AND DEVICE PITCH WILL DICTATE FINAL GROUNDING SOLUTION.

2.3 RECOMMENDED LAND PATTERN FOR PUSH PIN HEAT SINK

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3.0 POWER, VOLTAGE, EFFICIENCY RELATIONSHIPS

Because of the high frequency, fully resonant SAC topology,power dissipation and overall conversion efficiency of BCMconverters can be estimated as shown below.

Key relationships to be considered are the following:

1. Transfer Function

a. No load condition

VOUT = VIN • K Eq. 1

Where K (transformer turns ratio) is constant for each part number

b. Loaded condition

VOUT = Vin • K – IOUT • ROUT Eq. 2

2. Dissipated PowerThe two main terms of power losses in the BCM module are:

- No load power dissipation (PNL) defined as the power used to power up the module with an enabled power train at no load.

- Resistive loss (ROUT) refers to the power loss across the BCM modeled as pure resistive impedance.

PDISSIPATED ~ PNL + PROUT Eq. 3~

Therefore, with reference to the diagram shown in Figure 15

POUT = PIN – PDISSIPATED = PIN – PNL – PROUT Eq. 4

Notice that ROUT is temperature and input voltage dependentand PNL is temperature dependent (See Figure 15).

INPUT

POWER

OUTPUT

POWER

PNL

PROUT

Figure 15 – Power transfer diagram

The above relations can be combined to calculate the overall module efficiency:

η =POUT

=PIN – PNL – PROUT =

PIN PIN

VIN • IIN – PNL – (IOUT)2 • ROUT= 1 – ( PNL + (IOUT)2 • ROUT )VIN • IIN VIN • IIN

Eq. 5

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4.0 OPERATING 1

23

45

6

V UVL

O+

PC 5 V

3 V

LL •

K

A: T

ON

1B:

TO

VLO

*C:

Max

reco

very

tim

eD

:TU

VLO

E: T

ON

2F:

TO

CPG

: TPC

–DIS

H: T

SSP*

*

1: C

ontr

olle

r sta

rt2:

Con

trol

ler t

urn

off3:

PC

rele

ase

4: P

C pu

lled

low

5: P

C re

leas

ed o

n ou

tput

SC

6: S

C re

mov

ed

Vout TM

3 V

@ 2

7°C

0.4

V

V IN 3

V5

V2.

5 V

500m

Sbe

fore

retr

ial

V UVL

O–

A

B

E

H

I SSP

I OU

T

I OCP

G

F

D

C

V OVL

O+

V O

VLO

–

V OVL

O+

NL

Not

es:

– T

imin

g an

d vo

ltage

is n

ot to

sca

le

–

Err

or p

ulse

wid

th is

load

dep

ende

nt

*M

in v

alue

sw

itchi

ng o

ff**

From

det

ectio

n of

err

or to

pow

er tr

ain

shut

dow

n

C

Figure 16 – Timing diagram

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5.0 USING THE CONTROL SIGNALS TM AND PC

The PC control pin can be used to accomplish the following functions:

• Delayed start: At start-up, PC pin will source a constant 100 uA current to the internal RC network. Adding an external capacitor will allow further delay in reaching the 2.5 V threshold for module start.

• Synchronized start up: In a parallel module array, PC pins shall be connected in order to ensure synchronous start of all the units. While every controller has a calibrated 2.5 V reference on PC comparator, many factors might cause different timing in turning on the 100 uA current source on each module, i.e.:

– Different VIN slew rate

– Statistical component value distributionBy connecting all PC pins, the charging transient will be shared and all the modules will be enabled synchronously.

• Auxiliary voltage source: Once enabled in regular operational conditions (no fault), each BCM PC provides a regulated 5 V, 2 mA voltage source.

• Output Disable: PC pin can be actively pulled down in order to disable module operations. Pull down impedance shall be lower than 400 Ω and toggle rate lower than 1 Hz.

• Fault detection flag: The PC 5 V voltage source is internally turned off as soon as a fault is detected. After a minimum disable time, the module tries to re-start, and PC voltage is re-enabled. For system monitoring purposes (microcontroller interface) faults are detected on falling edges of PC signal.

It is important to notice that PC doesn’t have current sink capability (only 150 kΩ typical pull down is present), therefore, in an array, PC line will not be capable of disabling all the modules if a fault occurs on one of them.

The temperature monitor (TM) pin provides a voltage propor-tional to the absolute temperature of the converter control IC.

It can be used to accomplish the following functions:

• Monitor the control IC temperature: The temperature in Kelvin is equal to the voltage on the TM pin scaled by x100. (i.e. 3.0 V = 300 K = 27ºC). It is important to remember that V•I chips are multi-chip modules, whose temperature distribution greatly vary for each part number as well with input/output conditions, thermal management and environmental conditions. Therefore, TM cannot be used to thermally protect the system.

• Fault detection flag: The TM voltage source is internally turned off as soon as a fault is detected. After a minimum disable time, the module tries to re-start, and TM voltage is re-enabled.

6.0 FUSE SELECTION

V•I Chips are not internally fused in order to provide flexibilityin configuring power systems. Input line fusing of V•I Chips isrecommended at system level, in order to provide thermal protection in case of catastrophic failure.

The fuse shall be selected by closely matching system requirements with the following characteristics:

• Current rating (usually greater than maximum BCM current)

• Maximum voltage rating (usually greater than the maximum possible input voltage)

• Ambient temperature

• Nominal melting I2t• Recommended fuse: ≤2.5 A Bussmann PC-Tron or

SOC type 36CFA.

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7.0 CURRENT SHARING

The SAC topology bases its performance on efficient transferof energy through a transformer, without the need of closedloop control. For this reason, the transfer characteristic can beapproximated by an ideal transformer with some resistive dropand positive temperature coefficient.

This type of characteristic is close to the impedance characteristicof a DC power distribution system, both in behavior (AC dynamic) and absolute value (DC dynamic).

When connected in an array (with same K factor), the BCMmodule will inherently share the load current with parallelunits, according to the equivalent impedance divider that thesystem implements from the power source to the point of load.

It is important to notice that, when successfully started, BCMsare capable of bidirectional operations (reverse power transferis enabled if the BCM input falls within its operating range andthe BCM is otherwise enabled). In parallel arrays, because ofthe resistive behavior, circulating currents are never experienced(energy conservation law).

General recommendations to achieve matched array impedancesare (see also AN016 for further details):

• to dedicate common copper planes within the PCB to deliver and return the current to the modules

• to make the PCB layout as symmetric as possible

• to apply same input/output filters (if present) to each unit

Figure 17 – BCM Array

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8.0 INPUT AND OUTPUT FILTER DESIGN

A major advantage of SAC systems versus conventional PWMconverters is that the transformers do not require large functional filters. The resonant LC tank, operated at extremehigh frequency, is amplitude modulated as a function of inputvoltage and output current, and efficiently transfers chargethrough the isolation transformer. A small amount of capacitance, embedded in the input and output stages of themodule, is sufficient for full functionality and is key to achievepower density.

This paradigm shift requires system design to carefully evaluateexternal filters in order to:

1.Guarantee low source impedance:

To take full advantage of the BCM dynamic response, the impedance presented to its input terminals must be low from DC to approximately 5 MHz. The connection of the V•I Chip to its power source should be implemented with minimal distribution inductance. If the interconnect inductance exceeds 100 nH, the input should be bypassed with a RC damper to retain low source impedance and stable operation. With an interconnect inductance of 200 nH, the RC damper may be as high as 1 µF in series with 0.3 Ω. A single electrolytic or equivalent low-Q capacitor may be used in place of the series RC bypass.

2.Further reduce input and/or output voltage ripple without sacrificing dynamic response:

Given the wide bandwidth of the BCM, the source response is generally the limiting factor in the overall system response. Anomalies in the response of the source will appear at the output of the BCM multiplied by its K factor. This is illustrated in Figures 11 and 12.

3.Protect the module from overvoltage transients imposed by the system that would exceed maximum ratings and cause failures:

The V•I Chip input/output voltage ranges shall not be exceeded. An internal overvoltage lockout function prevents operation outside of the normal operating input range. Even during this condition, the powertrain is exposedto the applied voltage and power MOSFETs must withstand it. A criterion for protection is the maximum amount of energy that the input or output switches can tolerate if avalanched.

Total load capacitance at the output of the BCM shall not exceed the specified maximum. Owing to the wide bandwidthand low output impedance of the BCM, low frequency bypasscapacitance and significant energy storage may be moredensely and efficiently provided by adding capacitance at theinput of the BCM. At frequencies <500 kHz the BCM appearsas an impedance of ROUT between the source and load. Within this frequency range capacitance at the input appearsas effective capacitance on the output per the relationship defined in Eq. 5.

COUT =CIN Eq. 6K2

This enables a reduction in the size and number of capacitorsused in a typical system.

VIB0003TFJ

Rev. 1.62/2010

Page 16 of 17


vicorpower.com


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VIB0003TFJ

Rev. 1.62/2010

Page 17 of 17


vicorpower.com


Vicor’s comprehensive line of power solutions includes high density AC-DCand DC-DC modules and accessory components, fully configurable AC-DCand DC-DC power supplies, and complete custom power systems.

Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor forits use. Vicor components are not designed to be used in applications, such as life support systems, wherein a failure ormalfunction could result in injury or death. All sales are subject to Vicor’s Terms and Conditions of Sale, which are available upon request.

Specifications are subject to change without notice.

Intellectual Property Notice

Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patentapplications) relating to the products described in this data sheet. Interested parties should contact Vicor's Intel-lectual Property Department.

The products described on this data sheet are protected by the following U.S. Patents Numbers:5,945,130; 6,403,009; 6,710,257; 6,911,848; 6,930,893; 6,934,166; 6,940,013; 6,969,909; 7,038,917;7,166,898; 7,187,263; 7,361,844; D496,906; D505,114; D506,438; D509,472; and for use under 6,975,098and 6,984,965

Vicor Corporation25 Frontage Road

Andover, MA, USA 01810Tel: 800-735-6200Fax: 978-475-6715

emailCustomer Service: [email protected]

Technical Support: [email protected]

WarrantyVicor products are guaranteed for two years from date of shipment against defects in material or workmanship when innormal use and service. This warranty does not extend to products subjected to misuse, accident, or improper applica-tion or maintenance. Vicor shall not be liable for collateral or consequential damage. This warranty is extended to theoriginal purchaser only.

EXCEPT FOR THE FOREGOING EXPRESS WARRANTY, VICOR MAKES NO WARRANTY, EXPRESS OR IMPLIED, INCLUDING,BUT NOT LIMITED TO, THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.

Vicor will repair or replace defective products in accordance with its own best judgement. For service under this war-ranty, the buyer must contact Vicor to obtain a Return Material Authorization (RMA) number and shipping instructions.Products returned without prior authorization will be returned to the buyer. The buyer will pay all charges incurred in re-turning the product to the factory. Vicor will pay all reshipment charges if the product was defective within the terms ofthis warranty.

Information published by Vicor has been carefully checked and is believed to be accurate; however, no responsibility isassumed for inaccuracies. Vicor reserves the right to make changes to any products without further notice to improvereliability, function, or design. Vicor does not assume any liability arising out of the application or use of any product orcircuit; neither does it convey any license under its patent rights nor the rights of others. Vicor general policy does notrecommend the use of its components in life support applications wherein a failure or malfunction may directly threatenlife or injury. Per Vicor Terms and Conditions of Sale, the user of Vicor components in life support applications assumesall risks of such use and indemnifies Vicor against all damages.

Documents

NRTL US BCMTM Bus Converter - vicorpower.comv c1 1 µf in pc tm-out +out-in +in bcm pr pc vc tm il os sg prm cd +out-in +in pc tm vtm-out +out-in +in l o a d typical application bcm