NSS 1-Fixed-Width Booth Multiplier

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO. 1, JANUARY 2015 203

An Accuracy-Adjustment Fixed-Width Booth MultiplierBased on Multilevel Conditional Probability

Yuan-Ho Chen

Abstract— This brief proposes an accuracy-adjustment fixed-widthBooth multiplier that compensates the truncation error using a multilevelconditional probability (MLCP) estimator and derives a closed form forvarious bit widths L and column information w. Compared with theexhaustive simulations strategy, the proposed MLCP estimator substan-tially reduces simulation time and easily adjusts accuracy based on math-ematical derivations. Unlike previous conditional-probability methods,the proposed MLCP uses entire nonzero code, namely MLCP, to estimatethe truncation error and achieve higher accuracy levels. Furthermore,the simple and small MLCP compensated circuit is proposed in this brief.The results of this brief show that the proposed MLCP Booth multipliersachieve low-cost high-accuracy performance.

Index Terms— Fixed-width Booth multiplier, multilevelconditional probability (MLCP), truncation error.

I. INTRODUCTION

Fixed-width multipliers are widely used in digital signal processing(DSP) applications [1]–[4], such as fast Fourier transform [2] anddiscrete cosine transform [3], [4]. To generate an output with thesame width as the input, fixed-width multipliers truncate the halfleast significant bits (LSBs) in DSP applications. Thus, truncationerrors can occur in fixed-width multiplier designs. The fixed-widthmultiplier with highest accuracy is called a posttruncated (P-T)multiplier, which truncates half of the LSBs results after calculatingall products. However, a P-T multiplier requires a large circuit areato calculate truncation part products. By contrast, a direct-truncated(D-T) multiplier truncates half of the LSBs products directly toconserve circuit area, but produces a large truncation error.

To achieve a balanced design between accuracy (P-T) and area cost(D-T), several researchers have presented various error-compensatedcircuits to alleviate the truncation errors in Baugh–Wooley (BW)multipliers [5]–[10] and Booth multipliers [11]–[21]. Because a fewproducts are truncated after Booth encoding, the multipliers have asmaller truncation error than that of BW multipliers [17]. Therefore,many previous works have focused on the compensated circuit inBooth multipliers [11]–[21]. Song et al. [18] present a binarythreshold based on statistical analysis. Their compensated circuitconsumes a large circuit area because of the complex curve fittingrequired for statistical analysis. Wang et al. [19] use more productinformation to improve accuracy, but their exhaustive simulationrequired a considerable amount of established time. To reduce theestablished time for compensated circuits, Li et al. [20] presentprobability estimator (PEB) that substantially reduces calculationtime. An adaptive conditional-probability estimator (ACPE) [21] ispresented to improve the accuracy using conditional probability tofurther induce the column information w for adjusting the accuracy

Manuscript received August 23, 2013; revised November 30, 2013 andJanuary 21, 2014; accepted January 22, 2014. Date of publication February 11,2014; date of current version January 16, 2015. This work was supported bythe Chip Implementation Center and National Science Council (NSC) underProject CIC T18-102C-N0001, Project NSC 102-2221-E-033-030, and ProjectNSC 101-2218-E-033-005.

The author is with the Department of Information and Computer Engi-neering, Chung Yuan Christian University, Zhongli 320, Taiwan (e-mail:[email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TVLSI.2014.2302447

TABLE IMAPPED TABLE OF A MODIFIED BOOTH ENCODER

when applied to types of DSP systems. Therefore, two types ofcompensated circuits for various w are introduced in [18], and thegeneralized form of PEB is presented in [17]. In sum, the establishedtime for compensated circuits and adjustment are critical to fixed-width Booth multipliers.

This brief proposes an accuracy-adjustment fixed-width Boothmultiplier that uses the multilevel conditional probability (MLCP)method to implement the compensated circuit. The MLCP methodproduces a closed form with various bitwidths L and columninformation w; thus, the compensated circuit can be establishedquickly, and the accuracy can be adjusted by changing w. In contrastto the conditional-probability method for ACPE [21], which usessingle nonzero code to estimate truncation errors, the proposedMLCP generates estimates by employing all nonzero code, whichdemonstrates high levels of intercorrelation. Although MLCP methodhas higher complexity to estimate truncation errors when comparedwith ACPE one, the accuracy of MLCP method is higher than that ofACPE method. Furthermore, simple and small compensated circuitsare proposed from a single compensated closed form. According tothe tradeoff between accuracy and circuit area, the MLCP methodprovides a balance between accuracy and circuit area. The imple-mentation results of this brief show that the proposed MLCP Boothmultiplier achieves low-cost high-accuracy performance.

The remainder of this brief is organized as follows. Section IIpresents the fundamental derivation for a Booth multiplier. Thederivation and architecture of the proposed MLCP estimator areaddressed in Section III. Section IV presents comparisons and a dis-cussion of these approaches, and Section V provides the conclusion.

II. FIXED-WIDTH MODIFIED BOOTH MULTIPLIER

Modified Booth encoding is commonly used in multiplier designsto reduce the number of partial products [22]. The 2L-bit product Pcan be expressed in two’s complement representation as follows:

A = −aL−12L−1 +L−2∑

i=0

ai · 2i

B = −bL−12L−1 +L−2∑

i=0

bi · 2i

P = A × B. (1)

Table I lists three concatenated inputs b2i+1, b2i , and b2i−1mapped into yi using a Booth encoder, in which the nonzero codezi is an one-bit digit of which the value is determined according to

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204 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO. 1, JANUARY 2015

TABLE IIPARTIAL PRODUCTS FOR AN EIGHT-BIT BOOTH ENCODER

Fig. 1. Partial product array for Booth multiplier.

whether yi equals zero and z consists of zi . Table II shows the partialproducts with corresponding yi for an eight-bit Booth encoder. Afterencoding, the partial product array with an even width L containsQ = L/2 rows.

Fig. 1 shows the partial product array in a Booth multiplier forinducing the column information w, where w indicates the numberof true product columns included in the compensated circuit. Thedefinition of w is the same as that in [21].

III. PROPOSED MLCP ESTIMATOR

The quantized product Pq for a fixed-width multiplier can beexpressed as follows:

P ≈ Pq = M P + T P = M P + σ · 2L (2)

where MP is the main part of multiplier, which uses real partialproducts to calculate results; TP is the truncation part (Fig. 1, shadedregion), which will be truncated using fixed-width multiplication;and σ represents the compensated bias of the MLCP estimator,which consists of TPmj and TPmi parts by performing the roundingoperation Round()

σ = Round(TPmj + TPmi

). (3)

The major term TPmj provides true information and the minor termTPmi can be estimated based on the proposed MLCP method. Thus,the compensated bias σ can be summed by obtaining TPmj andestimating TPmi.

A. Derived MLCP Formula

Fig. 2 shows that the TP can be partitioned into encoding groupset (G) and column set (T). The encoding groups in G are definedas follows:

G0 = 2−L (p0,0 + n0) + · · · + 2−1−w pL−1−w,0

G1 = 2−(L−2)(p0,1 + n1) + · · · + 2−1−w pL−3−w,1

...

G Q−1 = 2−2(p0,Q−1 + nQ−1) (4)

Fig. 2. Truncation part of the proposed Booth multiplier.

Fig. 3. G set of the proposed Booth multiplier with w = 3.

and the column groups in T set are defined as follows:

T1 = 2−1(pL−1,0 + pL−3,1 + · · · + p1,Q−1)

T2 = 2−2(pL−2,0 + pL−4,1 + · · · + nQ−1)

...

TL = 2−L (p0,0 + n0). (5)

With the column information w, the terms TPmj and TPmi can beexpressed as the following equations:

TPmj = T1 + T2 + · · · + Tw (6)

TPmi = G0 + G1 + · · · + Gα (7)

where α = Q−1−�w/2�, �� represents the flooring operation, TPmjis constructed by summing Ti (w ≥ i ≥ 1), and TPmi consists ofG j , (α ≥ j ≥ 0). Note that the G set changes based on the columninformation w. Fig. 3 shows an example for TP, where w = 3.

The MLCP method proposed in this brief involves using thenonzero code z to establish an MLCP estimator. The expected valueson all elements in TPmi with corresponding nonzero code are derivedfirst. In contrast to the method in [21], the proposed MLCP methodinvolves using nonzero code to estimate TPmi. Therefore, moretruncation errors can be reduced compared with [21], which involvesusing only one nonzero bit. For example, the values L = 8, w = 1,and z = 1111 can be used to calculate the expected value of p0,1

E[p0,1|z = 1111]= P[p0,1 = 1]P[p0,1|z1 = 1]P[z1 = 1|z0 = 1]

=∑

m=±1,−2

⎛

⎝∑

n=±1,±2

P[p0,1 = 1]


Fig. 4. Examples of an 8 × 8 MLCP Booth multiplier with w = 1 and nonzero codes 1111, 1110, and 0101. (a) MLCP for z = 1111. (b) MLCP forz = 1110. (c) MLCP for z = 0101.

× P[p0,1|y1 = n]P[y1 = n|y0 = m]⎞

⎠

=(

1 × 0 + 1

2× 1

3+ 1

2× 1

3+ 0 × 1

3

)

m=−2

+(

1 × 0 + 1

2× 1

3+ 1

2× 1

3+ 0 × 1

3

)

m=−1

+(

1 × 1

3+ 1

2× 1

3+ 1

2× 1

3+ 0 × 0

)

m=1

= 4

9. (8)

Fig. 4(a) shows the expected values of all elements in TPmi. Then,a regular rule is observed, the expected values for all products withcorresponding z j = 1 are equal to 1/2 (except for p0, j and n j ).The expected values of p0, j and n j depend greatly on the numberof the nonzero code z j = 1; that is, the order of z j code can affectthe expected value, and the expected values for p0, j and n j can besummarized as follows:

E[n j |z], E[p0, j |z] =⎧⎨

⎩

13k × 3k+1

2 as k = odd13k × 3k−1

2 as k = even

k =j∑

ik=0

zik (9)

where k is the number of nonzero code z until j th bits. Fig. 4 showsthree examples. The expected values of p0,3 as z = 1111, p0,2 asz = 1110, and n0 as z = 0101 are 40/81, 4/9, and 2/3, respectively

E[p0,3|z = 1111] = 1

3k× 3k − 1

2|k=4 = 40

81(10)

E[p0,2|z = 1110] = 1

3k× 3k − 1

2|k=2 = 4

9(11)

E[n0|z = 0101] = 1

3k× 3k + 1

2|k=1 = 2

3. (12)

B. Proposed Generalized MLCP Format

With the derivation of the MLCP method, the expected value ofeach part in TPmi can be estimated as follows:

TPmi = T P0 + · · · + T Pα

� E[(T P0 + · · · + T Pα)|z]= E[T P0|z] + E[T P1|z] + · · · + E[T Pα|z]= E[T P0|z0] + E[T P1|{z1, z0}] + · · · + E[T Pα |z]= E0 + E1 + · · · + Eα (13)

where the conditional expected values E0, E1, . . . , Eα dependgreatly on the nonzero code nz. Therefore, the conditional expectedvalue can be estimated using (9), and which yields three cases forthe expected value of TPmi.

Case 1: β = odd

TPmi � β

2× 2−w. (14)

Case 2: β = even

TPmi � β − 1

2× 2−w. (15)

Case 3: β = 0

TPmi = 0 (16)

where

β =α∑

i=0

zi . (17)

Because only the carry propagation from TPmi to TPmj must beconsidered, the expected value of TPmi can be simplified as

TPmi =α∑

i=0

Ei � Sone × 2−w (18)

where{

Sone =⌊

β−12

⌋as z �= 00 · · · 0

Sone = 0 as z = 00 . . . 0.(19)

The expected value of TPmi is the function of the number of zi =1 for 0 ≤ i ≤ α, and Sone indicates the sum of nonzero code zwith corresponding w. Thus, the compensated bias can be obtainedby substituting σ in (3) with the expected value of TPmi in (18)and (19)

σ = Round(TPmj + TPmi)

= Round(TPmj + Sone · 2−w). (20)

C. Architecture of the Proposed MLCP Booth Multiplier

With the proposed MLCP formula in (20), the compensated biasσ can be obtained with the corresponding L and w. Fig. 5 showsthat the proposed MLCP Booth multiplier has a Booth encoderaddressed in [19] and a carry-save-adder (CSA) array with 4–2 and3–2 compressors [23]. The compensated circuit sums TPmj and TPmiall together. The proposed MLCP compensated circuit implements(18) using CSA architecture and the function of subtracting one is

206 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 23, NO. 1, JANUARY 2015

Fig. 5. Architecture of the proposed MLCP Booth multiplier for L = 16 and w = 3.

Fig. 6. Usage of MLCP circuit with corresponding w.

designed by adding all one values for twos complement representa-tion. Using L = 16 and w = 3 as an example, the Sone in (19) canbe expressed as follows:

Sone =⌊

β + 4′b1111

2

⌋. (21)

The proposed MLCP circuits depend on α, thus, various word lengthsL and column information w can use the same MLCP circuit. Usingα = 6 as an example, the MLCP circuit (Fig. 5) can be employed,yielding L = 16 with w = 3, L = 16 with w = 2, and L = 14 withw = 1, and so on. Fig. 6 shows the use of the MLCP circuit withcorresponding w.

Because the proposed MLCP method entails using the conditional-probability method, it yields considerable time saved for the com-pensated circuit compared with the exhaustive and time-consumingheuristic simulation methods [13], [14], [18], [19]. Therefore, theproposed MLCP compensated circuit can easily implement a largebitwidth (as L > 16) Booth multiplier and adjust accuracy bychanging the column information w.

IV. COMPARISONS AND DISCUSSION

This section presents a comparison of the accuracy, area cost, andcomputation delay of fixed-width Booth multipliers.

A. Accuracy

In this brief, the average absolute error |ε̄| is presented andcompared for accuracy. The definitions of |ε̄| are as follows:

|ε̄| = E[|P − Pq |]/2L . (22)

Table III shows the |ε̄| for D-T, P-T, the proposed MLCP estimator,and previous works [17]–[19] and [21], respectively. The |ε̄| is themost crucial metric for comparing the accuracy of a fixed-widthBooth multiplier. Table III shows that the proposed MLCP Boothmultipliers achieve high performance with various bitwidth L andcolumn information w. Because of the structure in [19] and [21],

TABLE IIICOMPARISON OF THE AVERAGE ABSOLUTE ERROR |ε̄| VALUES FOR

VARIOUS METHODS

which precalculates the summing of the p0,Q−1 and nQ−1 in thetruncation part, the |ε̄| values in [19] and [21] are more favorablethan that of the proposed MLCP estimator when w = 1; otherwise,the proposed MLCP Booth multiplier demonstrates superior |ε̄|performance for various L and w values. As the column informationw increases, the true partial products of TPmj also increase. It meansthe TPmi, which needs to be estimated, decreases. Thus, based on w

increasing, the accuracy of these methods comes very close.

B. Circuit Performance

Area cost and computation delay are critical in Booth multiplierdesigns. Table IV lists the area and delay of the proposed MLCPestimator and previous designs with various L and w values. Thearea and delay information was implemented using the Synopsysdesign compiler with a TSMC 40-nm CMOS standard cell library tosynthesize the RTL design. All the multipliers are implemented usingthe CSA architecture in Fig. 5 with their own compensated circuit.The methods presented in [18] and [19] involve using exhaustivesimulation to design the compensated circuit, and therefore requirea long simulation time to establish compensated circuit. However,the MLCP estimator and the method in [17] and [21] require usingmathematical derivation to establish a compensated circuit. Thesemethods greatly reduce the simulation time, and can be extendedto long bitwidth multiplier designs. The design in [17] outperformsother circuits in area and delay, but its |ε̄| values are higher thanthose of other circuits. Although the design in [18] has a largestcircuit area and delay, its |ε̄| values are lower than others when


TABLE IVCOMPARISONS OF AREA COST (μm2) AND DELAY (ns) FOR

VARIOUS METHODS

Fig. 7. Chip photomicrograph and characteristics.

w > 1. Compensated circuit designs generally include a tradeoffbetween accuracy and area. The MLCP method obtains a balancebetween accuracy and circuit area, and it further adjusts the accuracyby varying w based on the MLCP formula. Therefore, the proposedMLCP Booth multiplier achieves low cost and flexible accuracy.

C. Chip Implementation

To verify the circuit performance in a real chip, the proposedMLCP Booth multiplier was fabricated using the TSMC 0.18-μmCMOS process. Fig. 7 shows the chip photomicrograph and char-acteristics of the proposed 16 × 16 MLCP Booth multiplier, wherew = 3. To avoid the I/O limited phenomenon in the chip design, thetest module, which is positioned near the proposed MLCP multiplier(Fig. 7), was designed using serial-to-parallel buffers to reduce inputand output ports. The test pattern fed into the proposed core at afrequency of 100 MHz; thus, the proposed core demonstrated a delaypath smaller than 10 ns.

V. CONCLUSION

This brief presents a closed MLCP formula that includes columninformation w to adjust accuracy depending on system requirements.This formula is derived without performing time-consuming andexhaustive simulations, and can be applied to lengthy Booth multi-pliers to achieve high-accuracy performance. Therefore, the proposedMLCP compensated circuit can be used to develop a high-accuracy,low-cost, and flexible fixed-width Booth multiplier.

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NSS 1-Fixed-Width Booth Multiplier