Nuand bladeRF USB 3.0 Software Defined Radionuand.com/bladerf.pdf5 5 4 4 3 3 2 2 1 1 D D C C B B A A bladerRF - USB 3.0 Software Defined Radio Title Size Document Number Rev Date:

5

5

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C C

B B

A A

bladerRF - USB 3.0 Software Defined Radio

Title

Size Document Number Rev

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1 14Saturday, March 30, 2013

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5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

C4 handbook pg 171:MSEL[3..0] = PS-FAST = "1100" @ 3.3/3.0/2.5V PS-STD = "0000" @3.3/3.0/2.5V FPP-FAST = "1110" @3.3/3.0/2.5V FPP-FAST = "1111" @1.8/1.5 V (default)

MSEL[3..0]

MSEL pins should be connecteddirectly to VCCA or GND.

JTAG is on BANK 1 aka VCCIO_L_C4

Config is on BANK 1 aka VCCIO_L_C4

FPGA CONFIGURATION

VCCIO_L_C4

VCCIO_L_C4

VCCIO_L_C4

VCCA_C4 VCCA_C4 VCCA_C4 VCCA_C4

VCCIO_L_C4

VCCIO_L_C4

VCCIO_L_C4 VCCIO_L_C4

C4_NSTATUS

C4_DCLK

C4_NCONFIG

C4_CONFDONE

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R253

1K

R254

1K

EP4CE15A115F484

U43C

NCONFIG K5NSTATUS K6

MSEL3 K20

TMSL1

TCKL2

NCE L3

TDOL4

TDIL5 MSEL2 L17MSEL1 L18MSEL0 M17

CONF_DONE M18

DCLK K2 R259

10K R273

10K

R25510K

JTAG_ICE_CONN

J38

ALTERA_JTAG

TCK1

TDO3

TMS5

NC27

TDI9

GND 2

VCC_TRGT 4

NC1 6

NC3 8

GND 10

R25610K

R252

1K

TCK

TDITDO

TCK

TDO

TMS

TDI

MSEL3 MSEL2 MSEL0

MSEL3MSEL2MSEL1MSEL0

C4_NSTATUS

C4_CONFDONE

TMS

C4_NCONFIG

MSEL1

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Avoid VREF pins due to their slow IO times.UDCLK has to be a CTL pin.DATA[0..7] have to be from GPIF[0..15] FPGA "LEFT" BANK

Mini Expansion Header

VCCIO_L_C4

VD3P3 VD3P3

VD3P3

VD3P3

GPIF6

GPIF1GPIF0

GPIF3

GPIF8

GPIF5

GPIF10

GPIF12GPIF11GPIF13GPIF14

FX3_CTL0FX3_CTL1

FX3_CTL6

FX3_CTL2

FX3_CTL11FX3_CTL10

GPIF17

GPIF20

GPIF16

GPIF19GPIF21

GPIF22

GPIF25GPIF27

GPIF29

FX3_CTL5

FX3_CTL3

FX3_PCLK

FX3_CTL12

FX3_CTL8

GPIF28

GPIF23

GPIF24

GPIF30

GPIF31

FX3_CTL9 C4_DCLK

GPIF15

GPIF26FX3_CTL7

GPIF7

FX3_CTL4

GPIF9

GPIF4

GPIF2GPIF18

DAC_SDODAC_SDI

C4_CLK

DAC_SCLKDAC_CSB

FX3_UART_TXnFX3_UART_CS

FX3_UART_RX

C4_CONFDONE

C4_NCONFIG

C4_NSTATUS

FX3_GPIO50

FX3_GPIO51

FX3_GPIO52

SI_SCLSI_SDA

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J64

HEADER_1x3_100mil

1

2

3

R287820

BANK 3

EP4CE15A115F484

U43F

B3_IO_U9U9

B3_IO_U10U10

B3_IO_U11_VREFU11

B3_IO_V5V5

B3_IO_V8V8

B3_IO_V9_VREFV9

B3_IO_V10V10

B3_IO_V11V11

B3_IO_W6W6

B3_IO_W7W7

B3_IO_W8W8

B3_IO_W10W10

B3_IO_Y3Y3

B3_IO_Y4_VREFY4

B3_IO_Y6Y6

B3_IO_Y7Y7

B3_IO_Y8Y8

B3_IO_Y10Y10

B3_IO_AA3AA3

B3_IO_AA4AA4

B3_IO_AA5AA5

B3_IO_AA7AA7

B3_IO_AA8AA8

B3_IO_AA9AA9

B3_IO_AA10AA10

B3_CLK15AA11

B3_IO_AB3AB3

B3_IO_AB4_VREFAB4

B3_IO_AB5AB5

B3_IO_AB7AB7

B3_IO_AB8AB8

B3_IO_AB9AB9

B3_IO_AB10AB10

B3_CLK14AB11

R278820

D13LTST-C190KGKT

BANK 1

EP4CE15A115F484

U43D

B1_IO_B1B1

B1_IO_B2B2

B1_IO_C1C1

B1_IO_C2C2

B1_IO_D1_DATA1_ASDOD1

B1_IO_D2D2

B1_IO_E1E1

B1_IO_E2_FLASH_nCE_nCSOE2

B1_IO_E3E3

B1_IO_E4_NRESETE4

B1_IO_F1F1

B1_IO_F2F2

B1_CLK1G1

B1_IO_G3G3

B1_IO_G5_VREFG5

B1_IO_H1H1

B1_IO_H2H2

B1_IO_H5_VREFH5

B1_IO_H6H6

B1_IO_H7_VREFH7

B1_IO_J1J1

B1_IO_J2J2

B1_IO_J3_VREFJ3

B1_IO_J4J4

B1_IO_J6J6

B1_IO_K1_DATA0K1

R286820

BANK 8

EP4CE15A115F484

U43K

B8_IO_A3_DATA10A3

B8_IO_A4A4

B8_IO_A5_DATA5A5

B8_IO_A6_PADD19A6

B8_IO_A7_PADD18A7

B8_IO_A8_DATA2A8

B8_IO_A9_PADD16A9

B8_IO_A10A10

B8_CLK10A11

B8_IO_B3_DATA11B3

B8_IO_B4_DATA8B4

B8_IO_B5_VREFB5

B8_IO_B6_DATA15B6

B8_IO_B7_DATA4B7

B8_IO_B8_DATA3B8

B8_IO_B9_PADD17B9

B8_IO_B10_PADD15B10

B8_CLK11B11

B8_IO_C3C3

B8_IO_C4_DATA12C4

B8_IO_C6_DATA7C6

B8_IO_C7_DATA13C7

B8_IO_C8_DATA14C8

B8_IO_C10_VREFC10

B8_IO_D6_VREFD6

B8_IO_D10D10

B8_IO_E5E5

B8_IO_E6E6

B8_IO_E7E7

B8_IO_E9_VREFE9

B8_IO_F7F7

B8_IO_F8_DATA9F8

B8_IO_F9F9

B8_IO_F10_DATA6F10

D11LTST-C190KGKT

D12LTST-C190KGKT

BANK 2

EP4CE15A115F484

U43E

B2_IO_L6L6

B2_IO_M1M1

B2_IO_M2M2

B2_IO_M3M3

B2_IO_M4M4

B2_IO_M5_VREFM5

B2_IO_M6M6

B2_IO_N1N1

B2_IO_N2N2

B2_IO_N5N5

B2_IO_N6N6

B2_IO_P1P1

B2_IO_P2P2

B2_IO_P3P3

B2_IO_P4P4

B2_IO_P5P5

B2_IO_R1R1

B2_IO_R2R2

B2_IO_R5_VREFR5

B2_CLK3T1

B2_CLK2T2

B2_IO_T3_VREFT3

B2_IO_T4T4

B2_IO_T5T5

B2_IO_U1U1

B2_IO_U2U2

B2_IO_V1V1

B2_IO_V2V2

B2_IO_V3V3

B2_IO_V4V4

B2_IO_W1W1

B2_IO_W2W2

B2_IO_Y1Y1

B2_IO_Y2Y2

B2_IO_AA1AA1

J71

PWR_HDR6

1

2

3 4

6

5

FX3_UART_RX

FX3_UART_TX

LED1 LED2

LED1

LED2

MINI_EXP_1

MINI_EXP_1MINI_EXP_2

MINI_EXP_2

LED3

LED3

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LMS SIGNALS GO TO THE "RIGHT" OF THE C4BANKS 4, 5, 6, 7

Avoid VREF pins due to their slow IO times. FPGA "RIGHT" BANK Expansion Header

VCCIO_R_C4

VD3P3

VCCIO_R_C4

VCCIO_R_C4

LMS_RX_IQ_SEL

LMS_RXD0

LMS_RXD3

LMS_RXD4

LMS_RXD5

LMS_RXD6LMS_RXD7

LMS_RXD8LMS_RXD9

LMS_RXD10LMS_RXD11

LMS_TX_IQ_SEL

LMS_TXD0

LMS_TXD1

LMS_RXD2

LMS_TXD2

LMS_TXD3

LMS_TXD4

LMS_TXD5

LMS_TXD6

LMS_TXD7

LMS_TXD8

LMS_TXD9

LMS_TXD10

LMS_TXD11

LMS_RXD1

LMS_RX_CLK_OUTLMS_PLLOUT

LMS_SDIOLMS_SDOLMS_TXENLMS_SEN

LMS_RXENLMS_SCLK

LMS_RESETC4_TX_CLK

LMS_TX_V2

LMS_RX_V2LMS_RX_V1

LMS_TX_V1SI_SDA

SI_SCL

EXP_CLK

V5P0V5P0

V5P0V5P0

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R57 200

BANK 6

EP4CE15A115F484

U43I

B6_IO_B21_PADD21B21

B6_IO_B22_PADD22B22

B6_IO_C20_PADD20C20

B6_IO_C21C21

B6_IO_C22C22

B6_IO_D20_VREFD20

B6_IO_D21D21

B6_IO_D22D22

B6_IO_E21_NOEE21

B6_IO_E22_NWEE22

B6_IO_F17F17

B6_IO_F19F19

B6_IO_F20_NAVDF20

B6_IO_F21F21

B6_IO_F22F22

B6_IO_G18_PADD23G18

B6_CLK4G21

B6_CLK5G22

B6_IO_H18_VREFH18

B6_IO_H19H19

B6_IO_H20H20

B6_IO_H21H21

B6_IO_H22H22

B6_IO_J18J18

B6_IO_J21J21

B6_IO_J22J22

B6_IO_K18K18

B6_IO_K19_VREFK19

B6_IO_K21_CLKUSRK21

B6_IO_K22_NCEOK22

B6_IO_L21_CRC_ERRORL21

B6_IO_L22_INIT_DONEL22

R276

1.2K

BSH-30-XX-X-D-A

U74

11

33

55

77

99

1111

1313

1515

1717

1919

2121

2323

2525

2727

2929

3131

3333

3535

3737

3939

4141

4343

4545

4747

4949

5151

5353

5555

5757

5959

2 2

4 4

6 6

8 8

10 10

12 12

14 14

16 16

18 18

20 20

22 22

24 24

26 26

28 28

30 30

32 32

34 34

36 36

38 38

40 40

42 42

44 44

46 46

48 48

50 50

52 52

54 54

56 56

58 58

60 60

TOP_

PTH

61BO

TTO

M_P

TH62

R56 200

BANK 4

EP4CE15A115F484

U43G

B4_IO_R16R16

B4_IO_T15T15

B4_IO_T16T16

B4_IO_U12U12

B4_IO_U14U14

B4_IO_V12_VREFV12

B4_IO_V13V13

B4_IO_V14V14

B4_IO_V15V15

B4_IO_V16_VREFV16

B4_IO_W13W13

B4_IO_W14_VREFW14

B4_IO_W15W15

B4_IO_W17W17

B4_IO_Y13Y13

B4_IO_Y17Y17

B4_CLK13AA12

B4_IO_AA13AA13

B4_IO_AA14AA14

B4_IO_AA15AA15

B4_IO_AA16AA16

B4_IO_AA17AA17

B4_IO_AA18_VREFAA18

B4_IO_AA19AA19

B4_IO_AA20AA20

B4_CLK12AB12

B4_IO_AB13AB13

B4_IO_AB14AB14

B4_IO_AB15AB15

B4_IO_AB16AB16

B4_IO_AB17AB17

B4_IO_AB18AB18

B4_IO_AB19AB19

B4_IO_AB20AB20

TXB0104

U69

VCCA1

A12

A23

A34

A45

NC16

GND7 OE 8NC2 9B4 10B3 11B2 12B1 13VCCB 14R49 200

BANK 7

EP4CE15A115F484

U43J

B7_CLK8A12

B7_IO_A13_PADD11A13

B7_IO_A14_PADD9A14

B7_IO_A15_PADD5A15

B7_IO_A16A16

B7_IO_A17_PADD1A17

B7_IO_A18A18

B7_IO_A19A19

B7_IO_A20A20

B7_CLK9B12

B7_IO_B13_PADD12B13

B7_IO_B14_PADD10B14

B7_IO_B15_PADD6B15

B7_IO_B16B16

B7_IO_B17_PADD2B17

B7_IO_B18_PADD0B18

B7_IO_B19B19

B7_IO_B20B20

B7_IO_C13_PADD7C13

B7_IO_C15_VREFC15

B7_IO_C17C17

B7_IO_C19C19

B7_IO_D13_PADD8D13

B7_IO_D15D15

B7_IO_D17_VREFD17

B7_IO_D19D19

B7_IO_E11_PADD13E11

B7_IO_E12E12

B7_IO_E13_VREFE13

B7_IO_E14_PADD3E14

B7_IO_E15E15

B7_IO_E16E16

B7_IO_F11_PADD14F11

B7_IO_F13_PADD4F13

B7_IO_F14F14

B7_IO_F15F15

J55

DNP

GN

D1

3G

ND

2IN

R274

1.2K

BANK 5

EP4CE15A115F484

U43H

B5_IO_M16M16

B5_IO_M19M19

B5_IO_M20M20

B5_IO_M21M21

B5_IO_M22M22

B5_IO_N18N18

B5_IO_N19_VREFN19

B5_IO_N20N20

B5_IO_N21_DEV_CLRNN21

B5_IO_N22_DEV_OEN22

B5_IO_P20_VREFP20

B5_IO_P21P21

B5_IO_P22P22

B5_IO_R17_VREFR17

B5_IO_R19R19

B5_IO_R20R20

B5_IO_R21R21

B5_IO_R22R22

B5_IO_T17T17

B5_IO_T18T18

B5_CLK6T21

B5_CLK7T22

B5_IO_U20U20

B5_IO_U21U21

B5_IO_U22U22

B5_IO_V21V21

B5_IO_V22V22

B5_IO_W19_VREFW19

B5_IO_W20W20

B5_IO_W21W21

B5_IO_W22W22

B5_IO_Y22Y22

B5_IO_AA21AA21

R50 200

RX_V2

EXP_GPIO_17EXP_SPI_MOSI

EXP_GPIO_18EXP_GPIO_20EXP_GPIO_21EXP_GPIO_23EXP_GPIO_24EXP_GPIO_29EXP_PRSNT

EXP_GPIO_9

TX_V2

RX_V1TX_V1

TX_V2RX_V1RX_V2

TX_V1

EXP_SPI_CLK

EXP_SPI_MISO

EXP_PRSNT

EXP_SPI_MOSI

EXP_GPIO_1

EXP_GPIO_2

EXP_GPIO_17

EXP_GPIO_4

EXP_GPIO_5

EXP_GPIO_7

EXP_GPIO_8

EXP_GPIO_9

EXP_GPIO_10

EXP_GPIO_12

EXP_GPIO_13

EXP_GPIO_15

EXP_GPIO_16

EXP_GPIO_19

EXP_GPIO_20

EXP_GPIO_21

EXP_GPIO_22

EXP_GPIO_24

EXP_GPIO_25

EXP_GPIO_27

EXP_GPIO_28

EXP_GPIO_29

EXP_GPIO_30

EXP_GPIO_32

EXP_GPIO_18

EXP_GPIO_31

EXP_GPIO_23

EXP_GPIO_26

EXP_GPIO_6

EXP_GPIO_3

EXP_GPIO_14

EXP_GPIO_11

EXP_GPIO_16EXP_GPIO_25EXP_GPIO_26EXP_GPIO_27EXP_GPIO_28

EXP_GPIO_31EXP_GPIO_32

EXP_GPIO_30

EXP_SPI_MISO

EXP_SPI_CLK



EXP_GPIO_2EXP_GPIO_15EXP_GPIO_7EXP_GPIO_8


EXP_GPIO_12EXP_GPIO_13EXP_GPIO_14

EXP_GPIO_11

EXP_GPIO_10

EXP_GPIO_1

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VCCIO_L_C4 defines the "left" banks of the C4VCCIO_R_C4 defines the "right" banks of the C4The left side goes to the FX3, and the right side goes to the LMS.

This power condition is for the 115KE part at 3A

VCCINT @1.2V, MAX 3.1AVCCA2P5 @ 2.5, MAX 0.1AVCCIO @1.8V MAX 0.1AFPGA POWER

330uF

330uF

VA2P5

VCCINT_C4VCCIO_R_C4VCCIO_L_C4

VCCINT_C4

VCCA_C4

V1P2PLL_C4

V1P2PLL_C4

VCCIO_L_C4

VCCIO_R_C4

VCCINT_C4

V1P2

VCCA_C4

VCCINT_C4

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C236

DNP

C45

22nF

C118

4.7 uF

C275

470nF

EP4CE15A115F484

U43A

VCCA1 T6

VCCA2 F18

VCCA3 G6

VCCA4 U18

VCCD_PLL1 U6

VCCD_PLL2 E17

VCCD_PLL3 F6

VCCD_PLL4 V17

VCCINTJ8

VCCINTJ10

VCCINTJ11

VCCINTJ12

VCCINTJ13

VCCINTJ14

VCCINTK9

VCCINTK14

VCCINTL9

VCCINTL14

VCCINTM9

VCCINTM14

VCCINTN9

VCCINTP9

VCCINTP10

VCCINTP11

VCCINTP12

VCCINTP13

VCCINTT13

VCCINTU16

VCCINTU17

VCCINT_V115G4

VCCINT_V115G8

VCCINT_V115G10

VCCINT_V115G12

VCCINT_V115G14

VCCINT_V115G16

VCCINT_V115H9

VCCINT_V115H11

VCCINT_V115H15

VCCINT_V115H17

VCCINT_V115J7

VCCINT_V115J16

VCCINT_V115J17

VCCINT_V115K8

VCCINT_V115K15

VCCINT_V115K17

VCCINT_V115L7

VCCINT_V115L16

VCCINT_V115M8

VCCINT_V115M15

VCCINT_V115N7

VCCINT_V115N14

VCCINT_V115N16

VCCINT_V115P7

VCCINT_V115P14

VCCINT_V115P15

VCCINT_V115P17

VCCINT_V115R6

VCCINT_V115R8

VCCINT_V115R10

VCCINT_V115R12

VCCINT_V115R14

VCCINT_V115R15

VCCINT_V115T7

VCCINT_V115T9

VCCINT_V115T11

VCCINT_V115U8

VCCINT_V115U15

VCCINT_V115V7

VCCIO1 D4

VCCIO1 F4

VCCIO1 K4

VCCIO1_V15 H4

VCCIO2 N4

VCCIO2 U4

VCCIO2 W4

VCCIO2_V15 R4

VCCIO3 W5

VCCIO3 W9

VCCIO3 W11

VCCIO3 AB2

VCCIO3_V15 AA6

VCCIO4 W12

VCCIO4 W16

VCCIO4 W18

VCCIO4 AB21

VCCIO4_V15 Y14

VCCIO5 P18

VCCIO5 V19

VCCIO5 Y19

VCCIO5_V15 T19

VCCIO6 E19

VCCIO6 G19

VCCIO6 L19

VCCIO6_V15 J20

VCCIO7 A21

VCCIO7 D12

VCCIO7 D14

VCCIO7 D16

VCCIO7_V15 D18

VCCIO8 A2

VCCIO8 D5

VCCIO8 D9

VCCIO8 D11

VCCIO8_V15 E8

C120

4.7 uF

C282

100nF

C105

4.7 uF

C119

4.7 uF

C280

470nF

EP4CE15A115F484

U43B

GNDA1

GNDA22

GNDC5

GNDC9

GNDC11

GNDC12

GNDC14

GNDC16

GNDD3

GNDE20

GNDF3

GNDG2

GNDG20

GNDH8

GNDJ5

GNDJ9

GNDJ19

GNDK3

GNDK10

GNDK11

GNDK12

GNDK13

GNDL10

GNDL11

GNDL12

GNDL13

GNDL20

GNDM10

GNDM11

GNDM12

GNDM13

GNDN3

GNDN10

GNDN11

GNDN12

GNDN13

GNDP19

GNDU3

GNDV20

GNDW3

GNDY5

GNDY9

GNDY11

GNDY12

GNDY16

GNDY18

GNDY20

GNDAA2

GNDAA22

GNDAB1

GNDAB22

GNDA1U5

GNDA2E18

GNDA3F5

GNDA4V18

GND_V15 C18

GND_V15 D7

GND_V15 D8

GND_V15 H3

GND_V15 R3

GND_V15 T20

GND_V15 Y15

GND_V15 AB6

GND_V115 E10

GND_V115 F12

GND_V115 F16

GND_V115 G7

GND_V115 G9

GND_V115 G11

GND_V115 G13

GND_V115 G15

GND_V115 G17

GND_V115 H10

GND_V115 H12

GND_V115 H13

GND_V115 H14

GND_V115 H16

GND_V115 J15

GND_V115 K7

GND_V115 K16

GND_V115 L8

GND_V115 L15

GND_V115 M7

GND_V115 N8

GND_V115 N15

GND_V115 N17

GND_V115 P6

GND_V115 P8

GND_V115 P16

GND_V115 R7

GND_V115 R9

GND_V115 R11

GND_V115 R13

GND_V115 R18

GND_V115 T8

GND_V115 T10

GND_V115 T12

GND_V115 T14

GND_V115 U7

GND_V115 U13

GND_V115 U19

GND_V115 V6

GND_V115 Y21

+ C299DNP

Tantalum

12

C234

10nF

C116

4.7 uF

C117

4.7 uF

L29

MMZ1005S601C

C125

4.7 uF

+ C300DNP

Tantalum

12

C281

470nF

C126

4.7 uF

C278

470nF

C271

4.7nF

C58

100nF

C127

4.7 uF

C283

DNP

+ C301DNP

4VTantalum

12

C128

4.7 uF

C274

470nF

C59

DNP

C233

22nF

+ C297100uF

Tantalum

12

+ C302DNP4V

Tantalum

12

C57

4.7nF

C276

470nF

C235

1uF

+ C298100uF

Tantalum

12

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

In 32-bit GPIF mode UART is (FX3 data pg 33): GPIO[55](C2)=UART_TX GPIO[56](D5]=UART_RXUART_CS was added to allow the FPGA to use the MISO/MOSI lines to communicate via UART with the FX3.CS can also be deasserted to write to flash after boot.

FX3 datasheet pg 7:SPI+USB is primary, USB only should be achievableSPI+USB on failure - PMODE[2:0] = "0F1"USB boot - PMODE[2:0] = "F11"

PMODE[2..0] SPI Flash

FLASH VCC : 1.65V ~ 2V

FX3 GPIF + BOOT

Digital 20mAPlease verify this

Add R257 so that SPI-boot works. C4's HIGH-Z state has a weak pull up, so it can be balanced out with a weak pull-down.

VIO1_FXVIO1_FX

VIO4_FX

VIO4_FX

CVDDQVIO1_FX

FX3_UART_RX

FX3_UART_TX

FX3_PCLK

GPIF0

GPIF1

GPIF5

GPIF4

GPIF6

GPIF7

GPIF8

GPIF9

GPIF10

GPIF11

GPIF12

GPIF13

GPIF14

GPIF15

GPIF16

GPIF17

GPIF18

GPIF19

GPIF20

GPIF21

GPIF22

GPIF23

GPIF24

GPIF25

GPIF26

GPIF27

GPIF28

GPIF29

GPIF30

GPIF31GPIF2

GPIF3

FX3_CTL0

FX3_CTL1

FX3_CTL2

FX3_CTL3

FX3_CTL4

FX3_CTL5

FX3_CTL6

FX3_CTL7

FX3_CTL8

FX3_CTL9

FX3_CTL10

FX3_CTL11

FX3_CTL12

nFX3_UART_CS

FX3_GPIO50

FX3_GPIO51

FX3_GPIO52

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SEC 1/7P - PORT

VIO1

U2A

FX3

INT_N_CTL15 L8

DQ0 F10

DQ1 F9

DQ10 K11

DQ11 L10

DQ12 K10

DQ13 K9

DQ14 J8

DQ15 G8

PCLK J6

CTL0 K8

CTL1 K7

CTL2 J7

DQ2 F7

CTL3 H7

CTL4 G7

CTL5 G6

CTL6 K6

CTL7 H8

CTL8 G5

CTL9 H6

CTL10 K5

CTL11 J5

CTL12 H5

DQ3 G10

PMODE0 G4

PMODE1 H4

PMODE2 L4

DQ4 G9

DQ5 F8

DQ6 H10

DQ7 H9

DQ8 J10

DQ9 J9

RESET_N C5

R610K

C3412.2uF

R710K

R247100K

R2484.7KTP10

S0 - PORTSEC 2/7

VIO2

U2B

FX3

DQ16 K2

DQ17 J4

DQ18 K1

DQ19 J2

DQ20 J3

DQ21 J1

DQ22 H2

DQ23 H3

DQ24 F4

DQ25 G2

DQ26 G3

DQ27 F3

GPIO45 F2

TP12

R2494.7K

TP11

R8DNP

R251

DNP

C77

0.1uF

R910K

R2574.7K

R10DNP

R2504.7K

J68SWITCH

1

A

2

B

S1 - PORT

SEC 3/7

VIO3

VIO4

U2C

FX3

DQ28 F5

DQ29 E1

DQ30 E5

DQ31 E4

I2S-CLK D1

I2S-SD D2

I2S-WS D3

UART-RTS_SPI-SCK D4

UART-CTS_SPI-SSN C1

UART-TX_SPI-MISO C2

UART-RX_SPI-MOSI D5

I2S-MCLK C4

U26

PART_NUMBER = MX25U3235EM2I-10G

Manufacturer = Macronix

HOLD7

VCC 8

CS1

Q2

C6D5

VSS 4W/VPP3

SPI-MISO_UART-TX

SPI-MOSI_UART-RX

GPIF0

GPIF4

GPIF5

GPIF6

GPIF7

GPIF8

GPIF9

GPIF10

GPIF11

GPIF12

GPIF13

GPIF14

GPIF15

GPIF16

GPIF17

GPIF18

GPIF19

GPIF20

GPIF21

GPIF22

GPIF23

GPIF24

GPIF1

GPIF25

GPIF26

GPIF27

GPIF28

GPIF29

GPIF30

GPIF31

FX3_PCLK

GPIF2

GPIF3

FX3_CTL0

FX3_CTL1

FX3_CTL2

FX3_CTL3

FX3_CTL6

FX3_CTL7

FX3_CTL8

FX3_CTL9

FX3_CTL4

FX3_CTL5

FX3_CTL10

FX3_CTL12

FX3_CTL11

PMODE0

PMODE1

PMODE2

PMODE0PMODE1PMODE2

SPI-MISO_UART-TXSPI_CLK

SPI-SSN_UART-CS

SPI-MOSI_UART-RX

SPI_Hold#_flash

SPI_Wp#_flash

SPI-SSN_UART-CS

SPI_CLK

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

FX3 JTAG

FX3 DEBUG + CLOCK SEL

FX3 datasheet pg 8:38.4MHz input CLK - FSLC[2:0] = "110"

FSLC[2..0]

DEBUG TPs Debug LED

FPGA Version ResistorVIO5_FXVIO5_FX

CVDDQ CVDDQ

FX3_CLK

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D10LTST-C190KGKT

R210KTP6

R54

10K

TP1

R55

10K

R310DNP TP2

TP3

R310K

XTAL / CLKSEC 5/7

CVDDQ

U2E

FX3

CLKIN D7

CLKIN_32 D6

FSLC0 B2

FSLC1 B4

FSLC2 E6

XTALIN C6

XTALOUT C7

R51

10K

R110K

SEC 6/7

MISCVIO5

U2F

FX3

I2C-GPIO58_SCL D9

I2C-GPIO59_SDA D10

I2C-GPIO60_CHARGER-DETECT D11

TCK F6

TDI E7

TDO C10

TMS E8

TRST_N B11

R52

10K

JTAG_ICE_CONN

J51

N2520-6002-RB

PART_NUMBER = N2520-6002-RBManufacturer = 3M

VT_REF1

N_TRST3

TDI5

TMS7

TCK9

RTCK11

TDO13

N_SRST15

DBGRQ17

DBGACK19

V_SUPPLY 2

GND1 4

GND2 6

GND3 8

GND4 10

GND5 12

GND6 14

GND7 16

GND8 18

GND9 20

R53

10K

N_SRST

TCK

RTCK

TDI

TDO

TRST_N

TMS

TCK

TDI

TDO

TMS

TRST_N

FX3_I2C_SCL

FX3_I2C_SDA

CHARGER_DETECT

FSLC2 FSLC1 FSLC0

FSLC2

FSLC1

FSLC0

FSLC0

FSLC1

FSLC2

XTALIN

XTALOUT

CLKIN_32

CHARGER_DETECT

FX3_I2C_SCL

FX3_I2C_SDA

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USB3.0 MICRO TYPE B

ESD DEVICE

USB Positive OvervoltageProtection Controller

USB CONNECTIONS

VBUS_IN

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R190 1M

TP7

C43 0.1uF

C46 0.1uF

L2BLM21PG221SN1D

L5BLM21PG221SN1DUSB3TYPEB

U75

VBUS 1

D_M 2

D_P 3

GND 4

SS_TX_N 5

SS_TX_P 6

GND_D 7

SS_RX_N 8

SS_RX_P 9

GND_TAB_1 10

GND_TAB_2 11

R47200

C4 0.1uF

U9

ESD Protector

PART_NUMBER = SP3010-04UTGManufacturer = Littlefuse

8877

66 5 54 4

3 3

2 21 11010

99

C1851uF

R486.04K / 1%

U37

NCP361SNT1G

PART_NUMBER = NCP361SNT1G

Manufacturer = ON Semiconductor

IN1

GND2

OUT 5

FLAG 4

EN_L3

SEC 4/7

U - PORT

VBUS/VBAT

VBUS/VBAT

VBUS

U2D

FX3

DP A9

OTG_ID C9

R_USB2 C8

R_USB3 B3

SSRXM A3SSRXP A4

SSTXM A6SSTXP A5

VBUS E11

DM A10

NC A11

C1861uF

OTG_ID

SS_RX_MSS_RX_P

SS_RX_MSS_RX_P

SS_TX_MSS_TX_P

SS_TX_MSS_TX_P

SS_RX_PSS_RX_M

USB3_VBUS

FLAG

VBUS_IN

VBUS_IN

SS_DPSS_DM

OTG_ID

SS_TX_P

SS_TX_M

USB3_VBUS

VBUS_INSS_DMSS_DP

SS_TX_MSS_TX_P

SS_RX_PSS_RX_M

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

U3RX_VDDQ = V1P2U3TX_VDDQ = V1P2AVDD = V1P2CVDDQ = V1P8VDD = V1P2VIO1 = V1P8VIO2 = V1P8VIO3 = V1P8VIO4 = V1P8VIO5 = V1P8

U3RX_VDDQ

U3TX_VDDQ

AVDD

VDD

VIO1 VIO2

VIO3 VIO4 VIO5

CVDDQ

FPGA VCCIO

VDD+AVDD 1.2V@200mAU3VDDQ 1.8@60mA

FX3 POWER

Changed C103 from 2.2uF to 4.7uF

VIO3_FX

CVDDQ

AVDD_FX

VIO4_FXU3TX_VDDQ

VIO1_FX

VIO5_FX

VIO2_FX

U3RX_VDDQ

VDD_FX

VIO5_FX

AVDD_FX

U3TX_VDDQ

VIO1_FX

VDD_FX

VIO4_FX

VIO2_FX

VIO3_FX

U3RX_VDDQ

V1P2

V1P2

CVDDQ

V1P2

V1P2

VIO1_FX

VCCIO_L_C4

VD1P8

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C91

0.1uF

C114

0.1uF

C88

0.01uF

C83

0.1uF

C102

0.1uF

C113

0.01uF

FB9

MPZ2012S601A

C78

0.1uF

FB7

MPZ2012S601A

C109

0.01uF

C79

0.1uF

C86

0.1uF

C82

0.01uF

C84

0.1uF

C115

0.01uF

FB6

MPZ2012S601A

C87

0.1uF

C81

0.01uF

FB4

MPZ2012S601A

SEC 7/7

POWER

U2G

FX3

AVDDA7

AVSS B7

CVDDQ B6

VDD8B10

VIO5 C11

VIO4 B1

VIO1_1 L9

VIO1_2 H11

VIO2 F1

VIO3 E3

VDD6L5

VDD7J11

U2AFEVSSQ B9

U2PLLVSSQ B8

U3RXVDDQA2

U3TXVDDQB5

U3VSSQ A1

VBAT E10

VDD1H1

VDD2C3

VDD3L7

VDD4E9

VDD5F11

VSS1G1

VSS2L1

VSS3E2

VSS4L6

VSS5D8

VSS6G11

VSS7L11

VSS8K4

VSS9L3

VSS10K3

VSS11L2

VSS12A8

C89

0.1uF

FB8

MPZ2012S601A

C103

4.7 uF

C80

0.1uF

C110

0.1uF

C104

0.1uF

C106

0.1uF

C36322uF

C90

0.01uF

C107

0.01uF

C108

0.1uF

C85

0.01uF

C36422uF

C111

0.01uF

FB5

MPZ2012S601A

C112

0.1uF

C36722uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A APVDDAD33[A-D] are theADC/DAC IO buf Vref pins

PVDDVGGmust be 3.3V

Analog 1.8V Digital 1.8V

PVDDSPI33 is a Vref forthe SPI + PLLCLK.Pin 71,74 need split plane

PLLCLK is Vref'd by PVDDSPI33

Pin 34 is further away from theother pins so parts are replicated

Analog 3.3VAnalog 573.547mA

22mA

Digital 45.51mAAnalog 40mALMS DIGITAL Digital 1.8V

Total 22mA

ESD supply higher currentNeeds MPZ2012S601A

VCCIO_R_C4

V3P3_RX_LMS

V3P3_TX_LMS

VD1P8

V3P3_TX_LMS

VD3P3

VA1P8

V3P3_TX_LMS

VCCIO_R_C4

V3P3_RX_LMS

VCCIO_R_C4_CLK

VD1P8

LMS_TXD1LMS_TXD2LMS_TXD3

LMS_TXD0

LMS_TXD4

LMS_TXD6LMS_TXD7LMS_TXD8

LMS_TXD5

LMS_TXD9

LMS_TXENLMS_TX_CLKLMS_TX_IQ_SEL

LMS_TXD11LMS_TXD10

LMS_RESET

LMS_SENLMS_SCLKLMS_SDIOLMS_SDO

LMS_RXD0LMS_RXD1LMS_RXD2LMS_RXD3LMS_RXD4LMS_RXD5LMS_RXD6LMS_RXD7LMS_RXD8LMS_RXD9LMS_RXD10LMS_RXD11

LMS_RX_IQ_SELLMS_RX_CLKLMS_RXEN

LMS_RX_CLK_OUT

LMS_CLK

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L21MMZ0603S601C

C1991uF

C1880.1uF

L24MMZ0603S601C

L16MMZ0603S601C

C1970.1uF

C2020.1uF

C20610uF

L19MMZ0603S601C

C1960.1uF

L17MMZ0603S601C

R261

22

L22MMZ0603S601C

C2000.1uF

C2081uF

L8MMZ0603S601C

L14MMZ0603S601C

TP13

L25

MMZ0603S601C

C20510uF

L20MMZ0603S601C

R2910

L11MMZ0603S601C

C1890.1uF

TP14

L26

MMZ0603S601C

C1940.1uF

R290DNP

C1910.1uF

L23

MMZ0603S601C

C1900.1uF

C2041uF

C2310.01uF

C2031uF

R288100K

L56MMZ1005S601C

R260

22

C2470.1uF

L9MMZ0603S601C

R2920

C1930.1uF

L10MMZ0603S601C

L30MMZ0603S601C

L18MMZ0603S601C

C1980.1uF

C2071uF

L15MMZ0603S601C

LMS6002D

U1A

RDVDD1833

TXVCCPLL1861

TRXVDDDSM1872

VSPI1873

RXVCCPLL1883

RAVDD1835

TDVDD1836

TXVDDVCO1860

RXVDDVCO1884

TAVDD3337

PVDDSPI3374

PVDDAD33A1PVDDVGG7

PVDDAD33B12

PVDDAD33C18

PVDDAD33D34

TXVCCLPF33 43

TXVCCMIX33 45

TXVCCDRV33 49

TXPVDD33 47

RXVCCMIX33 90

RXVCCLNA33 101

RXPVDD33 107

RXVCCTIA33 109

RXVCCLPF33 111

RXVCCVGA33 112

TXPVDDPLL33A 58

TXPVDDPLL33B 62

TXVCCVCO33 59

TXVCCCHP33 63

RXVCCCHP33 78

RXVCCLOB33 79

RXVCCVCO33 82

RXVCCPLL33 85

RXPVDDPLL33A 86

RXPVDDPLL33B 81

GLOBAL_GND 117

L57MMZ1005S601C

C1920.1uF

C1950.1uF

R289DNP

LMS6002D

U1B

PLLCLK71

TXEN66

TX_CLK19

TX_IQ_SEL20

TXD021

TXD122

TXD223

TXD324

TXD425

TXD526

TXD627

TXD728

TXD829

TXD930

TXD1031

TXD1132

RXEN 76

RX_CLK 17

RX_IQ_SEL 16

RXD0 15

RXD1 14

RXD2 13

RXD3 10

RXD4 11

RXD5 8

RXD6 9

RXD7 6

RXD8 5

RXD9 4

RXD10 3

RXD11 2

RESET75

SEN67

SCLK70

SDIO69

SDO68

RX_CLK_OUT 40

TSTD_OUT1 65TSTD_OUT2 77

L7MMZ0603S601C

C1870.1uF

C2010.1uF

LMS_TX_CLKLMS_TX_IQ_SELLMS_TXD0LMS_TXD1LMS_TXD2LMS_TXD3LMS_TXD4LMS_TXD5LMS_TXD6LMS_TXD7LMS_TXD8LMS_TXD9LMS_TXD10LMS_TXD11

LMS_RXENLMS_RX_CLK

LMS_RX_IQ_SELLMS_RXD0LMS_RXD1LMS_RXD2LMS_RXD3LMS_RXD4LMS_RXD5LMS_RXD6LMS_RXD7LMS_RXD8LMS_RXD9LMS_RXD10LMS_RXD11

LMS_SENLMS_SCLKLMS_SDIOLMS_SDO

LMS_RESET

RXVCCPLL18RAVDD18

TXVDDVCO18

RXVDDVCO18

LMS_RX_CLK_OUT

LMS_RESET

LMS_TX_EN

LMS_RXEN

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LMS ANALOG + RF

300MHz - 2.8GHz

1.5GHz - 3.8GHz

1.5GHz - 3.8GHz

300MHz - 2.8GHz

RF Shield tabs

V3P3_TX_LMS

V3P3_TX_LMS

LMS_RX_V1

LMS_RX_V2

LMS_TX_V2

LMS_TX_V1

LMS_PLLOUT

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C237

1uF

R26851

C328100pF

C31720pF

J60

PWR_HDR6

1

2

3 4

6

5

C224

0.1uF

RFSHIELDTAB

U70

GND1

L43 2.7nH

C240

1uF

R26951

R28251

C226

0.1uF

C32120pF

R2706800

ESD0P8RFLU41

3D

2N

4D

1P1

D1N

2D

2P

R27951

L32 2.7nH

L37DNP

ESD0P8RFLU46

3D

2N

4D

1P1

D1N

2D

2P

C209470pF

L44 2.7nH

C2150.1uF J53

SMA

GN

D1

3G

ND

2IN

C31820pF

C2108.2nF

R263

1.2K

L36

TC1-1-43+

1SD

2 NC3 S 4P

6PD

R265

1.2K

C2458.2nF

J54

SMA

GN

D1

3G

ND

2IN

C211150pF

L40

TC1-1-13M

1SD

2 NC3 S 4P

6PD

C2468.2nF

C223

DNP

C3316.8pF

L33 2.7nH

C32320pF

R27112K

C2438.2nF

C3163.6pF

C3243.6pF

R272390

RFSHIELDTAB

U73

GND1

L3436nH

AS211-334

U62J31GND2J23

V1 4J1 5V2 6

C2448.2nF

L3536nH

C3226.8pF

C31920pF

L31

TC1-1-13M

1SD

2 NC3 S 4P

6PD

C30920pF

AS211-334

U63

J31

GND2

J23

V1 4

J1 5

V2 6

TP17

R264820

RFSHIELDTAB

U72

GND1

L42

TC1-1-43+

1SD

2 NC3 S 4P

6PD

C32020pF

C31020pF

C212470pF

C225

DNP

C3123.6pF

J61

PWR_HDR6

1

2

34

6

5

R26651

C3253.6pF

C3143.6pF

L3836nH

C213150pF

C3133.6pF

L41DNP

RFSHIELDTAB

U71

GND1

R262820

LMS6002D

U1D

TXOUT1P 48

TXOUT1N 50

TXOUT2N 44

TXOUT2P 46

OEXLNA1P 91

IEXMIX1P 92

IEXMIX1N 94

OEXLNA1N 95

RXIN1EP 97

RXIN1EN 99

RXIN1P 96

RXIN1N 98

RXIN2P 100

RXIN2N 102

OEXLNA2P 103

IEXMIX2P 104

IEXMIX2N 106

OEXLNA2N 105

RXIN3P 108

RXIN3N 110LMS6002D

U1C

TXINIP52

TXININ51

TXINQP54

TXINQN56

TXCPOUT64

TXVTUNE57

RXOUTIP116

RXOUTIN115

RXOUTQP113

RXOUTQN114

RXCPOUT80

RXVTUNE87

XRES12K89

XRESAD39

VREFAD38

ATP42

PLLCLKOUT41

UNUSED53

UNUSED55

UNUSED88

UNUSED93C326

3.6pF

R26751

C2148.2nF

L3936nH

C3153.6pF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

These caps have to be closeto their respective Vref pins.

CLOCKS

Digital 10mA

Digital 1mA

1.32KHz RC filter

Cap goes

between 2 and 4

Analog 2mA

V3P58

VCCIO_L_C4

VCCIO_R_C4_CLK

VA2P5V3P3_RX_LMS

VCCIO_R_C4

LMS_CLK

DAC_SDODAC_SDIDAC_SCLKDAC_CSB

EXP_CLK

C4_CLK

LMS_TX_CLK

LMS_RX_CLK

SI_SCLSI_SDA

C4_TX_CLK

FX3_CLK

Title


Date: Sheet of

<Doc> A

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Title


Date: Sheet of

<Doc> A

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Date: Sheet of

<Doc> A

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TP40

L50MMZ1005S601C

L46

MMZ1005S601C

C2290.01uF

TP29

L47MMZ1005S601C

CDC3RL02

U67

VBATTA1

VLDOB1

MCLK_INC1

GNDD1

CLK_OUT1 A2

CLK_REQ1 B2

CLK_REQ2 C2

CLK_OUT2 D2

R2771.2K

C3480.022uFL53

MMZ1005S601C

R284200

C2201uF

C2300.1uF

TC1014-3.0VCT713

U55

VIN1

GND2SHDN3

BYPASS 4

OUT 5

C2180.1uF

C3651uF

D1LTST-C190KGKT

Si5338

U68

IN11

IN22

IN33

IN44

IN55

IN66

CLK2B 13CLK2A 14VDDO2 15

VDDO1 16

CLK1B 17CLK1A 18

SDA19

VDDO0 20

CLK0B 21

CLK0A 22

RSV

D_G

ND

23

VDD

224

VDD

17

INTR8 CLK3B 9CLK3A 10VDDO3 11

SCL12

GN

D_P

AD25

TP30

J62

SMB

3G

ND

1IN

2

GN

D5

GN

D

4

GN

D

L52MMZ1005S601C

L51MMZ1005S601C

C362470pF

TP31C3450.022uFTP32

C3692.2uF

TP33

C2190.1uF

L55MMZ1005S601C

TP34

C2210.1uF

ASVTX-12-A-38.400MHZ-H10-T

U42

CLK 3

VCC

1

VDD

4

GND2

L48

MMZ1005S601C

C2160.1uF

DAC161S055

U56

VA1

VOUT 2

NC1 3

NC2 4

NC3 5

VREF

6

GN

D7

NC4 8

SDO9

SCLK10 SDI11

CSB12

LDACB13

CLRB14

MZB

15

VDDIO16

GN

D_P

AD17

C2220.1uF

R275

1.2K

C2170.1uF

L28

MM

Z100

5S60

1C

SMB_CAP

SMB_CAP

SMB_CAP

V1P8_CLK

V1P8_CLK

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

19.5mOhm

2mOhm

2mOhm

Ceramic caps will suffice

Ceramic caps will suffice

Analog 3.3V 280mA / 500mA


Digital 3.3V 106mA / 200mA

Digital 1.8V 190mA / 400mA

Analog 1.8V ~100mA / 200mA

1.2V (min:200mA, typ:800mA) / 3100mA / 90% eff

3.58V ~800mA / 1300mA / 95% eff

POWER DISTRIBUTIONThe idea is to drop to 1.2V and 3.58V with SMPS.Then drop to 3.3, 2.5, 1.8 from the 3.58V SMPS.

LMS - 67.1mAFPGA - 25mAFX3 - 25 mAClocks - XOs - 20mASPI flash - 20mA max (verify this)

10mOhm

2mOhm

2mOhm

VDO @ 200mA typ:90mV max:160mV

VDO @ 500mA 100mV

VDO @ 500mA 100mV

2mOhm


V3P58

VA1P8

VD1P8

V3P3_RX_LMS

V3P3_TX_LMS

V1P2

VD3P3

VA2P5

V5P0

V5P0

Title


Date: Sheet of

Power A

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Title


Date: Sheet of

Power A

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Title


Date: Sheet of

Power A

Nuand

B


C3611uF

C3352.2uF

R28036.5K

C3496.8nF

C3382.2uF

C35922uF

C3572.2uF

C3440.01uF

C3581uF

R3041

C35022uF

R28110.5K

TC1185-2.5VCT713

U66

VIN1

GND2SHDN3

BYPASS 4

OUT 5

C366470pF

C3511uF

FB14

MPZ2012S601A

R299154K

FB11

MPZ2012S601A

TPS79933DDCT

U65

EN3 IN1

GND2

OUT 5

NR/FB 4

R3051

C3462.2uF

R3034.32K

C3305.6nF

C3391uF

C35422uF

L49

4uH

C3552.2uF

FB15

MPZ2012S601A

C36822uF

TPS79533DCQR

U54

EN1

IN2

GND 3OUT 4

NR/FB5 GND 6

C3420.01uF

R30011.8K

C3470.01uF

R285100K

FB12

MPZ2012S601A

C3402.2uF

TPS73618DBVT

U50

IN1

GND2EN3

OUT 5

NR 4

R3015.9K

C3276.8nF

C3562.2uF

TPS79318DBVR

U49

IN1

GND2EN3

OUT 5

NR 4C3600.1uF

FB16

MPZ2012S601A

C32922uF

C3360.01uF

R306

49.9K

C35210nF

R2832.32K

FB13

MPZ2012S601A

C3432.2uF

R302

49.9K

TPS79533DCQR

U53

EN1

IN2

GND 3OUT 4

NR/FB5 GND 6

LM20145

U58

SS/TRK 1

FB 2

PGOOD 3

COMP4

NC5

PVIN6 PVIN7

SW 8SW 9

PGN

D10

PGN

D11

EN12

VCC 13

AVIN14

AGN

D15

RT16

GN

DPA

D17

LM20143

U48

SS/TRK 1

FB 2

PGOOD 3

COMP4

NC5

PVIN6 PVIN7

SW 8SW 9

PGN

D10

PGN

D11

EN12

VCC 13

AVIN14

AGN

D15

RT16

GN

DPA

D17 C333

0.01uF

C3342.2uF

L45

3.3uH

C33222uF

C3530.1uF

C3372.2uF

V3P58

V3P58

V3P58

V3P58

V3P58

V3P58

V3P58

V1P2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Scatter these testpoints throughout the design.Testpoints will be PTH

POWER SELECTION + DEBUG

Jumpered power selection DC barrel vs USB3 bus

VDC

VBUS_IN

V5P0

Title


Date: Sheet of

<Doc> A

Nuand

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Title


Date: Sheet of

<Doc> A

Nuand

B


Title


Date: Sheet of

<Doc> A

Nuand

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+ C122

100uF_10V

+ C124

330uF_10V

+C121

100uF_10V

+C123

330uF_10V

TP39

J49

RAPC712X

PART_NUMBER = RAPC712XManufacturer = Switchcraft Inc.

3

21

J70

PWR_HDR6

1

2

3 4

6

5

TP23

THIS DOCUMENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS ORCOPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE DOCUMENT OR THE USE OR OTHER DEALINGS IN THE DOCUMENT.

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