Nuovo Documento Di Testoljj

8/1/2019 Nuovo Documento Di Testoljj

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PrtparnjeaspektsasiortdallimitRISC/CISC,letmarrimnjshembullqkaumziminedynumrave:

TshkruhetproceduraqllogaritproduktinP=10X5nnjkompjutermeprocesorCISChepastajnnjRISC.CISC

movax,10

movbx,5

mulbx,axRISC

movax,0

movbx,10

movcx,5

begin:addax,bx;loopdoteekzekutohet5her(vleranCX)

loopbegin

Llogaritimnumrineciklevetclockutprdysekuencatemsiprmetinstruksioneve:CISC:Numriiciklevetclokutdotjet:

(2inst.movx1cikl)+(1inst.mulx30cikle)=32cikleclocku

RISC:Numriiciklevetclokutdotjet:

(3inst.movx1cikl)+(5inst.addx1cikl)+(5inst.loopx1cikl)=13cikleclocku

Dukeunisurngaekuacionithemelorillogritjessperformancavetnjprocesori:

KOHAexe=NI*CPI*Tc

Ku:

-NI:Numriiinstruksionevetprogramit.

-CPI:CiklePrInstruksiondheshprehnumrinmesatartciklevetclockuttnevojhmprekzekutiminenjinstruksioni.

-Tc:Eshtkohzgjatjaenjcikliclockudheshtfunksioniteknologjissprdo

mundtnxjerrimsiprfundim:

ProcesortCISC:KrkojntzvoglojnkohneekzekutimittnjprogramidukeredineinstruksionveNI.

ProcesortRISC:Krkojntzvoglojnkohneekzekutimittnjprogramidukeredineciklevetclockutprinstruksion(CPI).

Prciklclocku(Tc)tnjjt,kohaeekzekutimittproduktitP=10x5dotjetmeprprocesorinRISCnkrahasimmeatCISC(13/32cikleclocku).Pra,prfundimisht,rastinnfjal,procesoriRISCrezultonmperformantseCISC.


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Koment:,ShrimiProcesortdotjudrgojnprnjanaliztthelltarkitekturavessingUnitoseCPU-s.Dotflitetprhistorin,instrukcioneteprocesorve,tipatCdheRISC,FloatingPointUnitdheshumpjestjeraqjantlidhurametemneProe.Autoret(Kontribuesit):FisnikBullatovciBesimIsmailiBesnikDuriqingaFakultetiElektroteknik,Prishtine,Kosov

CPUnjprshkrimishkurtHistoriaeCPUfilloim1971,kurnjkompaniepanjohur,Intel,prhertparkombtranzistortshumfishtprtformuarnjqendrprocesimitprbashkt-ipiuquajAshtu,siishte8vjetmvonukonstruktuakompjuteriparpersonal..PC(kompjutertpersonal)kanqentdisajnuarngagjeneratatndryshmetprocesor).Intelnukshtevetmjakompaniqmerretmemanifakturimineprocesorve(CPU-ve)

,poataishintpartdhengelnmtmirt.TabelaeardhshmetregonllojetendrysgjenerataveCPU-ve.ShohimsedominantjanipatIntel,porngjeneratnepestneimalternativatjera:

CkashtCPU-ja?

CPU-janprgjithsishtevendosurnpllaknsistemore.MeqCPU-jaikryennjpunpjuter,tdhntkalojnvazhdimishtnprat.doinstruksionshtudhzimprprocetpunaprbhetkalkulimitdhetransportinetdhnave.

TdhnatekanrrugnevetderiteCPU-ja.shtsinjllojautostradeequajturbus'.

Dyllojetetdhnave

CPU-jafurnizohetmetdhnanprmjetsystembusit.CPUpranonspakudyllojetet:

-Instruksionetprtrajtiminetdhnave-Tdhnat,tcilatduhetttrajtohensipasinstruksionve

Instruksionequajmkodinprogramor.Kjoprfshinatomesazhe,tecilatqohenvazhdimishtnkompjuterprmesmausitapotastiers.Mesazhtprshtypje,ruajtjeetj.

8086instruksionetkompatibile

PunamemadheeCPU-nshtdekodimiiinstruksionvedhelokalizimiitedhnave.Vkuliminukhstpunevshtir.


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Dekodimiprbhetprejkuptimittinstruksionve,tcilatprogramiprdoruesIonnithaCPU-tpersonaljan'8086kompatibil'.KjodotthotseprogrametkomunikojnmePU-nnnjfamiljetcaktuarinstruksionesh.KtoinstruksionetjanorigjinalishttshkruaraprIntel8086procesor,tcilatkauarkonceptin'IBMkompatibilkompjuter'.8086Ivitit1978kapranuarinstruksionetnnjformattcaktuar.MeqkaekzistuardshiraqgjeneratateardhshmeteCPUkenmundsit'itrajtojntnjjtatinstruksionettcilat8086kamundur,kaqenenevojshmeqinstrionettjenkompatibile.CPU-trejaduhejt'ikuptojntnjejtatinstruksionet.

Tgjithprocesorteripamarparasyshsatavancumjanduhentjenngjendjeormatineinstruksionvet8086.

CISCdheRISCinstruksionetdhemanovrimimeto

CPUiparkapastashtuquajtur'ComplexInstructionSet(CISC)'.Kjodotthotseompjutertmundt'ikuptojnshuminstruksionekomplekse.GrupiiinstruksionveX86menjgjatsiprej8derin120bit,kaqenidizajnuarpr8086me29000tranzistora

ReducedInstructionSetCompjuter(RISC).InstruksionetRISCjantshkurtradhemegjatsi(prshembull32bita,njjtsitepentiumiPro),dheatoprocesojnshumpejtseCISCinstruksionet.PrktarsyeRISCprdoredntgjithaprocesorteri.Meproblemiqndronneatseinstruksionetarijnenprocesornformatin8086.Prandajd

hentkodohen.Prdogjenerattretprocesorvegrupiiinstruksioneveshtzgjeruar.386kaar6instruksionetreja,486me6instruksionetrejadhePentiumime8instruksionetreja.Ktondryshimekanbrqdisaprogrametkrkojnspaku386apopentiumtpunuar.

Floating-pointunitFPU

Procesoriiparkamundurtpunojvetmmenumratplot.Prktarsyekaqenenhtohetedhenjbashk-procesor(FPU).MvonFPUshtinstaluarnprocesor:

ThuhetseprocesorteIntelitkanFPUmtmir.ProcesortprejAMDdhetCYRIXkaniontmirnlidhjemeFPU.MirpojotgjithaprogrameeperdorinFPU-n.PrshumiruesveFPUjaluanpakdifirenc.

Shumemratndryshm

Ekzistojnprocesorttprodhuesvetndryshm(IBM,Texas,Cyrix,AMD),dheshumicnstveatoprodhojnmodeleqjansiurkaluesendrmjetdygjeneratve.Kjomundtsjitevshtirsimiiidentifikimittprocesorve.

Procesortzhvillimetdheprmisimet

Shumicaetdhnaveprocesohetbrendaprocesorit.Megjithattgjithatdhnaduhensportohenndheprejprocesoritnprmjetsystembus.Porkaeprcaktonshpejtsineesorit?

Clockfrequenci(Frekuencakohore)

Neshpeshdgjojm:Pentium250MHZapoPentium500MHZ.500MHZshtfrekuencakohor


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e.Aktualishtekzistonnjkristalivoglnpllaknsistemoreicilivazhdimishttikonprocesormenjnumrtbarabartttik-takvetorsprsekond.Prdotikdik.Prandajsamshumtik-takaprsekondaqmshumtdhnashprocesohennprocesord.

Procesoriiparkapunuarnnjfrekuencprej4.77MHZ.Prejateherfrekuencatjanrn16.25,90,133,200,250etj.Frekuencatjandukeuritur.

CashRAMiProcesorit

Procesoriduhettdrgojtdhnatnnjshpejtsishumtmadhe.RAM-ttzakonshmllojnshpejtsitetilla.PrktarsyenjRAMspecialiquajturcacheprdoretsib(deponimiprkohshm).Prtfituarperformansamtmiraprejprocesoritnumriaksionvedalseduhettminimizohet.Samshumtransmisioneqmbahenbrendaprocesoqmtmiradotjenperformansa.486kaqenipajisurmeFLOdhe8KBL1-cachmemori.Ktodytiparekanendihmuarnminimiziminerrjedhjessetdhnavendheprejprocesorit.

Fushatezhvillimit

Kurishiqojmprocesortindividualshpejtsiashttiparmirndesishm.Tgjithrimundtkryejnpunnenjjt.Ofisi97mundprdoretnindos95apoedhen386umngadalshmporshtemundshme.Shpejtsiashtdallimkryesorndrmjetprocesorve.

Ekzistojnshummetodaprmatjeneshpejtsissprocesorve.PrshumviteNortonSpkaqennjmetodshumeaplikuar.Mposhtshtdhntabelameqtregonshpejtyshmetprocesorve.

Ndryshimenprocesor-rishikimhistorik

8088dhe8086:Procesoriiparpersonalkaqen8088.shtprocesor16bitshdhemestembusprej8bitsh.

80286kaqennjprparimimadh.Frekuencashtriturporprmirsimimimadhkaiminetrajtimittinstruksionve.80386shtprodhuarnfundtviteve80,dhekaqenprocesoriipar32bitsh

80486:Nprgjithsi486shtprdyhermishpejtseparaardhsitetij.Kjoshtmentiminmtmirtinstruksionvex86.

Gjenerataepestdheegjashteprocesorve

PentiumClassic(P54C)

KyipshtndrtuarngaIntelinHaifa,Israel.Procesorishtsuperskalar,dotdettekzekutojmshumsenjinstruksionprnjsinjaltors.Nkohnenjjtkmetmdhajansystembus:gjrsiashtdyfishuarne64bitdheshpejtsiashtr


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66MHZ.Kjorezultonnprmirsimesubstancialeprej486teknologjis.NfillimPentiumiuparaqitndyverzione:60MHZdhe66MHZ.Tdytkanoperun5.Kjokaprodhunxehtsitmadhe.GjenerataeardhshmeePentiumit(P45C)kapastndrtume1,5ortdyfishuar,dhekapunuarn3,5Volt.Kkarezultuarnelimineproblemitttejnxemjes.Prejather,IntelikaprodhuardylinjatPentiumit:atoqpunojnnshpejtsi60systembus(P90,P120,P150,dheP180)dheatoqpunojnnshpejtsi66MHZnsystembus(P100,P133,P166dheP200)

Ftohja

Tgjithprocesorterikannevojprftohje.Ftohsiduhett'iprshtatetmadhsis:-Duhettngjitetnmenyrtrregulltprprocesorosemengjitsapodikatjetr.-Duhettketventilatormemadhsitkonsideruar,samimadhaqmimir.-Ventilatoriduhettvendosetnnjcilindrqtminimizohetzhurma.Mektoshtesaprocesoridotjetmiqndrueshmdhemjetgjat.

PentiumMMX(P55C)

MMXparaqetnjgruptriinstruksionesh(57instruksionetrejaintegjer,katrlljetrejatdhnashdhe64bitregjistra).

P55CPentiumajantprmirsuaredheme32KBL1cache.Tgjithaktoprmirsimeeefikasitetineprocesoritpr10%-20%.

AMD

AMDshtnjtjetrllojiprocesorit.AMDprdorteknologjitvetdhenukjankopumit.AMDikaktoseri:

-K5,qiprngjanPentiumitpaMMX-K6,qkonkuronmePentiumMMXdhePentiumII-K7,qvjennvitin1999dhenukshtsocked7kompatibil.

K5

K5ikaperformansagatisitPentiumitP133porpunonnshpejtsi100MHZ.K5iAMDgjithashtuekzistonedhesiPR166dhekonkuronmeP166tIntelit.PrparsiaeAMDshtsekushtonmlirsePentiumeteIntelit.

K6

K6iAMDshtdelnvitin1997.KyprocesorikaperformansamtmirasePentiumMMhtipajisurme32+32KBL1cachedheMMX.Ikanvete8.8miliontranzistor.

CYRIX6X86MX(M2)

Cyrixkagjithashtuprocesortmeperformansatlarta,tvendosurndrmjetgjenerattpestdhetgjasht.shtquajtursiM2porshtriemruarsi6X86MX.


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6X86MXka64KBL1cacheqshtsumimpresive.AtogjithashtuprdorinteknologjiqhtgjeturtePentiumiMMX.MundtkrahasohenmePentiumtvrtetedhepseshpejtsimbrenshmeetyreshtmevogl.

PentiumPro

PentiumProshtnjRISCprocesoripastr.shtoptimizuarprprocesim32bitshnOS/2.shtunikprshkaktL2cachtinstaluar.Kjoiprngjandyprocesorvenn

ZhvillimiiPentiumProkafilluarnvitin1991nOregon.shtparaqiturnfundt1995.Veoriterejaishin:

-IndrtuarnL2cacheme256KBapo512KB.Kjoshtelidhurmeporocesorinmean4bit'backsidebus'.

5,5miliontranzistoranprocesor,15milionpr256KBSRAML2cache(6tranzistorprbit).4gypaprekzekutimineinstruksionvenjkohsishtProtokoltpatentuar.Procesorttjernukmundtprdorin'PentiumProsocket'dhe'cset'.

PentiumII

PentiumPro"Klamath"shtemriikoduariprocesorittritIntelit.shtpjesrisrsuardhepjesrishtireduktuar.KonstruksioniiPentiumIIshtinteresantporedheontraverzal:

-MeMMXinstruksione

-Tprmirsuarekzekutimineprogramve16bitsh

TprmirsuardhetdyfishuarL1cache(16KB+16KB)

Shpejtsiaebrendshmeeritur:prej233MHZderin333MHZ.

NdryshimimimadhshtndarjaeprocesoritngaL2cach.PentiumIIshtnjkubimadhplastikqnvetiprmbanprocesorindhecach.Atygjishtevendosurnjkontrollorivogldhenjftohsidizajnuarmir.

PentiumII-SX,Celeron

IntelikakrijuarnjprocesortritquajturCeleron.KyshtnjPentiumIIvetmachekatlarguar.Prdor'CovingtonCore'dhemundt'aquajmPentiumII-SX.MvonnteliendronPentiumMMXmeCeleron.

PentiumIIXeon

Nkorriktvitit1998InteliparaqetediciontritPentiumII.ProcesorishtemntiumIIXeon.

Kyprocesorkrkonversiontritslotitnj(slotidy).ModulidotkettnjjtatnesiPentiumIIimparshm,porjandisarisidheprmirsimeqduhentprmende


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-100MHZsystembusmeortdyfishuar4.0dhe4.5(qdotthotsedotketshpeendshme400/450MHZ).-LlojetritL2cach:CSRAM,qmundettpunojnshpejtsitplottprocesori

512,1.024ose2.048KBL2RAM

Derin4GBRAMmundtvendoset.

TensioniTensioniidyfisht

Njprejteknologjivemtrejatprocesorveshtedhefutjaetelavemthollnsorit.KjorezultonnprodhimmtvogltnxehtsisdhemeaftsinqtpunojnshNjhapetjetrdrejtprmirsimitshtedhedizajnimiiprocesorvemetensiontdyf

Pllakaterejasistemorekandypjestregullatoritttensionitprtibrballnprocesorit.

LigjiiMurit

Procesortekandyfishuarkapacitetinetyredo18muaj.Kyndryshimquhet'Ligjii

Murit'shtparaparnvitin1965ngaGordonMoore.Ligjiitijkavlejturpr30v.PornseLigjiiMuritvlenedhentardhmenathermshumtranzistoraduhettnshtrestsilikonit.

RISCvsCISCisatopicquitepopularontheNet.EverytimeIntel(CISC)orApple(RISC)introducesanewCPU,thetopicpopsupagain.ButwhatareCISCandRISCexactly,andisoneofthemreallybetter?ThisarticletriestoexplaininsimpletermswhatRISCandCISCareandwhatth

efuturemightbringforthebothofthem.Thisarticleisbynomeansintendedasanarticlepro-RISCorpro-CISC.YoudrawyourownconclusionsCISCPronouncedsisk,andstandsforComplexInstructionSetComputer.MostPC'suseCPUbasedonthisarchitecture.ForinstanceIntelandAMDCPU'sarebasedonCISCarchitectures.TypicallyCISCchipshavealargeamountofdifferentandcomplexinstructions.Thephilosophybehinditisthathardwareisalwaysfasterthansoftware,thereforeoneshouldmakeapowerfulinstructionset,whichprovidesprogrammerswithassemblyinstructionstodoalotwithshortprograms.IncommonCISCchipsarerelativelyslow(comparedtoRISCchips)perinstruction,butuselittle(lessthanRISC)instructions.RISC

Pronouncedrisk,andstandsforReducedInstructionSetComputer.RISCchipsevolvedaroundthemid-1980asareactionatCISCchips.ThephilosophybehinditisthatalmostnooneusescomplexassemblylanguageinstructionsasusedbyCISC,andpeoplemostlyusecompilerswhichneverusecomplexinstructions.AppleforinstanceusesRISCchips.Thereforefewer,simplerandfasterinstructionswouldbebetter,thanthelarge,complexandslowerCISCinstructions.However,moreinstructionsareneededtoaccomplishatask.AnotheradvantageofRISCisthat-intheory-becauseofthemoresimpleinstructions,RISCchipsrequirefewertransistors,whichmakesthemeasiertodesig


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nandcheapertoproduce.Finally,it'seasiertowritepowerfuloptimisedcompilers,sincefewerinstructionsexist.

RISCvsCISCThereisstillconsiderablecontroversyamongexpertsaboutwhicharchitectureisbetter.SomesaythatRISCischeaperandfasterandthereforthearchitectureofthefuture.Othersnotethatbymakingthehardwaresimpler,RISCputsagreaterburdenonthesoftware.Softwareneedstobecomemorecomplex.Softwaredevelopersneedtowritemorelinesforthesametasks.ThereforetheyarguethatRISCisnotthearchitectureofthefuture,sinceconventionalCISCchipsarebecomingfasterandcheaperanyway.RISChasnowexistedmorethan10yearsandhasn'tbeenabletokickCISCoutofthemarket.IfweforgetabouttheembeddedmarketandmainlylookatthemarketforPC's,workstationsandserversIguessaleast75%oftheprocessorsarebasedontheCISCarchitecture.Mostofthemthex86standard(Intel,AMD,etc.),buteveninthemainframeterritoryCISCisdominantviatheIBM/390chip.LookslikeCISCisheretostayIsRISCthanreallynotbetter?Theanswerisn'tquitethatsimple.RISCandCISCarchitecturesarebecomingmoreandmorealike.Manyoftoday'sRISCchipssupportjustasmanyinstructionsasyesterday'sCISCchips.ThePowerPC601,forexample,supportsmoreinstructionsthanthePentium.Yetthe601isconsideredaRISCchip,whilethePentiumisdefinitelyCISC.Furthermoretoday'sCISCchip

susemanytechniquesformerlyassociatedwithRISCchips.

name="CISC">CISC

InstructionSet:largesetofinstructionwithvariablesize(16to64)AddressingModes:12-24GeneralPurposeregisters:8-24Clockrate:33-50MHzin1992

RISC

InstructionSet:Smallsetofinstructionwithfixedsize(32-bit)AddressingModes:3-5GeneralPurposeregisters:32-192Clockrate:50-150MHzin1993

Readmore:http://wiki.answers.com/Q/10_differences_between_RISC_and_CISC#ixzz1tz5oR4eP


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RISCisReducedInstructionSetComputer.CISCisComplexInstructionSetComputer.

RISChasfewerinstructionsandasimplerarchitecture.Thetradeoffisperformance,becausetheRISCisoftensomuchfasterthanaCISCthattheendresultisbetterperformance.

TheIA-32architecturepresentlyusedinmostPC'sisaCISC.TheIBM9113-550isanexampleofaRISC.CISCstandsforComplexInstructionSetComputer.

CISCchipsarerelativelyslowperinstruction,butuselittleinstructions

RISCstandsforReducedInstructionSetComputer.

Afewer,simplerandfasterinstructionswouldbebetter,thanthelarge,complexandslowerCISCinstructions.However,moreinstructionsareneededtoaccomplishatask.

It'seasiertowritepowerfuloptimisedcompilers,sincefewerinstructionsexist.CISCstandsforComplexInstructionSetComputer.

CISCchipsarerelativelyslowperinstruction,butuselittleinstructionsRISCstandsforReducedInstructionSetComputer.

Afewer,simplerandfasterinstructionswouldbebetter,thanthelarge,complexandslowerCISCinstructions.However,moreinstructionsareneededtoaccomplishatask.

It'seasiertowritepowerfuloptimisedcompilers,sincefewerinstructionsexist.CISCRISCEmphasisonhardwareEmphasisonsoftwareIncludesmulti-clockcomplexinstructionsSingle-clock,reducedinstructiononlyMemory-to-memory:

"LOAD"and"STORE"incorporatedininstructionsRegistertoregister:"LOAD"and"STORE"areindependentinstructionsSmallcodesizes,highcyclespersecondLowcyclespersecond,largecodesizesTransistorsusedforstoringcomplexinstructionsSpendsmoretransistorsonmemoryregistersRegards,FoadGodarzyNSWER:IbelieveaCISCprocessorisa32bitprocessorandaRISCisa64bitprocessorRISCisananagramforreducedinstructionsetcomputing.

CISCisananagramforcomplexinstructionsetcomputing.ARISCprocessorisoptimisedtohaveareducednumberofopcodeswhichusetheleastnumberofprocessorcyclestoexecute.Thisproducesveryfastmachinecodesincewastefulcomplextimeconsuminginstructionsarenotavailablefortheprogrammertouse.ACISCprocessoristheoppositeofaRISCprocessor.Ithasawidevarietyofopcodestouse,manyofwhichtakemultiplecyclestocomplete.Thisprovidesmorecodeflexibilitybutreducestheoverallspeedefficiency.RISCstandsforReducedInstructionSetComputer


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CISCstandsforComplexInstructionSetComputer

RISCprocessorshaveasimplersetofmachineinstructionsthanCISCprocessors,butareintendedtobemoreefficientandflexibleinprocessingprogramsanddata.

Becauseofthereducedinstructionset,RISCprocessorsdemandmoreeffortonthepartofthecompiler(nottheenduser)anduselongermachinelanguageprograms.

RISCprocessorsaremoreflexibleinthesensethattheyarenotaspreconfiguredinhowtheyprocessprogramsanddata.

CISCmicroprocessorsactuallyprecededRISCmicroprocessorsandwerederivedfrommicrocontrollerbasedmini-computerssuchastheHP2100.

SeetheWikipediaentrieson"ComplexInstructionSetComputer"and"ReducedInstructionSetComputer"formore.

riscisreducedinstructionset,cisciscomplicatedinstructionset.Soariscprocessorcanhandlesimplemathfunctionsmuchfaster,butaciscprocessorwillhandlecomplicatedfunctionsfasterbecauseitcandothemallatonceinsteadoftheseveralprocessingcommandsthatariscprocessorwouldhavetotaketocompletethesamefunction.

Readmore:http://wiki.answers.com/Q/What_is_the_main_difference_between_RISC_and_CISC_in_computer_science#ixzz1tz61AwRO

RISCvsCISC

RISC(ReducedInstructionSetComputing)andCISC(ComplexInstructionSetComputing)aretwocomputerarchitecturesthatarepredominantlyusednowadays.ThemaindifferencebetweenRISCandCISCisinthenumberofcomputingcycleseachoftheirinstructionstake.WithCISC,eachinstructionmayutilizeamuchgreaternumberofcyclesbeforecompletionthaninRISC.

Thereasonbehindthedifferenceinnumberofcyclesutilizedisthecomplexityandgoaloftheirinstructions.InRISC,eachinstructionisonlymeanttoachieveaverysmalltask.Soifyouwantacomplextaskdone,thenyouneedalotoftheseinstructionsstrungtogether.WithCISC,eachinstructionissimilartoahighlevellanguagecode.Youonlyneedafewinstructionstogetwhatyouwantaseachinstructiondoesalot.

Intermsofthelistofavailableinstructions,RISChasthelongeroneoverCISC.Thisisbecauseeachsmallstepmayneedaseparateinstruction,unlikeinCISCwhereasingleinstructionwouldalreadycovermultiplesteps.AlthoughCISCmaybeeasierforprogrammers,italsohasitsdownside.UsingCISCmaynotbeasefficientaswhenyouuseRISC.ThisisbecauseinefficienciesintheCISCcodewillthenbeusedagainandagain,leadingtowastedcycles.UsingRISCallowstheprogrammertoremoveunnecessarycodeandpreventwastingcycles.

Thepreviousdifferencesmaymakesensetothosewhoaretechnologicallyincline


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d.Butformostpeople,itwouldbegibberish.Tomakeiteasiertounderstand,itisbettertolookatwherethetwoarebeingused.CISChasmanagedtogainanearlyleadincomputingwiththedominanceofIntelsx86architecture,whichisthebasisforallothermoderncomputerarchitectures.Incontrast,RISChasmanagedtoworkitswayintoportabledeviceslikesmartphones,tablets,GPSreceivers,andothersimilardevices.ARMisoneofthenotableRISCarchitecturesusedinthesedevices.ThehigherefficiencyoftheRISCarchitecturemakesitdesirableintheseapplicationswherecyclesandpowerareusuallyinshortsupply.

Summary:

CISCinstructionsutilizemorecyclesthanRISCCISChaswaymorecomplexinstructionsthanRISCCISCtypicallyhasfewerinstructionsthanRISCCISCimplementationstendtobeslowerthanRISCimplementationsComputerstypicallyuseCISCwhiletablets,smartphonesandotherdevicesuseRISC

Readmore:DifferenceBetweenRISCandCISC|DifferenceBetween|RISCvsCISChttp://www.differencebetween.net/technology/protocols-formats/difference-between-risc-and-cisc/#ixzz1tz7HijuM

RISCvsCISCprocessor

RISCandCISCarecomputingsystemsdevelopedforcomputers.DifferencebetweenRISCandCISCiscriticaltounderstandinghowacomputerfollowsyourinstructions.Thesearecommonlymisunderstoodtermsandthisarticleintendstoclarifytheirmeaningsandconceptsbehindthetwoacronyms.

RISC

PronouncedsameasRISK,itisanacronymforReducedInstructionSetComputer.Itisatypeofmicroprocessorthathasbeendesignedtocarryoutfewinstructionsatthesametime.Till1980shardwaremanufacturersweretryingtobuildCPUsthatcouldcarryoutalargenumberofinstructionsatthesameinstant.Butthetrendwasreversedandmanufacturersdecidedtobuildcomputersthatwerecapableofcarryingoutrelativelyveryfewinstructions.Instructionsbeingsimpleandfew,CPUscouldexecutethemquickly.AnotheradvantageofRISCistheuseoffewertransistorsmakingtheminexpensivetoproduce.

FeaturesofRISC

-Demandslessdecoding

-Uniforminstructionset

-Identicalgeneralpurposeregistersusedinanycontext

-Simpleaddressingmodes

-Fewerdatatypesinhardware


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CISC

CISCstandsforComplexInstructionSetComputer.ItisactuallyaCPUwhichiscapableofexecutingmanyoperationsthroughasingleinstruction.Thesebasicoperationscouldbeloadingfrommemory,carryingoutamathematicaloperationetc.

FeaturesofCISC

-Complexinstructions

-Morenumberofaddressingmodes

-Highlypipelined

-Moredatatypesinhardware

Overtheperiodoftime,thetermsRISCandCISChavealmostbecomemeaninglessasbothRISCandCISChaveundergoneevolutionandthedistinctionbetweenthetwohasprogressivelybecomeblurredwithbothbeingusedincomputersystems.ManyoftodaysRISCchipssupportasmanyinstructionsasyesterdaysCISCchips.ThereareCISCchipsusingsametechniquesthatwereearlierconsideredtobeusedforRISCchipsonly.However,basicdifferencesbetweenthetwoareeasytocomp

rehendandareasfollows.Talkingofdifferences,RISCputsburdenonsoftwaremakersastheyhavetowritemorelinesforsametasks.RISCischeaperthanCISCbecauseoffewertransistorsrequired.Thespeedofthecomputerisalsohigherwithlesserinstructionstofollowatthesameinstant

Readmore:http://www.differencebetween.com/difference-between-risc-and-vs-cisc-processor/#ixzz1tz7URpat

Intheearlydaysofcomputing,youhadalumpofsiliconwhichperformedanumberofinstructions.Astimeprogressed,moreandmorefacilitieswererequired,somoreandmoreinstructionswereadded.However,accordingtothe20-80rule,20%oftheavailableinstructionsarelikelytobeused80%ofthetime,withsomeinstructionsonlyusedveryrarely.Someoftheseinstructionsareverycomplex,socreatingtheminsiliconisaveryarduoustask.Instead,theprocessordesignerusesmicrocode.Toillustratethis,weshallconsideramodernCISCprocessor(suchasaPentiumor68000seriesprocessor).Thecore,thebaselevel,isafastRISCprocessor.Ontopofthatisaninterpreterwhich'sees'theCISCinstructions,andbreaksthemdownintosimplerRISCinstructions.

Already,wecanseeaprettyclearpictureemerging.Why,iftheprocessorisasimpleRISCunit,don'tweusethat?Well,theanswerliesmoreinpoliticsthandesign.HoweverAcornsawthisandnotbeingconstrainedbytheneedtoremaintotallycompatiblewithearliertechnologies,theydecidedtoimplementtheirownRISCprocessor.

Upuntilnow,we'venotreallyconsideredtherealdifferencesbetweenRISCandCISC,so...


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AComplexInstructionSetComputer(CISC)providesalargeandpowerfulrangeofinstructions,whichislessflexibletoimplement.Forexample,the8086microprocessorfamilyhastheseinstructions:

JAJumpifAboveJAEJumpifAboveorEqualJBJumpifBelow...JPOJumpifParityOddJSJumpifSignJZJumpifZero

Thereare32jumpinstructionsinthe8086,andthe80386addsmore.I'venotreadaspecsheetforthePentium-classprocessors,butIsuspectit(andMMX)wouldgivemeaheartattack!

Bycontrast,theReducedInstructionSetComputer(RISC)conceptistoidentifythesub-componentsandusethose.Asthesearemuchsimpler,theycanbeimplementeddirectlyinsilicon,sowillrunatthemaximumpossiblespeed.Nothingis'translated'.ThereareonlytwoJumpinstructionsintheARMprocessor-BranchandBranchwithLink.The"ifequal,ifcarryset,ifzero"typeofselectionishandledbyconditionoptions,soforexample:

BLNVBranchwithLinkNeVer(useful!)

BLEQBranchwithLinkifEQualandsoon.TheBLpartistheinstruction,andthefollowingpartisthecondition.Thisismademorepowerfulbythefactthatconditionalexecutioncanbeappliedtomostinstructions!Thishasthebenefitthatyoucantestsomething,thenonlydothenextfewcommandsifthecriteriaofthetestmatched.Nobranchingoff,yousimplyaddconditionalflagstotheinstructionsyourequiretobeconditional:

SWI"OS_DoSomethingOrOther";calltheSWIMVNVSR0,#0;Iffailed,setR0to-1MOVVCR0,#0;ElsesetR0to0

Or,forthe80486:

INT$...whatever...;calltheinterruptCMPAX,0;diditreturnzero?JEfailed;ifso,itfailed,jumptofailcodeMOVDX,0;elsesetDXto0returnRET;andreturnfailedMOVDX,0FFFFH;failed-setDXto-1JMPreturn

Theoddflowinthatexampleisdesignedtoallowthefastestnon-branchingthro

ughputinthe'didnotfail'case.Thisisattheexpenseoftwobranchesinthe'failed'case.Iamnot,however,anx86coder,sothatcanpossiblybeoptimised-mailmeifyouhaveanysuggestions...

MostmodernCISCprocessors,suchasthePentium,usesafastRISCcorewithaninterpretersittingbetweenthecoreandtheinstruction.SowhenyouarerunningWindows95onaPC,itisnotthatmuchdifferenttotryingtogetW95running


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onthesoftwarePCemulator.JustimaginethepowerhiddeninsidethePentium...

AnotherbenefitofRISCisthatitcontainsalargenumberofregisters,mostofwhichcanbeusedasgeneralpurposeregisters.

ThisisnottosaythatCISCprocessorscannothavealargenumberofregisters,somedo.Howeverforit'suse,atypicalRISCprocessorrequiresmoreregisterstogiveitadditionalflexibility.Gonearethedayswhenyouhadtwogeneralpurposeregistersandan'accumulator'.

OnethingRISCdoesoffer,though,isregisterindependence.AsyouhaveseenabovetheARMregistersetdefinesatminimumR15astheprogramcounter,andR14asthelinkregister(although,aftersavingthecontentsofR14youcanusethisregisterasyouwish).R0toR13canbeusedinanywayyouchoose,althoughtheOperatingSystemdefinesR13isusedasastackpointer.Youcan,ifyoudon'trequireastack,useR13foryourownpurposes.APCSappliesfirmerrulesandassignsmorefunctionstoregisters(suchasStackLimit).However,noneofthese-withtheexceptionofR15andsometimesR14-isaconstraintappliedbytheprocessor.Youdonotneedtoworryaboutsavingyouraccumulatorinlonginstructions,yousimplymakegooduseoftheavailableregisters.

The8086offersyoufourteenregisters,butwithcaveats:Thefirstfour(A,B,C,andD)areDataregisters(a.k.a.scratch-padregisters).Theyare16bitandaccessedastwo8bitregisters,thusregisterAisreally

AH(A,high-orderbyte)andAL(Alow-orderbyte).Thesecanbeusedasgeneralpurposeregisters,buttheycanalsohavededicatedfunctions-Accumulator,Base,Count,andData.ThenextfourregistersareSegmentregistersforCode,Data,Extra,andStack.ThencomethefiveOffsetregisters:InstructionPointer(PC),SPandBPforthestack,thenSIandDIforindexingdata.Finally,theflagsregisterholdstheprocessorstate.Asyoucansee,mostoftheregistersaretiedupwiththebizarrememoryaddressingschemeusedbythe8086.Soonlyfourgeneralpurposeregistersareavailable,andeventheyarenotasflexibleasARMregisters.

TheARMprocessordiffersagaininthatithasareducednumberofinstructionclasses(DataProcessing,Branching,Multiplying,DataTransfer,SoftwareInterru

pts).

Afinalexampleofminimalregistersisthe6502processor,whichoffersyou:Accumulator-forresultsofarithmeticinstructionsXregister-FirstgeneralpurposeregisterYregister-SecondgeneralpurposeregisterPC-ProgramCounterSP-StackPointer,offsetintopageone(at&01xx).PSR-ProcessorStatusRegister-theflags.Whileitmightseemlikeuttermadnesstoonlyhavetwogeneralpurposeregisters,the6502wasaverypopularprocessorinthe'80s.Manyfamouscomputershavebeenbuiltaroundit.FortheEuropeans:considertheAcornBBCMicro,Master,Electron...

FortheAmericans:considertheApple2andtheCommadorePET.TheORICusesa6502,andtheC64usesavariantofthe6502.(incaseyouwerewondering,theSpeccyusestheotherpopularprocessor-theeverbizarreandfreakyZ80)

Soifentiresystemscouldbecreatedwitha6502,imaginetheflexibilityoftheARMprocessor.Ithasbeensaidthatthe6502isthebridgebetweenCISCdesignandRISC.Acornchosethe6502fortheiroriginalmachinessuchastheAtomandtheSystem#units.Theywentfromtheretodesigntheirownprocessor-theARM.


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Tosummarisetheabove,theadvantagesofaRISCprocessorare:

Quickertime-to-market.Asmallerprocessorwillhavefewerinstructions,andthedesignwillbelesscomplicated,soitmaybeproducedmorerapidly.Smaller'diesize'-theRISCprocessorrequiresfewertransistorsthancomparableCISCprocessors...Thisinturnleadstoasmallersiliconsize(IonceaskedRussellKingofARMLinuxfamewheretheStrongARMprocessorwas-andIwaslookingrightatit,itisthatsmall!)...which,inturnagain,leadstolessheatdissipation.MostoftheheatofmyARM710isactuallygeneratedbythe80486intheslotbesideit(andthat'swhenitissupposedtobein'standby').Relatedtoalloftheabove,itisamuchlowerpowerchip.ARMdesignprocessorsinstaticformsothattheprocessorclockcanbestoppedcompletely,ratherthansimplysloweddown.TheSolocomputer(designedforuseinthirdworldcountries)isasystemthatwillrunfroma12Vbattery,chargingfromasolarpanel.Internally,aRISCprocessorhasanumberofhardwiredinstructions.

ThiswasalsotrueoftheearlyCISCprocessors,butthesedaysatypicalCISCprocessorhasaheartwhichexecutesmicrocodeinstructionswhichcorrelatetotheinstructionspassedintotheprocessor.Ironically,this'heart'tendstobeRISC.:-)AstouchedonmyMatthiasbelow,aRISCprocessor'ssimplicitydoesnotnecessarilyrefertoasimpleinstructionset.HequotesLDREQR0,[R1,R2,LSR#16]!,thoughIwouldprefertoquotethe26bitinstructionLDMEQFDR13!,{R0,R2-R4,PC}^whichrestoresR0,R2,R3,R4,andR15fromthefullydescendingstackpointedtobyR13.Thestackisadjustedaccordingly.The'^'pushestheprocessorflagsintoR15aswellasthereturnaddress.Anditisconditionallyexecuted.Thisallowsatidy'exitfromroutine'tobeperformedinasingleinstruction.

Powerful,isn'tit?TheRISCconcept,however,doesnotstatethatalltheinstructionsaresimple.Ifthatweretrue,theARMwouldnothaveaMUL,asyoucandotheexactsamethingwithloopingADDing.No,theRISCconceptmeansthesiliconissimple.Itisasimpleprocessortoimplement.I'llleaveitasanexerciseforthereadertofigureoutthepowerofMathias'exampleinstruction.Itisexactlyonparwithmyexample,ifnotslightlymoreso!

CISCvs.RISC

CISCPrinciples

Largeinstructionset;


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Complexoperations;Complexaddressingmodes;Complexhardware,longexecutiontime;Minimumnumberofinstructionsneededforagiventask;Easytoprogram,simplercompiler.

Observations

Complexoperationsareinfrequentlyused;Complexaddressingmodesareinfrequentlyused,andtheycanalwaysberealizedusingseveralsimpleinstructions;Fewdatatypesarefrequentlyused;Constantsanddisplacements(offsets)ininstructionsareoftensmall;Compilercannoteasilyexploitcomplexinstructions.

RISCPrinciples

Smallinstructionset;Simpleinstructionstoallowforfastexecution(fewersteps);Bothoperandsshouldbeavailableinregisterstoallowforshortfetchtime;Largenumberofregisters;Onlyread/write(load/store)instructionsshouldaccessthemainmemory,oneMMaccessperinstruction;

Simpleaddressingmodestoallowforfastaddresscomputation;Fixed-lengthinstructionswithfewformatsandalignedfieldstoallowforfastinstructiondecoding;Complextasksarelefttothecompilertoconstructfromsimpleoperations,withincreasedcompilercomplexityandcompilingtime;simplerandfasterhardwareimplementation,especiallysuitableforpipelinedarchitecture.

Comparisons

Theexecutiontime

\begin{displaymath}CPUTime=N\timesCPI\timesCT\end{displaymath}

ofaprogramdependson

$N$:totalnumberofinstructionsintheprogram;$CPI$:averagenumberofcyclesineachinstruction$CT$:clockcycletime.

\begin{displaymath}\begin{tabular}{l\vert\vertl\vertl\vertl}\hline&N&C......large\\RISC&large&small&small\hline\end{tabular}\end{displaymath}

TheCISCinstructionsareclosertothehigh-levellanguages,whiletheRISCins

tructionsareclosertothesignel-stepmicro-instructions(tobediscussedlater).

risc_cisc.gif

Example:

CISC(M68000)

\begin{displaymath}\begin{tabular}{lll}Add&(A3)+,&100(A2)\end{tabular


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}\end{displaymath}

AddthecontentofMMlocationpointedtobyA3tothecomponentofanarraystartingatMMaddress100.TheindexnumberofthecomponentisinA2.ThecontentofA3isthenautomaticallyincrementedby1.

RISC(MIPS)

\begin{displaymath}\begin{tabular}{llll}lw&\$t0,&0(\$s3)\\lw&\$t1,......&\$t2,&100(\$s3)\\addi&\$s3,&\$s3,1\end{tabular}\end{displaymath}

California?Berkeley?led?by?David?Patterson,?who?coined?the?term?"RISC".[4]?They?

realized?thatRISC?promised?higher?performance,?less?cost?and?faster?design?time.The?design?philosophies?behind?RISC?chip?are?"make?common?case?faster"?and?"simple?is?best",which?are?based?on?the?premise?that?20%?of?a?computer's?instructions?do?80%?of?the?work.?In?aCISC?chip,?many?very?complex?instructions?never?or?seldom?used,?but?they?make?the?control?unitextremely?complex?and?thus?have?a?high?control?unit?delay.?A?RISC?instruction?set?includesfewer?and?simpler?instructions?with?hard-wired?control,?simpler?processor?pipeline,?a?largernumber?of?registers,?a?smaller?transistor?count?which?makes?it?easier?to?design?and?cheaper?toproduce,?and?a?higher?clock?rate?etc.?Since?fewer?instructions?exist,?it's?also?easier?to?writepowerful?optimized?compilers.?Also,?with?simpler?and?fixed-size?instructions?and?hardwaredecoding,?further?performance?improvement?such?as?superscalar?and?speculation?is?possibleeasier.As?researchers?continued?into?RISC?during?the?1970's?and?1980's?it?became?clear?that?the?factorsdescribed?above?resulted?in?a

?speed?increase?over?CISC?designs.However,?with?the?fleeting?of?time,?the?battle?over?RISC?and?CISC?became?blur,?though?pureRISC?machine?may?outperform?pure?CISC?machine,?but?both?of?each?have?some?bad?faces?whichinterfere?their?further?improvement?of?performance.?In?90's,?the?trend?is?migrating?toward?eachother,?RISC?machines?may?adopt?some?traits?from?CISC,?while?CISC?may?also?do?it?vice?versa.An?example?is?Intel?microprocessors,?though?they?use?a?CISC?instruction?set?and?are?consideredCISC?chips,?the?internal?architecture?has?gradually?migrated?to?RISC.?Beginning?with?thePentium?Pro,?Intel?used?a?RISC?core,?converting?CISC?instructions?to?RISC-like?instructions?thatIntel?calls?micro-ops?(Figure?2.1).?The?micro-ops?overcome?much?of?the?speed?penalty?of?CISCarchitecture?by?converting?all?instructions?to?the?same?length?before?they?are?processed.?Micro-ops?also?eliminate?arithmetic?operations?that?directly?change?memory?by?loading?memory?datainto?registers?before?processing.?Also,?Pentium?is?compatible?with?80486?and?outperf

orm?RISCmachine?in?performance?by?adopting?superscalar?and?pipeline?structure.?With?the?addition?ofRISC?core?technology,?MMX,?and?SSE,?CISC?performance?has?become?very?competitive?withthat?of?RISC?computers.Figure?2.1Another?important?thing?we?want?to?mention?here?is?that?although?a?significant?number?ofmicroprocessors?are?based?on?RISC?technology?today,?RISC?never?achieved?the?marketpenetration?that?its?early?proponents?hoped?for.?In?part,?this?limited?acceptance?was?because?theperformance?improvement?offered?by?RISC?was?offsetted?by?a?very?large?installed?base?of?x86-compatible?CISC?computers.?With?large?investments?in?software?for?CISC?computers,corporation?decision-makers?could?not?j


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ustify?switching?to?RISC?in?many?cases.In?the?section?2.2?we?provide?a?simple?comparison?between?CISC?and?RISC?that?is?based?on?thearchitecture?itself.2.2?RISC?versus?CISCA?CISC?processor?has?most?of?the?following?properties:?Richer?instruction?set,?some?simple,?some?very?complex?Instructions?generally?take?more?than?1?clock?to?execute?Instructions?of?a?variable?size?Instructions?interface?with?memory?in?multiple?mechanisms?with?complex?addressingmodes?No?pipelining?Upward?compatibility?within?a?family

?Microcode?control?Work?well?with?simpler?compilerAs?time?passed,?one?of?the?non-RISC?architecture?with?large?market?is?the?Intel?x86?family,?it?hassome?specific?characteristics?became?associated?with?CISC:?Segmented?memory?model?Few?registers

?Crappy?floating?point?performanceTypically?CISC?chips?have?a?large?amount?of?different?and?complex?instructions.?It?believes?thathardware?is?always?faster?than?software;?therefore?one?should?make?a?powerful?instruction?set,which?provides?programmers?with?assembly?instructions?to?do?a?lot?with?short?programs.?Incommon?CISC?chips?are?relatively?slow?per?instruction?compared?to?RISC?chips,?but?use?lessinstructions?than?RISC.Most?actual?RISC?machines?such?as?the?RISC?I?and?RISC?II?from?the?University?of?California?atBerkeley?and?the?MIPS?from?Stanford?University?have?most?of?the?following?commonproperties:?[6]?[9]?Simple?primitive?instructions?and?addressing?modes

?Instructions?execute?in?one?clock?cycle?Uniformed?length?instructions?and?fixed?instruction?format?Instructions?interface?with?memory?via?fixed?mechanisms?(load/store)


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?Pipelining?Instruction?set?is?orthogonal?(little?overlapping?of?instruction?functionality)?Hardwired?control?Complexity?pushed?to?the?compilerAlso,?more?ideas?added?to?new?RISC?technology,?including:?Superscalar?and?out-of-order?execution?Large?number?of?registers?Fast?floating?point?performanceThe?essence?of?RISC?architecture?is?that?it?allows?the?execution?of?more?operations?in?paralleland?at?a?higher?rate?than?possible?with?a?CISC?architecture?employing?similar?implementationcomplexity.?It?can?not

?only?improve?parallelism?by?pipelining,?but?also?make?superscalar?and?out-of?-order?execution?possible.Back?in?the?middle?to?late?80's,?the?battle?over?RISC?and?CISC?is?mainly?non-Intel?versus?Intelx86,?and?RISC?seemed?to?have?a?clearly?upside,?until?the?appearing?of?i486,?Pentium?and?nowPII,?PIII.?Now?Intel's?machines?still?run?the?old?instruction?set,?but?they?adopt?some?RISC-likecharacteristics?such?as?one?clock?execution,?clean?memory?models,?deep?pipelining,?superscalaroperations,?lots?of?registers?and?even?out-of-order?execution.?They?run?faster?and?faster?with?adecent?floating?point?performance.?On?the?other?hand,?some?RISC?machines?added?moreinstructions?to?their?architectures?for?new?data?types.?So,?it?seems?the?RISC-CISC?gap?isnarrowed.So,?nowadays,?the?difference?between?RISC?and?CISC?is?no?longer?one?of?instruction?sets,?but?ofthe?whole?chip?architecture?and?system.?The?designations?RISC?and?CISC?are?no?longermeaningful?in?the?original?sense.?What?counts?in?a?real?world?is?always?how?fast?a?chip?canexecute?the?

instructions?it?is?given?and?how?well?it?runs?existing?software.?[7]In?the?section?3,?we?using?two?chips?appeared?in?mid?80's?to?make?a?simple?comparison?betweenpure?RISC?and?pure?CISC?architecture.3.?Experiments?with?MIPS?2000?and?Intel?80386Typical?RISC?system?includes?HP?PA-RISC,?IBM?RT-PC,?IBM?RS6000,?Intel's?i860?and?i960,MIPS?R2000?(and?so?on),?Motorola's?88K,?Motolora/IBM's?PowerPc,?and?Sun's?SPARC?etc.Typical?CISC?system?includes?DEC?VAX,?Motolora?68K?and?680x0,?Intel?80x86?etc.?In?thisexperiment?part,?we?choose?to?compare?the?instruction?set?of?Intel?80386?(CISC,?1985)?and?MIPSR2000?(RISC,?1986)?that?appeared?almost?at?the?same?era.In?1985,?Intel?extended?the?80286?architecture?to?32-bit?80386.?The?32-bit?80386?is?an?advancedmicroprocessor?optimized?for?multitasking?operating?systems?and?designed?for?applicationsneeding?very?high?performance.?Its?32-bit?register

s?and?data?paths?support?32-bit?addresses?anddata?types.?In?addition?to?a?32-bit?architecture?with?32-bit?address?space,?the?80386?added?new

The?specific?numbers?of?above?measurements?depend?on?the?benchmarks?chosen?and?t


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hecompiler?technology?used.?Although?we?feel?that?our?measurements?are?reasonably?indicative?ofthe?usage?of?the?two?architectures,?other?programs?or?different?compilers?may?yield?slightlydifferent?numbers.?But?we?believe?what?we?do?here?to?Intel?80386?and?MIPS?R2000?primarilydisplays?the?most?common?differences?between?the?two?architectures?behind?them.4.?Discussions4.1?Who?wins?RISC?processors?gain?a?reputation?for?high?performance,?and?our?experiments?above?do?verifythis?point.?However,?nowadays,?the?difference?between?RISC?and?CISC?chips?is?getting?smallerand?smaller.?RISC?and?CISC?architectures?are?becoming?more?and?more?alike.?Many?of?today'sRISC?chips?support?just?as?many?instructions?as?yesterday's?CISC?chips.?The?PowerPC?601,?forexample,?supports?more?instructions?than?the?Pentium.?Yet?the?601?is?considered?a?RISC?chip,while?the?Pentium?is?definitely?CISC.?Further?more?today's?CISC?chips?use?many?techniquesformerly?associated?with?RISC?chips.?Here?maybe?we?can?simply?say?that?RISC?and?CISC?aregrowing?to?each?other?in?their?architecture?in?the?theoretical?point?of?view.In?reality,?what?counts?is?how?fast?a?chip?can?execute?the?instructions?it?is?given?and?how?well?itruns?existing?software.?Today,?both?RISC?and?CISC?manufacturers?are?doing?everything?to?get?anedge?on?the?competition.?In?90's,?most?new?generations?of?processors?employ?a?mixed?bag?ofarchitectural?features,?including?multiple?execution?units,?pipelining,?caches,?and?floating-pointintegration,?thus?makes?performance?comparisons?almost?useless?outside?of?a?specificapplication.Making?a?processor?successful?is?more?than?just?having?the?fastest?chip?available?at?an?attractiveprice.?There?is?a?problem?of?ensuring?quality?software?development?tools?are?available.?Thetypical?high-end?embedded?product?these?days?incorporates?comp

lex?software,?yet?most?dealwith?shrinking?time-to-market?requirements.?This?necessitates?a?productive?softwaredevelopment?environment.?Many?of?the?newer?RISC?processors?cannot?yet?offer?a?toolsenvironment?comparable?with?x86?offerings.?In?an?effort?to?accelerate?the?introduction?of?5thgeneration?processors?on?the?desktop,?Intel?rapidly?lowered?Pentium?prices,?forcing?down?theprice?of?the?486.?Consequently?high?performance?486?processors?-?costing?multi-millions?ofdollars?to?develop?-?became?available?at?very?aggressive?prices.?This?all?happened?quickly?andchanged?the?landscape?of?the?RISC?vs.?CISC?battlefield.It?seems?likely?that?the?PowerPC,?the?i960,?and?many?other?low-cost?RISC?processors?are?notgoing?to?easily?gain?a?significant?performance?advantage?over?future?implementation?of?the?x86architecture.?Embedded?product?designers?are?good?at?identifying?where?the?best?value?is.?Whenchoose?a?processor?for?embedded?real-time?application,?RISC?generally?don't?have?advantagesover?CISC,?since?most?of?real-time?systems?require?v

ery?fast?interrupt?handling?and?high?codedensity.?In?an?embedded?system,?due?to?the?size?limitation?of?chips,?it?is?unlikely?to?have?largememory,?so?high?code?density?is?important.?Also,?CISC?chips?such?as?Motorola's?68K?familyprovide?better?software?availability?for?such?system.?[5]The?debate?between?RISC?and?CISC?will?likely?continue,?even?if?the?battle?lines?are?nowbecoming?fuzzy.?This?seems?clear,?no?matter?what?your?RISC?or?CISC?persuasion?[1].?But?thefuture?might?not?bring?victory?to?one?of?them,?but?makes?both?extinct.?So,?who?wins??No?onewins.Finally,?we?want?to?point?out?that?the?biggest?threat?for?CISC?and?RISC?might?not?be?each?other,but?a?new?technology?called?EPIC.?EPIC?stands?for?Explicitly?Parallel?Instruction?Computing.Like?the?word?parallel?already?says?EPIC?can?do?many?instruction?executions?in?parallel?to?oneanother.EPIC?is?a?created?by?Intel?and?is?in?a?way?a?combination?of?both?CISC?and?RIS

C.?This?will?intheory?allow?the?processing?of?Windows-based?as?well?as?UNIX-based?applications?by?the?sameCPU.Intel?is?working?on?it?under?code-name?Merced.?Microsoft?is?already?developing?their?Win64standard?for?it.?Like?the?name?says,?Merced?will?be?a?64-bit?chip.If?Intel's?EPIC?architecture?is?successful,?it?might?be?the?biggest?thread?for?RISC.?All?of?the?bigCPU?manufactures?but?Sun?and?Motorola?are?now?selling?x86-based?products,?and?some?are?justwaiting?for?Merced?to?come?out?(HP,?SGI).?Because?of?the?x86?market?it?is?not?likely?that?CISCwill?die?soon,?but?RISC?may.So?the?future?might?bring?EPIC?processors?and?more?CISC?processors,?while?the?RISCprocessors?are?becoming?extinct.?And?finally,?EPIC?might?make?first?RISC?obsolete?and?laterCISC?too.


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4.2?SummaryFrom?our?limited?experience?based?on?the?results?of?our?benchmarks,?it?appears?that?theoreticallythe?pure?RISC?machine?such?as?MIPS?R2000?is?a?more?promising?style?of?computer?designcompared?to?Intel?80386?CISC?Chip?at?that?era.?With?time?fleeting,?however,?the?bottom?linebetween?CISC?and?RISC?becomes?blur,?in?real?world,?people?only?care?about?how?well?a?systemcan?serve?them,?how?fast?a?chip?can?execute?the?instructions?it?is?given?and?how?well?it?runsexisting?software.?We?think?the?adoption?of?each?others?technology?to?overcome?its?owndrawbacks?maybe?more?and?more?a?trend?in?future?CPU?design.?Also,?other?architecturesdifferent?from?CISC?and?RISC?may?appear.AcknowledgementsWe?would?like?to?express?our?sincere?gratitude?to?Dr.?Ethan?L.?Miller?for?his?excellent?teaching,timely?help?and?support,?and?enlightening?discussion.References[1]?Daniel?Mann,?"Why?the?x86?CISC?beat?RISC",?fromhttp://www.amd-embedded.com/Benchmarks/whyx86.htm[2]?Keith?Diefendorff,?"History?of?the?PowerPC?architecture",?Commun.?ACM?37,?6?(Jun.?1994),Pages?28?-?33[3]?Radin,?G.?"The?801?Minicomputer",?In?Proceedings?of?the?Symposium?on?ArchitecturalSupport?for?Programming?Languages?and?Operating?Systems?(March1982),?pp.?39-47[4]?Patterson,?D.S.?and?Ditzel,?D.R.?"The?case?for?the?reduced?instruction?set?computer",

Computer?Architecture?News?8:6?(Oct.15,?1980),?pp.?25-33.[5]?Dennis?Terry,?"Choosing?a?Processor?for?Embedded?Real-Time?Applications",?fromhttp://www.zytec.com/cp/html/choosingproc.html[6]?David?A.?Patterson,?Reduced?Instruction?Set?Computers,?Commun.?ACM?28,?1?(Jan.?1985),Pages?8?-?21[7]?Jeff?Prosise,?RISC?vs.?CISC:?The?Real?Story?--?What?makes?the?PowerPC?a?RISC?processorand?the?Pentium?a?CISC??,?fromhttp://www.zdnet.com/pcmag/pctech/content/14/18/tu1418.001.html[8]?Margarita?Esponda,?Ra'ul?Rojas,?The?RISC?Concept?-?A?Survey?of?Implementations,?fromhttp://www.inf.fu-berlin.de/lehre/WS94/RA/RISC-9.html[9]?David?A.?Patterson,?Carlo?H.?Sequin,?RISC?I:?A?Reduced?Instruction?Set?VLSI?Computer,25?years?of?the?international?symposia?on?Computer?architecture?(selected?papers),?June?27?-?July2,?1998,?Barcelona?Spain,?Pages?216-230[10]?Thomas?R.?Gross,?John?L.?Hennessy,?Steven?A.?Przybylski,?Chri

stopher?Rowen,Measurement?and?evaluation?of?the?MIPS?architecture?and?processor,?Volume?6,?Issue?3(1988),?Pages?229-257

ThesimplestwaytoexaminetheadvantagesanddisadvantagesofRISCarchitectureisbycontrastingitwithit'spredecessor:CISC(ComplexInstructionSetComputers)architecture.

MultiplyingTwoNumbersinMemoryOntherightisadiagramrepresentingthestorageschemeforagenericcomputer.Themainmemoryisdividedintolocationsnumberedfrom(row)1:(column)1to(row)6:(column)4.Theexecutionunitisresponsibleforcarryingoutallcomputations.However,theexecutionunitcanonlyoperateondatathathasbeenloadedintooneofthesixregisters(A,B,C,D,E,orF).Let'ssaywewanttofindtheproductoftwonumbers-onestoredinlocation2:3andanotherstoredinlocation5:2-andthenstoretheproductbackinthelocation2:3.

TheCISCApproach


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achinstructionrequiresonlyoneclockcycletoexecute,theentireprogramwillexecuteinapproximatelythesameamountoftimeasthemulti-cycle"MULT"command.TheseRISC"reducedinstructions"requirelesstransistorsofhardwarespacethanthecomplexinstructions,leavingmoreroomforgeneralpurposeregisters.Becausealloftheinstructionsexecuteinauniformamountoftime(i.e.oneclock),pipeliningispossible.

Separatingthe"LOAD"and"STORE"instructionsactuallyreducestheamountofworkthatthecomputermustperform.AfteraCISC-style"MULT"commandisexecuted,theprocessorautomaticallyerasestheregisters.Ifoneoftheoperandsneedstobeusedforanothercomputation,theprocessormustre-loadthedatafromthememorybankintoaregister.InRISC,theoperandwillremainintheregisteruntilanothervalueisloadedinitsplace.

ThePerformanceEquationThefollowingequationiscommonlyusedforexpressingacomputer'sperformanceability:

TheCISCapproachattemptstominimizethenumberofinstructionsperprogram,sacrificingthenumberofcyclesperinstruction.RISCdoestheopposite,reducingthecyclesperinstructionatthecostofthenumberofinstructionsperprogram.

RISCRoadblocks

DespitetheadvantagesofRISCbasedprocessing,RISCchipstookoveradecadetogainafootholdinthecommercialworld.Thiswaslargelyduetoalackofsoftwaresupport.

AlthoughApple'sPowerMacintoshlinefeaturedRISC-basedchipsandWindowsNTwasRISCcompatible,Windows3.1andWindows95weredesignedwithCISCprocessorsinmind.ManycompanieswereunwillingtotakeachancewiththeemergingRISCtechnology.Withoutcommercialinterest,processordeveloperswereunabletomanufactureRISCchipsinlargeenoughvolumestomaketheirpricecompetitive.

AnothermajorsetbackwasthepresenceofIntel.AlthoughtheirCISCchipswerebecomingincreasinglyunwieldyanddifficulttodevelop,Intelhadtheresourcestoplowthroughdevelopmentandproducepowerfulprocessors.AlthoughRISCchip

smightsurpassIntel'seffortsinspecificareas,thedifferenceswerenotgreatenoughtopersuadebuyerstochangetechnologies.

TheOverallRISCAdvantageToday,theIntelx86isarguabletheonlychipwhichretainsCISCarchitecture.Thisisprimarilyduetoadvancementsinotherareasofcomputertechnology.ThepriceofRAMhasdecreaseddramatically.In1977,1MBofDRAMcostabout$5,000.By1994,thesameamountofmemorycostonly$6(whenadjustedforinflation).Compilertechnologyhasalsobecomemoresophisticated,sothattheRISCuseofRAMandemphasisonsoftwarehasbecomeideal.

CISC

CISCisanacronymforComplexInstructionSetComputerandarechipsthatareeasytoprogramandwhichmakeefficientuseofmemory.Sincetheearliestmachineswereprogrammedinassemblylanguageandmemorywasslowandexpensive,theCISCphilosophymadesense,andwascommonlyimplementedinsuchlargecomputers


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asthePDP-11andtheDECsystem10and20machines.

MostcommonmicroprocessordesignssuchastheIntel80x86andMotorola68KseriesfollowedtheCISCphilosophy.

Butrecentchangesinsoftwareandhardwaretechnologyhaveforcedare-examinationofCISCandmanymodernCISCprocessorsarehybrids,implementingmanyRISCprinciples.

ThedesignconstraintsthatledtothedevelopmentofCISC(smallamountsofslowmemoryandfactthatmostearlymachineswereprogrammedinassemblylanguage)giveCISCinstructionssetssomecommoncharacteristics:

A2-operandformat,whereinstructionshaveasourceandadestination.Registertoregister,registertomemory,andmemorytoregistercommands.Multipleaddressingmodesformemory,includingspecializedmodesforindexingthrougharraysVariablelengthinstructionswherethelengthoftenvariesaccordingtotheaddressingmodeInstructionswhichrequiremultipleclockcyclestoexecute.MostCISChardwarearchitectureshaveseveralcharacteristicsincommon:Complexinstruction-decodinglogic,drivenbytheneedforasingleinstructiontosupportmultipleaddressingmodes.Asmallnumberofgeneralpurposeregisters.Thisisthedirectresultofha

vinginstructionswhichcanoperatedirectlyonmemoryandthelimitedamountofchipspacenotdedicatedtoinstructiondecoding,execution,andmicrocodestorage.Severalspecialpurposeregisters.ManyCTSCdesignssetasidespecialregistersforthestackpointer,interrupthandling,andsoon.Thiscansimplifythehardwaredesignsomewhat,attheexpenseofmakingtheinstructionsetmorecomplex.A'Conditioncode"registerwhichissetasaside-effectofmostinstructions.Thisregisterreflectswhethertheresultofthelastoperationislessthan,equalto,orgreaterthanzeroandrecordsifcertainerrorconditionsoccur.

Atthetimeoftheirinitialdevelopment,CISCmachinesusedavailabletechnologiestooptimizecomputerperformance.

Microprogramniingisaseasyasassemblylanguagetoimplement,andmuchlessexpensivethanhardwiringacontrolunit.TheeaseofmicrocodingnewinstructionsalloweddesignerstomakeCISCmachinesupwardlycompatible:anewcomputercouldrunthesameprogramsasearliercomputersbecausethenewcomputerwouldcontainasupersetoftheinstructionsoftheearliercomputers.Aseachinstructionbecamemorecapable,fewerinstructionscouldbeusedtoimplementagiventask.Thismademoreefficientuseoftherelativelyslowmainmemory.Becausemicroprograminstructionsetscanbewrittentomatchtheconstructsofhigh-levellanguages,thecompilerdoesnothavetobeascomplicated.

DesignerssoonrealisedthattheCISCphilosophyhaditsownproblems,including:

Earliergenerationsofaprocessorfamilygenerallywerecontainedasasubsetineverynewversion-soinstructionset&chiphardwarebecomemorecomplexwitheachgenerationofcomputers.Sothatasmanyinstructionsaspossiblecouldbestoredinmemorywiththeleastpossiblewastedspace,individualinstructionscouldbeofalmostanylength-thismeansthatdifferentinstructionswilltakedifferentamountsofclocktimetoexecute,slowingdowntheoverallperformanceofthemachine.


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Manyspecializedinstructionsaren'tusedfrequentlyenoughtojustifytheirexistence-approximately20%oftheavailableinstructionsareusedinatypicalprogram.CISCinstructionstypicallysettheconditioncodesasasideeffectoftheinstruction.Notonlydoessettingtheconditioncodestaketime,butprogrammershavetoremembertoexaminetheconditioncodebitsbeforeasubsequentinstructionchangesthem.

Asmemoryspeedincreased,andhigh-levellanguagesdisplacedassemblylanguage,themajorreasonsforCISCbegantodisappear,andcomputerdesignersbegantolookatwayscomputerperformancecouldbeoptimizedbeyondjustmakingfasterhardware.

Oneoftheirkeyrealizationswasthatasequenceofsimpleinstructionsproducesthesameresultsasasequenceofcomplexinstructions,butcanbeimplementedwithasimpler(andfaster)hardwaredesign.(Assumingthatmemorycankeepup.)RISC(ReducedInstructionSetComputers)processorsweretheresult.

CISCandRISCimplementationsarebecomingmoreandmorealike.ManyoftodaysRISCchipssupportasmanyinstructionsasyesterday'sCISCchips.Andtoday'sCISCchipsusemanytechniquesformerlyassociatedwithRISCchips.RISC

Pronounced'risk',RISCisanacronymforReducedInstructionSetComputerandi

satypeofmicroprocessorthatrecognisesarelativelylimitednumberofinstructions.

Untilthemid-1980s,thetendencyamongcomputermanufacturerswastobuildincreasinglycomplexCPUsthathadever-largersetsofinstructions.Atthattime,however,anumberofcomputermanufacturersdecidedtoreversethistrendbybuildingCPUscapableofexecutingonlyaverylimitedsetofinstructions.Oneadvantageofreducedinstructionsetcomputersisthattheycanexecutetheir

instructionsveryfastbecausetheinstructionsaresosimple.Another,perhapsmoreimportantadvantage,isthatRISCchipsrequirefewertransistors,whichmakesthemcheapertodesignandproduce.SincetheemergenceofRISCcomputers,conventionalcomputershavebeenreferredtoasCISC's(ComplexInstructionSetC

omputers).

ThemaincharacteristicsofCISCmicroprocessorsare:

Extensiveinstructions.Complexandefficientmachineinstructions.Microencodingofthemachineinstructions.Extensiveaddressingcapabilitiesformemoryoperations.Relativelyfewregisters.

Incomparison,RISCprocessorsaremoreorlesstheoppositeoftheabove:

Reducedinstructionset.

Lesscomplex,simpleinstructions.Hardwiredcontrolunitandmachineinstructions.Fewaddressingschemesformemoryoperandswithonlytwobasicinstructions,LOADandSTOREManysymmetricregisterswhichareorganisedintoaregisterfile.

ThereisstillconsiderablecontroversyamongexpertsabouttheultimatevalueofRISCarchitectures.ItsproponentsarguethatRISCmachinesarebothcheaperandfaster,andarethereforethemachinesofthefuture.


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However,bymakingthehardwaresimpler,RISCarchitecturesputagreaterburdenonthesoftware.Isthisworththetroublebecauseconventionalmicroprocessorsarebecomingincreasinglyfastandcheapanyway?

Tosomeextent,theargumentisbecomingmootbecauseCISCandRISCimplementationsarebecomingmoreandmorealike.Manyoftoday'sRISCchipssupportasmanyinstructionsasyesterday'sCISCchips.Andtoday'sCISCchipsusemanytechniquesformerlyassociatedwithRISCchips.

TheRISCconceptsoftheindividualmanufacturersare,naturally,slightlydifferent.Howevermanyoftheessentialpointsaresimilar,suchas:

reductionoftheinstructionset.instructionpipelining(theinterleavedexecutionofmanyinstructions).load/storearchitecture(onlytheloadandstoreinstructionshaveaccesstomemory,allothersworkwiththeinternalprocessorregisters).unityofRISCprocessorsandcompilers(thecompilerisnolongerdevelopedforaspecificchip,butinstead,attheoutset,thecompilerisdevelopedinconjunctionwiththechiptoproduceoneunit).amodifiedregisterconcept.InsomeRISCprocessors,forafastsubroutinecall,theregistersarenolongermanagedasax,bx,etc.butexistintheformofavariablewindowwhichallowsa'look'atcertainregisterfiles.

CloselyrelatedtotheabbreviationRISCisthereductionofthealmostunlimitedinstructionsetofhighlycomplexCISCs.OneofthefirstprototypesthatimplementedtheRISCconceptRISC-I,had31instructions,whereasitssuccessor,theRISCII,had39.

Thesimplicityofprocessorstructureisshownbythereducednumberofintegratedtransistors:intheRISCIIthereareonly41000(incomparisontomorethanonemillioninthe486andthreemillioninthePentium).

OneadditionalveryimportantcharacteristicisthehardwiredControlUnitCU(theinstructionsarehardwired)ThismeansthatinaRISCprocessor,theExecutionUnitEUisnolongercontrolledbytheCUwiththeassistanceofextensivemicrocodes.Instead,thewholeoperationisachievedintheformofhardwiredlogi

c.Thisgreatlyacceleratestheexecutionofaninstruction.

Forexample,inaCISCthecomplexityofamultiplicationinstructionislocatedinaveryextensivemicrocodewhichcontrolstheALU.ForaRISCCPUthechipdesignersputthecomplexityinacomplicatedhardwaremultiplier.Typically,inaCISCCPUmultiplicationsarecarriedoutbymanyadditionsandshifts,whereasaRISCmultiplierperformsthatoperationinoneortwo(dependentontheprecision)passes.

Duetothereducednumberofmachineinstructions,thereisnowenoughspaceonthechipforimplementingsuchhighlycomplexcircuitries.

Theexecutionstructureofaninstructionis,asaresultofthebasicmicroproc

essorworkingprinciples,thesameforthemajorityofmachinecodeinstructions.Thefollowingstepsmustbecarriedout:

readtheinstructionfrommemory(instructionfetching)decodetheinstruction(decodingphase)wherenecessary,fetchoperand(s)(operandfetchingphase)executetheinstruction(executionphase)writebacktheresult(write-backphase)

Everyinstructionisbrokendownintopartialstepsforexecutioninthestagep


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ipeline.Thepartialstepsareexecutedwithinonesingleclockcyclei.e.instruction'k'needsfiveclockcyclestocompletebutthenatthepipelineoutput,aninstructionresultisavailablewitheachclockcycle.

LatestdevelopmentsinRISCdesign

Withsomeprocessorsthephasesarecombinedintoonesinglephase;forexample,thedecodingphaseandtheoperandfetchingphase(whichiscloselylinkedtothedecodingphase)maybeexecutedinasinglepipelinestage.Theresultwouldbeafour-stagepipeline.Ontheotherhand,the

instructionphasescanbesub-dividedevenfurther,untileachelementhasitsownsub-phase,thus,throughsimplicity,veryquickpipelinestagescanbeimplemented.Suchastrategyleadstoasuperpipelinedarchitecherewithmanypipelinestages(tenormore).

Thistechniqueisusedcommercially(intheMIPSR4000RISCprocessor),butishardtoimplementandisnotbeingusedbyanyothercommercialchip.Inpracticalterms,superpipeliningwillnevergiveyoumorethana2ximprovementinperformance.

AnotherpossibilityforincreasingtheperformanceofaRISCmicroprocessoristheintegrationofmanypipelinesoperatinginparallel.Withthismethod,theresultisasuperscalar.Nearlyallmodernmicroprocessors,includingthePentium,

PowerPC,AlphaandSPARCmicroprocessorsaresuperscalar.OneofthefastestprocessorscurrentlyavailableistheMIPSRIOOOOMicroprocessor.Ithasa4-waysuper-scalararchitecturecontaininga64ksplit2-waycacheon-chipwhichfetchesanddecodesfourinstructionspercycle.Eachqueuecanperformdynamicschedulingofinstructions.Instructionscanbeexecutedandcompletedout-of-order,allowingtheprocessortohaveupto32instructionsinvariousstagesofexecutionAtafrequencyof200MHz,theR10000Microprocessordeliverspeakperformanceof800MIPSwithapeakdatatransferrateof3~2GBytes/secondtosecondarycache.CISCvsRISC

ThesimplestwaytoexaminetheadvantagesanddisadvantagesofRISCarchitectur

eisbycontrastingitwithit'spredecessor:CISC(ComplexInstructionSetComputers)architecture.

MultiplyingTwoNumbersinMemoryOntherightisadiagramrepresentingthestorageschemeforagenericcomputer.Themainmemoryisdividedintolocationsnumberedfrom(row)1:(column)1to(row)6:(column)4.Theexecutionunitisresponsibleforcarryingoutallcomputations.However,theexecutionunitcanonlyoperateondatathathasbeenloadedintooneofthesixregisters(A,B,C,D,E,orF).Let'ssaywewanttofindtheproductoftwonumbers-onestoredinlocation2:3andanotherstoredinlocation5:2-andthenstoretheproductbackinthelocation2:3.

TheCISCApproach

TheprimarygoalofCISCarchitectureistocompleteataskinasfewlinesofassemblyaspossible.Thisisachievedbybuildingprocessorhardwarethatiscapableofunderstandingandexecutingaseriesofoperations.Forthisparticulartask,aCISCprocessorwouldcomepreparedwithaspecificinstruction(we'llcallit"MULT").Whenexecuted,thisinstructionloadsthetwovaluesintoseparateregisters,multipliestheoperandsintheexecutionunit,andthenstorestheproductintheappropriateregister.Thus,theentiretaskofmultiplyingtwonumberscanbecompletedwithoneinstruction:

MULT2:3,5:2


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MULTiswhatisknownasa"complexinstruction."Itoperatesdirectlyonthecomputer'smemorybanksanddoesnotrequiretheprogrammertoexplicitlycallanyloadingorstoringfunctions.Itcloselyresemblesacommandinahigherlevellanguage.Forinstance,ifwelet"a"representthevalueof2:3and"b"representthevalueof5:2,thenthiscommandisidenticaltotheCstatement"a=a*b."

Oneoftheprimaryadvantagesofthissystemisthatthecompilerhastodoverylittleworktotranslateahigh-levellanguagestatementintoassembly.Becausethelengthofthecodeisrelativelyshort,verylittleRAMisrequiredtostoreinstructions.Theemphasisisputonbuildingcomplexinstructionsdirectlyintothehardware.

TheRISCApproachRISCprocessorsonlyusesimpleinstructionsthatcanbeexecutedwithinoneclockcycle.Thus,the"MULT"commanddescribedabovecouldbedividedintothreeseparatecommands:"LOAD,"whichmovesdatafromthememorybanktoaregister,"PROD,"whichfindstheproductoftwooperandslocatedwithintheregisters,and"STORE,"whichmovesdatafromaregistertothememorybanks.InordertoperformtheexactseriesofstepsdescribedintheCISCapproach,aprogrammerwouldneedtocodefourlinesofassembly:

LOADA,2:3

LOADB,5:2PRODA,BSTORE2:3,A

Atfirst,thismayseemlikeamuchlessefficientwayofcompletingtheoperation.Becausetherearemorelinesofcode,moreRAMisneededtostoretheassemblylevelinstructions.Thecompilermustalsoperformmoreworktoconvertahigh-levellanguagestatementintocodeofthisform.

However,theRISCstrategyalsobringssomeveryimportantadvantages.Becauseeachinstructionrequiresonlyoneclockcycletoexecute,theentireprogramwillexecuteinapproximatelythesameamountoftimeasthemulti-cycle"MULT"command.TheseRISC"reducedinstructions"requirelesstransistorsofhardwarespa

cethanthecomplexinstructions,leavingmoreroomforgeneralpurposeregisters.Becausealloftheinstructionsexecuteinauniformamountoftime(i.e.oneclock),pipeliningispossible.

Separatingthe"LOAD"and"STORE"instructionsactuallyreducestheamountofworkthatthecomputermustperform.AfteraCISC-style"MULT"commandisexecuted,theprocessorautomaticallyerasestheregisters.Ifoneoftheoperandsneedstobeusedforanothercomputation,theprocessormustre-loadthedatafromthememorybankintoaregister.InRISC,theoperandwillremainintheregisteruntilanothervalueisloadedinitsplace.

ThePerformanceEquationThefollowingequationiscommonlyusedforexpressingacomputer'sperformance

ability:

TheCISCapproachattemptstominimizethenumberofinstructionsperprogram,sacrificingthenumberofcyclesperinstruction.RISCdoestheopposite,reducingthecyclesperinstructionatthecostofthenumberofinstructionsperprogram.


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RISCvs.CISC:thePost-RISCEraAhistoricalapproachtothedebatebyHannibalFramingtheDebate

Themajorityoftoday'sprocessorscantrightfullybecalledcompletelyRISCorcompletelyCISC.Thetwotextbookarchitectureshaveevolvedtowardseachothertosuchanextentthattheresnolongeracleardistinctionbetweentheirrespectiveapproachestoincreasingperformanceandefficiency.Tobespecific,chipsthatimplementthex86CISCISAhavecometolookalotlikechipsthatimplementvariousRISCISAs;theinstructionsetarchitectureisthesame,butunderthehooditsawholedifferentballgame.Butthishasn'tbeenaone-waytrend.Rather,thesamegoesfortodaysso-calledRISCCPUs.TheyveaddedmoreinstructionsandmorecomplexitytothepointwheretheyreeverybitascomplexastheirCISCcounterparts.Thusthe"RISCvs.CISC"debatereallyexistsonlyinthemindsofmarketingdepartmentsandplatformadvocateswhosepurposeincreatingandperpetuatingthisfictitiousconflictistopromotetheirpetproductbymeansofname-callingandsloganeering.

Atthispoint,IdliketoreferenceastatementmadebyDavidDitzel,thechiefarchitectofSunsSPARCfamilyandCEOofTransmeta.

"Today[inRISC]wehavelargedesignteamsandlongdesigncycles,"hesaid."Theperformancestoryisalsomuchlessclearnow.Thediesizesarenolongersmall.Itjustdoesn'tseemtomakeasmuchsense."TheresultisthecurrentcropofcomplexRISCchips."Superscalarandout-of-orderexecutionarethebiggestproblemareasthathaveimpededperformance[leaps],"Ditzelsaid."TheMIPSR10,000andHPPA-8000seemmuchmorecomplextomethantoday'sstandardCISCarchitecture,whichisthePentiumII.SowhereistheadvantageofRISC,ifthechipsaren'tassimpleanymore?"

Thisstatementisimportant,anditsumsupthecurrentfeelingamongresearcher

s.InsteadofRISCorCISCCPUs,whatwehavenownolongerfitsintheoldcategories.Welcometothepost-RISCera.Whatfollowsisacompletelyrevisedandre-clarifiedthesiswhichfounditsfirstexpressionhereonArsoverayearago,beforeDitzelspokehismindonthematter,andbeforeIhadthechancetoexchangee-mailwithsomanythoughtfulandinformedreaders.

Inthispaper,I'llarguethefollowingpoints:

RISCwasnotaspecifictechnologyasmuchasitwasadesignstrategythatdevelopedinreactiontoaparticularschoolofthoughtincomputerdesign.Itwasarebellionagainstprevailingnorms--normsthatnolongerprevailintoday'sworld.NormsthatI'lltalkabout.

"CISC"wasinventedretroactivelyasacatch-alltermforthetypeofthinkingagainstwhichRISCwasareaction.

Wenowliveina"post-RISC"world,wherethetermsRISCandCISChavelosttheirrelevance(excepttomarketingdepartmentsandplatformadvocates).Inapost-RISCworld,eacharchitectureandimplementationmustbejudgedonitsownmerits,andnotintermsofanarrow,bipolar,compartmentalizedworldviewthattriestocramalldesignsintooneoftwo"camps."

AfterchartingthehistoricaldevelopmentoftheRISCandCISCdesignstrategies


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,andsituatingthosephilosophiesintheirproperhistorical/technologicalcontext,Illdiscusstheideaofapost-RISCprocessor,andshowhowsuchprocessorsdon'tfitneatlyintotheRISCandCISCcategories.

Thehistoricalapproach

PerhapsthemostcommonapproachtocomparingRISCandCISCistolistthefeaturesofeachandplacethemside-by-sideforcomparison,discussinghoweachfeatureaidsorhindersperformance.Thisapproachisfineifyourecomparingtwocontemporaryandcompetingpiecesoftechnology,likeOSs,videocards,specificCPUs,etc.,butitfailswhenappliedtoRISCandCISC.ItfailsbecauseRISCandCISCarenotsomuchtechnologiesastheyaredesignstrategies--approachestoachievingaspecificsetofgoalsthatweredefinedinrelationtoaparticularsetofproblems.Or,tobeabitmoreabstract,wecouldalsocallthemdesignphilosophies,orwaysofthinkingaboutasetofproblemsandtheirsolutions.

Itsimportanttoseethesetwodesignstrategiesashavingdevelopedoutofaparticularsetoftechnologicalconditionsthatexistedataspecificpointintime.Eachwasanapproachtodesigningmachinesthatdesignersfeltmadethemostefficientuseofthetechnologicalresourcesthenavailable.Informulatingandapplyingthesestrategies,researcherstookintoaccountthelimitationsofthedaystechnologylimitationsthatdontnecessarilyexisttoday.Understandingwhatthoselimitationswereandhowcomputerarchitectsworkedwithinthemisthekeyto

understandingRISCandCISC.Thus,atrueRISCvs.CISCcomparisonrequiresmorethanjustfeaturelists,SPECbenchmarksandsloganeeringitrequiresahistoricalcontext.

InordertounderstandthehistoricalandtechnologicalcontextoutofwhichRISCandCISCdeveloped,itisfirstnecessarytounderstandthestateoftheartinVLSI,storage/memory,andcompilersinthelate70sandearly80s.Thesethreetechnologiesdefinedthetechnologicalenvironmentinwhichresearchersworkedtobuildthefastestmachines.

Storageandmemory

Itshardtounderestimatetheeffectsthatthestateofstoragetechnologyhadoncomputerdesigninthe70sand80s.Inthe1970s,computersusedmagneticcorememorytostoreprogramcode;corememorywasnotonlyexpensive,itwasagonizinglyslow.AftertheintroductionofRAMthingsgotabitbetteronthespeedfront,butthisdidntaddressthecostpartoftheequation.Tohelpyouwrapyourmindaroundthesituation,considerthefactthatin1977,1MBofDRAMcostabout$5,000.By1994,thatpricehaddroppedtounder$6(in1977dollars)[2].InadditiontothehighpriceofRAM,secondarystoragewasexpensiveandslow,sopaginglargevolumesofcodeintoRAMfromthesecondarystoreimpededperformanceinamajorway.

Thehighcostofmainmemoryandtheslownessofsecondarystorageconspiredtomakecodebloatadeadlyseriousissue.Goodcodewascompactcode;youneededt

obeabletofitallofitinasmallamountofmemory.BecauseRAMcountedforasignificantportionoftheoverallcostofasystem,areductionincode-sizetranslateddirectlyintoareductioninthetotalsystemcost.(Intheearly90s,RAMaccountedforaround%36ofthetotalsystemcost,andthiswasafterRAMhadbecomequiteabitcheaper[4].)WelltalkabitmoreaboutcodesizeandsystemcostwhenweconsiderindetailtherationalesbehindCISCcomputing.

Compilers


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DavidPatterson,inarecentlypublishedretrospectivearticleonhisoriginalproposalpaperfortheRISCIprojectatBerkeley,writes:

Somethingtokeepinmindwhilereadingthepaperwashowlousythecompilerswereofthatgeneration.Cprogrammershadtowritetheword"register"nexttovariablestotrytogetcompilerstouseregisters.AsaformerBerkeleyPh.D.whostartedasmallcomputercompanysaidlater,"peoplewouldacceptanypieceofjunkyougavethem,aslongasthecodeworked."Partofthereasonwassimplythespeedofprocessorsandthesizeofmemory,asprogrammershadlimitedpatienceonhowlongtheywerewillingtowaitforcompilers.[3]

Thecompilersjobwasfairlysimpleatthatpoint:translatestatementswritteninahighlevellanguage(HLL),likeCorPASCAL,intoassemblylanguage.Theassemblylanguagewasthenconvertedintomachinecodebyanassembler.Thecompilationstagetookalongtime,andtheoutputwashardlyoptimal.AslongastheHLL=>assemblytranslationwascorrect,thatwasaboutthebestyoucouldhopefor.Ifyoureallywantedcompact,optimizedcode,youronlychoicewastocodeinassembler.(Infact,somewouldarguethatthisisstillthecasetoday.)

VLSI

ThestateoftheartinVeryLargeScaleIntegration(VLSI)yieldedtransistordensitiesthatwerelowbytodaysstandards.Youjustcouldntfittoomuchfunction

alityontoonechip.Backin1981whenPattersonandSequinfirstproposedtheRISCIproject(RISCIlaterbecamethefoundationforSunsSPARCarchitecture),amilliontransistorsonasinglechipwasalot[1].Becauseofthepaucityofavailabletransistorresources,theCISCmachinesoftheday,liketheVAX,hadtheirvariousfunctionalunitssplitupacrossmultiplechips.Thiswasaproblem,becausethedelay-powerpenaltyondatatransfersbetweenchipslimitedperformance.Asingle-chipimplementationwouldhavebeenideal,but,forreasonswellgetintoinamoment,itwasntfeasiblewithoutaradicalrethinkingofcurrentdesigns.

TheCISCsolutionTheHLLCAandthesoftwarecrisis

Boththesorrystateofearlycompilersandthememory-inducedconstraintsoncodesizecausedsomeresearchersinthelate60sandearly70stopredictacoming"softwarecrisis."Hardwarewasgettingcheaper,theyargued,whilesoftwarecostswerespiralingoutofcontrol.Anumberoftheseresearchersinsistedthattheonlywaytostaveoffimpendingdoomwastoshifttheburdenofcomplexityfromthe(increasinglyexpensive)softwareleveltothe(increasinglyinexpensive)hardwarelevel.Iftherewasacommonfunctionoroperationforwhichaprogrammerhadtowriteoutallthestepseverytimeheorsheusedit,whynotjustimplementthatfunctioninhardwareandmakeeveryoneslifeeasier?Afterall,hardw

arewascheap(relativelyspeaking)andprogrammertimewasnt.ThisideaofmovingcomplexityfromthesoftwarerealmtothehardwarerealmisthedrivingideabehindCISC,andalmosteverythingthatatrueCISCmachinedoesisaimedatthisend.

Someresearcherssuggestedthatthewaytomakeprogrammersandcompiler-writersjobseasierwasto"closethesemanticgap"betweenstatementsinahigh-levellanguageandthecorrespondingstatementsinassembler."Closingthesemanticgap"wasafancywayofsayingthatsystemdesignersshouldmakeassemblycodelookmorelikeCorPASCALcode.Themostextremeproponentsofthiskindofthinki


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ngwerecallingforthemovetoaHigh-LevelLanguageComputingArchitecture.

TheHLLCAwasCISCtakentotheextreme.Itsprimarymotivationwastoreduceoverallsystemcostsbymakingcomputerseasytoprogramfor.Bysimplifyingtheprogrammersandcompilersjobs,itwasthoughtthatsoftwarecostscouldbebroughtundercontrol.HeresalistofsomeofthemostcommonlystatedreasonsforpromotingHLLCAs[5]:

Reducethedifficultyofwritingcompilers.Reducethetotalsystemcost.Reducesoftwaredevelopmentcosts.Eliminateordrasticallyreducesystemsoftware.Reducethesemanticgapbetweenprogrammingandmachinelanguages.MakeprogramswritteninaHLLrunmoreefficiently.Improvecodecompaction.Easedebugging.

Tosummarizetheabove,ifacomplexstatementinaHLLweretotranslatedirectlyintoexactlyoneinstructioninassembler,then

Compilerswouldbemucheasiertowrite.Thiswouldsavetimeandeffortforsoftwaredevelopers,therebyreducingsoftwaredevelopmentcosts.Codewouldbemorecompact.ThiswouldsaveonRAM,therebyreducingtheoverallcostofthesystemhardware.

Codewouldbeeasiertodebug.Again,thiswouldsaveonsoftwaredevelopmentandmaintenancecosts.

Atthispointinourdiscussion,itsimportanttonotethatImnotassertingthattheflurryofliteraturepublishedonHLLCAsamountedtoa"CISCmovement"bysome"CISCcamp",inthewaythattherewasaRISCmovementledbytheBerkeley,IBM,andStanfordgroups.Thereneveractuallywasanysortof"CISCmovement"tospeakof.Infact,theterm"CISC"wasinventedonlyaftertheRISCmovementhadstarted."CISC"eventuallycametobeapejorativetermmeaning"anythingnotRISC."SoImnotequatingtheHLLCAliteraturewith"CISCliterature"producedbya"CISCmovement",butratherImusingittoexemplifyoneofthemainschoolsofthoughtincomputerarchitectureatthetime,aschoolofthoughttowhichRISCwasareaction.We'llseemoreofthatinabit.

CISCandtheperformanceequation

ThediscussionsofarhasfocusedmoreontheeconomicadvantagesofCISC,whileignoringtheperformancesideofthedebate.TheCISCapproachtoincreasingperformanceisrootedinthesamephilosophythatIvebeenreferringtoothusfar:movecomplexityfromsoftwaretohardware.Toreallyunderstandhowthisaffordsaperformanceadvantage,letslookattheperformanceequation.

time/program=[(instructions/program)x(cycles/instruction)x(time/cycle)]

Theaboveequationisacommonlyusedmetricforgaugingacomputersperformance.

Increasingperformancemeansreducingthetermontheleftsideofthe"=",becausethelesstimeittaketorunaprogram,thebetterthemachinesperformance.ACISCmachinetriestoreducetheamountoftimeittakestorunaprogrambyreducingthefirsttermtotherightofthe"=",thatis,thenumberofinstructionsperprogram.Researchersthoughtthatbyreducingtheoverallnumberofinstructionsthatthemachineexecutestoperformataskyoucouldreducetheoverallamountoftimeittakestofinishthattask,andthusincreaseperformance.

Sodecreasingthesizeofprogramsnotonlysavedmemory,italsosavedtimebecausetherewerefewerlinesofcodetoexecute.Whilethisapproachprovedfruit


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ful,ithaditsdrawbacks.Inamomentwelldiscussthosedrawbacks,andhowtheyledresearcherstofocusonothertermsintheequationintheireffortstoincreaseperformance.

Complexinstructions:anexample

Beforewegoanyfurther,letslookatanexamplesowecanbetterunderstandthemotivationsbehindincreasingthecomplexityofamachinesinstructions.Ifyouthinkyouhavetheabovedownpat,youcangoaheadandskiptothenextsection.

Considerthesituationwherewewanttotakethecubeof20andstoreitinavariable.Todothis,wewritesomecodeinahypotheticalhigh-levellanguagecalled"H."(Forthesakeofsimplicity,allvariablesinHdesignatespecificarchitecturalregisters.)OurHcompilertranslatesthiscodeintoassemblerfortheARS-1platform.TheARS-1ISAonlyhastwoinstructions:

MOVE[destinationregister,integerorsourceregister].Thisinstructiontakesavalue,eitheranintegerorthecontentsofanotherregister,andplacesitthedestinationregister.SoMOVE[D,5]wouldplacethenumber5inregisterD.MOVE[D,E]wouldtakewhatevernumberisstoredinEandplaceitinD.MUL[destinationregister,integerormultiplicandregister].Thisinstructiontakesthecontentsofthedestinationregisterandmultipliesitbyeitheran

integerorthecontentsofmultiplicandregister,andplacestheresultinthedestinationregister.SoMUL[D,70]wouldmultiplythecontentsofDby70andplacetheresultsinD.MUL[D,E]wouldmultiplythecontentsofDbythecontentsofE,andplacetheresultinD.

StatementsinH

StatementsinARS-1Assembly

A=20B=CUBE(A)

MOVE[A,20]MUL[A,A]MUL[A,A]MOVE[B,A]

[Editor'snote:thisexampleactuallyfinds20^4,not20^3.I'llcorrectitwhentheloadontheservergoesdown.Still,itservesitspurpose.]NoticehowintheaboveexampleittakesfourstatementsinARS-1assemblytodotheworkoftwostatementsinH?ThisisbecausetheARS-1computerhasnoinstructionfor

takingtheCUBEofanumber.YoujusthavetousetwoMULinstructionstodoit.SoifyouhaveanHprogramthatusestheCUBE()functionextensively,thenwhenyoucompileittheassemblerprogramwillbequiteabitlargerthantheHprogram.Thisisaproblem,becausetheARS-1computerdoesnthavetoomuchmemory.Inaddition,ittakesthecompileralongtimetotranslateallthoseCUBE()statementsintoMUL[]instructions.Finally,ifaprogrammerdecidestoforgetaboutHandjustwritecodeinARS-1assembler,heorshehasmoretypingtodo,andthefactthatthecodeissolongmakesithardertodebug.

OnewaytosolvethisproblemwouldbetoincludeaCUBEinstructioninthenext


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generationoftheARSarchitecture.SowhentheARS-2comesout,ithasaninstructionthatlooksasfollows:

CUBE[destinationregister,multiplicandregister].Thisinstructiontakesthecontentsofthemultiplicandregisterandcubesit.Itthenplacestheresultinthedestinationregister.SoCUBE[D,E]takeswhatevervalueisinE,cubesit,andplacestheresultinD.

StatementsinH

StatementsinARS-2Assembly

A=20B=CUBE(A)

MOVE[A,20]CUBE[B,A]

Sonowthereisaone-to-onecorrespondencebetweenthestatementsinH,onthe

right,andthestatementsinARS-2,ontheleft.The"semanticgap"hasbeenclosed,andcompiledcodewillbesmallereasiertogenerate,easiertostore,andeasiertodebug.Ofcourse,theARS-2computerstillcubesnumbersbymultiplyingthemtogetherrepeatedlyinhardware,buttheprogrammerdoesntneedtoknowthat.Alltheprogrammerknowsisthatthereisaninstructiononthemachinethatwillcubeanumberforhim;howithappenshedoesntcare.ThisisagoodexampleofthefundamentalCISCtenetofmovingcomplexityfromthesoftwareleveltothehardwarelevel.

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