i

朝陽科技大學

資訊工程系

碩士論文

實現與分析一個全數位鎖相迴路

The Implementation and Analysis of an All-digital

Phase-Locked Loop

指導教授 : 陳伯岳 博士

研究生 : 蘇鴻隆

中華民國九十五年七月二十日

ii

朝陽科技大學資訊工程系

Department of Computer Science and Information

Engineering

Chaoyang University of Technology

碩士論文

Thesis for Degree of Master

實現與分析一個全數位鎖相迴路

The Implementation and Analysis of an All-digital

Phase-Locked Loop

指導教授 : 陳伯岳博士(Po-Yueh Chen)

研 究 生 : 蘇 鴻 隆(Hung-Lung Su)

中華民國九十五年七月二十日

19,July 2006

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iv

v

vi

摘要

在此論文中主要介紹分析全數位鎖相迴路，在全數位鎖相迴路電路

架構中，相位頻率偵測器的靈敏度及數位控制震盪器效能，決定整體

全數位鎖相迴路的整體效能。在於現今的超大型積體電路的工業技術

中，所強調的不只是電子產品有高的效能，最重要的縮短其生產製造

的時間，所以運用標準電路原件達到自動化並縮短製造時間顯得更加

重要，所提出的全數位鎖相迴路可以運用標準原件縮短製造時間。

在全數位鎖相迴路中數位控制震盪器，決定全數位鎖相迴路鎖定

的時間以及輸出頻寬及頻率，本文中的全數位鎖相迴路具有更適合的

延遲時間、更快的進行階段調整和更寬的鎖定範圍。

本論文完成高效能的數位控制振盪器及高靈敏度的頻率相位偵

測器，縮短全數位鎖相迴路的設計時間及設計的複雜度，非常適合應

用於系統晶片的運用。

關鍵字 : 全數位鎖相迴路,相位頻率偵測器,數位控制震盪器

vii

Abstract

An all-digital phase-locked loop (ADPLL) circuit is presented. The feature of the ADPLL is that its resolution in the Phase and Frequency detector (PFD) and digitally controlled oscillator (DCO) exactly matches the gate-delay time. With the advances in deep-submicron technologies, the demand for high performance and short time-to-market integrated circuits has dramatically grown recently. The utilization of automated synthesis approach benefits from the standard cell-based design flow and hence implements a user-specified ADPLL within a short time.

A DCO is implemented for ADPLL applications. The DCO exactly matches the gate-delay time and is implemented with faster phase alignment and wider locking range using the same number of ring oscillator stages. Simulation results are presented to evaluate the performance of the DCO.

This paper presents a scheme to overcome the limitations of standard cells and to build up high resolution delay cell and high sensitivity PFD. Since both the design time and design complexity of the ADPLL is greatly reduced, the proposed scheme is very suitable for System-On-Chip (SOC) applications. Keywords: All-digital Phase-Locked Loop (ADPLL), Phase Frequency Detector (PFD), Digitally Controlled Oscillator (DCO)

viii

誌謝

(Acknowledgments)

謹於此向我的指導教授陳伯岳博士獻上最誠摯的敬意。感謝教授這

些日子來辛勤的教導，讓我在學業上有很豐富的收穫，更開拓了我對

人事物的看法；由於教授的耐心指導及寶貴建議，使我能順利完成此

論文。

感謝父母親多年來辛苦的養育與栽培，他們提供我一個健全成長與

自由發展的生活環境，並且支持我、關懷著我，讓我能全心全力地求

學，沒有後顧之憂；非常感謝家人的支持與包容。

感謝晶片與系統實驗室的所有成員：感謝林宏儒學長、林漢忠學

長、楊峻泓學長、陳政威學長，感謝他們給予我諸多的建議和幫助，

感謝秦國銘、張志鵬、蔡俊威、林元煌、陳燕虹、黃啟峰、曾約棋,

謝謝他們的討論與指教；也謝謝冠甫、加璠、維恩、廷杰、雅芬、百

發一起研討及陪伴我度過這一些日子讓生活充滿意義；更感謝所有幫

助我、關心我的朋友們。

蘇鴻隆 謹識

中華民國九十五年七月

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Contents

摘要 ix

Abstract ix

誌謝 (Acknowledgments) ix

Contents ix List of Figures ix Chapter 1 Introduction 1

1-1 Research Motivation 1 1-2 Thesis Outline 2

Chapter 2 Overview of A PLL 3

2-1 Analog Phase-Locked Loop (PLL) 3 2-2 Digital Phase-Locked Loop (DPLL) 7 2-3 All-Digital PLL (ADPLL) 102-4 Chapter Summary 11

Chapter 3 All-Digital Phase-locked loop (ADPLL) 12

3-1 ADPLL Design Issues 123-2 ADPLL Basic Block 13

Chapter 4 PFD Overview 14

4-1 Basic Concept 144-2 Finite-State Machine Analysis 164-3 PFD Circuit Design and Analysis 18

4-3.1 Phase Detector 184-3.2 Frequency Detector 20

4-4 Chapter Summary 21

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Chapter 5 DCO Overview 21

5-1 Delay Cell Basic Circuit 215-1.1 AND-OR-INV Basic Circuit 225-1.2 OR-AND-INV Basic Circuit 22

5-2 Delay Line Circuit Overview 245-2.1 Delay Line Based Converter Architecture 245-2.2 Introduction to Digital Delay-Locked Loop 24

5-3 Introduction to Cycle -Controlled Delay Unit (CCDU) 265-3.1 Introduction to Hierarchical Delay Unit (HDU) 275-3.2 High Efficiency DCO Design Using CCDU and HDU 27

5-4 Chapter Summary 28

Chapter 6 System Simulation and Analysis 296-1 PFD Design and Analysis 29

6-1.1 PD Design and Analysis 296-1.2 FD Design and Analysis 306-1.3 PFD Design 31

6-2 DCO Design 326-2.1 CCDU Design 336-2.2 CDU Design 346-2.3 FDU Design 346-2.4 Control Unit Design 36

6-3 ADPLL System Design 37 Chapter 7 Conclusions 40

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List of Figures Figure 2-1 Block diagram of the PLL 3

Figure 2-2 Operating diagram of a four-quadrant multiplier PD 4

Figure 2-3 Basic circuit for the lag loop 5

Figure 2-4 The frequency response of a lag loop 5

Figure 2-5 VCO symbol 5

Figure 2-6 Block diagram of the DPLL 7

Figure 2-7 Traditions of an ideal phase frequency detector 8

Figure 2-8 The waveform of an ideal phase frequency detector 8

Fig 2-9 Output frequency difference signals in a PFD 9

Figure 2-10 A charge pump circuit 9

Figure 2-11 Block diagram of the ADPLL 10

Figure 3-1 Block diagram of the ADPLL 13

Figure 4-1 Block diagram of a digital PFD 14

Figure 4-2 Analog PFD with CMOS design using 12 transistors 15

Figure 4-3 The characteristic of an XNOR gate PD 15

Figure 4-4 Phase tracking process 16

Figure 4-5 PFD state diagram 16

Figure 4-6 PFD change state diagram (a) FSM in F1 (b) FSM in F2 17

Figure 4-6 PFD change state diagram (c) FSM in F3 (d) FSM in F2 17

Figure 4-7 Block diagram of the PFD 18

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Figure 4-8 PD for phase tracking while the phase changes 19

Figure 4-9 FD for frequency search while frequencies change 20

Figure 5-1 The basic circuit for a delay cell 21

Figure 5-2 (a) Fine-tuning stage 22

Figure 5-2(b) Coarse-tuning stage 23

Figure 5-2(c) The CMOS circuit of the proposed delay cell 23

Figure 5-3 Base Delay-Locked Loop 24

Figure 5-4 Block diagram of the line-DCO 25

Figure 5-5 A binary-weighted digital-controlled delay line 26

Figure 5-6 Block diagram for phase resolution improvement 26

Figure 5-7 Hierarchical delay unit (HDU) 27

Figure 5-8 DCO design using CCDU and HDU 28

Figure 6-1 Xilinx IES 7.1i Synthesized design for PD 29

Figure 6-2(a) Q1 represents a phase difference at the PD 30

Figure 6-2(b) Q2 represents another phase difference at the PD 30

Figure 6-3 Xilinx IES 7.1i Synthesized design for FD 30

Figure 6-4(a) Up represents a frequency difference at the FD 31

Figure 6-4(b) Down represents another frequency difference at the FD 31

Figure 6-5 (a) Xilinx IES 7.1i Synthesized design for PFD 31

Figure 6-5(b) PFD output signals 32

Figure 6-6 Xilinx IES 7.1i Synthesized design for DCO 32

Figure 6-7 (a) Xilinx IES 7.1i Synthesized design for CCDU 33

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Figure 6-7(b) CCDU design and analysis 33

Figure 6-8 (a) Xilinx IES 7.1i Synthesized design for CDU 34

Figure 6-8 (b) CDU simulation waveforms 34

Figure 6-9 (a) Xilinx IES 7.1i Synthesized design for FDU 35

Figure 6-9 (b) FDU simulation waveforms 35

Figure 6-10 Xilinx IES 7.1i Synthesized design for control unit 36

Figure 6-11 the simulation results for DCO 37

Figure 6-12 Xilinx IES 7.1i Synthesized design for the ADPLL 38

Figure 6-13 The PFD simulation results 38

Figure 6-14 The simulation results for the DCOs 39

Figure 6-15 The ADPLL simulation results 39

1

Chapter 1 Introduction

1-1 Research Motivation

As VLSI technology rapidly develops, system-level integration and single-chip solution become the mainstream in the industry. Scalable microprocessor and graphic-processor systems can be cost-effectively ported on advanced technologies to reduce the design turn-around time. Although the system-level design flow leads to more cost-effective realizations, it also results in more design complexity and design efforts [1] [2] [5]. However, the utilization of automated synthesis approach benefits from the standard cell-based design flow and hence implements a user-specified ADPLL within a short time [2]. For example, when many ADPLL are employed as clock generation circuits in several ICs, the synchronization among IC modules becomes an essential issue. Elimination of externally attached components (and the need for adjustments), small size, high performance, low cost, improved durability, and more than anything else, high-speed phase locking is also required. Hence, considerable efforts have been spent on the development of high-performance digital interfaces for communication between digital systems.

PLL have been widely used in many high-speed microprocessors and memory chips. If the frequency synthesis is not required, the ADPLL are preferred for their unconditional stability, faster locking time, and better jitter performance. However, with a traditional ADPLL, the applicable frequency range is several megahertz lower than that of an analog PLL. The reason is that the upper limit of operating speed for the applied circuits, such as the counter and analog-to-digital converter (ADC), is determined by the corresponding clock frequency [1] [2].

The ADPLL became more and more popular in recently years. Its digital

nature makes it possible to achieve a very fast locking time. The core of an ADPLL is the digitally controlled oscillator (DCO). The DCO can be applied in wireless receivers for signal synchronization. The resolution of the DCO determines the phase error and frequency mismatch of an ADPLL. Moreover, the operating range of the DCO limits an ADPLL’s pulling range. A DCO can be

2

implemented using an all frequency synthesizer [5].

1-2 Thesis Outline

Applying hardware description language, the proposed system adopts Xilinx ISE 7.1i, Model Technology ModelSim 6.0a, Candence, Hspice, orCAD 9.1, and Pspice for circuit design and simulation. The rest of this thesis is organized as follows.

We will introduce the basic concepts and classification of PLL in Chapter 2.

In Chapter 3, the design of a basic ADPLL is reviewed. Chapter 4 describes the classification and working principle for PFD. A DCO is constructed with some well defined parameters in Chapter 5. Basic component circuits such as base delay cell and Delay-Line-Loop are reviewed as well. Finally, the ADPLL simulation results, conclusions, and future works are provided in Chapter6.

3

Chapter 2 Overview of A PLL Historical development of PLL can be divided into three categories as follows. 1. Analog Phase-Locked Loop (PLL) 2. Digital Phase-Locked Loop (DPLL) 3. All-Digital Phase-Locked Loop (ADPLL) We briefly review these PLL in following sub-sections.

2-1 Analog Phase-Locked Loop (PLL)

The analog PLL is built with purely analog functional blocks as follows. An

analog multiplier is used as the Phase Detector (PD); a Voltage-Controlled Oscillator (VCO) is a ring oscillator constructed by differential inverters; and a Loop Filter is built with a passive or an active filter. The overall block diagram is shown in Figure 2-1[14] [15] [16].

The PD detects the phase difference between the reference clock and the feedback clock. The output phase difference signal is consigned to the Loop Filter. The Loop Filter transforms the signal and then transmits it to the VCO. As a result, the VCO changes its operating frequency and hence changes the output feedback clock signal as well. Then PD detects the new phase difference again, the same feedback process occurs. In this way, the phase error vanishes eventually and the phase locking is completed.

Figure 2-1 Block diagram of the PLL

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A four-quadrant multiplier PD is shown in Figure 2-2[15] which is a perfect analog design. The phase detector is applied for determining the phase relationship between the reference clock and the feedback clock. A number of different logic circuits can be adopted as the four-quadrant multiplier base gates.

Figure 2-2 Operating diagram of a four-quadrant multiplier PD

It is interesting to note that when the PLL is locked, the four-quadrant multiplier PD forces the static phase difference between the reference clock and the feedback clock to an odd multiple of π/2. Furthermore, its average output depends on the duty cycle ( between -πandπ ). This effect induces a static phase error in a PLL.

A basic circuit of the loop filter is shown in Figure 2-3. It is the standard

second-order passive loop filter working together with the third-order VCO in a PLL. Normally, the lag loop gain bandwidth and the phase margin are applied to determine the component parameters in the loop filter design. When locating the minimum phase shift at the unity gain frequency, we must ensure the loop stability. The phase relationship between the phase and the zero allows us to determine the loop bandwidth and the component parameters.

The phase margin is defined as the difference between 180° and the phase of lag loop filter corresponding to unity gain. The diagram of a lag loop in frequency response is shown in Figure 2-4. When the system has a higher phase margin, it would be more stable. However, it suffers from a longer response time and less attenuation of input reference clock. A common rule of thumb is to start the design with a 45° phase margin.

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Figure 2-3 Basic circuit for the lag loop

Figure 2-4 The frequency response of a lag loop

1

1F( ) = (2-1) 1+j

jωωτ

where 1τ =time constant.

VCO is a critical component for a PLL. There are various types of VCO that can be used in a PLL. The idea is to control the output frequency of an oscillator using an input voltage. Most VCO for radio frequency applications generate a pure sinusoidal output waveform whose frequency is controlled by the control voltage VCTR. The basic symbol and I/O relationship of a VCO are shown in Figure 2-5.

Figure 2-5 VCO symbol

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The frequency spectrum of the VCO output should demonstrate ideal phase stability. In other words, the phase noise of a VCO must be as low as possible. The tunable frequency range of a VCO has to cover the entire required frequency range of the interested application. Figure 2-5(b) illustrates the relationship between the input signal and the output angle frequency of an ideal VCO. Different PLL types are built using different component blocks. Following descriptions give brief concept for analyzing and designing a PLL.

The phaseθi and θo are the phase of the reference clock the phase of the output feedback clock respectively. The PD outputθe =θi -θo is the phase difference betweenθi andθo. θe is filtered by the loop filter to produce a controlling voltage Vc. Vc controls the output signal frequency of the VCO. As a result, the feedback loop adjusts the output phaseθo so as to track the phaseθi.

A linear mathematical model for the PLL system is expressed as follows. Assume the output of PD is given by: V ( ) (2 1)d d i oK θ θ= − − and the output frequency of VOC is given by:

( ) ( ) (2 2)VCO o v cs K V sω ω= + − The transfer function of a PLL can be expressed as:

( ) ( ) /( ) (2 3)( ) 1 ( ) /

o O

i O

s K K F s sB ss K K F s s

θ

θ

θθ

= = −+

The quantity BW= KV x Kd is referred to as the “PLL bandwidth”. The

precise form of the transfer function depends on the type of the loop filter used. In this analysis, it is assumed that the type of phase detector used is an ideal multiplier.

A linear model is suitable to explain the tracking performance of a PLL if the PLL is initially locked. If the PLL is initially unlocked, however, the phase error can take on arbitrarily large values, and hence the linear model is no longer

7

valid.

2-2 Digital Phase-Locked Loop (DPLL)

The DPLL is actually a hybrid system built from analog and digital functional

blocks. Only the phase frequency detector is built from a digital circuit. The remaining blocks are still analog circuits. The block diagram is shown in Figure 2-6. A DPLL consists of a phase frequency detector (PFD), a charge pump, a loop filter, and a VCO. The divided by N block is an optional component.

Figure 2-6 Block diagram of the DPLL

The PFD detects the frequency difference and the phase difference between the reference clock and the feedback clock. It produces a sequence of Up or Down pulses which serve as the inputs of the charge pump. These pulses are used to switch current sources which charge or discharge the capacitor of the charge pump. The Loop Filter transforms the signal and feeds it back to the VCO. The VCO outputs a feedback clock, which is controlled by the PLL output voltage. By including a divided-by-N divider in the feedback path, the VCO clock runs N times faster than the reference clock. This enables the VCO change operating frequency. In this manner, the phase error will finally vanish.

In a DPLL the PFD resorts to digital designs. An ideal phase frequency detector is shown in Figure 2-7. It produces an output signal (Up or Down) whose average direct current value is linearly proportional to the phase error between the two periodic input signals (reference clock and feedback clock) [14] [15].

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Figure 2-7 Traditions of an ideal phase frequency detector

The waveform of an ideally linear (for the entire phase difference range of -2πto 2π) PFD is shown in Figure 2-8. When the inputs differ in frequency, the phase difference is denoted byθe =2π(θi-θo)/max(θi ,θo). During the frequency acquisition, the phase difference steps from 0 to +/- 2π when the output clock cycle slips.

Figure 2-8 The waveform of an ideal phase frequency detector The PFD is a circuit triggered by the trailing edges of the inputs (reference clock and feedback clock) to generate the corresponding control signals (Up and Down). With this behavioral model of the PFD, the relative signal waveforms shown in Figure 2-9 can be explained. From this figure, it is clear that Up is used to increase and Down is used to decrease the frequency. The PFD always generates the right signals to equalize the frequency of both input signals.

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Fig 2-9 Output frequency difference signals in a PFD

A charge pump circuit consists of 2 matched current sources, each with a fixed output value CPOUT (charge pump circuit output signals). A charge pump circuit is shown in Figure 2-10 [10] [11]. It serves to convert the two digital output signals Up and Down (from PFD) into an analog signal (voltage or current) which is proportional to the phase difference.

The current sinks from two different sources depending on the state of the switches CPU and CPD. CPU is closed if Up is active while CPD is closed if Down is active. The current vanishes if both switches are open, leaving the output node in a high-impedance state [11] [12].

Figure 2-10 A charge pump circuit

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2-3 All-Digital PLL (ADPLL)

The ADPLL is entirely built from digital functional blocks. It does not

contain any passive components such as resistors and capacitors. Therefore, cell-based design is suitable to be applied. As shown in Figure 2-11, the ADPLL consists of a PFD, a control unit, and a digitally controlled oscillator (DCO).

Figure 2-11 Block diagram of the ADPLL

The PFD detects the frequency difference (or phase difference) between the

reference clock and the feedback clock. The control unit receives the signal produced by the PFD, and generates a set of digitally controlled signals (binary signals) to control the DCO. The functional blocks of the ADPLL imitate the functions of the corresponding analog blocks. Because the ADPLL consists of digital circuits only, there are many kinds of design methods available for implement [13].

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2-4 Chapter Summary

The analog circuits take much time to design and hence require long

turnaround time. Moreover, digital circuits have higher noise immunity than the analog ones. The VCO of an analog PLL or a DPLL produces a continuous frequency band while the DCO of an ADPLL produces a discrete frequency band. In other word, the VCO has higher resolution than the DCO. The digital circuits generally have lower power consumption than the analog ones. An ADPLL may have smaller chip area because the loop filter of an analog PLL or a DPLL always has one or more large capacitors, whose area cannot be efficiently reduced as the process technology improving. An ADPLL also shorten the locking time by appropriately manipulating corresponding digital signals.

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Chapter 3 All-Digital Phase-Locked Loop (ADPLL)

3-1 ADPLL Design Issues

There is not a complete and systematic method to design an ADPLL so far. In this chapter, we try to list some key points when we analyze and design an ADPLL. An ADPLL is entirely built from digital functional blocks and these digital blocks imitate the function of the corresponding analog blocks. An ADPLL consists of three kinds of functional blocks: PFD, control unit, and DCO. Based on the mentioned basic concepts in above, we discuss some design issues as follows before we design an ADPLL [1] [2].

An ADPLL is a feedback system in which the phase of a local oscillator is locked to the phase of an external signal (from a reference oscillator). The phase-frequency detector compares the phase difference (or frequency difference) between the reference clock signal and the feedback clock signal of a frequency divider. According to the phase difference and frequency difference, the control unit provides an appropriate signal to adjust the DCO. In the locked condition, the frequencies of input and output are exactly equal.

The first step is to analyze and design a PFD (chapter 4). It must be sensitive to detect both the frequency difference and the phase difference. The resolution of an ideal PFD should take as higher value as possible. In this manner, the PFD should be equipped with two properties simultaneously. One is to judge the modulating phase and the other is to judge the modulating magnitude. The second step is to analyze and design a DCO (chapter 5). It is the kernel of an ADPLL. The output clock a DCO is discrete, so the resolution of a DCO should be sufficiently high to maintain acceptable functionality. Besides, for searching target frequency and phase easily and efficiently, a DCO should approach to a monotonic response according to the DCO control word.

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3-2 ADPLL Basic Blocks

An ADPLL which achieves fine resolution and fast lock-in time is demonstrated in Figure 3-1. There are four major blocks, one PFD, two DCOs (notice that there are two DCOs in this ADPLL: One is used for tracking the reference clock and the other is used for generating the clock output), and one control unit [2] (a critical component for an ADPLL. There are various types of control units available).

Figure 3-1 Block diagram of the ADPLL

Two DCOs are applied to effectively reduce the output clock jitter. The proposed frequency tracking algorithm (applied by the PFD) uses an adaptive search step to achieve fast lock-in time. These two DCOs and the speedy frequency tracking PFD occupy a large silicon area and hence consume considerable amount of power as well. However, applying this architecture, the design time and effort for building a high-efficiency ADPLL are reduced greatly [1] [2] [4].

14

Chapter 4 PFD Overview

A PD is also called a phase comparator. Its main structure origins from PLL,

and its design methods can be divided into the analog type and the digital type. The different PFD types result in an analog PLL, a digital DPLL, or an all digital ADPLL. In this thesis, we use the digital designed PFD which is a suitable design for an ADPLL.

4-1 Basic Concept

The traditional design of a PFD applies edge-trigger JK flip-flops as shown

in Figure 4-1. The phase detector is in charge for determining the relationship between reference clock and the feedback clock form the phase and frequency of views. For the phase and frequency detector, a number of different logic circuit can be used. However, a digital design always includes two JK flip-flops. Analog approaches, on the other hand, usually employ the CMOS design of 12 transistors as shown in Figure 4-2 [4] [5].

Although the circuit, the function, and the operation are similar, both digital

and analog structures will be reviewed. The key features to be analyzed are focus on the make time, the make cost and the IC size.

Figure 4-1 Block diagram of a digital PFD

15

Figure 4-2 Analog PFD with CMOS design using 12 transistors

The working principle of an XNOR gate PD is illustrated in Figure 4-3. The phase detecting region is between ± π. Furthermore, its average output depends on the length of duty cycles. This kind of phase detector has a dead zone around the balance point. When the phase error is very small, width of phase detector output pulse is very small as well. The control voltage of delay line cannot response to a phase error which is extremely small. This thus induces phase errors or clock jitters.

Figure 4-3 The characteristic of an XNOR gate PD

In both designs, if reference clock signal leads the feedback clock signal, the Up output is asserted to denote the phase difference. Similarly, if reference clock

16

signal lags the feedback clock signal, the Down output is asserted to denote the phase difference. The phase tracking process is demonstrated in Figure 4-4. Comparing the digital phase detector with the analog one, the digital one has a shorter lock time and smaller the dead zone. However, the analog one has smaller IC size and hence lesser power consumption.

Figure 4-4 Phase tracking process

4-2 Finite-State Machine Analysis

The state of a finite-state machine (FSM) moves from an initial state F2

(Q1Q2=00) to F1 (Q1Q2=10) or F3 (Q1Q2=01) state. As shown in Figure 4-5, the state is held until the machine returns to the initial state. In addition to high speed, low power and high phase/frequency sensitivity are also important for the design of PFD. There should be no dead-zone in the PFD characteristics. Because of the sequential order of triggering of F1, F2, and F3, the PFD is not vulnerable to the dead zone [6].

Figure 4-5 PFD state diagram

17

In a PD employing the D-type master-slave flip-flops, signals Q1, Q2 change

values according to the combinations of reference and feedback clocks. Four possible combinations are demonstrated in Figure 4-6(a) (b) (c) (d).

If reference clock is high and feedback clock is low, Q1 outputs high and Q2 outputs low, the FSM goes to state F1 as shown in Figure 4-6(a). This means reference clock is leading, we need to generate an Up control signal.

If both clocks are low, Q2 is held low and Q1 discharges to low, the FSM goes to the initial state F2 as shown in Figure 4-6(b).

Figure 4-6 PFD change state diagram (a) FSM in F1 (b) FSM in F2

When reference clock is low and feedback clock is high, Q2 outputs high

and Q1 stays at low, the FSM goes to state F3 as shown in Figure 4-6(c). This means reference clock is lagging, we need to generate a Down control signal.

Finally, if both clocks are high, Q1 is held low and Q2 discharges to low, the FSM goes to the initial state F2 as shown in Figure 4-6 (d).

Figure 4-6 PFD change state diagram

(c) FSM in F3 (d) FSM in F2

18

4-3 PFD Circuit Design and Analysis

The PFD can detect the phase and frequency errors between the reference

clock and the feedback clock. The PFD produces two sets of output signals, Q1, Q2 (PD output signals) and Up, Down (FD output signals), and sends them to the control unit. In an analog phase–locked loop or a digital delay-locked loop, the pulse width of the Q1 and Q2 (or the Up and Down pulses), which represents the amount of the phase error, controls the leads/low (lags/ high) time for the charge control unit. A typical design for a PFD could be some D Flip-Flops and NAND gates. An implementation of the PFD circuit is displayed in Figure 4-7[1].

Figure 4-7 Block diagram of the PFD

The novel three states PFD applies one NAND gate and four D-flip-flop multiplexers. It generates an Up or a Down signal to switch the current of the control unit. Initially, both outputs are low. When one of the PFD inputs rises, the corresponding output becomes high as well.

4-3.1 Phase Detector

The PD can detect the phase error between the reference clock and the feedback clock. The PD produces two output signals, Q1 and Q2, to feedback into the control unit.

In practice, the phase tracking is like a frequency search process. In other

words, it slightly modifies the signal frequency in order to reach the target phase gradually. We introduce the digital symmetric PD circuit as illustrated in Figure

19

4-8 (a) [1] [6]. In Figure 4-8(b) the phase of the feedback clock is tracking the phase of the

reference clock. Since the phase of the feedback clock lags the phase of the reference clock, the PD increases the frequency of the feedback clock to track the target phase.

On the contrary, in Figure 4-8(c), since the phase of the feedback clock leads the phase of the reference clock, PD decreases the frequency of the feedback clock as a result.

Figure 4-8 PD for phase tracking while the phase changes

4-3.2 Frequency Detector

The Frequency Detector (PD) can detect the frequency error between the

reference clock and the feedback clock. The FD produces two output signals, UP and Down, to feedback into the control unit.

The frequency search process slightly modifies the signal frequency in order to reach the target phase gradually. We introduce the symmetric digital FD circuit as illustrated in Figure 4-9 (a) [1] [7]. The PD outputs two signals (Q1 and Q2) into the FD input signals and generates the corresponding UP and Down signals.

The frequency search is just like the phase tracking process. In Figure 4-9 (b), since the frequency of the feedback clock is less than the frequency of the reference clock, the FD increases the frequency of the feedback clock to reach the target frequency.

On the contrary, in Figure 4-9 (c), since the frequency of the feedback clock is greater than the frequency of the reference clock, FD decreases the frequency of the feedback clock as a result.

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Figure 4-9 FD for frequency search while frequencies change

4-4 Chapter Summary

The proposed ADPLL adopts the PFD shown in Figure 4-7. The control unit

(see Figure 4-8 and Figure 4-9) receives the signals produced by the PFD and generates signals accordingly to appropriately control the DCO. It decides the adjustment for the phase clock and frequency clock. If PFD outputs a signal as phase lags or frequency low, the control unit makes the DCO exporting an increase signal. On the contrary, if the PFD outputs a signal as phase leads or frequency high, the control unit makes the DCO exporting a decrease signal.

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Chapter 5 DCO Overview

In a digital-controlled delay cell, the output delay time is quantized. The resolution of the output delay time must be sufficient to meet the design specifications. The digital control codes are applied to the delay cell, the output delay time difference is defined as the resolution of the delay cell. If an inverter-based (or buffer-based) delay line is used in delay cell design, the delay cell produces different propagation delays by selecting different number of inverters (or buffers). Then the resolution of the delay cell is limited by the delay time of one inverter (or one buffer). However, such a resolution is often not sufficient to be used in an ADPLL design [2] [8].

5-1 Delay Cell Basic Circuit

The DCO is in charge of signals synchronization and hence an important component of an ADPLL. A DCO can be implemented with an all frequency synthesizer. The frequency synthesizer can generate any desired frequency within one cycle. It can be applied as a phase synthesizer as well.

One inverter inverts (compliments) signal while two inverters in series cancel the complementation and form a buffer. The buffer is a base delay cell as well as a DCO base unit. A typical circuit for a delay cell is shown in Figure 5-1. The delay cell period of the ring oscillator is twice the delay time. The delay time of the invertors is the key parameter for modifying the clock period of the ring oscillator. The “input clock” and “output clock” are of the same waveform except in different phases [8] [17].

Figure 5-1The basic circuit for a delay cell

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5-1.1 AND-OR-INV Basic Circuit

The previous designs proposed in [1] provide a better resolution by phase interpolation. The delay matrix, which uses parallel state buffers to enhance the resolution of the delay cell, is proposed in [1] [13]. However, the intrinsic delay time of the phase blender is too large to use in high-speed applications. This is because in the phase blender architecture, high resolution requires increasing of the phase blender stages. Furthermore, its area cost and power consumption is very large as well. Two different low cost and high resolution delay cells are presented in this section.

The fine-tuning delay cell consists of an AND-OR-INV (AOI) cell as shown

in Figure 5-2 (a) [1]. Shunted state buffers can increase the controllable range of the fine-tuning delay cell.

Figure 5-2 (a) Fine-tuning stage

5-1.2 OR-AND-INV Basic Circuit

The coarse-tuning delay cell consists of an OR-AND-INV (OAI) cell as shown in Figure 5-2 (b) [1]. Shunted state buffers can increase the controllable range of the coarse-tuning delay cell. The controllable range of the fine-tuning delay cell should cover one coarse-tuning step.

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Figure 5-2(b) Coarse-tuning stage

The OAI delay cell differs greatly from AOI delay cell in resolution of view.

It has smaller resolution and greater delay time step. In this simulation, a standard 0.35 um 1p4m COMS process cell library is used to construct the delay cell. In the proposed delay cell, there are only six standard cells used. Thus its area cost and power consumption is very low. Moreover, its resolution is also sufficient to be used in an ADPLL design [1]. The CMOS circuit of the proposed delay cell is shown in Figure 5-2(c).

Figure 5-2(c) The CMOS circuit of the proposed delay cell

The utilization of automated synthesis approach benefits from the standard

cell-based design flow and hence implements a user-specified delay cell within a short time. This thesis presents a scheme to overcome the limitations of standard cells and to build up a high resolution delay cell. As a result, both the design time and design complexity of the DCO is greatly reduced.

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5-2 Delay Line Circuit Overview

5-2.1 Delay Line Based Converter Architecture

How we perform delay time variation of digital signals is expressed as follows. A base delay line circuit for jitter measurement is proposed in [9]. However, the resolution is as low as a single gate delay. A significant improvement to delay-gate resolution was recently reported using a Vernier delay line [14]. For implanting a Time-to-Digital Converter (TDC), the architecture based delay cell named Delay-Locked Loop is shown in Figure 5-3. It is a continuous based delay line for making different delay paths. This is a high resolution TDC circuit, where the number of buffers (n) determines the total propagation delay. For example, the delay between the (N+5)th signal and the (N+2)th signal is 6τminus 3τ[13] [15].

Figure 5-3 Base Delay-Locked Loop 5-2.2 Introduction to Digital Delay-Locked Loop Several delay-locked loop architectures have been developed. They can be divided roughly into two categories – Analog Delay-Locked Loop and Digital Delay-Locked Loop. Each of them has different applications depending on system requirements.

In the beginning of this subsection, DCO will be described because the proposed designs in this thesis are of the digital type. A traditional line-DCO is shown in Figure 5-4 [13]. The architecture of this frequency synthesizer based DCO adopts an n-bit frequency control word to configure n multiplexers. In [13], the authors proposed a line-DCO cell which controls the propagation delay time

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of the inverters with an n-bit control word. It consists of n paths and n DCO cells.

Figure 5-4 Block diagram of the line-DCO

They also proposed a multiple path selection DCO with a delay matrix. The delay matrix consists of several parallel state inverters. The DCO is integrated with the path selection, the delay cells, and the delay matrix (which consists of several inverters in parallel).

The control unit receives the signals produced by the PFD and then

generates signals accordingly to appropriately control the DCO. It determines the adjustment for the phase clock and frequency clock. If the PFD outputs a signal as phase lags or frequency low, the control unit makes the DCO export an increase signal. On the contrary, if the PFD outputs a signal as phase leads or frequency high, the control unit makes the DCO export a decrease signal.

Digital type designs require a Binary-Weighted Digital-Controlled Delay Line Loop which is explained as follows. The circuit of a binary-weighted digital-controlled line is shown in Figure 5-5. The number marked at each stage indicates the number of unit delays it provides. The delay line is divided into two sections, coarse tuning and fine tuning. Both of these two sections consist of 4 delay stages. The stages with smaller number of unit delays are put in the front end. This is because the longer the delay is, the more difficult the rise time and fall time of the delay stage can be matched. It may result in large variation in clock duty cycle, especially in low supply voltage. To prevent this problem, stages with smaller size of delay are put in the front end of the whole delay line [13] [15].

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Figure 5-5 A binary-weighted digital-controlled delay line The above method uses two inverters to generate one unit delay. However, there is another method which generates one inverter delay time and hence improves the phase resolution by differential clock inputs (as shown in Figure 5-6). The drawback is that the circuit needs two clock inputs and hence increases the circuit design complexity and power consumption. However, for realizing a small delay time, the delay stage using two inverters is still an attractive and promising approach.

Figure 5-6 Block diagram for phase resolution improvement

5-3 Introduction to Cycle -Controlled Delay Unit (CCDU)

Using the cycle-controlled delay unit (CCDU), a new designed Delay-Locked Loop [2] achieves both wide rage and fast locking operation. To facilitate the DCO for various clock-generation circuits or phase-alignment circuits, the operating frequency range should be as large as possible to meet different product specifications. Furthermore, the wide-range Delay-Locked Loop should tolerate a wide range of input clock frequency. The highest operating frequency of a Delay-Locked Loop is limited by the bandwidth of a single delay unit while the lowest operating frequency is restricted by the length of the delay line.

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5-3.1 Introduction to Hierarchical Delay Unit (HDU)

The core of a DCO design for instance binary-weighted digital-controlled line is the hierarchical delay unit (HDU) shown in Figure 5-7. It consists of three major parts: a controller, a CDU, and a FDU. The FDU controls a least significant bit delay time (fine delay time) while the CDU dominating a coarser delay time [2]. The DCO starts the phase detection with a user CDU search input word. Then FDU improves the resolution in the next stage.

Figure 5-7 Hierarchical delay unit (HDU)

5-3.2 High Efficiency DCO Design Using CCDU and HDU

The DCO can be divided into two parts: a CCDU and a HDU (consists of CDU and FDU). The CCDU is actually an even coarser version of CDU. If the initial phase error is large, the delay units in the CCDU take over to adjust the delay time. The optimum cycle number of the CCDU is determined by the control bits from the controller. The phase error is further reduced within one cycle delay. If the maximum delay of the HDU is larger than one cycle delay of the CCDU, the residue phase error could be compensated by the HDU.

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Figure 5-8 DCO design using CCDU and HDU

In summary, the delay line is formed in a specific order: CCDU, CDU, and then FDU so as to accomplish the same operating frequency range proposed in [2] at the same timing resolution.

5-4 Chapter Summary

In this thesis, the proposed ADPLL adopts the DCO architecture shown in

Figure 5-8. The control unit (see Figure 5-6) receives the signals produced by the PFD and generates signals accordingly to appropriately control the DCO. It decides the adjustment for the feedback clock and output signal.

Three delay-cell cycles are applied to generate an appropriate delay time. There is another method to generate one inverter delay time and improve the phase resolution. However, it requires three clock inputs and hence increases the circuit design complexity and power consumption.

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Chapter 6 System Simulation and Analysis

The proposed ADPLL achieves fine resolution and fast lock-in time. Its block diagram is shown in Figure 3-1. There are three major blocks, namely the phase/frequency detector (PFD), the digitally controlled oscillators (DCOs), and the control unit. Notice that there are two DCOs in this ADPLL. One is used for tracking the reference clock and the other is for generating the clock output.

6-1 PFD Design and Analysis

6-1.1 PD Design

The combination of the two edge-trigger D flip-flops and one AND-gate

constructs the symmetric PD illustrated in Figure 4-8 (a). The thesis uses FPGA design tool named Xilinx ISE 7.1i to synthesize the PD circuit shown in Figure 6-1. The simulation results are demonstrated in Figure 6-2 (a) (b) using ModelSim 6.0a.

Figure 6-1 Xilinx IES 7.1i Synthesized design for PD

The PD determines the relationship between reference clock and the feedback clock from the phase of view. Refer to Figure 4-8(b) and (c) for recalling the definition of signals Q1 and Q2. In Figure 6-2(a), q1 represents a phase difference at the PD. Phase of the feedback clock is tracking the phase of the reference clock since it lags in this case.

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Figure 6-2(a) Q1 represents a phase difference at the PD

On the contrary, in Figure 6-2 (b), q2 represents another phase difference at the PD. Since the feedback clock leads, it should be slowed down gradually.

Figure 6-2(b) Q2 represents another phase difference at the PD

6-1.2 FD Design

The combination of the two edge-trigger D flip-flops constructs the

symmetric FD illustrated in Figure 4-9 (a). The synthesized PD circuit is shown in Figure 6-3. The simulation results are demonstrated in Figure 6-3 (a) (b) using ModelSim 6.0a.

Figure 6-3 Xilinx IES 7.1i Synthesized design for FD

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The FD determines the relationship between reference clock and the

feedback clock from the phase of view. Refer to Figure 4-9(b) and (c) for recalling the definition of signals Up and Down. In Figure 6-4(a), up represents a phase difference at the FD. Phase of the feedback clock is tracking the phase of the reference clock since it lags in this case.

Figure 6-4(a) Up represents a frequency difference at the FD

On the contrary, in Figure 6-4 (b), down represents another phase difference at

the FD. Since the feedback clock leads, it will be slowed down gradually.

Figure 6-4(b) Down represents another frequency difference at the FD

6-1.3 PFD Design

Four edge-trigger D flip-flops and two AND-gates are applied to construct the PFD illustrated in Figure 4-7 (chapter 4). The synthesized PFD circuit is shown in Figure 6-5(a). The simulation results are demonstrated in Figure 6-5 (b).

Figure 6-5 (a) Xilinx IES 7.1i Synthesized design for PFD

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In this case, clock and feedback clock are identical in both phase and

frequency (locking is completed). The resulted q1/q2 and up/down signals are low as shown in Figure 6-5 (b) [23] [24].

Figure 6-5(b) PFD output signals

6-2 DCO Design

The Xilinx IES 7.1i synthesized high sensitivity DCO is demonstrated in Figure 6-6. The output clock is a 12-bit internal signal, which can be divided into two parts: a CCDU output and a HDU output: CCDU [3:0] and HDU [7:0] (HDU[7:0] can be further divided into two parts: CDU [3:0] and FDU [3:0]).

This digital DCO consists of a CCDU, a CDU, a FDU and control unit. The block diagram is shown in Figure 5-8.

Figure 6-6 Xilinx IES 7.1i Synthesized design for DCO

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6-2.1 CCDU Design In this thesis, the design of a high efficiency DCO using CCDU achieves both

wide range and fast locking. The synthesized CCDU circuit is shown in Figure 6-7.

Figure 6-7 (a) Xilinx IES 7.1i Synthesized design for CCDU

The simulation waveforms use Modelsim 6.0a is shown in Figure 6-7 (b). It represents a scene at CCDU output signal (ccout[3:0]).

Figure 6-7(b) CCDU design and analysis The HDU design is an instance binary-weighted digital-controlled line. It is

also a hierarchical design which is described in the following sub-sections.

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6-2.2 CDU Design The CDU output is a 4-bit internal signal. To a certain extent, CDU is

responsible for the delay. The field programmable gate array (FPGA) designed CDU circuit is shown in Figure 6-8(a)

Figure 6-8 (a) Xilinx IES 7.1i Synthesized design for CDU

The CDU adopts the CCDU output signal and produces a finer control word to control the FDU. As shown in Figure 6-8 (b), the CDU is working correctly.

Figure 6-8 (b) CDU simulation waveforms

6-2.3 FDU Design The FDU output is a 4-bit internal signal which controls the DCO output

signal. The FPGA designed FDU circuit is shown in Figure 6-9(a).

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Figure 6-9 (a) Xilinx IES 7.1i Synthesized design for FDU

The FDU input clock for CDU control unit output signal. That FDU control unit output data signal is DCO output signal. The FDU simulation waveforms lookup gate use Modelsim 6.0a show Figure 6-9 (b).

Figure 6-9 (b) FDU simulation waveforms

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6-2.4 Control Unit Design The control unit in a DCO is implemented as shown in Figure 6-10. Integrate

it with CCDU, CDU, and FDU to form the whole DCO (Refer to section 5-4 to recall the corresponding block diagram and descriptions). Now we are ready to simulate the DCO circuit shown in Figure 6-6.

Figure 6-10 Xilinx IES 7.1i Synthesized design for control unit

The basic operating simulation waveforms are shown in Figure 6-11. The resulted waveforms are consistent with the results demonstrated in Figure 6-7(b), 6-8(b), and 6-9(b).

The CCDU in the first place starts coarse search. If the initial phase (frequency) error is large, the input clock can reuse the delay units in the CCDU to increase the delay time. When the phase (frequency) error becomes smaller than the unit delay, the CCDU outputs a “locked” signal to HDU in the next stage. Then the DCO starts making the coarse search and the fine search. Refer to Figure 5-8 (chapter 5) to recall the DCO block diagram.

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Figure 6-11 The simulation results for DCO

6-3 ADPLL System Design

To our best knowledge, there is not yet a complete and systematic method to

design an ADPLL. An ADPLL is built from digital functional blocks only. The ADPLL consists of following functional blocks: a PFD, two DCO, and several control units. Refer to Figure 3-1 (chapter 3) to recall the block diagram and working principle for the ADPLL. The DCO control unit, which costs the most chip area of the DCO (refer to the block diagram in Figure 5-8), consists of a start circuit, an input DCO control unit, a decision making circuit, and an output DCO control unit.

The synthesized circuit for the entire ADPLL system is shown in Figure 6-12.

As shown in Figure 6-13, PFD functions correctly. The control signal q1, q2, up, and down are all low indicating that the locking is completed. The input DCO and the output DCO are also working correctly as shown in Figure 6-14. As shown in Figure 6-15, the ADPLL system provides satisfactory performance.

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Figure 6-12 Xilinx IES 7.1i Synthesized design for the ADPLL

Figure 6-13 The PFD simulation results

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Figure 6-14 The simulation results for the DCOs

Figure 6-15 The ADPLL simulation results

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Chapter 7 Conclusions In this thesis, for ADPLL implementation, a refined all digital frequency synthesizers is designed based on the DCO structure proposed in [1] and [3]. Since the proposed ADPLL can be implemented with standard cells, it maintains good portability over different process technologies. To achieve a faster phase alignment and a larger output range, two frequency control words (for CCDU and HDU) are employed for low and high resolutions respectively. Since the replica delay line occupies a quarter of the area of the core DCO, the area cost and power consumption of the prototype chip is greater than those of other wide-range DCOs. However, applying the proposed architecture, the design time and effort for establishing a high-efficiency ADPLL are reduced significantly. According to the simulation results, the proposed ADPLL functions efficiently. However, due to the FPGA chip characteristics, delay time for a single inverter is too short to be observed. The chip testing and verification encounter some problems. These problems can be solved by ASIC approach or some modification on the FPGA configuration. In the future, as soon as the problem mentioned is solved, a real prototype will be implemented and tested.

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