G. Oliver Stone(603) 883-0086 (Home) os tone@charter.net 41 Louise Dr.(603) 508-2419 (Cell) Hollis, NH 03049

Objective: Principal FPGA/ASIC Design Position

SummaryA highly productive, principal-level engineer with eighteen years of experience in the communications field.

Expertise in the following technologies:• HDL design. Control and data path structures. Multiple clock domains. Resource sharing . Efficient use of

DSP blocks in FPGAs. DSP techniques in FPGA design. • Embedded software development and scripting.• Electrical and optical communications board design.• LAN and WAN communication and interconnect standards (10/100/1000Base-T, POS, ATM, T/E3, PCIe,

HyperTransport). • Optical components including MEMS switches, tunable lasers, Mach-Zehnder modulators, AWG

demultiplexers, and coherent receivers . Expertise with the following implementation tools:

• Verilog and SystemVerilog. (Working knowledge of VHDL).• Altera, Xilinx, and Lattice tool flows and the Synplicity and ModelSim tools. • C, C++, Python and Perl programming languages in both Windows and UNIX environments.• Mentor schematic capture and Cadence layout tools.• Lab equipment (SmartBits, Agilent and TEK oscilloscopes and logic analyzers, soldering station tools).

Accomplishment Highlights• Specified, designed, wrote, compiled and tested control-path FPGAs for several 40-100Gbps optical

modules using the Xilinx Spartan6 family. These FPGAs interface to the card's processor and ASICs and also contain control loops to keep the optics at their optimal operating points. One of these control loops comprised the injection of a dither tone onto a bias voltage through an off-chip DAC, retrieval of the output signal from an ADC, signal processing to extract the effect of the dither tone using DSP blocks, and then adjustment of the bias voltage according to the result. Implementing the optics control loops digitally in the FPGA saved valuable board space, allowing a size reduction of the module.

• Wrote HDL as part of a three person team for a 108,000-register FPGA with 7Mbits of memory, targeted to an Altera Stratix II 180 part. This design offloads up to two companion packet processors and enables generic classification, shaping, and replication of traffic at 10Gbps bi-directionally. My individual accomplishments included interfacing to Altera’s SPI4.2 core, designing an interface to an external TCAM, and creating a weighted round robin algorithm to choose between multicast and unicast traffic. Created design constraints and performed the design compilation. Worked closely with the design verification team and the board design teams to smooth out issues with their tests. This design allows significant performance improvements over designs based on the packet processor alone.

• Retargeted the above design to an ASIC while doubling the supported IO paths and integrating the packet processors. Wrote additional code for End-to-End Flow Control handling, a traffic manager interface, and a simplified packet processor interface. Interfaced with the synthesis group to identify clock domain crossing false paths and other constraints. This ASIC provides greater bandwidth at a lower cost than the discrete solution.

• Implemented a multiple-channel modulator which allowed different modulation modes and symbol rates in an FPGA. Coded a module for BPSK, QPSK, 8PSK , and QAM encoding, one for an optimized root-raised cosine FIR filter, and glue logic to support between 1 and 48 channels at various bandwidths. Optimized the FIR filter design to take advantage of reuse among channels and zeros in the interpolated input stream.

• Architected portions of several ASICs for Boeing’s Transformational Satellite (TSAT) program. These ASICs were responsible for receiving, decapsulating, deframing, storing and forwarding traffic received on the input channels of the satellite. Wrote architecture/register specs with design requirements, performed

sizing/power estimates, analyzed radiation hardness, wrote DV requirements, and interfaced with Boeing’s design team.

• Architected and implemented a board design for an I/O base card for a LAN/WAN security router. Custom base card used either off-the-shelf PMC daughter cards for low-bandwidth IO or custom HyperTransport based cards for high-bandwidth I/O. Designed and coded an FPGA for data path processing and backplane interfacing with a custom SERDES protocol. Schematic design included a Broadcom communications processor for packet processing and control, PCI bridge to Fast Ethernet MACs for interfacing two redundant Switch/Services Cards, dual DDR DIMM interfaces, I²C peripherals, and HT and PCI interfaces for daughter cards. Also responsible for the FPGA implementation of the backplane protocol and system control.

• Engineering liaison for outside vendors developing I/O daughter cards. Worked closely with an external group to generate the layout of these cards, performed extensive lab testing, and helped out our diagnostics group by writing the diagnostic tests for a number of the card’s functions.

• Lead board designer and co-architect for an all-optical WDM switch card. This card allowed adding or dropping of specific wavelengths from a WDM traffic stream. Designed the microprocessor control and statistics gathering system, optical control circuitry, and a separate OC-3 POS (Packet-over-SONET) stream for inter-chassis communication. Wrote verilog code for an FPGA to control data flow and to manage the optics.

• Designed significant portions of a dual OC-48c POS (Packet-over-SONET) blade of a multi-gigabit switch/router. This included board design and schematic entry. Also designed and wrote verilog code for two Xilinx Virtex FPGAs including a 200K gate design to encapsulate outgoing packets, and a 30K gate design to interface the switch fabric with the routing processor. Directed contractors through system simulation. Gave initial placement constraints for this 20”x16” card with actives on both sides. Interfaced with layout house to approve critical routes and final design. Debugged card in the lab running diagnostics and initial software with sample traffic patterns.

• Wrote C++ applications using the Windows GUI libraries for a company that markets foreign language teaching software.

• Performed half of all design and coding of Game-Maker. Game-Maker was a WYSIWYG CAD product for creating tile-based arcade-style games for (486 era) PCs. It enabled users to create original games without any coding. Built using C and C++, Game-Maker incorporated features such as animation, music, sound effects, and full-screen scrolling. Set up and manned the company’s booth at the Consumer Electronics Show in Chicago.

ExperienceJuly 2009 to July 2014. Oclaro, Inc., Acton, MA.Principal Hardware Engineer

• Oclaro's only FPGA designer in New England. Primarily created FPGAs as optics control systems.• Created SystemVerilog test bench suite to verify designs.

February 2009 to July 2009. Innovative Communications Engineering, LLC. (ICE) North Chelmsford, MA.Principal Hardware Engineer

• ASIC architect for satellite communications system.• DSP designer for FPGA-based low-cost modulator.

July 1998 to January 2009. Nortel Networks Billerica, MA.Hardware Engineer, JCI 4

• HDL designer for FPGA/ASIC packet manager.• Lead board designer and co-architect of an all-optical WDM switch card. Developed FPGA code for

control data flow and optics management.• Designer of an I/O base card for a LAN/WAN security router.• Designer of a management card for a multi-service switch, taken from an inherited proof-of-concept design.• Member of a design team responsible for a 108,000 register FPGA (appox 1.5M gates).

January 1997 to July 1998. Cabletron Systems’ Digital Network Products Group (via the acquisition of Digital Equipment’s High-Performance Network division by Cabletron). Littleton, MA.Hardware Engineer

• FPGA and hardware designer of an ATM switch line card.

Fall 1994 to December 1996. Northwestern University Evanston, IL.• Created Master’s thesis that analyzed available ASIC technologies.

Summer 1994. Transparent Language Hollis, NH.• Software engineer developing foreign-language interactive software in C++.

Winter to Spring 1994. Yale University New Haven, CT.• As an undergraduate, added new algorithm to existing timing analyzer software.

1990-1993. Recreational Software Designs Amherst, NH.Vice-President and Co-Founder

• Software engineer creating computer game development systems.

CAE Tool ExperienceCAE Tools:

• Altera’s Quartus II, Altera Qsys, Xilinx ISE and Vivado; Xilinx System Generator for DSP, Xilinx XPS (EDK tool), Lattice Diamond; Synopsys' Synplify; Mentor's Modelsim and Questa; Cadence’s Allegro, Mentor's DX Designer (ViewDraw). Emacs. Eclipse programming environment.

Test Equipment:• HP (Agilent) and Tektronix scopes and logic analyzers; SmartBits and Adtech traffic generators/analyzers;

DVMs; optical power meters, modulation analyzers, and spectrum analyzers.

EducationNorthwestern University, M.S. Electrical Engineering, 1996Yale University, B.S. Electrical Engineering, 1994The Derryfield School, Manchester, New Hampshire, Graduated 1990Research Science Institute, Washington D.C., Summer 1989

Honors and AwardsWalter P. Murphy Fellowship Recipient (Northwestern)National Merit Scholarship FinalistDartmouth Book AwardRensselaer Polytechnic Institute Medal for Mathematics and Science1990 Derryfield Scholar Athlete Award; Math Award; Science AwardSelected as a Research Science Institute student (about 80 students selected annually world wide)