On-Chip Voltage and Timing Diagnostic Circuits · Presentation Flow We’ll discuss key metrics and the limitations of off-chip measurements Then we’ll see how to solve these with

On-Chip Voltage and Timing Diagnostic Circuits

Frank O’Mahony

Advanced Design, Intel Hillsboro, Oregon

October 2014

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Why Measure Time/Voltage On-Chip?

1. Routing signals to equipment can filter and corrupt measurement

Loss, delay, discontinuities, loading, noise

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Scope

Pkg/Socket

PCB

Connectors

Cable

Circuit Die Pkg/Skt PCB Connector Cable

Scope

Why Measure Time/Voltage On-Chip?

2. Some measurements must be done w/o external equipment

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Wafer Sort

Ref: www.besi.com

In-Situ Test

Ref: www.intel.com

Presentation Flow

We’ll discuss key metrics and the limitations of off-chip measurements

Then we’ll see how to solve these with on-die measurement circuits

My objective is that you will leave today with a set of simple but very useful techniques that you can apply to your own designs

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Outline

Delay Measurement

Power Supply Characterization

I/O System Characterization

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Outline

Delay Measurement

Delay Metrics

Off-chip measurement limitations

On-Chip Phase Detector

Code Density Test (CDT)



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Delay/Skew Measurements

Measuring the delay between two or more signals (often clocks) can be critical for circuit debug and characterization

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clk skew

refclk PLL clkout

Lock error

ckI

ckQ ckΦ

phase_sel

Phase Interp.

Phase linearity

Off-Chip Clock Skew Measurement

External measurement limitations

Delay matching to equipment delay error

Filtering for high-speed signals delay error

VCM and edge rate differences cause error

Delay stability poor repeatability

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Scope ckA

ckB

TA

TB

TA≠TB

Scope ckA ckB

ckref

trig

Basic off-chip setup Improved off-chip setup

Poor ck edge and repeatability

On-Chip Phase Detector

Mix phase difference down to DC on chip

Other types of phase detectors can also work

Measure DC component off- or on-chip

Shared Mixer reduces mismatch. Still has MUX mismatch.

Requires calibration for Voltage-to-Time constant (A)

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N:1

Mixer LPF

Vmeas

-π π 0

cos 𝜔𝑡 + 𝜃1 cos 𝜔𝑡 + 𝜃2

cos 𝜔𝑡 + 𝜃𝑁

cos 𝜔𝑡 + 𝜃𝑟𝑒𝑓

𝜃𝑛 − 𝜃𝑟𝑒𝑓

A ∙ cos 𝜃𝑛 − 𝜃𝑟𝑒𝑓

Example: 10GHz Clock Skew Measurements

Meas. resonant clock grid skew w/ sub-ps accuracy

Minimize/match routing to phase detectors

Measure externally with voltmeter

Calibrate externally using adjustable delay line

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Ref: F. O'Mahony, ISSCC 2003

Voltmeter 𝜃𝑟𝑒𝑓

CKref chip boundary T

Code Density Test (CDT) Method

Basic Idea: Count the # of Reference Edges that occur between two clock edges

Likelihood of “Hit” is ΔT/T

Asynchronous ring VCO provides uniform Edge PDF

Jitter and spread-spectrum improve the distribution

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ck

ck+ΔT

Async. Edge PDF

ΔT[°]

360 180 0

1

0

ΣHits ΣEdges

ΔT

T

Ref: J. Doernberg, JSSC 1984

Code Density Test (CDT) Method

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ck

ck+ΔT

ΔT

XOR

ΣEdges

ck ck+ΔT ΔT(periods)

Σ

Σ ΣHits

ΣHits ΣEdges

Async. Edge PDF

Async.

Oscillator

ΔT[°]

360 180 0

1

0

ΣHits ΣEdges

Spread

Spectrum

tune

T

Ref: M. Mansuri, VLSIC, 2012

Time-Domain Circuit Operation

Likelihood of “Hit” is ΔT/T

Async. clock period must be >2∙ΔTmax

A simple VCO frequency calibration ensures this

Jitter helps by randomizing edge location 13 of 63

ck

ck+ΔT ΔT

# Hits

# Edges

0 1 2

0 4 3 2 1

T

Async. Clock

Delay Measurement Accuracy

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Re[Φck]

Im[Φck]

Model w/ Binomial Distrib. (think “many coin flips”)

Accuracy improves as (1/ΣEdges)0.5

Higher Resolution Longer measurement time

ΔT/T

Synchronizer

Synchronizer aligns samples across full 360˚ range

Clocks for ΔT=N∙Tck+Δt are identical. Synchronizer

adds programmable # of cycles of delay.

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ck

ck+ΔT

Async.

Oscillator sel

0∙Tck

0.5∙Tck

1∙Tck edge

Delay Measurement Range

Measure ck[1..N] relative to ck,fixed

ck[1..N] are all later than ck,fixed

Removes circuit mismatch (e.g. FF’s) except Mux

Use cycdel to select which edges to compare

Synchronizer extends range to >360° 16 of 63

360 180 0

1

0

ck,fixed

ΣHits ΣEdges

ck[1..N]

cksel cycdel

Delay Analyzer

ck

ck+ΔT

ΔT[°]

Detailed Circuit Implementation

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Entirely digital implementation

Counter depth depends on required accuracy

DCO

ck,

fixed

ck+DT

XO

R LFSR 2M

Cntr

rst

fine[4:0]

ckDCO

Async. DCO + LFSR

Phase detector

24

16

cyccnt

edgecnt

2N

Cntr 24

FF D

FF D

SCK

Syn

c

SCK+DT

RZ

frz_sel[3:0]

cnt

frz

rst

cnt

frz

rst cycdel

ck[1..N]

cksel

Ref: M. Mansuri, VLSIC, 2012

Measured Phase Interpolator (PI) Linearity

Fully on-die measurement of quadrature PI w/ CDT

Phase transfer function provides INL/DNL

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0 33 66 99 1320

45

90

135

180

225

270

315

360

PI phase select code (132 steps)

Pha

se (

degre

es)

PI ckI

ckQ ckΦ

phase_sel

Delay Analyzer

phase_meas

Measured Phase Error – Repeatability

Measurement error reduces as (1/ΣEdges)0.5

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106

108

1010

10-5

10-4

10-3

Total DCO cycles count

Rep

eata

bili

ty (

rms)

no

rmaliz

ed

to c

lock p

eriod

Ref: M. Mansuri, VLSI 2012

ΣEdges

σ(ΔT/T)

Outline

Delay Measurement


Power Supply metrics


Real vs. Equivalent time measurement

Supply noise waveform

Supply impedance

Supply noise spectrum


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Power Supply Metrics

Used to design, model and debug the chip

Examples: Quantify Vcc droop V(t)

Verify Grid model Z(f)

Find aggressors PSD(f)

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frequency

PSD

(f)

Noise spectrum

Power Delivery Impedance

Time

V(t

) Waveform Capture

|Z(f

)|

frequency

Power Supply Grid on Die

External Power Supply Measurements

Packages commonly have supply probes


External probing loads the power supply

Probe measurements are not local

Limited # of probe points due to pkg routing

Package filters the supply measurements

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Spectrum Analyzer

Oscilloscope

Time-Domain Reflectometer (TDR)

On-Die High-Speed ADC

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Ideally embed local ADCs to digitize these metrics

High resolution (10+ bits) and BW (>1GHz) presents a significant implementation challenge

ADC Vcc(t) meas

Power Supply Grid on Die

Real vs. Equivalent-Time Measurement

One-shot meas.

Most complete info

Time, spectral

Limited by ADC fsamp, resolution

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TS

T+TS

Eqiv. time

Voltage

Voltage

Real time

Equivalent time

time

Periodic waveforms

No spectral info.

Effective BW and resolution not limited by ADC

TS

T

Equivalent-Time Measurement

Time Base Generator (TBG) provides strobe

Sweeps strobe position in equivalent time

Sampler output is postprocessed (e.g. averaged)

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strobe

ckref

wave

Time Base Generator

Post- processor

Sampler out

Refs: E. Alon, Trans. Adv. Pkg. 2009. S. Nafzigger, JSSC 2006.

Tdelay Treset

Treset

Tdelay

Sampler Option #1: 1-bit Comparators

Programmable threshold Voltage CDF/PDF

Center of this PDF is the Average Voltage (μ)

CDF/PDF also captures Voltage Noise(e.g. σ)

…along with comparator noise and strobe jitter

Extract fit to distribution (normal, uniform, sinusoid)

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strobe

1-bit ADC

Vth

Vin Σ cnt

All 1’s

All 0’s

Vin Equal

Vin=Vth

cnt

Sampler Option #1: 1-bit Comparators

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strobe

1-bit ADC

Vth

Vin Σ cnt

Vth 0

1

0

CDF

PDF (CDF deriv.)

cnt

# strobes

0.5

Programmable threshold Voltage CDF/PDF

Center of this PDF is the Average Voltage (μ)

CDF/PDF also captures Voltage Noise(e.g. σ)

…along with comparator noise and strobe jitter

Extract fit to distribution (normal, uniform, sinusoid)

Vth=Vin

Waveform Capture w/ 1-bit Comp.

Combine 1-bit ADC with Equivalent-Time sampling to get full Waveform Capture

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strobe

1-bit ADC

Vth

Vin Σ cnt

T

Equiv. Time (T) Ref. K. Soumyanath, JSSC 1999.


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strobe

1-bit ADC

Vth

Vin Σ cnt

T

Equiv. Time (T)


Ref. K. Soumyanath, JSSC 1999.


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strobe

1-bit ADC

Vth

Vin Σ cnt

T

Equiv. Time (T)


Ref. K. Soumyanath, JSSC 1999.

Example: Simple Power Supply Measurement

Re-used RX sampler from to sample Vcc,noise

AC couple Vcc,noise sets correct common mode for sampler

Limits measurement to freq > RC

Simplest TBG – strobe is the delayed noise signal

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Ref: F. O'Mahony, VLSIC 2006

Measured Noise @ 400MHz 100

50

0

0 1 2 3

Vnois

e [

mV]

Vcc,avg

Vss,avg

Vcc,noise

LPF

Voltmeter

Noise injector

Vth

Pulse Gen.

T

Time [ns]

Rbig

Sampler Option #2: VCO-based ADC

Idea #1: Count Async. VCO edges during fixed ΔT

Pro: Directly attach VCO to power supply, real- or equivalent-time meas.

Con: Quant. error trades off with fint and fNyq

This is a variation of the Code Density Test!

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samp

Cntr (Σ) cnt

VCO

cnt

Vcc

VCO

samp Tint

Ts

0 1 2 3 0 1

en


Idea #2: Sample-and-Hold the supply voltage

Pro: Quantization error is independent of fint and fNyq*

Con: S/H leakage, Supply voltage buffer, Equivalent-Time measurement only (or else fNyq degrades)

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Ref: E. Alon, VLSIC 2004

Vcc

samp

Vbuf

0 1 2 3 4 5 6 7 cnt

vco

Tint

Ts (equiv. time)

Vbuf

vco

*Note: This is the Equivalent-Time Nyquist frequency


Idea #3: Very short aperture with averaging

Pro: Quantization error independent of fint and fNyq. Directly connect VCO to power supply. No sampling switch. Very short Tint, set by passive RC and calibrated.

Con: Not capable of real-time measurement, increased measurement time

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Ref: V. Abramzon, E. Alon, ESSCIRC 2005

cnt

Vcc

vco

samp Tint

1 0 2

samp’ XOR

samp’

cnt

samp

VCO RZ

Cntr

Tint

Sampler Calibration

Map Vcccnt with DC sweep of Vcc

Can be approximated as linear fit

Avoid operating close to VT - Variation/Linearity

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XOR

samp’

cnt

samp

VCO RZ

Cntr

cnt

Vcc [V]

VT Tint

Unknowns are removed w/ this

calibration

RC delay is not a function of Vcc,noise

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TBG Cntrs

Samp[0]

PSN inj. noiseinj

clk cnt

Samp[5] Ref: F. O’Mahony, ISSCC 2010

TBG, Cntrs and PSN inj.

I/O Lanes

I/O Lanes

Scan

Noise Samplers

Supply Noise Meas. on I/O Testchip

noiseinj

en[1:N]

Vcc

Periodic Noise Waveform Capture

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Probes local Vcc noise waveforms

1GHz Noise

0 0.2 0.4 0.6 0.8 1

0.78

0.8

0.82

0 0.2 0.4 0.6 0.8 1

0.78

0.8

0.82

0 0.2 0.4 0.6 0.8 1

0.78

0.8

0.82

Time [ps]

260μm

780μm

1300μm

Voltage

Time [ns]

Noise propagation

Power Supply Impedance Meas.

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0 1 2 3 4 5

x 10-8

-0.1

0

0.1

Time

Vo

lta

ge

Step Response

0 1 2 3 4 5

x 10-8

-2

0

2

x 108

Time

Vo

lta

ge

Impulse Response

107

108

109

0

0.2

0.4

0.6

Frequency [Hz]

Z(f

) [

]

Frequency Response

0 1 2 3 4 5

x 10-8

-0.1

0

0.1

Time

Vo

lta

ge

Step Response

0 1 2 3 4 5

x 10-8

-2

0

2

x 108

Time

Vo

lta

ge

Impulse Response

107

108

109

0

0.2

0.4

0.6

Frequency [Hz]

Z(f

) [

]

Frequency Response

0 1 2 3 4 5

x 10-8

-0.1

0

0.1

Time

Vo

lta

ge

Step Response

0 1 2 3 4 5

x 10-8

-2

0

2

x 108

Time

Vo

lta

ge

Impulse Response

107

108

109

0

0.2

0.4

0.6

Frequency [Hz]

Z(f

) [

]

Frequency Response

[V]

[10

8 V

] Z(f

)[Ω

]

Time [ns]

Time [ns]

Freq.[Hz]

Step Response (w/ current step)

Impulse Response

Freq. Response Z(f)

Impedance Measurement Example

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101

102

103

0

0.1

0.2

0.3

0.4

0.5

Frequency [MHz]

|Z(f

)| [

]Power Delivery Response from Step

Neg. step

Pos. step

Note that Q depends on the power grid loading

Measuring PSD w/ Autocorrelation

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V

time

s1 s2 s1 s2 s1 s2

R()

DFT Power Spectral

Density PSD(f)

Circuitry for PSD Meas.

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Measure R() with dual samplers

Digitally sweep = ts2-ts1

DFT of R() = PSD (post-process off-chip)

Cntr

TBG s1

s2

Samp2

Samp1

Vcc(t)

clk

ts1

ts2

Cntr

Cntr

s1

s2

s2_acc

s1_acc

r_acc

Ref: E. Alon, VLSIC 2004

PSD Measurement Example

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600 620 640 660 680 700 720 740 760-0.01

0

0.01

R(

) [V

2]

[ns]

102

103

-50

-40

-30

-20

Frequency [MHz]

PS

D [

dB

V]

R(

) [V

2]

PSD

[dBV]

[ns]

Freq. [MHz]

600 620 640 660 680 700 720 740 760-0.01

0

0.01

R(

) [V

2]

[ns]

102

103

-50

-40

-30

-20

Frequency [MHz]

PS

D [

dB

V] -22.7dBV (200mV-pp)

Outline

Delay Measurement



Bit Error Rate (BER) Eye

Waveform capture

RX noise

Clk-data jitter

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Transceiver Metrics

Link measurements

BER eye / Eye Margins

Receiver noise

Clock/Data jitter

Waveform capture

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TX RX

PI ck,RX

ck,TX

Din Dout [1 0 1 1 0 0 1 0 1 1] [1 0 1 1 0 0 1 0 1 1]

V

t

1 0 1 1 0 0 1 0 1 1

BER Eye and Margins

Probability of error in Equivalent time

Sweeps Voltage and Equivalent Time

“Margin” represents how robust the link is

Voltage margin (vert.), Timing margin (horiz.)

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V

Time

1UI

Time [UI]V

olta

ge

[V

]

-0.5 0 0.5

-0.06

-0.04

-0.02

0

0.02

0.04

0.06 -10

-9

-8

-7

-6

-5

-4

-3

-2

-1

10X BER

Bit Error Ratio Eye

BER Eye and Margins

Probability of error in Equivalent time

Sweeps Voltage and Equivalent Time

“Margin” represents how robust the link is

Voltage margin (vert.), Timing margin (horiz.)

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V

Time

1UI

10X BER

0UI 1UI

Timing Margin

BER Eye Measurement

Phase Interpolator (PI) Time Sweep

Sampler Offset Voltage Sweep

Masking can be used optionally to target certain characteristics

e.g. Loop-unrolled eye, Even/Odd eyes

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Vth

Pattern Checker

Mask Error Cntr data

clk

delay

Optional

PI Cycle Cntr

BER Eye Measurement

Keep in mind Nerr/Nbits is just an estimation of BER

Rule of Thumb: 95% Confidence Level requires error-free transmission for Nbits = 3xBERmin

e.g. No errors for 3x1012 bits indicates BER≤10-12 with 95% certainty

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Pass

Fail

V

Time

Ref: http://cp.literature.agilent.com/litweb/pdf/5989-2933EN.pdf

BER Eye Measurement

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V

# errors

Keep in mind Nerr/Nbits is just an estimation of BER

Rule of Thumb: 95% Confidence Level requires error-free transmission for Nbits = 3xBERmin

e.g. No errors for 3x1012 bits indicates BER≤10-12 with 95% certainty

Time

Ref: http://cp.literature.agilent.com/litweb/pdf/5989-2933EN.pdf

Measured BER Eye Example

Often measure a subset of points to save time

Voltage or Time Margin “bathtub” plots

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Time [UI]

Vo

lta

ge

[V

]

-0.5 0 0.5

-0.06

-0.04

-0.02

0

0.02

0.04

0.06 -10

-9

-8

-7

-6

-5

-4

-3

-2

-1

10X BER

Voltage [V]

Time [UI]

RX Sampler Characterization

Voltage CDF (PDF) RX characterization

Reflects all RX noise as “input referred”

Fully in-situ if TX provides VDC

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Vth

Cntr VDC

clk All 1’s

All 0’s Vth

cnt

Input-Referred Voltage Noise

RX Sampler Characterization

Voltage CDF (PDF) RX characterization

Reflects all RX noise as “input referred”

Fully in-situ if TX provides VDC

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PDF

Vth [mV] -10 0 +10

10-2

10-4

10-6

10-8

σ=1.1mV-rms Bimodal=1mV-pp

Vth

Cntr VDC

clk

Input-Referred Voltage Noise

Clock-Data Jitter

Time CDF (PDF) RX clk-data jitter

Fully in-situ if TX provides “slow clock”

Applicable to any clock circuit

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PI

N

Cntr clk

delay

Slow clk

Sweep sampler delay

All 1’s All 0’s

cnt

Slow clk

Ref: B. Casper, ISSCC 2006

Clock-Data Jitter

Time CDF (PDF) RX clk-data jitter

Fully in-situ if TX provides “slow clock”

Applicable to any clock circuit

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PDF

Time [ps] -5 0 +5

10-2

10-4

10-6

10-8

σ=820fs-rms

PI

N

Cntr clk

delay

Slow clk

Ref: B. Casper, ISSCC 2006

On-die waveform capture

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Equiv. Time

Vth

PI

N

Cntr

data

clk

delay

Ref: B. Casper, JSSC 2003

Mask 1:N periodic N-bit waveform

CDF mean = V(t)

PI sweeps time


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Equiv. Time


CDF mean = V(t)

PI sweeps time

Vth

PI

N

Cntr

data

clk

delay



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Equiv. Time


CDF mean = V(t)

PI sweeps time

Vth

PI

N

Cntr

data

clk

delay


Waveform Capture Example

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0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

-0.25

-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2

0.25

Time (nsec)

Vo

ltag

e (

V)

Voltage [

V]

Time [ns]

1 0 1 1 1 0 0 0 1 0 0 0 1 1 0 1

Summary

On-die measurement is useful when:

No external equipment available

Accuracy lost by routing out to scopes

A simple set of digital-friendly techniques provide accurate time and voltage on-chip

Code Density Test

Equivalent time/Sub-sampling/Bit Masking

Time/Voltage sweep with 1-bit ADC

Use measurement circuits that are already on chip!

Offset comparators, phase shifters, digital counters, pattern checkers

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Key Refs: Delay Measurement

F. O'Mahony et al. "A 10-GHz global clock distribution using coupled standing-wave oscillators,“ ISSCC 2003, paper 24.4. Expanded version in JSSC, Nov. 2003, pp. 1813-1820.

J. Doernberg et al., "Full-speed testing of A/D converters," JSSC, pp. 820- 827, Dec 1984.

L.-M Lee et. al, "A sub-10-ps multiphase sampling system using redundancy," JSSC Jan. 2006, pp. 265-273.

L. Xia, et al., “Sub-2ps, static phase error calibration technique incorporating measurement uncertainty cancellation for multi-gigahertz time-interleaved T/H circuits,” TCAS-I, Jan. 2012, pp.1-9.

Mansuri, M. et al., "An on-die all-digital delay measurement circuit with 250fs accuracy," Symp. VLSI Circuits (VLSIC) 2012, pp.98-99.

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Key Refs: Power Supply Measurement

E. Alon et al., “Circuits and Techniques for High-Resolution Measurement of On-Chip Power Supply Noise,” Symp. VLSI Circuits (VLSIC) 2004, pp. 463-466.

V.A. Abramzon et al., "Scalable circuits for supply noise measurement," ESSCIRC 2005., pp. 463- 466.

S. Naffziger et al., "The implementation of a 2-core, multi-threaded itanium family processor," JSSC, pp. 197-209, Jan. 2006.

E. Alon, "On-Die Power Supply Noise Measurement Techniques," IEEE Transactions on Advanced Packaging, pp.248-259, May 2009.

F. O'Mahony et al., "A Low-Jitter PLL and Repeaterless Clock Distribution Network for a 20Gb/s Link," Symp. VLSI Circuits (VLSIC), 2006, pp.29

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Key References: I/O Characterization

Soumyanath, K. et al., "Accurate on-chip interconnect evaluation: a time-domain technique ," JSSC, pp.623-631, May 1999.

M. Takamiya, M. Mizuno, and K. Nakamura, “An on-chip 100GHz-sampling rate 8-channel sampling oscilloscope with Embedded sampling clock generator,” ISSCC 2002.

B. Casper et al., "An 8-Gb/s simultaneous bidirectional link with on-die waveform capture," JSSC, pp. 2111- 2120, Dec. 2003.

D. Oh et al., "In-situ characterization of 3D package systems with on-chip measurements," Electronic Components and Technology Conference (ECTC), 2010 pp.1485-1492.

M. Mueller et al., “Total Jitter Measurement at Low Probability Levels, Using Optimized BERT Scan Method”, Agilent White Paper. http://cp.literature.agilent.com/litweb/pdf/5989-2933EN.pdf

B. Casper et al., "A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS," ISSCC 2006, pp.263-272.

F. O’Mahony et al., “A 47x10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45nm CMOS,” JSSC, pp. 2828 - 2837, Dec. 2010.

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http://cp.literature.agilent.com/litweb/pdf/5989-2933EN.pdf





Documents

On-Chip Voltage and Timing Diagnostic Circuits · Presentation Flow We’ll discuss key metrics and the limitations of off-chip measurements Then we’ll see how to solve these with