OpAmp (OTA) Design

OpAmp (OTA) Design

The design process involves two distinct activities:

• Architecture Design– Find an architecture already available and

adapt it to present requirements– Create a new architecture that can meet

requirements

• Component Design– Design transistor sizes– Design compensation network

All op amps used as feedback amplifier:

If not compensated well, closed-loop can be oscillatory or unstable.damping ratio ≈ phase margin PM / 100

Value of : 1 0.7 0.6 0.5 0.4 0.3Overshoot: 0 5% 10% 16% 25% 37%

0 2 4 6 8 10 12 14 16

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

=0.7

=1

=2

=5

=10

=0.1

=0.2

=0.3

=0.4=0.5=0.6

G(s)=n2/(s2+2

ns+

n2)

Unit step responses for various

nt (radians)

Bode Diagram

Frequency (rad/sec)

Phase (

deg)

Magnitude (

dB

)

-50

0

50

100Gm = 18.065 dB (at 1.4145e+009 rad/sec), Pm = 38.171 deg (at 4.2821e+008 rad/sec)

104

105

106

107

108

109

1010

-270

-225

-180

-135

-90

-45

0

UGF: frequency at which gain = 1 or 0 dBPM: phase margin = how much the phase is above critical (-180o) at UGF

Closed-loop is unstable if PM < 0

PM

UGF

Two Stage Op Amp Architecture

z

Bode Diagram

Frequency (rad/sec)

Pha

se (

deg)

Mag

nitu

de (

dB)

-40

-20

0

20

40

60

80Gm = -19.172 dB (at 7.4229e+008 rad/sec), Pm = -22.486 deg (at 2.3493e+009 rad/sec)

106

107

108

109

1010

1011

-270

-225

-180

-135

-90

-45

0

GM<0

PM<0

p1 p2 z1

UGF

Bode Diagram

Frequency (rad/sec)

Pha

se (

deg)

Mag

nitu

de (

dB)

-50

0

50


104

105

106

107

108

109

1010

-270

-225

-180

-135

-90

-45

0

UGF

p1 p2

Bode Diagram

Frequency (rad/sec)

Pha

se (

deg)

Mag

nitu

de (

dB)

-100

-50

0

50


104

105

106

107

108

109

1010

1011

-270

-225

-180

-135

-90

-45

0

PM

GM

p1 p2 z1

UGF

Types of Compensation• Miller - Use of a capacitor feeding back around a

high-gain, inverting stage.– Miller capacitor only– Miller capacitor with an unity-gain buffer to block the

forward path through the compensation capacitor. Can eliminate the RHP zero.

– Miller with a nulling resistor. Similar to Miller but with an added series resistance to gain control over the RHP zero.

• Self compensating - Load capacitor compensates the op amp (later).

• Feedforward - Bypassing a positive gain amplifier resulting in phase lead. Gain can be less than unity.

General Miller effect

v1 v2=AVv1

i

i = (v1-v2)/Zf

=v1(1-AV)/Zf

= - v2(1-1/AV)/Zf

i=v1/Z1

i=-v2/Z2

v1 v2

i

Miller compensator capacitor CC

C1 and CM are parasitic capacitances

DC gain of first stage:

AV1 = -gm1/(gds2+gds4)=-2 gm1/(I5(2+ 4))

DC gain of second stage:

AV2 = -gm6/(gds6+gds7)=- gm6/(I6(6+ 7))

Total DC gain:

AV = gm1gm6

(gds2+gds4)(gds6+gds7)

GBW = gm1/CC

2gm1gm6

I5I6 (2+ 4)(6+ 7)AV =

Zf = 1/s(CC+Cgd6) ≈ 1/sCC

When considering p1 (low freq), can ignore CL (including parasitics at vo):

Therefore, AV6 = -gm6/(gds6+gds7)

Z1eq = 1/sCC(1+ gm6/(gds6+gds7))

C1eq=CC(1+ gm6/(gds6+gds7))≈CCgm6/(gds6+gds7)

-p1 ≈ 1 ≈ (gds2+gds4)/(C1+C1eq) ≈ (gds2+gds4)/(C1+CCgm6/(gds6+gds7))

≈ (gds2+gds4)(gds6+gds7)/(CCgm6)

Note: 1 decreases with increasing CC

At frequencies much higher than 1, gds2

and gds4 can be viewed as open.

C1

CC

CL

vo

Total go at vo:

gds6+gds7+gm6

CC

CC+C1

Total C at vo:

CL+C1CC

CC+C1

-p2=2=

CCgm6+(C1+CC)(gds6+gds7)

CL(C1+CC)+CCC1

Note that when CC=0, 2 = gds6+gds7

CL

As CC is increased, 2 increases also.

However, when CC is large, 2 does not increase as much with CC. 2 has a upperlimit given by: gm6+gds6+gds7

CL+C1

Hence, once CC is large, its main effect isto lower 1, and hence lower GBW.

≈gm6

CL+C1

When CC=C1, w2 ≈ (½gm6+gds6+gds7)/(CL+½C1)

Also note that, in contrast to single stage amplifiers for which increasing CL improvesPM, for the two stage amplifier increasingCL actually reduces 2 and reduces PM.

Hence, needs to design for max CL

There are two RHP zeros:

z1 due to CC and M6

z1 = gm6/(CC+Cgd6) ≈ gm6/CC

z2 due to Cgd2 and M2

z2 = gm2/Cgd2 >> z1

z1 significantly affects achievable GBW.

gm6/(CL+C1)f (I6)

z1 ≈ gm6/Cgd6

A0

2

-90

-180

1 z2 ≈ gm2/Cgd2

No PM

gm6/(CL+C1)f (I6)

z1 ≈ gm6/Cgd6

A0

2

-90

-180

1

z2 ≈ gm2/Cgd2

No PM

z1 ≈ gm6/Cc

gm6/(CL+C1)f (I6)

z1 ≈ gm6/CC

A0

2

-90

-180PM

1

gm1/CC

It is easy to see:

PM ≈ 90o – tan-1(UGF/2) – tan-1(UGF/z1)To have sufficient PM, need UGF < 2

and UGF << z1

In such case, UGF ≈ GB ≈ gm1/CC = z1 * gm1/gm6.

PM ≈ 90o – tan-1(GB/2) – tan-1(GB/z1)

Hence, need: GB < 2GB << z1

PM requirement decides how much lower:

Possible design steps for max GB• For a given CL and Itot

• Assume a current share ratio i.e.– I6+I5 = Itot, I5 = I6 , I1 = I2 = I5/2

• Size W6, L6 to achieve max gm6/(CL+Cgs6) which is > 2

– C1 W6*L6, gm6 (W6/L6)0.5

• Size W1, L1 so that gm1 ≈ 0.1gm6

– this make z1 ≈ 10*GBW

• Select CC to achieve required PM– by making gm1/CC < 0.5 2

• Check slew rate: SR = I5/CC

• Size M5, M7, M3/4 for current ratio, IMCR, etc

Comment

• If we run the same total current Itot through a single stage common source amplifier made of M6 and M7– Single pole go/CL– Gain gm6/go– Single stage amp GB = gm6/CL >gm6/(CL+C1)

> 2 > gm1/CC = GB of two stage amp

• Two stage amp achieves higher gain but speed is much slower!

• Can the single stage speed be recovered?

Other considerations

• Output slew rate: SR = I5/CC

• Output swing range: VSS+Vdssat7 to VDD – Vdssat6

• Min ICM: VSS + Vdssat5 + VTN + Von1

• Max ICM: VDD - |VTP| - Von3 + VTN

• Mirror node approx. pole/zero cancellation– Closed-loop pole stuck near by– Can cause slow settling

When vin is short, the D1 node sees a capacitance CM and a conductance of gm3 through the diode con.So: p3 = -gm3/CMWhen vin is float and vo=0. gm4 generate a current in id4=id2=id1. So the total conductance at D1 is gm3 + gm4.So: z3 = -(gm3+gm4)/CM

=2*p3If |p3| << GB, one closed-loop pole stuck nearby, causing slow settling!

Eliminating RHP Zero at gm6/CC

CCdvCC/dt

vg= RZCCdvCC/dt +vcc

icc = vg gm6

= CCdvCC/dt

(gm6RZ-1)CCdvCC/dt + gm6vcc=0

For the zero at M6 and CC, it becomes

z1 = gm6/[CC(1-gm6Rz)]

So, if Rz = 1/gm6, z1 →

For such Rz, its effect on the p1 node can be ignored so p1 remains as before.

Similarly, p2 does not change very much.

similar design approach.

Realization of Rz

vb

VDD

Another choice of Rz is to make z1 cancel2:

z1=gm6/CC(1-gm6Rz) ≈ - gm6/(CL+C1)

Rz = gm6CC

CC+CL+C1

= gm6

1 (1+ )CC

CL+C1

Let ID8 = ID6, size M6 and M8 so that VSG6 = VSG8

Then VSGz=VSG9

Assume Mz in triodeRz = z(VSGz – |VT| - VSDz) ≈ z(VSGz – |VT|) = z(2ID8/9)0.5

= z(2ID6/6)0.5(6/9)0.5

= z/6 *6VON6 *(6/9)0.5

= z/6 *1/gm6*(6/9)0.5

Hence need: z/6 *(6/9)0.5 =(CC+CL+C1)/CC

gm6/(CL+C1)f (I6)

-z1 ≈

A0

2

-90

-180PM

1

gm1/CC

• With the same CC as before– Z1 cancels p2– P3, z3, z2, not affected– P1 not affected much– Phase margin drop due to p2 and z1 nearly

removed – Overall phase margin greatly improved– Effects of other poles and zero become more

important

• Can we reduce CC and improve GB?

gm6/CL

z1 ≈ p2

A0

2

-90

-180

1

z2 ≈ gm2/Cgd2

Operate not on this but on this or this z4 ≈ gm6/Cgd6

Increasing GB by using smaller CC

• It is possible to reduce CC to increase GB if z1/p2 pole zero cancellation is achieved– Can extend to gm6/CL

– Or even a little bit higher

• But cannot push up too much higher– Other poles, zeros– Imprecise mirror pole/zero cancellation– P2/z1 cancellation– GB cannot be too high relative to these p/z

cancellation

• Z2, z4, and pz=-1/RZCC must be much higher than GB

Possible design steps for max GB• For a given CL and Itot

• Assume a current share ratio i.e.– I6+I5 = Itot, I5 = I6 , I1 = I2 = I5/2

• Size W6, L6 to achieve max single stage GB1 = gm6/(CL+Coutpara)

– Make z4=gm6/Cgd6 > (10~50)GB1• Choose GB = GB1, • Choose CC to make p2 ≈ GB/(10~20)• Size W1, L1 and adjust so that gm1/CC ≈ GB

– Make z2=gm2/Cgd2 > (10~20)GB• Size Mz so that z1 cancels p2

– Make sure |pz| due to Mz and CC >> GB• Make sure PM at f=GB is sufficient• Size M3/4 so that gm3/CM is > GB/(10~20)• Check slew rate, and size other transistors for ICMR,

OSR, etc

Simple transistor circuits

• Can use any # of ideal current or voltage sources, resisters, and switches

• Use one or two transistors

• Examine various ways to place the input and output nodes

• Find optimal connections for– high gain– high bandwidth– high or low output impedance– low input referred noise

Single transistor configurations

• It’s a four terminal device• Three choices of input node• For each input choice, there are two

choices for the output node• The other two terminals can be at VDD,

GND, virtual short (V source), virtual open (I source), input, or output node

• Most connections are non-operative or duplicates– D and S symmetric; B not useful

2 valid input choice and 1 output choice

Connection of other terminals:

or

Resister

Capacitor

Gnd or virtualCommon source

To VDD

This is D

Source follower

N-channel common gate

p-channel common gate

Diode connections

Building realistic circuits from simple connections

N common source

flip vertical

Combine

N common source

flip left-right

Combine to formdifferential pair

flip upside down to get current source load

Combine to formdifferential amp

Vbb

Vbb

Replace virtual gndby current source

Can also use self biasingand convert to single ended output

two transistor connections• Start with one T connections, and add a

second T

• Many possibilities– many useless– some obtainable by flip and combine from one

T connections– some new two T connections

• Search for ones with special properties– in terms of AV, BW, ro, ri, etc

First MOST is CSD1 connects to D2: (with appropriate n-p pairing)

vin

vo

-kvo

CS withnegative gm at output node

CS Push pullCS

VDD

Vx

When Vx = gndT2 is not useful

When Vx = Vin, T2 and T1 are just one T

When Vx = -kVo

what do we get?

Vo

VDD

Vx

Vo

M1 M2

Vx=gnd, M2 is I source

Vx = vin, ?

Vx = ─ vin, ?

Vx = vo, capacitor

Vx = kvo, negativegds feedback

vin

vo

-vin

-vokk

VDDVDD

gm1vin+gds1vo+gds3vo-kvogm3=0

M1

M3

M2

M4

M5 AV=gm1

gds1+gds3-kgm3

AV= when k = gds1+gds3

gm3

GBW=gm1/Co = GBW of simple CS

D1 connects to S2VDD

just a single NMOST

VDDVDD

Cascodeany benefits?

VDD

Cascodewith positiveVx feedback

VDD

Cascodewith positiveVo feedback

-kVx

Vx

Vo-kVo

VDD

Vo

VDD

Vo

VDD

Vo

Vin

Folded cascode Effects on GBW?

VDD

Vo

VDD

Vo

Vx

-Vx-kVo

folded cascode with positive feedback

VDD

Vbb

Vin

CL

Rb

connecting D1 to S2cascoding

flip up-downfor source

Vbb

Vin

CL

Vyy

Vxx

VDD

flip left-rightto get thisdifferentialtelescopiccascodedamplifier

VDDVDD

Vbb

Vin-

CL

Vin+

CL

Vyy

Vxx

add M9 to changegnd to virtual gnd GBW=gm1/Co

How to connectG3 to –Vx, –kVx, or – kVo

Vin-

CL

Vin+

CL

Vyy

VDD VDD

Vx

Vo

Same GBWGain can be very high

How to connectG3 to –Vx, –kVx, or – kVo

Vin-

CL

Vin+

CL

Vyy

VDD VDD

Vx

Vo

Same GBWGain can be very high

VDD

Vin CL

Vbb

VDD

Vin CL

Vbb

flip up-down for I sources

connecting n-D to p-S

VDD

Vin+CL

VDD

Vin-

Vbb

folded cascode amp

Same GBW

VDD

Vin+CL

VDD

Vin-

Vbb

How to connect forpositive feedback?

D1 connects to G2, two stages

VDD

VDD VDDVDD

two stageCS amplifier

CS amplifier with a source follower buffer

VDD

VDD

VDD

VDDVDD

VDD

•Needs compensation and CM feedback•Can gain be higher than single stage?•Can GBW be improved vs single stage?

VDD

VDD

VDD

VDD

Vx

-Vx-vin

Can you connectwithout loading effect?

VDD

VDDVDD

VDD

Vomin = Vin-min + Vdssat

or = VT + 3Vdssat

Biasing?

VDD

VDDVDD

VDD

VDDVDD

Vomin = 2VdssatBut is the gain improved?Is GBW improved?

VDD

Vx

VDDVDD

Vx

V?

Same as above,only T2 is pMOS

Connecting S1 to D2makes ro really smallbuffer or output stage

VDD VDD

or

VDDVDD

VDD

VDD

connecting S1 to G2

VDD

VxVx

VDD VDD

VDD

Vx

Vx?

VDD

connecting S1 to S2

Vo

-Vin

Vo

connecting S1 to D2

V?

V?

?

?

e.g.

M1 is common gate:D1 connects to G2

Vin

VDD

D1 connects to S2

Vin

PSRR

0

ssdd vvin

outv v

vA

0

ssin vvdd

outdd v

vA

0

ddin vvss

outss v

vA

ss

in

dd

in

A

APSRR

A

APSRR

Vout = AddVdd + Av(V1-V2) = AddVdd - AvVout

Vout(1+Av) = AddVdd

PSRRA

A

A

A

v

v

dd

v

dd

v

out

dd 1

Good as long as Av >> 1, or f < GB

For zeros, set vdd = 0, vout float.This is the unity gain buffer configuration of the amp.Hence, char roots are: -GB and p2

DC gain: ignore all caps and find relationship between vdd and voutat vout gm1 at Id1same at Id2gm1/(gds2+gds4) at G6vg6gm6/gds6 across DS6 vdd= gm1/(gds2+gds4) *gm6/gds6 Vdd/vout = gm6gm1/gds6(gds2+gds4)

For poles, make vout = 0, vdd float.Three nodes: S3/S4/S6, G3/G4/D1: ignoreWrite KCL at D2/D4/G6 node:v(gds2+gds4+sCI+sCC)=vdd(gds4+gds1*1)Current balance in M6:gm6(v-vdd)=gds6vdd v=(1+gds6/gm6)vddgds6/gm6*(gds2+gds4)+(1+gds6/gm6)s(CI+sCC)=0

gds6/gm6*(gds2+gds4)= -s(CI+sCC)Pole at

- gds6(gds2+gds4) /(gm6(CC+CI))

Similar computation for PSRR-

1. Get DC gain2. Get zeros: they

are the same as in PSRR+, and the same as poles of unity feedback Avd

3. Get dominant pole:

Practice this, and see if you get similar results as in book

Two-Stage Cascode Architecture• Why Cascode Op Amps?

– Control the frequency behavior– Increase PSRR– Simplifies design

• Where is the Cascode Technique Applied?– First stage -

• Good noise performance• Requires level translation to second stage• Requires Miller compensation

– Second stage -• Self compensating• Reduces the efficiency of the Miller compensation• Increases PSRR

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OpAmp (OTA) Design