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OPB External Peripheral Controller (EPC) v100a
DS325 August 10 2007 0 0 Product Specification
IntroductionThis specification defines the architecture and interface requirements for the External Peripheral Controller (EPC) The controller supports data transfers between the On-Chip Peripheral Bus (OPB) and the external synchronous andor asynchronous peripheral devices
Examples of peripheral devices supported by the EPC include the 10100 non-PCI Ethernet single chip (SMSC LAN91C111) from SMSC and CY7C67300 USB Controller from Cypress Semiconductor devices
Featuresbull OPB v20 bus interface with byte-enable support
bull Parameterized support of up to four external peripheral devices with each device configured with separate base address and high address range
bull Supports both synchronous and asynchronous access modes of peripheral devices with the support for a separate clock domain for synchronous peripheral devices
bull Supports both multiplexed and non-multiplexed address and data buses
bull The data width of peripheral devices is independently configured to 8-bit 16-bit or 32-bit with the provision to enable data width matching when the OPB data width is greater than that of peripheral device
bull Configurable timing parameters for peripheral bus interface
bull Tested with the SMSC LAN91C111 and the Cypress CY7C67300 USB Controller device
bull OPB slave only device
LogiCOREtrade Facts
Core Specifics
Supported Device Family
Virtextrade-II Virtex-II Pro Virtex-4
Spartantrade-3 and Virtex-5
Version of Core opb_epc v100a
Resources Used
Min Max
Slices
Refer Table 6 amp Table 7LUTs
FFs
Block RAMs NA NA
Provided with Core
Documentation Product Specification
Design File Formats VHDL
Constraints File NA
Verification NA
Instantiation Template NA
Reference Designs None
Design Tool Requirements
Xilinx Implementation Tools
ISE 82i or later
Verification ModelSim SEEE 60c or later
Simulation ModelSim SEEE 60c or later
Synthesis XST 82i or later
Support
Support provided by Xilinx Inc
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DS325 August 10 2007 wwwxilinxcom 1Product Specification
copy 2006 Xilinx Inc All rights reserved All Xilinx trademarks registered trademarks patents and further disclaimers are as listed at httpwwwxilinxcomlegalhtm All other trademarks and registered trademarks are the property of their respective owners All specifications are subject to change without noticeNOTICE OF DISCLAIMER Xilinx is providing this design code or information as is By providing the design code or information as one possible implementation of this feature application or standard Xilinx makes no representation that this implementation is free from any claims of infringement You are responsible for obtaining any rights you may require for your implemen-tation Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation including but not limited to any warranties or representations that this imple-mentation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose
OPB External Peripheral Controller (EPC) v100a
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F
Functional Description
OPB EPC Design DescriptionThe OPB External Peripheral Controller (EPC) interface diagram shown in Figure 1 depicts the major interfaces of the design
Figure 1 OPB EPC Interface Diagram
igure Top x-ref 1
DS325_01_071406
IPICInterface
OPB SlaveInterface
OPB EPC ExternalPeripheralInterface
OPB_IPIF EPC_CORE
ExternalPeripheralDevice 1
ExternalPeripheralDevice 4
The OPB EPC design provides a general purpose interface to external peripheral devices and the OPB It is a OPB slave only device The OPB EPC can be configured to provide support for multiple external peripherals up to a maximum of four devices and each device is independently configured to respond either in synchronous or asynchronous mode The timing parameters governing the access cycles such as setuphold time cycle access time cycle recovery time etc are configured by the user It receives read or write operation commands from the OPB and generates a corresponding access cycle to one of the four peripheral devices
The OPB EPC core is comprised of the following modules
bull OPB_IPIF
bull EPC_CORE
OPB_IPIF
The OPB_IPIF provides an interface between the EPC_CORE and the 32-bit OPB The OPB_IPIF module implements the basic functionality of the OPB slave operation and does the necessary protocol and timing translation between the OPB and the IPIC interface
For more information on the OPB_IPIF refer to the OPB IPIF documents listed in the Reference Documents section
EPC_CORE
The EPC_CORE provides an interface between the IPIC interface and the external peripheral devices The EPC_CORE consists of the logic necessary to convert the access cycles on the IPIC interface to the corresponding access cycles on the peripheral bus adhering to the device specific timing parameters
The block diagram for the EPC_CORE is shown in Figure 2
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Figure 2 OPB EPC Block Diagram
igure Top x-ref 2
DS325_02_071406
AddressData Mux
AccessMux
Control Signal Mux
Control SignalGeneration
Async Control
Cycle TimeGeneration
SyncControl
DataSteer
IPIC IF Decode
IPIC Interface
PeripheralControl Signals
PeripheralAddress Bus
PeripheralData Bus
IPIC Control SignalsDataBus
AddressBus
OPB Bus
OPB IPIF
EPC CORE
OPB_ClkPRH_Clk
AddressGeneration
The EPC_CORE consists of
bull The IPIC_IF Decode module This module provides decoding of IPIC signals and synchronization of control signals
bull The Sync Control module This module implements the state machine which controls the synchronous interface
bull The Async Control module This module implements the state machine which controls the asynchronous interface including the asynchronous timing parameters
bull The Data Steer module This module provides the data bus width matching and data steering logic
bull The Address Generation module This module provides the generation of the lower address bits
bull The Access Mux module This module provides the multiplexing of address data and other control signals
A detailed description of the modules is provided below
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IPIC IF Decode Module
The IPIC IF Decode module implements the interface to the OPB_IPIF It also configures the EPC_CORE and interfaces to the Async Control module and Sync Control module by driving the necessary control signals based on user parameter settings
Sync Control and Async Control Modules
In Figure 2 the Sync Control and Async Control modules depict the synchronous and asynchronous paths of the EPC_ CORE This ensures that the read and write accesses to the external device(s) adheres to the specific timing parameters defined for the external device(s) Implementation of the Sync Control and Async Control modules is dependent on the parameter C_PRHx_SYNC If synchronous and asynchronous external peripheral devices exist simultaneously then both the Sync Control and Async Control modules will be implemented
The Sync Control module operates either on the OPB clock (OPB_Clk) or on the external peripheral clock (PRH_Clk) depending on the generic C_PRH_CLK_SUPPORT If C_PRH_CLK_SUPPORT = 1 then the Sync Control module operates on external device peripheral clock (PRH_Clk) that is different from the OPB clock If more than one device is synchronous then the frequency for the PRH_Clk should be chosen as the minimum of the operating frequencies of those devices The IPIC control signals that are inputs to the Sync Control module are synchronized to the PRH_Clk in the IPIC IF Decode module to indicate the start of a transaction Similarly the control signals from the Sync Control module to the IPIC interface such as data acknowledge are synchronized to the OPB clock in the IPIC IF Decode module If C_PRH_CLK_SUPPORT = 0 the Sync Control module operates on the OPB clock and the IPIC Decode module interface does not perform synchronization of control signals
The Async Control module operates on the OPB clock This module generates the control signals to the initiate read and write access cycles to the external peripheral device based on the asynchronous timing parameters set by the user
Data Steer and Address Generation Modules
The data bus of the external device must be less than or equal to the OPB data width and may be 8-bit 16-bit or 32-bit When the width of the external peripheral data bus is less than that of OPB and if C_PRHx_DWIDTH_MATCH = 1 for a particular device then the Data Steer Module will generate multiple read or write cycles to the external device to match a single access on the OPB
In order to map a single 32-bit OPB access to multiple 8-bit or 16-bit accesses the lower bits of the address bus are internally generated within the Address Generation module to provide the correct address to the external peripheral device The address bus increments as each transaction completes
For example if the external device is 8-bit wide then four read or write cycles to the device will be performed in order to match a single read or write transaction on the OPB For a write cycle the first byte of the OPB data bus (OPB_DBus[07]) is presented on the peripheral data bus (PRH_Data[07]) When the external device accepts the transaction a new write cycle is generated and the second byte of the OPB data bus (OPB_DBus[815]) is presented on the peripheral data bus (PRH_Data[07]) and so on When the last byte of the OPB data bus (OPB_DBus[2431]) is accepted by the peripheral the data acknowledge signal is generated to the OPB_IPIF interface to indicate that the access is complete on the peripheral interface
Similarly for a read cycle when the external device indicates it is ready to complete the transaction the data on the peripheral data bus (PRH_Data[07]) is internally registered as the first byte to be presented to OPB data bus (OPB_DBus[07]) followed by initiation of new read cycle on the peripheral interface The second read access on the peripheral data bus (PRH_Data[07]) is internally registered as the
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second byte to be presented to OPB data bus (OPB_DBus[815]) and so on When all four bytes are read from the external device an acknowledge is generated to the OPB_IPIF to indicate that the data is ready to be transferred to OPB data bus
When support for data width match is enabled for any of the external devices then the access to that device should respect data alignment ie a half word access should be aligned to a 16-bit boundary and a word access should be aligned to a 32-bit boundary
Access Mux Module
The interface to the external peripherals supports both multiplexed and non-multiplexed address and data bus to the external devices The Access Mux module controls the multiplexing of the peripheral address and data buses based on the parameter C_PRHx_BUS_MULTIPLEX If C_PRHx_BUS_MULTIPLEX = 1 the address and the data bus are multiplexed and presented to the corresponding external device on PRH_Data bus The address will be valid on the PRH_Data bus as long as the address strobe is active (PRH_ADS) This access will be performed in two phases (address phase and data phase) The data phase will be followed by the address phase If C_PRHx_BUS_MULTIPLEX = 0 then the address and the data are presented to the device on separate buses (PRH_Addr bus and PRH_Data bus) and the access cycle will contain only one phase
OPB EPC IO SignalsThe Table 1 provides a summary of all OPB EPC inputoutput (IO) signals
Table 1 OPB EPC IO Signal Description
Port Signal Name InterfaceSignal Type
Initial Status
Description
OPB Signals
P1OPB_ABus[0C_OPB_AWIDTH-1]
OPB I - OPB address bus
P2OPB_BE[0C_OPB_DWIDTH8-1]
OPB I - OPB byte enables
P3OPB_DBus[0C_OPB_DWIDTH-1]
OPB I - OPB data bus
P4 OPB_RNW OPB I - OPB read not write
P5 OPB_Select OPB I - OPB select
P6 OPB_seqAddr OPB I - OPB sequential address
P7Sln_DBus[0C_OPB_DWIDTH-1]
OPB O 0 OPB EPC data bus
P8 Sln_errAck OPB O 0 OPB EPC error acknowledge
P9 Sln_retry OPB O 0 OPB EPC retry
P10 Sln_toutSup OPB O 0 OPB EPC timeout suppress
P11 Sln_xferAck OPB O 0 OPB EPC transfer acknowledge
System Interface Signals
P12 OPB_Clk OPB I - OPB clock
P13 OPB_Rst OPB I - OPB reset
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OPB EPC Signals
P14 PRH_Clk(1) EPC I - External peripheral clock input
P15 PRH_Rst EPC I -External peripheral reset inputActive high input signal to the core
P16PRH_CS_n[0C_NUM_PERIPHERALS-1]
EPC O 1External peripheral chip selectActive low output signal from the core
P17PRH_Addr[0C_PRH_MAX_AWIDTH-1](2) EPC O - External peripheral address bus
P18 PRH_ADS EPC O 0
External peripheral address strobe in case of multiplexed address and data busActive high output signal from the core
P19PRH_BE[0C_PRH_MAX_DWIDTH8-1]
EPC O -External peripheral byte enablesActive high output signal from the core
P20 PRH_RNW EPC O 1
External peripheral readwrite signal for synchronous access modeActive high output signal from the core
P21 PRH_Rd_n EPC O 1
External peripheral read signal for asynchronous access modeActive low output signal from the core
P22 PRH_Wr_n EPC O 1
External peripheral write signal for asynchronous access modeActive low output signal from the core
P23 PRH_Burst EPC O 0
Burst cycle indication to external peripheralActive high output signal from the core
P24PRH_Rdy[0C_NUM_PERIPHERALS-1]
EPC I -
Peripheral ready signal This signal is used by the external peripheral to extend the transactionActive high input signal to the core
P25PRH_Data_I[0C_PRH_MAX_ADWIDTH-1]
EPC I - External peripheral input data bus
P26PRH_Data_O[0C_PRH_MAX_ADWIDTH-1] EPC O - External peripheral output data bus
Table 1 OPB EPC IO Signal Description (Contd)
Port Signal Name InterfaceSignal Type
Initial Status
Description
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P27PRH_Data_T[0C_PRH_MAX_ADWIDTH-1]
EPC O -3-state control for external peripheral output data bus
Notes 1 PRH_Clk is utilized only when C_PRH_CLK_SUPPORT = 1 and the interface to the external peripheral is
synchronous2 External peripheral devices are considered as byte addressable irrespective of the data bus width
Table 1 OPB EPC IO Signal Description (Contd)
Port Signal Name InterfaceSignal Type
Initial Status
Description
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OPB EPC Design ParametersTo allow a user to create the OPB EPC that is uniquely tailored for the system certain features can be parameterized in the OPB EPC design Some of these parameters control the interface to the OPB while others control the interface to the peripheral devices This allows the user to have a design that only utilizes the minimum resources required by the system and operating at the best possible performance
The features that could be parameterized in the OPB EPC are shown in Table 2
Table 2 OPB EPC Design Parameters
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
OPB EPC Features
G1OPB clock period
C_OPB_CLK_PERIOD_PS
Integer number of picoseconds
10000 integer
G2 Target FPGA family C_FAMILYvirtex2 virtex2p virtex4 virtex5 spartan3
virtex2p string
G3 OPB address width C_OPB_AWIDTH 32 32 integer
G4 OPB data width C_OPB_DWIDTH 32 32 integer
OPB EPC Interface Parameters
G5 Peripheral clock periodC_PRH_CLK_PERIOD_PS(1)
Integer number of picoseconds
20000 integer
G6 Number of peripheralsC_NUM_PERIPHERALS
1-4 1 integer
G7Maximum of address bus width of all external peripherals
C_PRH_MAX_AWIDTH 3-32 32integer
G8Maximum of data bus width of all external peripherals
C_PRH_MAX_DWIDTH 8 16 or 32 32 integer
G9
Maximum of data bus width of all peripherals and address bus with of peripherals employing addressdata multiplexing
C_PRH_MAX_ADWIDTH(2) 8-32 32 integer
G10 Peripheral clock supportC_PRH_CLK_SUPPORT(1)
0 = Peripheral device interface operates at the OPB clock 1 = Peripheral device interface operates at external peripheral clock
0 integer
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G11 OPB burst supportC_PRH_BURST_SUPPORT(24)
0 = No burst support from OPB 1 = Not supported
0 integer
OPB EPC Peripheral Address Space
G12External peripheral base address
C_PRHx_BASEADDR(3) Valid address(4 5)
User must set values(6)
std_logic_vector
G13External peripheral high address
C_PRHx_HIGHADDR(3) Valid address(4 5)
User must set values(6)
std_logic_vector
OPB EPC Peripheral Interface Parameters
G14Support for access to FIFO within the external peripheral
C_PRHx_FIFO_ACCESS(3)
0 = No support for the external peripheral FIFO access1 = Access to FIFO structures within the external peripheral device is supported
0 integer
G15External peripheral FIFO offset from peripheral base address
C_PRHx_FIFO_OFFSET(3 7 8)
Any valid offset within the base and high address range assigned to the peripheral device
0 integer
G16Address bus width of peripherals
C_PRHx_AWIDTH(3) 3-32 32 integer
G17Data bus width of peripherals
C_PRHx_DWIDTH(3) 8 16 or 32 32 integer
G18
Support for data width match when the peripheral device data width is less than the OPB data width
C_PRHx_DWIDTH_MATCH(3 9)
0 = No multiple cycles on the peripheral interface for single OPB read or write cycle 1 = Run multiple cycles on the peripheral interface for single OPB read or write cycle
0 integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
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G19 Peripheral access mode C_PRHx_SYNC(1 3)
0 = External device is asynchronous 1 = External device is synchronous
1 integer
G20 Peripheral bus typeC_PRHx_BUS_MULTIPLEX(3)
0 = External device has separate address and data bus1 = External device has multiplexed address and data bus
0 integer
OPB EPC Timing Parameters
G21
Address bus (PRH_Addr) setup with respect to rising edge of address strobe (PRH_ADS) or falling edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_ADDR_TSU(3 10)
Integer number of picoseconds
User must set values(11)
integer
G22
Address bus (PRH_Addr) hold with respect to falling edge of address strobe (PRH_ADS) or rising edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_ADDR_TH(3 12 16 19)
Integer number of picoseconds
User must set values(11)
integer
G23Minimum pulse width of address strobe (PRH_ADS)
C_PRHx_ADS_WIDTH(3)
Integer number of picoseconds
User must set values(11)
integer
G24
Chip select (PRH_CS_n) setup with respect to falling edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_CSN_TSU(3 10)
Integer number of picoseconds
User must set values(13)
integer
G25
Chip select (PRH_CS_n) hold with respect to rising edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_CSN_TH(3 16 19)
Integer number of picoseconds
User must set values(13)
integer
G26Minimum pulse width of write signal (PRH_Wr_n)
C_PRHx_WRN_WIDTH(3 14 15 16)
Integer number of picoseconds
User must set values(13)
integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
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G27Cycle time of write signal (PRH_Wr_n)
C_PRHx_WR_CYCLE(3 15 16)
Integer number of picoseconds
User must set values(13)
integer
G28
Data bus (PRH_Data) setup with respect to falling edge of write signal (PRH_Wr_n)
C_PRHx_DATA_TSU(3 14)
Integer number of picoseconds
User must set values(13)
integer
G29
Data bus (PRH_Data) hold with respect to rising edge of write signal (PRH_Wr_n)
C_PRHx_DATA_TH(3 16)
Integer number of picoseconds
User must set values(13)
integer
G30Minimum pulse width of read signal (PRH_Rd_n)
C_PRHx_RDN_WIDTH(3 17 18 19)
Integer number of picoseconds
User must set values(13)
integer
G31Cycle time of read signal (PRH_Rd_n)
C_PRHx_RD_CYCLE(3 18 19)
Integer number of picoseconds
User must set values(13)
integer
G32
Data bus (PRH_Data) validity from falling edge of read signal (PRH_Rd_n)
C_PRHx_DATA_TOUT(3 17)
Integer number of picoseconds
User must set values(13)
integer
G33
Data bus (PRH_Data) high impedance from rising edge of read (PRH_Rd_n)
C_PRHx_DATA_TINV(3 19)
Integer number of picoseconds
User must set values(13)
integer
G34
Device ready (PRH_Rdy) validity from the falling edge of read or write (PRH_Rd_n PRH_Wr_n)
C_PRHx_RDY_TOUT(3 20 22)
Integer number of picoseconds
User must set values(13)
integer
G35
Maximum period of device ready signal (PRH_Rdy) to wait before device timeout
C_PRHx_RDY_WIDTH(3 21 22)
Integer number of picoseconds
User must set values(23)
integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
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Notes 1 The generic C_PRH_CLK_SUPPORT is relevant only when the device is configured for synchronous access
ie C_PRHx_SYNC = 1 If more than one device is synchronous then the frequency for the peripheral clock (PRH_Clk) should be chosen as the minimum of the operating frequencies of those devices
2 The C_PRH_MAX_ADWIDTH determines the size of the data bus For all non multiplexed devices the C_PRH_MAX_ADWIDTH reflects the maximum of data bus width of all external devices ie C_PRH_MAX_ADWIDTH equals C_PRH_MAX_DWIDTH However if any of the devices is configured for multiplexed address and data bus then C_PRH_MAX_ADWIDTH should be set as the maximum of data bus of all external devices and the address bus of device(s) employing multiplexed address and data bus
3 rsquoxrsquo in the generic refers to the number of the peripheral device and takes a value in the range of 0 to C_NUM_PERIPHERALS - 1
4 OPB EPC design can accommodate up to four peripheral devices The address range for the devices are designated as C_PRH0_BASEADDR C_PRH0_HIGHADDR C_PRH1_BASEADDR C_PRH1_HIGHADDR etc
5 The range specified by C_PRHx_BASEADDR and C_PRHx_HIGHADDR must comprise a contiguous range and the size of the range must be a power of two ie size of range = 2m Further the rsquomrsquo least significant bits of C_PRHx_BASEADDR must be zero The base and high address range assigned to different peripherals must be mutually exclusive
6 No default value will be specified to ensure that the actual value is set ie if the value is not set a compiler error will be generated
7 C_PRHx_FIFO_ACCESS must be set to 1 if the support for access to FIFO within external peripheral device is to be included
8 C_PRHx_FIFO_OFFSET is the byte offset of the external peripheral FIFO from the base address (C_PRHx_BASEADDR) of the peripheral irrespective of the data width of the peripheral device If C_PRHx_FIFO_ACCESS = 1 then C_PRHx_FIFO_OFFSET must be set to a valid offset within the address range assigned to the peripheral
9 The generic C_PRHx_DWIDTH_MATCH is relevant only when the width of the peripheral data (PRH_Data) bus is less than the OPB data bus (OPB_DBus)
10Address setup time is with respect to falling edge of address strobe (PRH_ADS) if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 and must be set both in synchronous and asynchronous mode Address setup time is with respect to falling edge of readwrite signals (PRH_Wr_nPRH_Rd_n) if the device is non multiplexed and is relevant only if the access mode is asynchronous
11Value for the parameter must be assigned if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 This parameter assignment is appicalble for synchronous and asynchronous devices
12Address hold time is with respect to falling edge of address strobe (PRH_ADS) if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 and must be set both in synchronous and asynchronous mode Address hold time is with respect to rising edge of readwrite signals (PRH_Wr_nPRH_Rd_n) if the address and the data bus are separate and is relevant only if the access mode is asynchronous
13Value must be assigned if the access mode of the peripherals is asynchronous ie C_PRHx_SYNC = 0 If the access mode of the peripheral is synchronous ie C_PRHx_SYNC = 1 then the zero should be assigned to the parameter
14Write signal (PRH_Wr_n) low time is the maximum of C_PRHx_WRN_WIDTH and C_PRHx_DATA_TSU15The value of C_PRHx_WRN_WIDTH must be smaller than C_PRHx_WR_CYCLE16 In non-multiplexed address and data bus mode write recovery time will be maximum of C_PRHx_ADDR_TH
C_PRHx_CSN_TH C_PRHx_DATA_TH and PRH_Wr_n high time (ie C_PRHx_WR_CYCLE minus C_PRHx_WRN_WIDTH) If the peripheral uses multiplexed address and data bus then the write recovery time will be maximum of C_PRHx_CSN_TH C_PRHx_DATA_TH and PRH_Wr_n high time
17Read signal (PRH_Rd_n) low time is the maximum of C_PRHx_RDN_WIDTH and C_PRHx_DATA_TOUT18The value of C_PRHx_RDN_WIDTH must be smaller than C_PRHx_RD_CYCLE19 In non-multiplexed address and data bus mode read recovery time will be maximum of C_PRHx_ADDR_TH
C_PRHx_CSN_TH C_PRHx_DATA_TINV and PRH_Rd_n high time (ie C_PRHx_RD_CYCLE minus C_PRHx_RDN_WIDTH) If the peripheral uses multiplexed address and data bus then the read recovery time will be maximum of C_PRHx_CSN_TH C_PRHx_DATA_TINV and PRH_Rd_n high time
20Device ready validity period (C_PRHx_RDY_TOUT) must be set as the maximum of the values specified for read and write transactions
21Device ready pulse width (C_PRHx_RDY_WIDTH) must be set as the maximum of the values specified for read and write transactions
22Device ready validity (C_PRHx_RDY_TOUT) period must be less than the write strobe width (C_PRHx_WRN_WIDTH) read strobe width (C_PRHx_RDN_WIDTH) and device ready signal width (C_PRHx_RDY_WIDTH)
23Device ready signal width (C_PRHx_RDY_WIDTH) must be set for both synchronous and asynchronous
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
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Allowable Parameter Combinations
When the peripheral devices are confugured in non multiplexed mode the C_PRH_MAX_AWIDTH should be the maximum of C_PRHx_AWIDTH of all peripherals in the system ie if C_NUM_PERIPHERALS is 2 then C_PRH_MAX_AWIDTH should be maximum of C_PRH0_AWIDTH and C_PRH1_AWIDTH
C_PRH_MAX_DWIDTH should be the maximum of C_PRHx_DWIDTH of all peripherals in the system ie if C_NUM_PERIPHERALS is 2 then C_PRH_MAX_DWIDTH should be maximum of C_PRH0_DWIDTH and C_PRH1_DWIDTH
If any of the peripheral devices are configured for a multiplexed address and data buses then the parameter C_PRH_MAX_ADWIDTH should be set as the maximum of the data bus and address bus of the device(s) employing a multiplexed address and data bus If all devices employ non-multiplexed address and data buses then C_PRH_MAX_ADWIDTH reflects the maximum of data bus width of all external devices Therefore for any configuration the parameter C_PRH_MAX_ADWIDTH should be greater than or equal to C_PRH_MAX_DWIDTH
The generic C_PRH_CLK_SUPPORT is relevant only when the devices are configured for the synchronous access ie C_PRHx_SYNC = 1 If more than one of the devices are synchronous then the frequency for the peripheral clock should be chosen as the minimum of the operating frequencies of those devices
The range specified by C_PRHx_BASEADDR and C_PRHx_HIGHADDR parameters must comprise a contiguous range and the size of the range must be a power of two ie size of range = 2m Furthermore the rsquomrsquo least significant bits of C_PRHx_BASEADDR must be zero The base and high address range assigned to different peripherals must be mutually exclusive No default value will be specified for C_PRHx_BASEADDR and C_PRHx_HIGHADDR in order to enforce that the user configures these parameters with the actual values If the values are not set for C_PRHx_BASEADDR and C_PRHx_HIGHADDR a compiler error will be generated
In order to access FIFO like structures within the external peripheral devices C_PRHx_FIFO_ACCESS must be set to rsquo1rsquo When FIFO access is enabled C_PRHx_FIFO_OFFSET specifies the offset of the FIFO in terms of number of byte locations from the base address (C_PRHx_BASEADDR) of the peripheral and should be set to an offset that lies within the address range assigned to the peripheral device ie C_PRHx_BASEADDR + C_PRHx_FIFO_OFFSET le C_PRHx_HIGHADDR Furthermore the FIFO offset should be within the range addressable by the address bus ie C_PRHx_FIFO_OFFSET lt 2n
where n = C_PRHx_AWIDTH
The width of the readwrite strobe must be less than the cycle time of the corresponding access ie C_PRHx_WRN_WIDTH lt C_PRHx_WR_CYCLE and C_PRHx_RDN_WIDTH lt C_PRHx_RD_CYCLE The value of device ready validity period must be less than the readwrite strobe width and the maximum pulse width of the device ready signal ie C_PRHx_RDY_TOUT lt minimum of C_PRHx_WRN_WIDTH C_PRHx_RDN_WIDTH and C_PRHx_RDY_WIDTH
Parameter - Port Dependencies
The dependencies between the OPB EPC design parameters and the IO ports are shown in Table 3 The width of the OPB EPC signals depend on some of the parameters In addition when certain features are parameterized away the related logic is removed
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ust 10 2007 wwwxilinxcom 13ecification
OPB External Peripheral Controller (EPC) v100a
14
Table 3 Parameter - Port Dependencies
Generic or Port
Name Affects Depends Description
Design Parameters
G3 C_OPB_AWIDTH P1 -The OPB address width parameter sets the width of the OPB address bus
G4 C_OPB_DWIDTHP2 P3
P7-
The OPB data width parameter affects the number of byte enables configured for the OPB data bus width of the OPB data bus and the width of the OPB slave read data bus
G6C_NUM_PERIPHERALS
P16 P24-
The number of peripherals in the system determines the number of chip select signals driven and the number of device ready inputs decoded by the OPB external peripheral controller
G7C_PRH_MAX_AWIDTH
P17- The width of the peripheral address bus is set to
the maximum of address bus width of all peripheral devices
G8C_PRH_MAX_DWIDTH
P19- The number of byte enables for the peripheral data
bus is determined by the maximum of data bus width of the peripheral devices
G9C_PRH_MAX_ADWIDTH
P25 P26 P27
-
The width of the peripheral input data bus peripheral output data bus and the peripheral output data bus 3-state control are determined by the maximum of data bus width of all peripherals and the address bus width of peripherals employing address data bus multiplexing
G10C_PRH_CLK_SUPPORT
P14- If C_PRH_CLK_SUPPORT = 0 then all external
devices operate on OPB clock The input PRH_Clk must be driven high externally
G18C_PRHx_DWIDTH_MATCH
P23-
If the device is configured for synchronous mode with data width matching enabled then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
Discontinued IP
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OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G19 C_PRHx_SYNCP14 P20 P21 P22
P23
-
If the device is configured for asynchronous mode
bull With peripheral clock support the peripheral clock input (PRH_Clk) must be driven high externally
bull PRH_RNW is driven high as PRH_Rd_n and PRH_Wr_n should be used as read and write strobe
bull With data width matching enabled the OPB EPC drives PRH_Burst to its default low
If the device is configured for synchronous mode
bull The OPB EPC drives PRH_Rd_n and PRH_Wr_n outputs to their default state of high since PRH_RNW output is used as readwrite strobe
G20C_PRHx_BUS_MULTIPLEX
P18- PRH_ADS is driven low if the device does not use
multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
IO Signals
P1 OPB_ABus - G3The OPB address bus width is determined by the C_OPB_AWIDTH parameter
P2 OPB_BE - G4The number of byte enables for the OPB data bus is determined by the C_OPB_DWIDTH parameter
P3 OPB_DBus - G4The OPB data bus width is determined by the C_OPB_DWIDTH parameter
P7 Sln_DBus-
G4The width of the OPB slave read data bus is determined by the C_OPB_DWIDTH parameter
P14 PRH_Clk-
G10 G19
PRH_Clk is selected as operating clock only if the device is configured for synchronous mode with peripheral clock support ie C_PRHx_SYNC = 1 and C_PRH_CLK_SUPPORT = 1 Asynchronous interface always operates on OPB_Clk Therefore if no device is configured for synchronous mode with peripheral clock support enabled then the input PRH_Clk must be driven high
P16 PRH_CS_n-
G6The number of chip select signals driven by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P17 PRH_Addr-
G7The width of the peripheral address bus is determined by the C_PRH_MAX_AWIDTH parameter
P18 PRH_ADS-
G20PRH_ADS is driven low if the device does not use multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
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ust 10 2007 wwwxilinxcom 15ecification
OPB External Peripheral Controller (EPC) v100a
16
OPB EPC Design Considerations
The OPB EPC is an OPB slave only device It receives read or write instructions from the processor and generates a corresponding access cycle on the peripheral interface Examples of read and write accesses are illustrated in the Timing Diagrams section The user must take the following considerations into account while designing with the OPB EPC
Device Ready Signal
The OPB EPC readwrite access cycles are executed only when the external device assert the device ready signal (PRH_Rdy) If the external peripheral device does not have a device ready signal then the PRH_Rdy input of the OPB EPC must be tied to logic high
P19 PRH_BE - G8The number of byte enables for the peripheral data bus is determined by the C_PRH_MAX_DWIDTH parameter
P20 PHR_RNW-
G19
If the device is synchronous ie C_PRHx_SYNC = 1 then PRH_RNW should be used as the readwrite control signal For asynchronous mode of operation PRH_RNW is driven high
P21 PRH_Rd_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Rd_n should be used as the read strobe For synchronous mode of operation PRH_Rd_n is driven high
P22 PRH_Wr_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Wr_n should be used as the write strobe For synchronous mode of operation PRH_Wr_n is driven high
P23 PRH_Burst-
G18 G19
If the device is synchronous with data width matching enabled ie C_PRHx_SYNC = 1 and C_PRHx_DWIDTH_MATCH = 1 then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
P24 PRH_Rdy-
G6The number of device ready inputs decoded by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P25 PRH_Data_I-
G9The peripheral input data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P26 PRH_Data_O - G9The peripheral output data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P27 PRH_Data_T - G9
The peripheral output data bus 3-state control width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
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OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
FIFO Transactions
When C_PRHx_FIFO_ACCESS = 1 the OPB EPC supports access to FIFOrsquos within the external peripheral devices When the FIFO within the external device is accessed then the peripheral address bus (PRH_Addr) must remain constant representing the FIFO address within the address range assigned to the peripheral device When data width matching is enabled and the access corresponds to the FIFO the OPB EPC does not increment the peripheral address (PRH_Addr) bus
Abnormal Terminations
If PRH_Rdy is de-asserted for more than the maximum period as specified by C_PRHx_RDY_WIDTH then the OPB EPC terminates the current access to the external device and signals an error to the OPB master by asserting Sln_errAck on the OPB Similarly when the OPB master terminates the current access (master abort on the OPB) OPB EPC terminates the access to the external device immediately In both cases the access to the external device is terminated abnormally Therefore the external device may be in an indeterminate state and the exceptions should be handled appropriately at the system level
Interrupt Handling
If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Peripheral Data Bus Mapping
The peripheral data bus (PRH_Data) uses big endian bit labelling (ie bit-0 is Most Significant Bit (MSB) and bit-31 is Least Significant Bit (LSB) for a 32-bit bus) and is sized according to the C_PRH_MAX_ADWIDTH parameter Peripherals that have smaller widths should connect to this bus starting at bit 0 (MSB) For example if three external devices are present in the system with data bus width of 8-bit 16-bit and 32-bit the 8-bit device should connect to PRH_Data[07] the 16-bit wide peripheral should connect to PRH_Data[015] and the 32-bit peripheral should connect to PRH_Data[031]
The bit and byte labeling for the big endian data types is shown in Figure 3
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ust 10 2007 wwwxilinxcom 17ecification
F
OPB External Peripheral Controller (EPC) v100a
18
Figure 3 OPB EPC Big Endian Data Type
igure Top x-ref 3
2 3
n+2 n+3
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 15
Halfword
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 31
Word
Byte
MS Byte
LS BitMS Bit
0
nByte address
Byte label
Byte significance
Bit label
Bit significance
0 7
DS325_03_071406
Unsupported Features
Many peripheral devices have the device specific inputoutput ports such as status remote reset remote wakeup interrupts etc The OPB EPC does not have any provision to support these device specific inputoutput ports Therefore if the external device has any such device specific ports then these inputoutput ports may be connected directly to system general purpose input output controller or to the system interrupt controller If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Many peripheral devices support DMA capability However currently OPB EPC is an OPB slave only device and therefore does not support DMA operations from the external peripheral devices
Current version of the OPB EPC does not support burst transactions tofrom the OPB
OPB EPC Latency
The OPB EPC latency calculations are based on the OPB clock The OPB latency is defined as the number of OPB clock cycles elapsed from the time an access is initiated to the time the access is completed (Sln_xferAck is asserted) on the OPB Table 4 shows the latency calculations for asynchronous mode and Table 5 shows the latency calculations for synchronous mode of operation
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 4 Asynchronous Mode OPB EPC Latency
Transaction Type
ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation(1)
OPB Latency
50 MHz
OPB Latency 100 MHz
ReadWrite access to asynchronous device when addressdata bus is not multiplexed
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5)
9(7) 12(7)
1FIFO
Memory
5 + N(2) (T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5))
21(7) 33(7)
ReadWrite access to asynchronous device when addressdata bus is multiplexed (Register access)
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + (T_SETUP(3) + T_ADDR_HOLD(6) + 1 + CONTROL_WIDTH(4) + T_HOLD(5))
11(7) 14(7)
1 FIFO
5 + T_SETUP(3) + T_ADDR_HOLD(6) + 1 + N(2) (CONTROL_WIDTH(4) + T_HOLD(5))
20(7) 29(7)
1 Memory
4 + N(2) (T_SETUP(3) + T_ADDR_HOLD(6) + CONTROL_WIDTH(4) + T_HOLD(5) + 2)
32(7) 44(7)
Notes 1 Latency calculations assumes the device is always ready2 If C_PRHx_DWIDTH_MATCH = 1 then N = Access size on OPB (in bytes)width of peripheral data bus (in
bytes)3 T_SETUP is the setup time requirement on various control signals in terms of number of OPB clocks and is
device specific4 CONTROL_WIDTH represents the required width for readwrite signal in terms of number of OPB clocks and
is device specific 5 T_HOLD is the hold time requirement on various control signals in terms of number of OPB clocks and is
device specific6 T_ADDR_HOLD is the required hold time on the address bus (as specified by generic C_PRHx_ADDR_TH) in
terms of number of OPB clocks and is device specific 7 Calculation are made for typical values of various timing parameters with T_SETUP = 20ns T_HOLD = 10ns
T_ADDR_HOLD = 6ns and STROBE_WIDTH = 40ns
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ust 10 2007 wwwxilinxcom 19ecification
OPB External Peripheral Controller (EPC) v100a
20
Table 5 Synchronous Mode OPB EPC Latency
Transaction Type ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory 9
1FIFO
Memory 8 + N(2)
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory 11
1 FIFO 10 + N(2)
1 Memory 6 + 5N(2)
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 7 peripheral clocks
1FIFO
Memory
7 OPB clocks + (6+N(2)) peripheral clocks
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 9 peripheral clocks
1 FIFO7 OPB clocks + (8+N(2)) peripheral clocks
1 Memory7 OPB clocks + (4+5N(2)) peripheral clocks
Notes 1 Latency calculations assumes the device is always ready2 N = Access size on the OPB (in bytes)width of peripheral data bus (in bytes) where access size on OPB
equals or less than C_OPB_DWIDTH expressed in terms of bytes3 Latency calculation assumes that the requirement on address setup (C_PRHx_ADDR_TSU) address hold
(C_PRHx_ADDR_TH) and ADS pulse width (C_PRHx_ADS_WIDTH) are all less than one OPB clock
OPB EPC External Peripheral ConnectionsThe OPB EPC interface to the external device is based upon the width of the OPB data bus address and data width of the peripheral subsystem number of peripherals in the system addressdata multiplex support mode of operation (synchronous or asynchronous) and if synchronous device the operating clock for the synchronous data path
Determining Address and Data Width
The address bus width of the peripheral subsystem is the maximum width of the address bus of all peripheral devices connected to the OPB EPC If all devices employ non-multiplexed address and data bus the data bus width of the peripheral subsystem is the maximum of the data bus width of all external devices If any of the devices are configured for multiplexed address and data bus then the data bus width of the peripheral subsystem should be set as the maximum of the data bus and the address bus of the device(s) employing a multiplexed address and data bus
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Endian Considerations
The peripheral address and data bus of the OPB EPC is labeled with big endian bit labeling (D0 is the MSB and D31 is the LSB for a 32-bit bus) while most peripheral devices are either endian agnostic ie they can be connected either way or little endian (D31 is the MSB and D0 is the LSB for a 32-bit bus) Caution must be exercised with the connection to the external peripheral devices to avoid incorrect data and address connections
Clock Generation
When connecting to a synchronous external device the OPB EPC may operate either on the OPB clock (OPB_Clk) or on a peripheral clock (PRH_Clk) The operating clock for the synchronous interface is based on the generic C_PRH_CLK_SUPPORT If C_PRH_CLK_SUPPORT = 1 the peripheral clock is used else the OPB clock is used The external devices connected to the OPB EPC will determine the operating frequency of the peripheral clock The minimum of the operating frequencies of various devices connected to OPB EPC should be used as the operating frequency of the peripheral clock (PRH_Clk)
Figure 4 illustrates a block diagram for generating a device specific clock source clock source using two DCMs The DCM modules are located within the FPGA but are external to the OPB EPC An external clock source is used to generate the OPB clock (OPB_Clk) to the OPB EPC The device clock source (PRH_Clk) is also generated from the same DCM (DCM0) using the CLKFX output and must be routed on the board to be fed back to the FPGA Another DCM (DCM1) is used to synchronize the device peripheral clock to the OPB EPC PRH_Clk
Figure 4 External Peripherals clocked by FPGA output with feedback
igure Top x-ref 4
DS325_04_071406
CLKFB CLK0
CLKFXCLKIN
DCM0
PRH_Clk_FB
PRH_Clk
OPB_Clk
CLKFB CLK0
CLKIN
DCM1
PRH_Clk
OPB_Clk
OPB EPCExternalDevice
CLK
FPGA
Example Peripheral Connections
Example SMSC LAN91C111 10100 non-PCI Ethernet Single Chip MAC + PHY
An example peripheral device supported by the OPB EPC is the SMSC 10100 non-PCI Ethernet Single Chip MAC + PHY LAN91C111 The OPB EPC allows OPB masters to access the device both in synchronous and asynchronous mode The device connections for synchronous and asynchronous mode of operations are outlined in the Asynchronous Mode and Synchronous Mode sections
Discontinued IP
ust 10 2007 wwwxilinxcom 21ecification
OPB External Peripheral Controller (EPC) v100a
22
F
Asynchronous Mode
Figure 5 illustrates the SMSC LAN91C111 connections to the OPB EPC in asynchronous mode with non-multiplexed address and data buses In asynchronous mode the input clock source (PRH_Clk) to the external device must be tied to VCC When the SMSC LAN91C111 is accessed through the asynchronous mode the rising edge of PRH_Rd_n and PRH_Wr_n signals are used to control the read and the write operations respectively As the device uses Asynchronous Ready (ARDY) signal to indicate its readiness in asynchronous mode This signal is connected to the PRH_Rdy input of the OPB EPC Since the address and the data buses are not multiplexed PRH_ADS will be driven low by the OPB EPC
The following parameter settings apply for the connections shown in Figure 5
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 5 SMSC LAN91C111 Connection to OPB EPC in Asynchronous Mode
igure Top x-ref 5
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]
PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
To System Interrupt Controller
VCC
LCLKResetAENnADSA[151]
nBE[30]
ARDYnRdnWR
D[310]
INTRO
WnRnVLBUSnCYCLE
nRDYRTNnDADACS
nLDEVnSARDY
SMSC LAN91C111
ExternalGlue Logic
PPC
OP
B B
us
FPGA
DS325_05_071406
ExternalReset VCC
External Glue Logic
Special attention must be given while interfacing the OPB EPC to the SMSC LAN91C111 in asynchronous mode The OPB EPC drives the PRH_BE active high while the SMSC LAN91C111 requires the input byte enable to be active low To match this requirement external glue logic is required to invert the PRH_BE signals before they are interfaced with the byte enable signals of the SMSC LAN91C111
Discontinued IP
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OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Synchronous Mode
Figure 6 illustrates the SMSC LAN91C111 connection to the OPB EPC in synchronous VL Bus mode with non-multiplexed address and data buses In synchronous mode the device requires an input clock source to the LCLK pin with a maximum operating frequency of 50MHz The local clock generated by the DCM for the peripheral interface must be routed to the LCLK input of SMSC LAN91C111 and PRH_Clk of OPB EPC When the device is accessed PRH_RNW is used as the control signal to indicate a readwrite access When PRH_RNW is high it indicates a read operation and when low it indicates a write operation The SMSC LAN91C111 uses nSRDY signal to indicate the device readiness This signal is connected to PRH_Rdy input of the OPB_EPC As the address and the data bus are not multiplexed PRH_ADS will be driven low
The following parameter settings apply for the connections shown in Figure 6
bull C_PRH_CLK_SUPPORT = 1
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 1
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 6 SMSC LAN91C111 Connection to OPB EPC in Synchronous Mode
igure Top x-ref 6
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
LCLKResetAENnADSA[151]nBE[30]WnRnSRDY
D[310]
nCYCLEnRDYRTN
INTRO
nRdnWR
nDADACSnLDEVARDY
nVLBUS
SMSC LAN91C111
ExternalGlue Logic
DigitalClock
Manager
PP
C
OP
B B
us
FPGA
DS325_06_071406
External Reset
VCC
GND
To System Interrupt Controller
External Glue Logic
The SMSC LAN91C111 device requires two inputs nCYCLE and nRDYRTN to control synchronous operation The definition of these signals is outside the scope of this document and can be found in the documents listed in the Reference Documents section The nCYCLE and nRDYRTN signals are generated in external glue logic nCYCLE may be generated from PRH_CS_n and is driven low for a
Discontinued IP
ust 10 2007 wwwxilinxcom 23ecification
OPB External Peripheral Controller (EPC) v100a
24
single clock cycle on a high to low transition on PRH_CS_n nRDYRTN is simply the registered value of the nSRDY signal
Design Considerations
When the OPB EPC is interfaced to the SMSC LAN91C111 with data width match enabled (C_PRHx_DWIDTH_MATCH = 1) and the internal SRAM of the peripheral is being accessed the device has to be configured in the address auto increment mode Address auto increment mode can be configured by setting AUTO INCR bit in the Bank 2 Pointer Register of SMSC LAN91C111 More information can be obtained by referring the registers of Bank 2 in SMSC LAN91C111 data sheet See the Reference Documents section
Example Cypress Semiconductorrsquos CY7C67300 EZ-Host Programmable Embedded USB HostPeripheral Controller
The Cypress Semiconductorrsquos CY7C67300 EZ-Hosttrade Programmable Embedded USB HostPeripheral Controller is another example of a peripheral device supported by the OPB EPC Since the Cypress USB controller operates in asynchronous mode the OPB EPC must be configured to support asynchronous mode operation
Asynchronous Mode
Figure 7 illustrates the CY7C67300 USB Controller connection to the OPB EPC in asynchronous mode with non-multiplexed address and data buses
The following parameter settings apply for the connection shown in Figure 7
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 4
bull C_PRH0_DWIDTH = 16
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Configuration of CY7C67300 USB Controller
The CY7C67300 USB Controller is configured as a Host Processor Interface (HPI) The boot-up sequence code for the CY7C67300 USB Controller in this particular example is present on the external Compact Flash memory device and is accessed through the OPB SYSACE interface This code is downloaded to the CY7C67300 USB Controller through the HPI interface Once this boot-up sequence is executed by the CY7C67300 USB Controller it becomes ready to operate in normal HPI mode with the external host controller (OPB EPC)
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
F
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 7 CY7C67300 USB Controller connection to OPB EPC in asynchronous mode
igure Top x-ref 7
SysACE_mpd_I[015]SysACE_mpd_O[015]SysACE_mpd_T[015]
SysACE_mpweSysACE_mpoe
SysACE_MPA[06]
SysACE_CEN
OPB SYS ACE Cntlr[150][150][150]
[60]
PRH_RstPRH_Rdy
PRH_CS_n
PRH_Data_I[015]PRH_Data_O[015]PRH_Data_T[015]
PRH_ADSPRH_RRNW
PRH_BurstPRH_Rd_nPRH_Wr_n
PRH_Addr[01]
OPB EPC
VCC
Ext
erna
l US
B P
orts
P
ort 1
A 1
B 2
AnCS
nRD
nWR
[D15D0]
[A1A0]
INT
CompactFLASH
TQFP144 SYSTEMACE
System ACE CompactFlash Controller
Ext
erna
l Glu
e Lo
gic
OPBINTC
US
B C
Y7C
6730
0
PP
C
OP
B B
us
FPGA
DS325_07_071406
Sysace_epc_data[150]
HPI interface
Sysace_epc_rd_n
Sysace_epc_wr_n
Sysace_epc_a[10]
DM1B
DP1B
DM2A
DP2A
DM1A
DP1A
External Glue Logic
In the interface diagram shown in Figure 7 the OPB EPC as well as the OPB SYSACE share the interface for data address and control lines on the board This requires external multiplex logic to be placed outside of IP cores in the FPGA The OPB EPC control signals PRH_RD_n and PRH_WR_n are muxed with the MEM_CEN and MEM_WEN signals of the OPB SYSACE When CY7C67300 USB Controller is accessed through the asynchronous mode the rising edge of sysace_epc_rd_n and sysace_epc_wr_n signals are used to control the read and the write operations respectively See the Reference Documents section for more information on OPB SYSACE
Design Constraints
Timing Constraints
Timing constraints must be placed on the system clock and the peripheral clock setting the frequency to meet the bus timing requirements An example is shown in Figure 8
Discontinued IP
ust 10 2007 wwwxilinxcom 25ecification
F
OPB External Peripheral Controller (EPC) v100a
26
Figure 8 EPC Timing Constraints
igure Top x-ref 8
Following constraint must be placed on the system clock
TIMESPEC TS_OPB_Clk = PERIOD OPB_Clk 10 ns HIGH 50
NET OPB_Clk TNM_NET = OPB_Clk
If C_PRH_CLK_SUPPORT=1 then the following constraint must be placed on the peripheral clock
TIMESPEC TS_PRH_Clk = PERIOD PRH_Clk 20 ns HIGH 50
NET PRH_Clk TNM_NET = PRH_Clk
DS325_08_071406
Design Implementation
Timing Diagrams
The timing diagrams in the figures below show various OPB transactions and the resulting access cycles on the peripheral interface Timing diagrams are not shown for all possible combinations of generics and the resulting access cycles However the timing diagrams shown are sufficient for the basic understanding of various access cycles supported by the OPB EPC
Figure 9 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 9
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
DS325_09_071206
8
4000000
004
04
Figure 10 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 10
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
04000000
20000004
8
00000000
004
04DS325_10_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 11 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 11
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000000
F
00010203
000 001 002 003
00 01 02 03DS325_11_071206
Figure 12 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 12
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
20000000
F
0000000000000000
000 001 002 003
00 01 02 03DS325_12_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 27ecification
OPB External Peripheral Controller (EPC) v100a
28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 29ecification
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
2
F
Functional Description
OPB EPC Design DescriptionThe OPB External Peripheral Controller (EPC) interface diagram shown in Figure 1 depicts the major interfaces of the design
Figure 1 OPB EPC Interface Diagram
igure Top x-ref 1
DS325_01_071406
IPICInterface
OPB SlaveInterface
OPB EPC ExternalPeripheralInterface
OPB_IPIF EPC_CORE
ExternalPeripheralDevice 1
ExternalPeripheralDevice 4
The OPB EPC design provides a general purpose interface to external peripheral devices and the OPB It is a OPB slave only device The OPB EPC can be configured to provide support for multiple external peripherals up to a maximum of four devices and each device is independently configured to respond either in synchronous or asynchronous mode The timing parameters governing the access cycles such as setuphold time cycle access time cycle recovery time etc are configured by the user It receives read or write operation commands from the OPB and generates a corresponding access cycle to one of the four peripheral devices
The OPB EPC core is comprised of the following modules
bull OPB_IPIF
bull EPC_CORE
OPB_IPIF
The OPB_IPIF provides an interface between the EPC_CORE and the 32-bit OPB The OPB_IPIF module implements the basic functionality of the OPB slave operation and does the necessary protocol and timing translation between the OPB and the IPIC interface
For more information on the OPB_IPIF refer to the OPB IPIF documents listed in the Reference Documents section
EPC_CORE
The EPC_CORE provides an interface between the IPIC interface and the external peripheral devices The EPC_CORE consists of the logic necessary to convert the access cycles on the IPIC interface to the corresponding access cycles on the peripheral bus adhering to the device specific timing parameters
The block diagram for the EPC_CORE is shown in Figure 2
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Figure 2 OPB EPC Block Diagram
igure Top x-ref 2
DS325_02_071406
AddressData Mux
AccessMux
Control Signal Mux
Control SignalGeneration
Async Control
Cycle TimeGeneration
SyncControl
DataSteer
IPIC IF Decode
IPIC Interface
PeripheralControl Signals
PeripheralAddress Bus
PeripheralData Bus
IPIC Control SignalsDataBus
AddressBus
OPB Bus
OPB IPIF
EPC CORE
OPB_ClkPRH_Clk
AddressGeneration
The EPC_CORE consists of
bull The IPIC_IF Decode module This module provides decoding of IPIC signals and synchronization of control signals
bull The Sync Control module This module implements the state machine which controls the synchronous interface
bull The Async Control module This module implements the state machine which controls the asynchronous interface including the asynchronous timing parameters
bull The Data Steer module This module provides the data bus width matching and data steering logic
bull The Address Generation module This module provides the generation of the lower address bits
bull The Access Mux module This module provides the multiplexing of address data and other control signals
A detailed description of the modules is provided below
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IPIC IF Decode Module
The IPIC IF Decode module implements the interface to the OPB_IPIF It also configures the EPC_CORE and interfaces to the Async Control module and Sync Control module by driving the necessary control signals based on user parameter settings
Sync Control and Async Control Modules
In Figure 2 the Sync Control and Async Control modules depict the synchronous and asynchronous paths of the EPC_ CORE This ensures that the read and write accesses to the external device(s) adheres to the specific timing parameters defined for the external device(s) Implementation of the Sync Control and Async Control modules is dependent on the parameter C_PRHx_SYNC If synchronous and asynchronous external peripheral devices exist simultaneously then both the Sync Control and Async Control modules will be implemented
The Sync Control module operates either on the OPB clock (OPB_Clk) or on the external peripheral clock (PRH_Clk) depending on the generic C_PRH_CLK_SUPPORT If C_PRH_CLK_SUPPORT = 1 then the Sync Control module operates on external device peripheral clock (PRH_Clk) that is different from the OPB clock If more than one device is synchronous then the frequency for the PRH_Clk should be chosen as the minimum of the operating frequencies of those devices The IPIC control signals that are inputs to the Sync Control module are synchronized to the PRH_Clk in the IPIC IF Decode module to indicate the start of a transaction Similarly the control signals from the Sync Control module to the IPIC interface such as data acknowledge are synchronized to the OPB clock in the IPIC IF Decode module If C_PRH_CLK_SUPPORT = 0 the Sync Control module operates on the OPB clock and the IPIC Decode module interface does not perform synchronization of control signals
The Async Control module operates on the OPB clock This module generates the control signals to the initiate read and write access cycles to the external peripheral device based on the asynchronous timing parameters set by the user
Data Steer and Address Generation Modules
The data bus of the external device must be less than or equal to the OPB data width and may be 8-bit 16-bit or 32-bit When the width of the external peripheral data bus is less than that of OPB and if C_PRHx_DWIDTH_MATCH = 1 for a particular device then the Data Steer Module will generate multiple read or write cycles to the external device to match a single access on the OPB
In order to map a single 32-bit OPB access to multiple 8-bit or 16-bit accesses the lower bits of the address bus are internally generated within the Address Generation module to provide the correct address to the external peripheral device The address bus increments as each transaction completes
For example if the external device is 8-bit wide then four read or write cycles to the device will be performed in order to match a single read or write transaction on the OPB For a write cycle the first byte of the OPB data bus (OPB_DBus[07]) is presented on the peripheral data bus (PRH_Data[07]) When the external device accepts the transaction a new write cycle is generated and the second byte of the OPB data bus (OPB_DBus[815]) is presented on the peripheral data bus (PRH_Data[07]) and so on When the last byte of the OPB data bus (OPB_DBus[2431]) is accepted by the peripheral the data acknowledge signal is generated to the OPB_IPIF interface to indicate that the access is complete on the peripheral interface
Similarly for a read cycle when the external device indicates it is ready to complete the transaction the data on the peripheral data bus (PRH_Data[07]) is internally registered as the first byte to be presented to OPB data bus (OPB_DBus[07]) followed by initiation of new read cycle on the peripheral interface The second read access on the peripheral data bus (PRH_Data[07]) is internally registered as the
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second byte to be presented to OPB data bus (OPB_DBus[815]) and so on When all four bytes are read from the external device an acknowledge is generated to the OPB_IPIF to indicate that the data is ready to be transferred to OPB data bus
When support for data width match is enabled for any of the external devices then the access to that device should respect data alignment ie a half word access should be aligned to a 16-bit boundary and a word access should be aligned to a 32-bit boundary
Access Mux Module
The interface to the external peripherals supports both multiplexed and non-multiplexed address and data bus to the external devices The Access Mux module controls the multiplexing of the peripheral address and data buses based on the parameter C_PRHx_BUS_MULTIPLEX If C_PRHx_BUS_MULTIPLEX = 1 the address and the data bus are multiplexed and presented to the corresponding external device on PRH_Data bus The address will be valid on the PRH_Data bus as long as the address strobe is active (PRH_ADS) This access will be performed in two phases (address phase and data phase) The data phase will be followed by the address phase If C_PRHx_BUS_MULTIPLEX = 0 then the address and the data are presented to the device on separate buses (PRH_Addr bus and PRH_Data bus) and the access cycle will contain only one phase
OPB EPC IO SignalsThe Table 1 provides a summary of all OPB EPC inputoutput (IO) signals
Table 1 OPB EPC IO Signal Description
Port Signal Name InterfaceSignal Type
Initial Status
Description
OPB Signals
P1OPB_ABus[0C_OPB_AWIDTH-1]
OPB I - OPB address bus
P2OPB_BE[0C_OPB_DWIDTH8-1]
OPB I - OPB byte enables
P3OPB_DBus[0C_OPB_DWIDTH-1]
OPB I - OPB data bus
P4 OPB_RNW OPB I - OPB read not write
P5 OPB_Select OPB I - OPB select
P6 OPB_seqAddr OPB I - OPB sequential address
P7Sln_DBus[0C_OPB_DWIDTH-1]
OPB O 0 OPB EPC data bus
P8 Sln_errAck OPB O 0 OPB EPC error acknowledge
P9 Sln_retry OPB O 0 OPB EPC retry
P10 Sln_toutSup OPB O 0 OPB EPC timeout suppress
P11 Sln_xferAck OPB O 0 OPB EPC transfer acknowledge
System Interface Signals
P12 OPB_Clk OPB I - OPB clock
P13 OPB_Rst OPB I - OPB reset
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OPB EPC Signals
P14 PRH_Clk(1) EPC I - External peripheral clock input
P15 PRH_Rst EPC I -External peripheral reset inputActive high input signal to the core
P16PRH_CS_n[0C_NUM_PERIPHERALS-1]
EPC O 1External peripheral chip selectActive low output signal from the core
P17PRH_Addr[0C_PRH_MAX_AWIDTH-1](2) EPC O - External peripheral address bus
P18 PRH_ADS EPC O 0
External peripheral address strobe in case of multiplexed address and data busActive high output signal from the core
P19PRH_BE[0C_PRH_MAX_DWIDTH8-1]
EPC O -External peripheral byte enablesActive high output signal from the core
P20 PRH_RNW EPC O 1
External peripheral readwrite signal for synchronous access modeActive high output signal from the core
P21 PRH_Rd_n EPC O 1
External peripheral read signal for asynchronous access modeActive low output signal from the core
P22 PRH_Wr_n EPC O 1
External peripheral write signal for asynchronous access modeActive low output signal from the core
P23 PRH_Burst EPC O 0
Burst cycle indication to external peripheralActive high output signal from the core
P24PRH_Rdy[0C_NUM_PERIPHERALS-1]
EPC I -
Peripheral ready signal This signal is used by the external peripheral to extend the transactionActive high input signal to the core
P25PRH_Data_I[0C_PRH_MAX_ADWIDTH-1]
EPC I - External peripheral input data bus
P26PRH_Data_O[0C_PRH_MAX_ADWIDTH-1] EPC O - External peripheral output data bus
Table 1 OPB EPC IO Signal Description (Contd)
Port Signal Name InterfaceSignal Type
Initial Status
Description
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P27PRH_Data_T[0C_PRH_MAX_ADWIDTH-1]
EPC O -3-state control for external peripheral output data bus
Notes 1 PRH_Clk is utilized only when C_PRH_CLK_SUPPORT = 1 and the interface to the external peripheral is
synchronous2 External peripheral devices are considered as byte addressable irrespective of the data bus width
Table 1 OPB EPC IO Signal Description (Contd)
Port Signal Name InterfaceSignal Type
Initial Status
Description
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OPB EPC Design ParametersTo allow a user to create the OPB EPC that is uniquely tailored for the system certain features can be parameterized in the OPB EPC design Some of these parameters control the interface to the OPB while others control the interface to the peripheral devices This allows the user to have a design that only utilizes the minimum resources required by the system and operating at the best possible performance
The features that could be parameterized in the OPB EPC are shown in Table 2
Table 2 OPB EPC Design Parameters
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
OPB EPC Features
G1OPB clock period
C_OPB_CLK_PERIOD_PS
Integer number of picoseconds
10000 integer
G2 Target FPGA family C_FAMILYvirtex2 virtex2p virtex4 virtex5 spartan3
virtex2p string
G3 OPB address width C_OPB_AWIDTH 32 32 integer
G4 OPB data width C_OPB_DWIDTH 32 32 integer
OPB EPC Interface Parameters
G5 Peripheral clock periodC_PRH_CLK_PERIOD_PS(1)
Integer number of picoseconds
20000 integer
G6 Number of peripheralsC_NUM_PERIPHERALS
1-4 1 integer
G7Maximum of address bus width of all external peripherals
C_PRH_MAX_AWIDTH 3-32 32integer
G8Maximum of data bus width of all external peripherals
C_PRH_MAX_DWIDTH 8 16 or 32 32 integer
G9
Maximum of data bus width of all peripherals and address bus with of peripherals employing addressdata multiplexing
C_PRH_MAX_ADWIDTH(2) 8-32 32 integer
G10 Peripheral clock supportC_PRH_CLK_SUPPORT(1)
0 = Peripheral device interface operates at the OPB clock 1 = Peripheral device interface operates at external peripheral clock
0 integer
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G11 OPB burst supportC_PRH_BURST_SUPPORT(24)
0 = No burst support from OPB 1 = Not supported
0 integer
OPB EPC Peripheral Address Space
G12External peripheral base address
C_PRHx_BASEADDR(3) Valid address(4 5)
User must set values(6)
std_logic_vector
G13External peripheral high address
C_PRHx_HIGHADDR(3) Valid address(4 5)
User must set values(6)
std_logic_vector
OPB EPC Peripheral Interface Parameters
G14Support for access to FIFO within the external peripheral
C_PRHx_FIFO_ACCESS(3)
0 = No support for the external peripheral FIFO access1 = Access to FIFO structures within the external peripheral device is supported
0 integer
G15External peripheral FIFO offset from peripheral base address
C_PRHx_FIFO_OFFSET(3 7 8)
Any valid offset within the base and high address range assigned to the peripheral device
0 integer
G16Address bus width of peripherals
C_PRHx_AWIDTH(3) 3-32 32 integer
G17Data bus width of peripherals
C_PRHx_DWIDTH(3) 8 16 or 32 32 integer
G18
Support for data width match when the peripheral device data width is less than the OPB data width
C_PRHx_DWIDTH_MATCH(3 9)
0 = No multiple cycles on the peripheral interface for single OPB read or write cycle 1 = Run multiple cycles on the peripheral interface for single OPB read or write cycle
0 integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
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G19 Peripheral access mode C_PRHx_SYNC(1 3)
0 = External device is asynchronous 1 = External device is synchronous
1 integer
G20 Peripheral bus typeC_PRHx_BUS_MULTIPLEX(3)
0 = External device has separate address and data bus1 = External device has multiplexed address and data bus
0 integer
OPB EPC Timing Parameters
G21
Address bus (PRH_Addr) setup with respect to rising edge of address strobe (PRH_ADS) or falling edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_ADDR_TSU(3 10)
Integer number of picoseconds
User must set values(11)
integer
G22
Address bus (PRH_Addr) hold with respect to falling edge of address strobe (PRH_ADS) or rising edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_ADDR_TH(3 12 16 19)
Integer number of picoseconds
User must set values(11)
integer
G23Minimum pulse width of address strobe (PRH_ADS)
C_PRHx_ADS_WIDTH(3)
Integer number of picoseconds
User must set values(11)
integer
G24
Chip select (PRH_CS_n) setup with respect to falling edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_CSN_TSU(3 10)
Integer number of picoseconds
User must set values(13)
integer
G25
Chip select (PRH_CS_n) hold with respect to rising edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_CSN_TH(3 16 19)
Integer number of picoseconds
User must set values(13)
integer
G26Minimum pulse width of write signal (PRH_Wr_n)
C_PRHx_WRN_WIDTH(3 14 15 16)
Integer number of picoseconds
User must set values(13)
integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
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G27Cycle time of write signal (PRH_Wr_n)
C_PRHx_WR_CYCLE(3 15 16)
Integer number of picoseconds
User must set values(13)
integer
G28
Data bus (PRH_Data) setup with respect to falling edge of write signal (PRH_Wr_n)
C_PRHx_DATA_TSU(3 14)
Integer number of picoseconds
User must set values(13)
integer
G29
Data bus (PRH_Data) hold with respect to rising edge of write signal (PRH_Wr_n)
C_PRHx_DATA_TH(3 16)
Integer number of picoseconds
User must set values(13)
integer
G30Minimum pulse width of read signal (PRH_Rd_n)
C_PRHx_RDN_WIDTH(3 17 18 19)
Integer number of picoseconds
User must set values(13)
integer
G31Cycle time of read signal (PRH_Rd_n)
C_PRHx_RD_CYCLE(3 18 19)
Integer number of picoseconds
User must set values(13)
integer
G32
Data bus (PRH_Data) validity from falling edge of read signal (PRH_Rd_n)
C_PRHx_DATA_TOUT(3 17)
Integer number of picoseconds
User must set values(13)
integer
G33
Data bus (PRH_Data) high impedance from rising edge of read (PRH_Rd_n)
C_PRHx_DATA_TINV(3 19)
Integer number of picoseconds
User must set values(13)
integer
G34
Device ready (PRH_Rdy) validity from the falling edge of read or write (PRH_Rd_n PRH_Wr_n)
C_PRHx_RDY_TOUT(3 20 22)
Integer number of picoseconds
User must set values(13)
integer
G35
Maximum period of device ready signal (PRH_Rdy) to wait before device timeout
C_PRHx_RDY_WIDTH(3 21 22)
Integer number of picoseconds
User must set values(23)
integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
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Notes 1 The generic C_PRH_CLK_SUPPORT is relevant only when the device is configured for synchronous access
ie C_PRHx_SYNC = 1 If more than one device is synchronous then the frequency for the peripheral clock (PRH_Clk) should be chosen as the minimum of the operating frequencies of those devices
2 The C_PRH_MAX_ADWIDTH determines the size of the data bus For all non multiplexed devices the C_PRH_MAX_ADWIDTH reflects the maximum of data bus width of all external devices ie C_PRH_MAX_ADWIDTH equals C_PRH_MAX_DWIDTH However if any of the devices is configured for multiplexed address and data bus then C_PRH_MAX_ADWIDTH should be set as the maximum of data bus of all external devices and the address bus of device(s) employing multiplexed address and data bus
3 rsquoxrsquo in the generic refers to the number of the peripheral device and takes a value in the range of 0 to C_NUM_PERIPHERALS - 1
4 OPB EPC design can accommodate up to four peripheral devices The address range for the devices are designated as C_PRH0_BASEADDR C_PRH0_HIGHADDR C_PRH1_BASEADDR C_PRH1_HIGHADDR etc
5 The range specified by C_PRHx_BASEADDR and C_PRHx_HIGHADDR must comprise a contiguous range and the size of the range must be a power of two ie size of range = 2m Further the rsquomrsquo least significant bits of C_PRHx_BASEADDR must be zero The base and high address range assigned to different peripherals must be mutually exclusive
6 No default value will be specified to ensure that the actual value is set ie if the value is not set a compiler error will be generated
7 C_PRHx_FIFO_ACCESS must be set to 1 if the support for access to FIFO within external peripheral device is to be included
8 C_PRHx_FIFO_OFFSET is the byte offset of the external peripheral FIFO from the base address (C_PRHx_BASEADDR) of the peripheral irrespective of the data width of the peripheral device If C_PRHx_FIFO_ACCESS = 1 then C_PRHx_FIFO_OFFSET must be set to a valid offset within the address range assigned to the peripheral
9 The generic C_PRHx_DWIDTH_MATCH is relevant only when the width of the peripheral data (PRH_Data) bus is less than the OPB data bus (OPB_DBus)
10Address setup time is with respect to falling edge of address strobe (PRH_ADS) if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 and must be set both in synchronous and asynchronous mode Address setup time is with respect to falling edge of readwrite signals (PRH_Wr_nPRH_Rd_n) if the device is non multiplexed and is relevant only if the access mode is asynchronous
11Value for the parameter must be assigned if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 This parameter assignment is appicalble for synchronous and asynchronous devices
12Address hold time is with respect to falling edge of address strobe (PRH_ADS) if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 and must be set both in synchronous and asynchronous mode Address hold time is with respect to rising edge of readwrite signals (PRH_Wr_nPRH_Rd_n) if the address and the data bus are separate and is relevant only if the access mode is asynchronous
13Value must be assigned if the access mode of the peripherals is asynchronous ie C_PRHx_SYNC = 0 If the access mode of the peripheral is synchronous ie C_PRHx_SYNC = 1 then the zero should be assigned to the parameter
14Write signal (PRH_Wr_n) low time is the maximum of C_PRHx_WRN_WIDTH and C_PRHx_DATA_TSU15The value of C_PRHx_WRN_WIDTH must be smaller than C_PRHx_WR_CYCLE16 In non-multiplexed address and data bus mode write recovery time will be maximum of C_PRHx_ADDR_TH
C_PRHx_CSN_TH C_PRHx_DATA_TH and PRH_Wr_n high time (ie C_PRHx_WR_CYCLE minus C_PRHx_WRN_WIDTH) If the peripheral uses multiplexed address and data bus then the write recovery time will be maximum of C_PRHx_CSN_TH C_PRHx_DATA_TH and PRH_Wr_n high time
17Read signal (PRH_Rd_n) low time is the maximum of C_PRHx_RDN_WIDTH and C_PRHx_DATA_TOUT18The value of C_PRHx_RDN_WIDTH must be smaller than C_PRHx_RD_CYCLE19 In non-multiplexed address and data bus mode read recovery time will be maximum of C_PRHx_ADDR_TH
C_PRHx_CSN_TH C_PRHx_DATA_TINV and PRH_Rd_n high time (ie C_PRHx_RD_CYCLE minus C_PRHx_RDN_WIDTH) If the peripheral uses multiplexed address and data bus then the read recovery time will be maximum of C_PRHx_CSN_TH C_PRHx_DATA_TINV and PRH_Rd_n high time
20Device ready validity period (C_PRHx_RDY_TOUT) must be set as the maximum of the values specified for read and write transactions
21Device ready pulse width (C_PRHx_RDY_WIDTH) must be set as the maximum of the values specified for read and write transactions
22Device ready validity (C_PRHx_RDY_TOUT) period must be less than the write strobe width (C_PRHx_WRN_WIDTH) read strobe width (C_PRHx_RDN_WIDTH) and device ready signal width (C_PRHx_RDY_WIDTH)
23Device ready signal width (C_PRHx_RDY_WIDTH) must be set for both synchronous and asynchronous
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
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Allowable Parameter Combinations
When the peripheral devices are confugured in non multiplexed mode the C_PRH_MAX_AWIDTH should be the maximum of C_PRHx_AWIDTH of all peripherals in the system ie if C_NUM_PERIPHERALS is 2 then C_PRH_MAX_AWIDTH should be maximum of C_PRH0_AWIDTH and C_PRH1_AWIDTH
C_PRH_MAX_DWIDTH should be the maximum of C_PRHx_DWIDTH of all peripherals in the system ie if C_NUM_PERIPHERALS is 2 then C_PRH_MAX_DWIDTH should be maximum of C_PRH0_DWIDTH and C_PRH1_DWIDTH
If any of the peripheral devices are configured for a multiplexed address and data buses then the parameter C_PRH_MAX_ADWIDTH should be set as the maximum of the data bus and address bus of the device(s) employing a multiplexed address and data bus If all devices employ non-multiplexed address and data buses then C_PRH_MAX_ADWIDTH reflects the maximum of data bus width of all external devices Therefore for any configuration the parameter C_PRH_MAX_ADWIDTH should be greater than or equal to C_PRH_MAX_DWIDTH
The generic C_PRH_CLK_SUPPORT is relevant only when the devices are configured for the synchronous access ie C_PRHx_SYNC = 1 If more than one of the devices are synchronous then the frequency for the peripheral clock should be chosen as the minimum of the operating frequencies of those devices
The range specified by C_PRHx_BASEADDR and C_PRHx_HIGHADDR parameters must comprise a contiguous range and the size of the range must be a power of two ie size of range = 2m Furthermore the rsquomrsquo least significant bits of C_PRHx_BASEADDR must be zero The base and high address range assigned to different peripherals must be mutually exclusive No default value will be specified for C_PRHx_BASEADDR and C_PRHx_HIGHADDR in order to enforce that the user configures these parameters with the actual values If the values are not set for C_PRHx_BASEADDR and C_PRHx_HIGHADDR a compiler error will be generated
In order to access FIFO like structures within the external peripheral devices C_PRHx_FIFO_ACCESS must be set to rsquo1rsquo When FIFO access is enabled C_PRHx_FIFO_OFFSET specifies the offset of the FIFO in terms of number of byte locations from the base address (C_PRHx_BASEADDR) of the peripheral and should be set to an offset that lies within the address range assigned to the peripheral device ie C_PRHx_BASEADDR + C_PRHx_FIFO_OFFSET le C_PRHx_HIGHADDR Furthermore the FIFO offset should be within the range addressable by the address bus ie C_PRHx_FIFO_OFFSET lt 2n
where n = C_PRHx_AWIDTH
The width of the readwrite strobe must be less than the cycle time of the corresponding access ie C_PRHx_WRN_WIDTH lt C_PRHx_WR_CYCLE and C_PRHx_RDN_WIDTH lt C_PRHx_RD_CYCLE The value of device ready validity period must be less than the readwrite strobe width and the maximum pulse width of the device ready signal ie C_PRHx_RDY_TOUT lt minimum of C_PRHx_WRN_WIDTH C_PRHx_RDN_WIDTH and C_PRHx_RDY_WIDTH
Parameter - Port Dependencies
The dependencies between the OPB EPC design parameters and the IO ports are shown in Table 3 The width of the OPB EPC signals depend on some of the parameters In addition when certain features are parameterized away the related logic is removed
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Table 3 Parameter - Port Dependencies
Generic or Port
Name Affects Depends Description
Design Parameters
G3 C_OPB_AWIDTH P1 -The OPB address width parameter sets the width of the OPB address bus
G4 C_OPB_DWIDTHP2 P3
P7-
The OPB data width parameter affects the number of byte enables configured for the OPB data bus width of the OPB data bus and the width of the OPB slave read data bus
G6C_NUM_PERIPHERALS
P16 P24-
The number of peripherals in the system determines the number of chip select signals driven and the number of device ready inputs decoded by the OPB external peripheral controller
G7C_PRH_MAX_AWIDTH
P17- The width of the peripheral address bus is set to
the maximum of address bus width of all peripheral devices
G8C_PRH_MAX_DWIDTH
P19- The number of byte enables for the peripheral data
bus is determined by the maximum of data bus width of the peripheral devices
G9C_PRH_MAX_ADWIDTH
P25 P26 P27
-
The width of the peripheral input data bus peripheral output data bus and the peripheral output data bus 3-state control are determined by the maximum of data bus width of all peripherals and the address bus width of peripherals employing address data bus multiplexing
G10C_PRH_CLK_SUPPORT
P14- If C_PRH_CLK_SUPPORT = 0 then all external
devices operate on OPB clock The input PRH_Clk must be driven high externally
G18C_PRHx_DWIDTH_MATCH
P23-
If the device is configured for synchronous mode with data width matching enabled then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
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G19 C_PRHx_SYNCP14 P20 P21 P22
P23
-
If the device is configured for asynchronous mode
bull With peripheral clock support the peripheral clock input (PRH_Clk) must be driven high externally
bull PRH_RNW is driven high as PRH_Rd_n and PRH_Wr_n should be used as read and write strobe
bull With data width matching enabled the OPB EPC drives PRH_Burst to its default low
If the device is configured for synchronous mode
bull The OPB EPC drives PRH_Rd_n and PRH_Wr_n outputs to their default state of high since PRH_RNW output is used as readwrite strobe
G20C_PRHx_BUS_MULTIPLEX
P18- PRH_ADS is driven low if the device does not use
multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
IO Signals
P1 OPB_ABus - G3The OPB address bus width is determined by the C_OPB_AWIDTH parameter
P2 OPB_BE - G4The number of byte enables for the OPB data bus is determined by the C_OPB_DWIDTH parameter
P3 OPB_DBus - G4The OPB data bus width is determined by the C_OPB_DWIDTH parameter
P7 Sln_DBus-
G4The width of the OPB slave read data bus is determined by the C_OPB_DWIDTH parameter
P14 PRH_Clk-
G10 G19
PRH_Clk is selected as operating clock only if the device is configured for synchronous mode with peripheral clock support ie C_PRHx_SYNC = 1 and C_PRH_CLK_SUPPORT = 1 Asynchronous interface always operates on OPB_Clk Therefore if no device is configured for synchronous mode with peripheral clock support enabled then the input PRH_Clk must be driven high
P16 PRH_CS_n-
G6The number of chip select signals driven by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P17 PRH_Addr-
G7The width of the peripheral address bus is determined by the C_PRH_MAX_AWIDTH parameter
P18 PRH_ADS-
G20PRH_ADS is driven low if the device does not use multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
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ust 10 2007 wwwxilinxcom 15ecification
OPB External Peripheral Controller (EPC) v100a
16
OPB EPC Design Considerations
The OPB EPC is an OPB slave only device It receives read or write instructions from the processor and generates a corresponding access cycle on the peripheral interface Examples of read and write accesses are illustrated in the Timing Diagrams section The user must take the following considerations into account while designing with the OPB EPC
Device Ready Signal
The OPB EPC readwrite access cycles are executed only when the external device assert the device ready signal (PRH_Rdy) If the external peripheral device does not have a device ready signal then the PRH_Rdy input of the OPB EPC must be tied to logic high
P19 PRH_BE - G8The number of byte enables for the peripheral data bus is determined by the C_PRH_MAX_DWIDTH parameter
P20 PHR_RNW-
G19
If the device is synchronous ie C_PRHx_SYNC = 1 then PRH_RNW should be used as the readwrite control signal For asynchronous mode of operation PRH_RNW is driven high
P21 PRH_Rd_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Rd_n should be used as the read strobe For synchronous mode of operation PRH_Rd_n is driven high
P22 PRH_Wr_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Wr_n should be used as the write strobe For synchronous mode of operation PRH_Wr_n is driven high
P23 PRH_Burst-
G18 G19
If the device is synchronous with data width matching enabled ie C_PRHx_SYNC = 1 and C_PRHx_DWIDTH_MATCH = 1 then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
P24 PRH_Rdy-
G6The number of device ready inputs decoded by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P25 PRH_Data_I-
G9The peripheral input data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P26 PRH_Data_O - G9The peripheral output data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P27 PRH_Data_T - G9
The peripheral output data bus 3-state control width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
FIFO Transactions
When C_PRHx_FIFO_ACCESS = 1 the OPB EPC supports access to FIFOrsquos within the external peripheral devices When the FIFO within the external device is accessed then the peripheral address bus (PRH_Addr) must remain constant representing the FIFO address within the address range assigned to the peripheral device When data width matching is enabled and the access corresponds to the FIFO the OPB EPC does not increment the peripheral address (PRH_Addr) bus
Abnormal Terminations
If PRH_Rdy is de-asserted for more than the maximum period as specified by C_PRHx_RDY_WIDTH then the OPB EPC terminates the current access to the external device and signals an error to the OPB master by asserting Sln_errAck on the OPB Similarly when the OPB master terminates the current access (master abort on the OPB) OPB EPC terminates the access to the external device immediately In both cases the access to the external device is terminated abnormally Therefore the external device may be in an indeterminate state and the exceptions should be handled appropriately at the system level
Interrupt Handling
If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Peripheral Data Bus Mapping
The peripheral data bus (PRH_Data) uses big endian bit labelling (ie bit-0 is Most Significant Bit (MSB) and bit-31 is Least Significant Bit (LSB) for a 32-bit bus) and is sized according to the C_PRH_MAX_ADWIDTH parameter Peripherals that have smaller widths should connect to this bus starting at bit 0 (MSB) For example if three external devices are present in the system with data bus width of 8-bit 16-bit and 32-bit the 8-bit device should connect to PRH_Data[07] the 16-bit wide peripheral should connect to PRH_Data[015] and the 32-bit peripheral should connect to PRH_Data[031]
The bit and byte labeling for the big endian data types is shown in Figure 3
Discontinued IP
ust 10 2007 wwwxilinxcom 17ecification
F
OPB External Peripheral Controller (EPC) v100a
18
Figure 3 OPB EPC Big Endian Data Type
igure Top x-ref 3
2 3
n+2 n+3
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 15
Halfword
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 31
Word
Byte
MS Byte
LS BitMS Bit
0
nByte address
Byte label
Byte significance
Bit label
Bit significance
0 7
DS325_03_071406
Unsupported Features
Many peripheral devices have the device specific inputoutput ports such as status remote reset remote wakeup interrupts etc The OPB EPC does not have any provision to support these device specific inputoutput ports Therefore if the external device has any such device specific ports then these inputoutput ports may be connected directly to system general purpose input output controller or to the system interrupt controller If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Many peripheral devices support DMA capability However currently OPB EPC is an OPB slave only device and therefore does not support DMA operations from the external peripheral devices
Current version of the OPB EPC does not support burst transactions tofrom the OPB
OPB EPC Latency
The OPB EPC latency calculations are based on the OPB clock The OPB latency is defined as the number of OPB clock cycles elapsed from the time an access is initiated to the time the access is completed (Sln_xferAck is asserted) on the OPB Table 4 shows the latency calculations for asynchronous mode and Table 5 shows the latency calculations for synchronous mode of operation
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 4 Asynchronous Mode OPB EPC Latency
Transaction Type
ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation(1)
OPB Latency
50 MHz
OPB Latency 100 MHz
ReadWrite access to asynchronous device when addressdata bus is not multiplexed
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5)
9(7) 12(7)
1FIFO
Memory
5 + N(2) (T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5))
21(7) 33(7)
ReadWrite access to asynchronous device when addressdata bus is multiplexed (Register access)
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + (T_SETUP(3) + T_ADDR_HOLD(6) + 1 + CONTROL_WIDTH(4) + T_HOLD(5))
11(7) 14(7)
1 FIFO
5 + T_SETUP(3) + T_ADDR_HOLD(6) + 1 + N(2) (CONTROL_WIDTH(4) + T_HOLD(5))
20(7) 29(7)
1 Memory
4 + N(2) (T_SETUP(3) + T_ADDR_HOLD(6) + CONTROL_WIDTH(4) + T_HOLD(5) + 2)
32(7) 44(7)
Notes 1 Latency calculations assumes the device is always ready2 If C_PRHx_DWIDTH_MATCH = 1 then N = Access size on OPB (in bytes)width of peripheral data bus (in
bytes)3 T_SETUP is the setup time requirement on various control signals in terms of number of OPB clocks and is
device specific4 CONTROL_WIDTH represents the required width for readwrite signal in terms of number of OPB clocks and
is device specific 5 T_HOLD is the hold time requirement on various control signals in terms of number of OPB clocks and is
device specific6 T_ADDR_HOLD is the required hold time on the address bus (as specified by generic C_PRHx_ADDR_TH) in
terms of number of OPB clocks and is device specific 7 Calculation are made for typical values of various timing parameters with T_SETUP = 20ns T_HOLD = 10ns
T_ADDR_HOLD = 6ns and STROBE_WIDTH = 40ns
Discontinued IP
ust 10 2007 wwwxilinxcom 19ecification
OPB External Peripheral Controller (EPC) v100a
20
Table 5 Synchronous Mode OPB EPC Latency
Transaction Type ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory 9
1FIFO
Memory 8 + N(2)
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory 11
1 FIFO 10 + N(2)
1 Memory 6 + 5N(2)
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 7 peripheral clocks
1FIFO
Memory
7 OPB clocks + (6+N(2)) peripheral clocks
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 9 peripheral clocks
1 FIFO7 OPB clocks + (8+N(2)) peripheral clocks
1 Memory7 OPB clocks + (4+5N(2)) peripheral clocks
Notes 1 Latency calculations assumes the device is always ready2 N = Access size on the OPB (in bytes)width of peripheral data bus (in bytes) where access size on OPB
equals or less than C_OPB_DWIDTH expressed in terms of bytes3 Latency calculation assumes that the requirement on address setup (C_PRHx_ADDR_TSU) address hold
(C_PRHx_ADDR_TH) and ADS pulse width (C_PRHx_ADS_WIDTH) are all less than one OPB clock
OPB EPC External Peripheral ConnectionsThe OPB EPC interface to the external device is based upon the width of the OPB data bus address and data width of the peripheral subsystem number of peripherals in the system addressdata multiplex support mode of operation (synchronous or asynchronous) and if synchronous device the operating clock for the synchronous data path
Determining Address and Data Width
The address bus width of the peripheral subsystem is the maximum width of the address bus of all peripheral devices connected to the OPB EPC If all devices employ non-multiplexed address and data bus the data bus width of the peripheral subsystem is the maximum of the data bus width of all external devices If any of the devices are configured for multiplexed address and data bus then the data bus width of the peripheral subsystem should be set as the maximum of the data bus and the address bus of the device(s) employing a multiplexed address and data bus
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Endian Considerations
The peripheral address and data bus of the OPB EPC is labeled with big endian bit labeling (D0 is the MSB and D31 is the LSB for a 32-bit bus) while most peripheral devices are either endian agnostic ie they can be connected either way or little endian (D31 is the MSB and D0 is the LSB for a 32-bit bus) Caution must be exercised with the connection to the external peripheral devices to avoid incorrect data and address connections
Clock Generation
When connecting to a synchronous external device the OPB EPC may operate either on the OPB clock (OPB_Clk) or on a peripheral clock (PRH_Clk) The operating clock for the synchronous interface is based on the generic C_PRH_CLK_SUPPORT If C_PRH_CLK_SUPPORT = 1 the peripheral clock is used else the OPB clock is used The external devices connected to the OPB EPC will determine the operating frequency of the peripheral clock The minimum of the operating frequencies of various devices connected to OPB EPC should be used as the operating frequency of the peripheral clock (PRH_Clk)
Figure 4 illustrates a block diagram for generating a device specific clock source clock source using two DCMs The DCM modules are located within the FPGA but are external to the OPB EPC An external clock source is used to generate the OPB clock (OPB_Clk) to the OPB EPC The device clock source (PRH_Clk) is also generated from the same DCM (DCM0) using the CLKFX output and must be routed on the board to be fed back to the FPGA Another DCM (DCM1) is used to synchronize the device peripheral clock to the OPB EPC PRH_Clk
Figure 4 External Peripherals clocked by FPGA output with feedback
igure Top x-ref 4
DS325_04_071406
CLKFB CLK0
CLKFXCLKIN
DCM0
PRH_Clk_FB
PRH_Clk
OPB_Clk
CLKFB CLK0
CLKIN
DCM1
PRH_Clk
OPB_Clk
OPB EPCExternalDevice
CLK
FPGA
Example Peripheral Connections
Example SMSC LAN91C111 10100 non-PCI Ethernet Single Chip MAC + PHY
An example peripheral device supported by the OPB EPC is the SMSC 10100 non-PCI Ethernet Single Chip MAC + PHY LAN91C111 The OPB EPC allows OPB masters to access the device both in synchronous and asynchronous mode The device connections for synchronous and asynchronous mode of operations are outlined in the Asynchronous Mode and Synchronous Mode sections
Discontinued IP
ust 10 2007 wwwxilinxcom 21ecification
OPB External Peripheral Controller (EPC) v100a
22
F
Asynchronous Mode
Figure 5 illustrates the SMSC LAN91C111 connections to the OPB EPC in asynchronous mode with non-multiplexed address and data buses In asynchronous mode the input clock source (PRH_Clk) to the external device must be tied to VCC When the SMSC LAN91C111 is accessed through the asynchronous mode the rising edge of PRH_Rd_n and PRH_Wr_n signals are used to control the read and the write operations respectively As the device uses Asynchronous Ready (ARDY) signal to indicate its readiness in asynchronous mode This signal is connected to the PRH_Rdy input of the OPB EPC Since the address and the data buses are not multiplexed PRH_ADS will be driven low by the OPB EPC
The following parameter settings apply for the connections shown in Figure 5
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 5 SMSC LAN91C111 Connection to OPB EPC in Asynchronous Mode
igure Top x-ref 5
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]
PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
To System Interrupt Controller
VCC
LCLKResetAENnADSA[151]
nBE[30]
ARDYnRdnWR
D[310]
INTRO
WnRnVLBUSnCYCLE
nRDYRTNnDADACS
nLDEVnSARDY
SMSC LAN91C111
ExternalGlue Logic
PPC
OP
B B
us
FPGA
DS325_05_071406
ExternalReset VCC
External Glue Logic
Special attention must be given while interfacing the OPB EPC to the SMSC LAN91C111 in asynchronous mode The OPB EPC drives the PRH_BE active high while the SMSC LAN91C111 requires the input byte enable to be active low To match this requirement external glue logic is required to invert the PRH_BE signals before they are interfaced with the byte enable signals of the SMSC LAN91C111
Discontinued IP
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OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Synchronous Mode
Figure 6 illustrates the SMSC LAN91C111 connection to the OPB EPC in synchronous VL Bus mode with non-multiplexed address and data buses In synchronous mode the device requires an input clock source to the LCLK pin with a maximum operating frequency of 50MHz The local clock generated by the DCM for the peripheral interface must be routed to the LCLK input of SMSC LAN91C111 and PRH_Clk of OPB EPC When the device is accessed PRH_RNW is used as the control signal to indicate a readwrite access When PRH_RNW is high it indicates a read operation and when low it indicates a write operation The SMSC LAN91C111 uses nSRDY signal to indicate the device readiness This signal is connected to PRH_Rdy input of the OPB_EPC As the address and the data bus are not multiplexed PRH_ADS will be driven low
The following parameter settings apply for the connections shown in Figure 6
bull C_PRH_CLK_SUPPORT = 1
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 1
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 6 SMSC LAN91C111 Connection to OPB EPC in Synchronous Mode
igure Top x-ref 6
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
LCLKResetAENnADSA[151]nBE[30]WnRnSRDY
D[310]
nCYCLEnRDYRTN
INTRO
nRdnWR
nDADACSnLDEVARDY
nVLBUS
SMSC LAN91C111
ExternalGlue Logic
DigitalClock
Manager
PP
C
OP
B B
us
FPGA
DS325_06_071406
External Reset
VCC
GND
To System Interrupt Controller
External Glue Logic
The SMSC LAN91C111 device requires two inputs nCYCLE and nRDYRTN to control synchronous operation The definition of these signals is outside the scope of this document and can be found in the documents listed in the Reference Documents section The nCYCLE and nRDYRTN signals are generated in external glue logic nCYCLE may be generated from PRH_CS_n and is driven low for a
Discontinued IP
ust 10 2007 wwwxilinxcom 23ecification
OPB External Peripheral Controller (EPC) v100a
24
single clock cycle on a high to low transition on PRH_CS_n nRDYRTN is simply the registered value of the nSRDY signal
Design Considerations
When the OPB EPC is interfaced to the SMSC LAN91C111 with data width match enabled (C_PRHx_DWIDTH_MATCH = 1) and the internal SRAM of the peripheral is being accessed the device has to be configured in the address auto increment mode Address auto increment mode can be configured by setting AUTO INCR bit in the Bank 2 Pointer Register of SMSC LAN91C111 More information can be obtained by referring the registers of Bank 2 in SMSC LAN91C111 data sheet See the Reference Documents section
Example Cypress Semiconductorrsquos CY7C67300 EZ-Host Programmable Embedded USB HostPeripheral Controller
The Cypress Semiconductorrsquos CY7C67300 EZ-Hosttrade Programmable Embedded USB HostPeripheral Controller is another example of a peripheral device supported by the OPB EPC Since the Cypress USB controller operates in asynchronous mode the OPB EPC must be configured to support asynchronous mode operation
Asynchronous Mode
Figure 7 illustrates the CY7C67300 USB Controller connection to the OPB EPC in asynchronous mode with non-multiplexed address and data buses
The following parameter settings apply for the connection shown in Figure 7
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 4
bull C_PRH0_DWIDTH = 16
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Configuration of CY7C67300 USB Controller
The CY7C67300 USB Controller is configured as a Host Processor Interface (HPI) The boot-up sequence code for the CY7C67300 USB Controller in this particular example is present on the external Compact Flash memory device and is accessed through the OPB SYSACE interface This code is downloaded to the CY7C67300 USB Controller through the HPI interface Once this boot-up sequence is executed by the CY7C67300 USB Controller it becomes ready to operate in normal HPI mode with the external host controller (OPB EPC)
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
F
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 7 CY7C67300 USB Controller connection to OPB EPC in asynchronous mode
igure Top x-ref 7
SysACE_mpd_I[015]SysACE_mpd_O[015]SysACE_mpd_T[015]
SysACE_mpweSysACE_mpoe
SysACE_MPA[06]
SysACE_CEN
OPB SYS ACE Cntlr[150][150][150]
[60]
PRH_RstPRH_Rdy
PRH_CS_n
PRH_Data_I[015]PRH_Data_O[015]PRH_Data_T[015]
PRH_ADSPRH_RRNW
PRH_BurstPRH_Rd_nPRH_Wr_n
PRH_Addr[01]
OPB EPC
VCC
Ext
erna
l US
B P
orts
P
ort 1
A 1
B 2
AnCS
nRD
nWR
[D15D0]
[A1A0]
INT
CompactFLASH
TQFP144 SYSTEMACE
System ACE CompactFlash Controller
Ext
erna
l Glu
e Lo
gic
OPBINTC
US
B C
Y7C
6730
0
PP
C
OP
B B
us
FPGA
DS325_07_071406
Sysace_epc_data[150]
HPI interface
Sysace_epc_rd_n
Sysace_epc_wr_n
Sysace_epc_a[10]
DM1B
DP1B
DM2A
DP2A
DM1A
DP1A
External Glue Logic
In the interface diagram shown in Figure 7 the OPB EPC as well as the OPB SYSACE share the interface for data address and control lines on the board This requires external multiplex logic to be placed outside of IP cores in the FPGA The OPB EPC control signals PRH_RD_n and PRH_WR_n are muxed with the MEM_CEN and MEM_WEN signals of the OPB SYSACE When CY7C67300 USB Controller is accessed through the asynchronous mode the rising edge of sysace_epc_rd_n and sysace_epc_wr_n signals are used to control the read and the write operations respectively See the Reference Documents section for more information on OPB SYSACE
Design Constraints
Timing Constraints
Timing constraints must be placed on the system clock and the peripheral clock setting the frequency to meet the bus timing requirements An example is shown in Figure 8
Discontinued IP
ust 10 2007 wwwxilinxcom 25ecification
F
OPB External Peripheral Controller (EPC) v100a
26
Figure 8 EPC Timing Constraints
igure Top x-ref 8
Following constraint must be placed on the system clock
TIMESPEC TS_OPB_Clk = PERIOD OPB_Clk 10 ns HIGH 50
NET OPB_Clk TNM_NET = OPB_Clk
If C_PRH_CLK_SUPPORT=1 then the following constraint must be placed on the peripheral clock
TIMESPEC TS_PRH_Clk = PERIOD PRH_Clk 20 ns HIGH 50
NET PRH_Clk TNM_NET = PRH_Clk
DS325_08_071406
Design Implementation
Timing Diagrams
The timing diagrams in the figures below show various OPB transactions and the resulting access cycles on the peripheral interface Timing diagrams are not shown for all possible combinations of generics and the resulting access cycles However the timing diagrams shown are sufficient for the basic understanding of various access cycles supported by the OPB EPC
Figure 9 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 9
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
DS325_09_071206
8
4000000
004
04
Figure 10 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 10
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
04000000
20000004
8
00000000
004
04DS325_10_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 11 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 11
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000000
F
00010203
000 001 002 003
00 01 02 03DS325_11_071206
Figure 12 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 12
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
20000000
F
0000000000000000
000 001 002 003
00 01 02 03DS325_12_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 27ecification
OPB External Peripheral Controller (EPC) v100a
28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 29ecification
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
F
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 2 OPB EPC Block Diagram
igure Top x-ref 2
DS325_02_071406
AddressData Mux
AccessMux
Control Signal Mux
Control SignalGeneration
Async Control
Cycle TimeGeneration
SyncControl
DataSteer
IPIC IF Decode
IPIC Interface
PeripheralControl Signals
PeripheralAddress Bus
PeripheralData Bus
IPIC Control SignalsDataBus
AddressBus
OPB Bus
OPB IPIF
EPC CORE
OPB_ClkPRH_Clk
AddressGeneration
The EPC_CORE consists of
bull The IPIC_IF Decode module This module provides decoding of IPIC signals and synchronization of control signals
bull The Sync Control module This module implements the state machine which controls the synchronous interface
bull The Async Control module This module implements the state machine which controls the asynchronous interface including the asynchronous timing parameters
bull The Data Steer module This module provides the data bus width matching and data steering logic
bull The Address Generation module This module provides the generation of the lower address bits
bull The Access Mux module This module provides the multiplexing of address data and other control signals
A detailed description of the modules is provided below
Discontinued IP
ust 10 2007 wwwxilinxcom 3ecification
OPB External Peripheral Controller (EPC) v100a
4
IPIC IF Decode Module
The IPIC IF Decode module implements the interface to the OPB_IPIF It also configures the EPC_CORE and interfaces to the Async Control module and Sync Control module by driving the necessary control signals based on user parameter settings
Sync Control and Async Control Modules
In Figure 2 the Sync Control and Async Control modules depict the synchronous and asynchronous paths of the EPC_ CORE This ensures that the read and write accesses to the external device(s) adheres to the specific timing parameters defined for the external device(s) Implementation of the Sync Control and Async Control modules is dependent on the parameter C_PRHx_SYNC If synchronous and asynchronous external peripheral devices exist simultaneously then both the Sync Control and Async Control modules will be implemented
The Sync Control module operates either on the OPB clock (OPB_Clk) or on the external peripheral clock (PRH_Clk) depending on the generic C_PRH_CLK_SUPPORT If C_PRH_CLK_SUPPORT = 1 then the Sync Control module operates on external device peripheral clock (PRH_Clk) that is different from the OPB clock If more than one device is synchronous then the frequency for the PRH_Clk should be chosen as the minimum of the operating frequencies of those devices The IPIC control signals that are inputs to the Sync Control module are synchronized to the PRH_Clk in the IPIC IF Decode module to indicate the start of a transaction Similarly the control signals from the Sync Control module to the IPIC interface such as data acknowledge are synchronized to the OPB clock in the IPIC IF Decode module If C_PRH_CLK_SUPPORT = 0 the Sync Control module operates on the OPB clock and the IPIC Decode module interface does not perform synchronization of control signals
The Async Control module operates on the OPB clock This module generates the control signals to the initiate read and write access cycles to the external peripheral device based on the asynchronous timing parameters set by the user
Data Steer and Address Generation Modules
The data bus of the external device must be less than or equal to the OPB data width and may be 8-bit 16-bit or 32-bit When the width of the external peripheral data bus is less than that of OPB and if C_PRHx_DWIDTH_MATCH = 1 for a particular device then the Data Steer Module will generate multiple read or write cycles to the external device to match a single access on the OPB
In order to map a single 32-bit OPB access to multiple 8-bit or 16-bit accesses the lower bits of the address bus are internally generated within the Address Generation module to provide the correct address to the external peripheral device The address bus increments as each transaction completes
For example if the external device is 8-bit wide then four read or write cycles to the device will be performed in order to match a single read or write transaction on the OPB For a write cycle the first byte of the OPB data bus (OPB_DBus[07]) is presented on the peripheral data bus (PRH_Data[07]) When the external device accepts the transaction a new write cycle is generated and the second byte of the OPB data bus (OPB_DBus[815]) is presented on the peripheral data bus (PRH_Data[07]) and so on When the last byte of the OPB data bus (OPB_DBus[2431]) is accepted by the peripheral the data acknowledge signal is generated to the OPB_IPIF interface to indicate that the access is complete on the peripheral interface
Similarly for a read cycle when the external device indicates it is ready to complete the transaction the data on the peripheral data bus (PRH_Data[07]) is internally registered as the first byte to be presented to OPB data bus (OPB_DBus[07]) followed by initiation of new read cycle on the peripheral interface The second read access on the peripheral data bus (PRH_Data[07]) is internally registered as the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
second byte to be presented to OPB data bus (OPB_DBus[815]) and so on When all four bytes are read from the external device an acknowledge is generated to the OPB_IPIF to indicate that the data is ready to be transferred to OPB data bus
When support for data width match is enabled for any of the external devices then the access to that device should respect data alignment ie a half word access should be aligned to a 16-bit boundary and a word access should be aligned to a 32-bit boundary
Access Mux Module
The interface to the external peripherals supports both multiplexed and non-multiplexed address and data bus to the external devices The Access Mux module controls the multiplexing of the peripheral address and data buses based on the parameter C_PRHx_BUS_MULTIPLEX If C_PRHx_BUS_MULTIPLEX = 1 the address and the data bus are multiplexed and presented to the corresponding external device on PRH_Data bus The address will be valid on the PRH_Data bus as long as the address strobe is active (PRH_ADS) This access will be performed in two phases (address phase and data phase) The data phase will be followed by the address phase If C_PRHx_BUS_MULTIPLEX = 0 then the address and the data are presented to the device on separate buses (PRH_Addr bus and PRH_Data bus) and the access cycle will contain only one phase
OPB EPC IO SignalsThe Table 1 provides a summary of all OPB EPC inputoutput (IO) signals
Table 1 OPB EPC IO Signal Description
Port Signal Name InterfaceSignal Type
Initial Status
Description
OPB Signals
P1OPB_ABus[0C_OPB_AWIDTH-1]
OPB I - OPB address bus
P2OPB_BE[0C_OPB_DWIDTH8-1]
OPB I - OPB byte enables
P3OPB_DBus[0C_OPB_DWIDTH-1]
OPB I - OPB data bus
P4 OPB_RNW OPB I - OPB read not write
P5 OPB_Select OPB I - OPB select
P6 OPB_seqAddr OPB I - OPB sequential address
P7Sln_DBus[0C_OPB_DWIDTH-1]
OPB O 0 OPB EPC data bus
P8 Sln_errAck OPB O 0 OPB EPC error acknowledge
P9 Sln_retry OPB O 0 OPB EPC retry
P10 Sln_toutSup OPB O 0 OPB EPC timeout suppress
P11 Sln_xferAck OPB O 0 OPB EPC transfer acknowledge
System Interface Signals
P12 OPB_Clk OPB I - OPB clock
P13 OPB_Rst OPB I - OPB reset
Discontinued IP
ust 10 2007 wwwxilinxcom 5ecification
OPB External Peripheral Controller (EPC) v100a
6
OPB EPC Signals
P14 PRH_Clk(1) EPC I - External peripheral clock input
P15 PRH_Rst EPC I -External peripheral reset inputActive high input signal to the core
P16PRH_CS_n[0C_NUM_PERIPHERALS-1]
EPC O 1External peripheral chip selectActive low output signal from the core
P17PRH_Addr[0C_PRH_MAX_AWIDTH-1](2) EPC O - External peripheral address bus
P18 PRH_ADS EPC O 0
External peripheral address strobe in case of multiplexed address and data busActive high output signal from the core
P19PRH_BE[0C_PRH_MAX_DWIDTH8-1]
EPC O -External peripheral byte enablesActive high output signal from the core
P20 PRH_RNW EPC O 1
External peripheral readwrite signal for synchronous access modeActive high output signal from the core
P21 PRH_Rd_n EPC O 1
External peripheral read signal for asynchronous access modeActive low output signal from the core
P22 PRH_Wr_n EPC O 1
External peripheral write signal for asynchronous access modeActive low output signal from the core
P23 PRH_Burst EPC O 0
Burst cycle indication to external peripheralActive high output signal from the core
P24PRH_Rdy[0C_NUM_PERIPHERALS-1]
EPC I -
Peripheral ready signal This signal is used by the external peripheral to extend the transactionActive high input signal to the core
P25PRH_Data_I[0C_PRH_MAX_ADWIDTH-1]
EPC I - External peripheral input data bus
P26PRH_Data_O[0C_PRH_MAX_ADWIDTH-1] EPC O - External peripheral output data bus
Table 1 OPB EPC IO Signal Description (Contd)
Port Signal Name InterfaceSignal Type
Initial Status
Description
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
P27PRH_Data_T[0C_PRH_MAX_ADWIDTH-1]
EPC O -3-state control for external peripheral output data bus
Notes 1 PRH_Clk is utilized only when C_PRH_CLK_SUPPORT = 1 and the interface to the external peripheral is
synchronous2 External peripheral devices are considered as byte addressable irrespective of the data bus width
Table 1 OPB EPC IO Signal Description (Contd)
Port Signal Name InterfaceSignal Type
Initial Status
Description
Discontinued IP
ust 10 2007 wwwxilinxcom 7ecification
OPB External Peripheral Controller (EPC) v100a
8
OPB EPC Design ParametersTo allow a user to create the OPB EPC that is uniquely tailored for the system certain features can be parameterized in the OPB EPC design Some of these parameters control the interface to the OPB while others control the interface to the peripheral devices This allows the user to have a design that only utilizes the minimum resources required by the system and operating at the best possible performance
The features that could be parameterized in the OPB EPC are shown in Table 2
Table 2 OPB EPC Design Parameters
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
OPB EPC Features
G1OPB clock period
C_OPB_CLK_PERIOD_PS
Integer number of picoseconds
10000 integer
G2 Target FPGA family C_FAMILYvirtex2 virtex2p virtex4 virtex5 spartan3
virtex2p string
G3 OPB address width C_OPB_AWIDTH 32 32 integer
G4 OPB data width C_OPB_DWIDTH 32 32 integer
OPB EPC Interface Parameters
G5 Peripheral clock periodC_PRH_CLK_PERIOD_PS(1)
Integer number of picoseconds
20000 integer
G6 Number of peripheralsC_NUM_PERIPHERALS
1-4 1 integer
G7Maximum of address bus width of all external peripherals
C_PRH_MAX_AWIDTH 3-32 32integer
G8Maximum of data bus width of all external peripherals
C_PRH_MAX_DWIDTH 8 16 or 32 32 integer
G9
Maximum of data bus width of all peripherals and address bus with of peripherals employing addressdata multiplexing
C_PRH_MAX_ADWIDTH(2) 8-32 32 integer
G10 Peripheral clock supportC_PRH_CLK_SUPPORT(1)
0 = Peripheral device interface operates at the OPB clock 1 = Peripheral device interface operates at external peripheral clock
0 integer
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G11 OPB burst supportC_PRH_BURST_SUPPORT(24)
0 = No burst support from OPB 1 = Not supported
0 integer
OPB EPC Peripheral Address Space
G12External peripheral base address
C_PRHx_BASEADDR(3) Valid address(4 5)
User must set values(6)
std_logic_vector
G13External peripheral high address
C_PRHx_HIGHADDR(3) Valid address(4 5)
User must set values(6)
std_logic_vector
OPB EPC Peripheral Interface Parameters
G14Support for access to FIFO within the external peripheral
C_PRHx_FIFO_ACCESS(3)
0 = No support for the external peripheral FIFO access1 = Access to FIFO structures within the external peripheral device is supported
0 integer
G15External peripheral FIFO offset from peripheral base address
C_PRHx_FIFO_OFFSET(3 7 8)
Any valid offset within the base and high address range assigned to the peripheral device
0 integer
G16Address bus width of peripherals
C_PRHx_AWIDTH(3) 3-32 32 integer
G17Data bus width of peripherals
C_PRHx_DWIDTH(3) 8 16 or 32 32 integer
G18
Support for data width match when the peripheral device data width is less than the OPB data width
C_PRHx_DWIDTH_MATCH(3 9)
0 = No multiple cycles on the peripheral interface for single OPB read or write cycle 1 = Run multiple cycles on the peripheral interface for single OPB read or write cycle
0 integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
ust 10 2007 wwwxilinxcom 9ecification
OPB External Peripheral Controller (EPC) v100a
10
G19 Peripheral access mode C_PRHx_SYNC(1 3)
0 = External device is asynchronous 1 = External device is synchronous
1 integer
G20 Peripheral bus typeC_PRHx_BUS_MULTIPLEX(3)
0 = External device has separate address and data bus1 = External device has multiplexed address and data bus
0 integer
OPB EPC Timing Parameters
G21
Address bus (PRH_Addr) setup with respect to rising edge of address strobe (PRH_ADS) or falling edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_ADDR_TSU(3 10)
Integer number of picoseconds
User must set values(11)
integer
G22
Address bus (PRH_Addr) hold with respect to falling edge of address strobe (PRH_ADS) or rising edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_ADDR_TH(3 12 16 19)
Integer number of picoseconds
User must set values(11)
integer
G23Minimum pulse width of address strobe (PRH_ADS)
C_PRHx_ADS_WIDTH(3)
Integer number of picoseconds
User must set values(11)
integer
G24
Chip select (PRH_CS_n) setup with respect to falling edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_CSN_TSU(3 10)
Integer number of picoseconds
User must set values(13)
integer
G25
Chip select (PRH_CS_n) hold with respect to rising edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_CSN_TH(3 16 19)
Integer number of picoseconds
User must set values(13)
integer
G26Minimum pulse width of write signal (PRH_Wr_n)
C_PRHx_WRN_WIDTH(3 14 15 16)
Integer number of picoseconds
User must set values(13)
integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G27Cycle time of write signal (PRH_Wr_n)
C_PRHx_WR_CYCLE(3 15 16)
Integer number of picoseconds
User must set values(13)
integer
G28
Data bus (PRH_Data) setup with respect to falling edge of write signal (PRH_Wr_n)
C_PRHx_DATA_TSU(3 14)
Integer number of picoseconds
User must set values(13)
integer
G29
Data bus (PRH_Data) hold with respect to rising edge of write signal (PRH_Wr_n)
C_PRHx_DATA_TH(3 16)
Integer number of picoseconds
User must set values(13)
integer
G30Minimum pulse width of read signal (PRH_Rd_n)
C_PRHx_RDN_WIDTH(3 17 18 19)
Integer number of picoseconds
User must set values(13)
integer
G31Cycle time of read signal (PRH_Rd_n)
C_PRHx_RD_CYCLE(3 18 19)
Integer number of picoseconds
User must set values(13)
integer
G32
Data bus (PRH_Data) validity from falling edge of read signal (PRH_Rd_n)
C_PRHx_DATA_TOUT(3 17)
Integer number of picoseconds
User must set values(13)
integer
G33
Data bus (PRH_Data) high impedance from rising edge of read (PRH_Rd_n)
C_PRHx_DATA_TINV(3 19)
Integer number of picoseconds
User must set values(13)
integer
G34
Device ready (PRH_Rdy) validity from the falling edge of read or write (PRH_Rd_n PRH_Wr_n)
C_PRHx_RDY_TOUT(3 20 22)
Integer number of picoseconds
User must set values(13)
integer
G35
Maximum period of device ready signal (PRH_Rdy) to wait before device timeout
C_PRHx_RDY_WIDTH(3 21 22)
Integer number of picoseconds
User must set values(23)
integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
ust 10 2007 wwwxilinxcom 11ecification
OPB External Peripheral Controller (EPC) v100a
12
Notes 1 The generic C_PRH_CLK_SUPPORT is relevant only when the device is configured for synchronous access
ie C_PRHx_SYNC = 1 If more than one device is synchronous then the frequency for the peripheral clock (PRH_Clk) should be chosen as the minimum of the operating frequencies of those devices
2 The C_PRH_MAX_ADWIDTH determines the size of the data bus For all non multiplexed devices the C_PRH_MAX_ADWIDTH reflects the maximum of data bus width of all external devices ie C_PRH_MAX_ADWIDTH equals C_PRH_MAX_DWIDTH However if any of the devices is configured for multiplexed address and data bus then C_PRH_MAX_ADWIDTH should be set as the maximum of data bus of all external devices and the address bus of device(s) employing multiplexed address and data bus
3 rsquoxrsquo in the generic refers to the number of the peripheral device and takes a value in the range of 0 to C_NUM_PERIPHERALS - 1
4 OPB EPC design can accommodate up to four peripheral devices The address range for the devices are designated as C_PRH0_BASEADDR C_PRH0_HIGHADDR C_PRH1_BASEADDR C_PRH1_HIGHADDR etc
5 The range specified by C_PRHx_BASEADDR and C_PRHx_HIGHADDR must comprise a contiguous range and the size of the range must be a power of two ie size of range = 2m Further the rsquomrsquo least significant bits of C_PRHx_BASEADDR must be zero The base and high address range assigned to different peripherals must be mutually exclusive
6 No default value will be specified to ensure that the actual value is set ie if the value is not set a compiler error will be generated
7 C_PRHx_FIFO_ACCESS must be set to 1 if the support for access to FIFO within external peripheral device is to be included
8 C_PRHx_FIFO_OFFSET is the byte offset of the external peripheral FIFO from the base address (C_PRHx_BASEADDR) of the peripheral irrespective of the data width of the peripheral device If C_PRHx_FIFO_ACCESS = 1 then C_PRHx_FIFO_OFFSET must be set to a valid offset within the address range assigned to the peripheral
9 The generic C_PRHx_DWIDTH_MATCH is relevant only when the width of the peripheral data (PRH_Data) bus is less than the OPB data bus (OPB_DBus)
10Address setup time is with respect to falling edge of address strobe (PRH_ADS) if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 and must be set both in synchronous and asynchronous mode Address setup time is with respect to falling edge of readwrite signals (PRH_Wr_nPRH_Rd_n) if the device is non multiplexed and is relevant only if the access mode is asynchronous
11Value for the parameter must be assigned if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 This parameter assignment is appicalble for synchronous and asynchronous devices
12Address hold time is with respect to falling edge of address strobe (PRH_ADS) if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 and must be set both in synchronous and asynchronous mode Address hold time is with respect to rising edge of readwrite signals (PRH_Wr_nPRH_Rd_n) if the address and the data bus are separate and is relevant only if the access mode is asynchronous
13Value must be assigned if the access mode of the peripherals is asynchronous ie C_PRHx_SYNC = 0 If the access mode of the peripheral is synchronous ie C_PRHx_SYNC = 1 then the zero should be assigned to the parameter
14Write signal (PRH_Wr_n) low time is the maximum of C_PRHx_WRN_WIDTH and C_PRHx_DATA_TSU15The value of C_PRHx_WRN_WIDTH must be smaller than C_PRHx_WR_CYCLE16 In non-multiplexed address and data bus mode write recovery time will be maximum of C_PRHx_ADDR_TH
C_PRHx_CSN_TH C_PRHx_DATA_TH and PRH_Wr_n high time (ie C_PRHx_WR_CYCLE minus C_PRHx_WRN_WIDTH) If the peripheral uses multiplexed address and data bus then the write recovery time will be maximum of C_PRHx_CSN_TH C_PRHx_DATA_TH and PRH_Wr_n high time
17Read signal (PRH_Rd_n) low time is the maximum of C_PRHx_RDN_WIDTH and C_PRHx_DATA_TOUT18The value of C_PRHx_RDN_WIDTH must be smaller than C_PRHx_RD_CYCLE19 In non-multiplexed address and data bus mode read recovery time will be maximum of C_PRHx_ADDR_TH
C_PRHx_CSN_TH C_PRHx_DATA_TINV and PRH_Rd_n high time (ie C_PRHx_RD_CYCLE minus C_PRHx_RDN_WIDTH) If the peripheral uses multiplexed address and data bus then the read recovery time will be maximum of C_PRHx_CSN_TH C_PRHx_DATA_TINV and PRH_Rd_n high time
20Device ready validity period (C_PRHx_RDY_TOUT) must be set as the maximum of the values specified for read and write transactions
21Device ready pulse width (C_PRHx_RDY_WIDTH) must be set as the maximum of the values specified for read and write transactions
22Device ready validity (C_PRHx_RDY_TOUT) period must be less than the write strobe width (C_PRHx_WRN_WIDTH) read strobe width (C_PRHx_RDN_WIDTH) and device ready signal width (C_PRHx_RDY_WIDTH)
23Device ready signal width (C_PRHx_RDY_WIDTH) must be set for both synchronous and asynchronous
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
access mode in order to prevent the device from holding the OPB indefinitely24Current version of the OPB EPC do not support the burst transactions tofrom the OPB
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Allowable Parameter Combinations
When the peripheral devices are confugured in non multiplexed mode the C_PRH_MAX_AWIDTH should be the maximum of C_PRHx_AWIDTH of all peripherals in the system ie if C_NUM_PERIPHERALS is 2 then C_PRH_MAX_AWIDTH should be maximum of C_PRH0_AWIDTH and C_PRH1_AWIDTH
C_PRH_MAX_DWIDTH should be the maximum of C_PRHx_DWIDTH of all peripherals in the system ie if C_NUM_PERIPHERALS is 2 then C_PRH_MAX_DWIDTH should be maximum of C_PRH0_DWIDTH and C_PRH1_DWIDTH
If any of the peripheral devices are configured for a multiplexed address and data buses then the parameter C_PRH_MAX_ADWIDTH should be set as the maximum of the data bus and address bus of the device(s) employing a multiplexed address and data bus If all devices employ non-multiplexed address and data buses then C_PRH_MAX_ADWIDTH reflects the maximum of data bus width of all external devices Therefore for any configuration the parameter C_PRH_MAX_ADWIDTH should be greater than or equal to C_PRH_MAX_DWIDTH
The generic C_PRH_CLK_SUPPORT is relevant only when the devices are configured for the synchronous access ie C_PRHx_SYNC = 1 If more than one of the devices are synchronous then the frequency for the peripheral clock should be chosen as the minimum of the operating frequencies of those devices
The range specified by C_PRHx_BASEADDR and C_PRHx_HIGHADDR parameters must comprise a contiguous range and the size of the range must be a power of two ie size of range = 2m Furthermore the rsquomrsquo least significant bits of C_PRHx_BASEADDR must be zero The base and high address range assigned to different peripherals must be mutually exclusive No default value will be specified for C_PRHx_BASEADDR and C_PRHx_HIGHADDR in order to enforce that the user configures these parameters with the actual values If the values are not set for C_PRHx_BASEADDR and C_PRHx_HIGHADDR a compiler error will be generated
In order to access FIFO like structures within the external peripheral devices C_PRHx_FIFO_ACCESS must be set to rsquo1rsquo When FIFO access is enabled C_PRHx_FIFO_OFFSET specifies the offset of the FIFO in terms of number of byte locations from the base address (C_PRHx_BASEADDR) of the peripheral and should be set to an offset that lies within the address range assigned to the peripheral device ie C_PRHx_BASEADDR + C_PRHx_FIFO_OFFSET le C_PRHx_HIGHADDR Furthermore the FIFO offset should be within the range addressable by the address bus ie C_PRHx_FIFO_OFFSET lt 2n
where n = C_PRHx_AWIDTH
The width of the readwrite strobe must be less than the cycle time of the corresponding access ie C_PRHx_WRN_WIDTH lt C_PRHx_WR_CYCLE and C_PRHx_RDN_WIDTH lt C_PRHx_RD_CYCLE The value of device ready validity period must be less than the readwrite strobe width and the maximum pulse width of the device ready signal ie C_PRHx_RDY_TOUT lt minimum of C_PRHx_WRN_WIDTH C_PRHx_RDN_WIDTH and C_PRHx_RDY_WIDTH
Parameter - Port Dependencies
The dependencies between the OPB EPC design parameters and the IO ports are shown in Table 3 The width of the OPB EPC signals depend on some of the parameters In addition when certain features are parameterized away the related logic is removed
Discontinued IP
ust 10 2007 wwwxilinxcom 13ecification
OPB External Peripheral Controller (EPC) v100a
14
Table 3 Parameter - Port Dependencies
Generic or Port
Name Affects Depends Description
Design Parameters
G3 C_OPB_AWIDTH P1 -The OPB address width parameter sets the width of the OPB address bus
G4 C_OPB_DWIDTHP2 P3
P7-
The OPB data width parameter affects the number of byte enables configured for the OPB data bus width of the OPB data bus and the width of the OPB slave read data bus
G6C_NUM_PERIPHERALS
P16 P24-
The number of peripherals in the system determines the number of chip select signals driven and the number of device ready inputs decoded by the OPB external peripheral controller
G7C_PRH_MAX_AWIDTH
P17- The width of the peripheral address bus is set to
the maximum of address bus width of all peripheral devices
G8C_PRH_MAX_DWIDTH
P19- The number of byte enables for the peripheral data
bus is determined by the maximum of data bus width of the peripheral devices
G9C_PRH_MAX_ADWIDTH
P25 P26 P27
-
The width of the peripheral input data bus peripheral output data bus and the peripheral output data bus 3-state control are determined by the maximum of data bus width of all peripherals and the address bus width of peripherals employing address data bus multiplexing
G10C_PRH_CLK_SUPPORT
P14- If C_PRH_CLK_SUPPORT = 0 then all external
devices operate on OPB clock The input PRH_Clk must be driven high externally
G18C_PRHx_DWIDTH_MATCH
P23-
If the device is configured for synchronous mode with data width matching enabled then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G19 C_PRHx_SYNCP14 P20 P21 P22
P23
-
If the device is configured for asynchronous mode
bull With peripheral clock support the peripheral clock input (PRH_Clk) must be driven high externally
bull PRH_RNW is driven high as PRH_Rd_n and PRH_Wr_n should be used as read and write strobe
bull With data width matching enabled the OPB EPC drives PRH_Burst to its default low
If the device is configured for synchronous mode
bull The OPB EPC drives PRH_Rd_n and PRH_Wr_n outputs to their default state of high since PRH_RNW output is used as readwrite strobe
G20C_PRHx_BUS_MULTIPLEX
P18- PRH_ADS is driven low if the device does not use
multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
IO Signals
P1 OPB_ABus - G3The OPB address bus width is determined by the C_OPB_AWIDTH parameter
P2 OPB_BE - G4The number of byte enables for the OPB data bus is determined by the C_OPB_DWIDTH parameter
P3 OPB_DBus - G4The OPB data bus width is determined by the C_OPB_DWIDTH parameter
P7 Sln_DBus-
G4The width of the OPB slave read data bus is determined by the C_OPB_DWIDTH parameter
P14 PRH_Clk-
G10 G19
PRH_Clk is selected as operating clock only if the device is configured for synchronous mode with peripheral clock support ie C_PRHx_SYNC = 1 and C_PRH_CLK_SUPPORT = 1 Asynchronous interface always operates on OPB_Clk Therefore if no device is configured for synchronous mode with peripheral clock support enabled then the input PRH_Clk must be driven high
P16 PRH_CS_n-
G6The number of chip select signals driven by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P17 PRH_Addr-
G7The width of the peripheral address bus is determined by the C_PRH_MAX_AWIDTH parameter
P18 PRH_ADS-
G20PRH_ADS is driven low if the device does not use multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
Discontinued IP
ust 10 2007 wwwxilinxcom 15ecification
OPB External Peripheral Controller (EPC) v100a
16
OPB EPC Design Considerations
The OPB EPC is an OPB slave only device It receives read or write instructions from the processor and generates a corresponding access cycle on the peripheral interface Examples of read and write accesses are illustrated in the Timing Diagrams section The user must take the following considerations into account while designing with the OPB EPC
Device Ready Signal
The OPB EPC readwrite access cycles are executed only when the external device assert the device ready signal (PRH_Rdy) If the external peripheral device does not have a device ready signal then the PRH_Rdy input of the OPB EPC must be tied to logic high
P19 PRH_BE - G8The number of byte enables for the peripheral data bus is determined by the C_PRH_MAX_DWIDTH parameter
P20 PHR_RNW-
G19
If the device is synchronous ie C_PRHx_SYNC = 1 then PRH_RNW should be used as the readwrite control signal For asynchronous mode of operation PRH_RNW is driven high
P21 PRH_Rd_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Rd_n should be used as the read strobe For synchronous mode of operation PRH_Rd_n is driven high
P22 PRH_Wr_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Wr_n should be used as the write strobe For synchronous mode of operation PRH_Wr_n is driven high
P23 PRH_Burst-
G18 G19
If the device is synchronous with data width matching enabled ie C_PRHx_SYNC = 1 and C_PRHx_DWIDTH_MATCH = 1 then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
P24 PRH_Rdy-
G6The number of device ready inputs decoded by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P25 PRH_Data_I-
G9The peripheral input data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P26 PRH_Data_O - G9The peripheral output data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P27 PRH_Data_T - G9
The peripheral output data bus 3-state control width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
FIFO Transactions
When C_PRHx_FIFO_ACCESS = 1 the OPB EPC supports access to FIFOrsquos within the external peripheral devices When the FIFO within the external device is accessed then the peripheral address bus (PRH_Addr) must remain constant representing the FIFO address within the address range assigned to the peripheral device When data width matching is enabled and the access corresponds to the FIFO the OPB EPC does not increment the peripheral address (PRH_Addr) bus
Abnormal Terminations
If PRH_Rdy is de-asserted for more than the maximum period as specified by C_PRHx_RDY_WIDTH then the OPB EPC terminates the current access to the external device and signals an error to the OPB master by asserting Sln_errAck on the OPB Similarly when the OPB master terminates the current access (master abort on the OPB) OPB EPC terminates the access to the external device immediately In both cases the access to the external device is terminated abnormally Therefore the external device may be in an indeterminate state and the exceptions should be handled appropriately at the system level
Interrupt Handling
If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Peripheral Data Bus Mapping
The peripheral data bus (PRH_Data) uses big endian bit labelling (ie bit-0 is Most Significant Bit (MSB) and bit-31 is Least Significant Bit (LSB) for a 32-bit bus) and is sized according to the C_PRH_MAX_ADWIDTH parameter Peripherals that have smaller widths should connect to this bus starting at bit 0 (MSB) For example if three external devices are present in the system with data bus width of 8-bit 16-bit and 32-bit the 8-bit device should connect to PRH_Data[07] the 16-bit wide peripheral should connect to PRH_Data[015] and the 32-bit peripheral should connect to PRH_Data[031]
The bit and byte labeling for the big endian data types is shown in Figure 3
Discontinued IP
ust 10 2007 wwwxilinxcom 17ecification
F
OPB External Peripheral Controller (EPC) v100a
18
Figure 3 OPB EPC Big Endian Data Type
igure Top x-ref 3
2 3
n+2 n+3
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 15
Halfword
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 31
Word
Byte
MS Byte
LS BitMS Bit
0
nByte address
Byte label
Byte significance
Bit label
Bit significance
0 7
DS325_03_071406
Unsupported Features
Many peripheral devices have the device specific inputoutput ports such as status remote reset remote wakeup interrupts etc The OPB EPC does not have any provision to support these device specific inputoutput ports Therefore if the external device has any such device specific ports then these inputoutput ports may be connected directly to system general purpose input output controller or to the system interrupt controller If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Many peripheral devices support DMA capability However currently OPB EPC is an OPB slave only device and therefore does not support DMA operations from the external peripheral devices
Current version of the OPB EPC does not support burst transactions tofrom the OPB
OPB EPC Latency
The OPB EPC latency calculations are based on the OPB clock The OPB latency is defined as the number of OPB clock cycles elapsed from the time an access is initiated to the time the access is completed (Sln_xferAck is asserted) on the OPB Table 4 shows the latency calculations for asynchronous mode and Table 5 shows the latency calculations for synchronous mode of operation
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OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 4 Asynchronous Mode OPB EPC Latency
Transaction Type
ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation(1)
OPB Latency
50 MHz
OPB Latency 100 MHz
ReadWrite access to asynchronous device when addressdata bus is not multiplexed
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5)
9(7) 12(7)
1FIFO
Memory
5 + N(2) (T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5))
21(7) 33(7)
ReadWrite access to asynchronous device when addressdata bus is multiplexed (Register access)
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + (T_SETUP(3) + T_ADDR_HOLD(6) + 1 + CONTROL_WIDTH(4) + T_HOLD(5))
11(7) 14(7)
1 FIFO
5 + T_SETUP(3) + T_ADDR_HOLD(6) + 1 + N(2) (CONTROL_WIDTH(4) + T_HOLD(5))
20(7) 29(7)
1 Memory
4 + N(2) (T_SETUP(3) + T_ADDR_HOLD(6) + CONTROL_WIDTH(4) + T_HOLD(5) + 2)
32(7) 44(7)
Notes 1 Latency calculations assumes the device is always ready2 If C_PRHx_DWIDTH_MATCH = 1 then N = Access size on OPB (in bytes)width of peripheral data bus (in
bytes)3 T_SETUP is the setup time requirement on various control signals in terms of number of OPB clocks and is
device specific4 CONTROL_WIDTH represents the required width for readwrite signal in terms of number of OPB clocks and
is device specific 5 T_HOLD is the hold time requirement on various control signals in terms of number of OPB clocks and is
device specific6 T_ADDR_HOLD is the required hold time on the address bus (as specified by generic C_PRHx_ADDR_TH) in
terms of number of OPB clocks and is device specific 7 Calculation are made for typical values of various timing parameters with T_SETUP = 20ns T_HOLD = 10ns
T_ADDR_HOLD = 6ns and STROBE_WIDTH = 40ns
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OPB External Peripheral Controller (EPC) v100a
20
Table 5 Synchronous Mode OPB EPC Latency
Transaction Type ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory 9
1FIFO
Memory 8 + N(2)
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory 11
1 FIFO 10 + N(2)
1 Memory 6 + 5N(2)
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 7 peripheral clocks
1FIFO
Memory
7 OPB clocks + (6+N(2)) peripheral clocks
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 9 peripheral clocks
1 FIFO7 OPB clocks + (8+N(2)) peripheral clocks
1 Memory7 OPB clocks + (4+5N(2)) peripheral clocks
Notes 1 Latency calculations assumes the device is always ready2 N = Access size on the OPB (in bytes)width of peripheral data bus (in bytes) where access size on OPB
equals or less than C_OPB_DWIDTH expressed in terms of bytes3 Latency calculation assumes that the requirement on address setup (C_PRHx_ADDR_TSU) address hold
(C_PRHx_ADDR_TH) and ADS pulse width (C_PRHx_ADS_WIDTH) are all less than one OPB clock
OPB EPC External Peripheral ConnectionsThe OPB EPC interface to the external device is based upon the width of the OPB data bus address and data width of the peripheral subsystem number of peripherals in the system addressdata multiplex support mode of operation (synchronous or asynchronous) and if synchronous device the operating clock for the synchronous data path
Determining Address and Data Width
The address bus width of the peripheral subsystem is the maximum width of the address bus of all peripheral devices connected to the OPB EPC If all devices employ non-multiplexed address and data bus the data bus width of the peripheral subsystem is the maximum of the data bus width of all external devices If any of the devices are configured for multiplexed address and data bus then the data bus width of the peripheral subsystem should be set as the maximum of the data bus and the address bus of the device(s) employing a multiplexed address and data bus
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DS325 AugProduct Sp
F
Endian Considerations
The peripheral address and data bus of the OPB EPC is labeled with big endian bit labeling (D0 is the MSB and D31 is the LSB for a 32-bit bus) while most peripheral devices are either endian agnostic ie they can be connected either way or little endian (D31 is the MSB and D0 is the LSB for a 32-bit bus) Caution must be exercised with the connection to the external peripheral devices to avoid incorrect data and address connections
Clock Generation
When connecting to a synchronous external device the OPB EPC may operate either on the OPB clock (OPB_Clk) or on a peripheral clock (PRH_Clk) The operating clock for the synchronous interface is based on the generic C_PRH_CLK_SUPPORT If C_PRH_CLK_SUPPORT = 1 the peripheral clock is used else the OPB clock is used The external devices connected to the OPB EPC will determine the operating frequency of the peripheral clock The minimum of the operating frequencies of various devices connected to OPB EPC should be used as the operating frequency of the peripheral clock (PRH_Clk)
Figure 4 illustrates a block diagram for generating a device specific clock source clock source using two DCMs The DCM modules are located within the FPGA but are external to the OPB EPC An external clock source is used to generate the OPB clock (OPB_Clk) to the OPB EPC The device clock source (PRH_Clk) is also generated from the same DCM (DCM0) using the CLKFX output and must be routed on the board to be fed back to the FPGA Another DCM (DCM1) is used to synchronize the device peripheral clock to the OPB EPC PRH_Clk
Figure 4 External Peripherals clocked by FPGA output with feedback
igure Top x-ref 4
DS325_04_071406
CLKFB CLK0
CLKFXCLKIN
DCM0
PRH_Clk_FB
PRH_Clk
OPB_Clk
CLKFB CLK0
CLKIN
DCM1
PRH_Clk
OPB_Clk
OPB EPCExternalDevice
CLK
FPGA
Example Peripheral Connections
Example SMSC LAN91C111 10100 non-PCI Ethernet Single Chip MAC + PHY
An example peripheral device supported by the OPB EPC is the SMSC 10100 non-PCI Ethernet Single Chip MAC + PHY LAN91C111 The OPB EPC allows OPB masters to access the device both in synchronous and asynchronous mode The device connections for synchronous and asynchronous mode of operations are outlined in the Asynchronous Mode and Synchronous Mode sections
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OPB External Peripheral Controller (EPC) v100a
22
F
Asynchronous Mode
Figure 5 illustrates the SMSC LAN91C111 connections to the OPB EPC in asynchronous mode with non-multiplexed address and data buses In asynchronous mode the input clock source (PRH_Clk) to the external device must be tied to VCC When the SMSC LAN91C111 is accessed through the asynchronous mode the rising edge of PRH_Rd_n and PRH_Wr_n signals are used to control the read and the write operations respectively As the device uses Asynchronous Ready (ARDY) signal to indicate its readiness in asynchronous mode This signal is connected to the PRH_Rdy input of the OPB EPC Since the address and the data buses are not multiplexed PRH_ADS will be driven low by the OPB EPC
The following parameter settings apply for the connections shown in Figure 5
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 5 SMSC LAN91C111 Connection to OPB EPC in Asynchronous Mode
igure Top x-ref 5
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]
PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
To System Interrupt Controller
VCC
LCLKResetAENnADSA[151]
nBE[30]
ARDYnRdnWR
D[310]
INTRO
WnRnVLBUSnCYCLE
nRDYRTNnDADACS
nLDEVnSARDY
SMSC LAN91C111
ExternalGlue Logic
PPC
OP
B B
us
FPGA
DS325_05_071406
ExternalReset VCC
External Glue Logic
Special attention must be given while interfacing the OPB EPC to the SMSC LAN91C111 in asynchronous mode The OPB EPC drives the PRH_BE active high while the SMSC LAN91C111 requires the input byte enable to be active low To match this requirement external glue logic is required to invert the PRH_BE signals before they are interfaced with the byte enable signals of the SMSC LAN91C111
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F
Synchronous Mode
Figure 6 illustrates the SMSC LAN91C111 connection to the OPB EPC in synchronous VL Bus mode with non-multiplexed address and data buses In synchronous mode the device requires an input clock source to the LCLK pin with a maximum operating frequency of 50MHz The local clock generated by the DCM for the peripheral interface must be routed to the LCLK input of SMSC LAN91C111 and PRH_Clk of OPB EPC When the device is accessed PRH_RNW is used as the control signal to indicate a readwrite access When PRH_RNW is high it indicates a read operation and when low it indicates a write operation The SMSC LAN91C111 uses nSRDY signal to indicate the device readiness This signal is connected to PRH_Rdy input of the OPB_EPC As the address and the data bus are not multiplexed PRH_ADS will be driven low
The following parameter settings apply for the connections shown in Figure 6
bull C_PRH_CLK_SUPPORT = 1
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 1
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 6 SMSC LAN91C111 Connection to OPB EPC in Synchronous Mode
igure Top x-ref 6
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
LCLKResetAENnADSA[151]nBE[30]WnRnSRDY
D[310]
nCYCLEnRDYRTN
INTRO
nRdnWR
nDADACSnLDEVARDY
nVLBUS
SMSC LAN91C111
ExternalGlue Logic
DigitalClock
Manager
PP
C
OP
B B
us
FPGA
DS325_06_071406
External Reset
VCC
GND
To System Interrupt Controller
External Glue Logic
The SMSC LAN91C111 device requires two inputs nCYCLE and nRDYRTN to control synchronous operation The definition of these signals is outside the scope of this document and can be found in the documents listed in the Reference Documents section The nCYCLE and nRDYRTN signals are generated in external glue logic nCYCLE may be generated from PRH_CS_n and is driven low for a
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24
single clock cycle on a high to low transition on PRH_CS_n nRDYRTN is simply the registered value of the nSRDY signal
Design Considerations
When the OPB EPC is interfaced to the SMSC LAN91C111 with data width match enabled (C_PRHx_DWIDTH_MATCH = 1) and the internal SRAM of the peripheral is being accessed the device has to be configured in the address auto increment mode Address auto increment mode can be configured by setting AUTO INCR bit in the Bank 2 Pointer Register of SMSC LAN91C111 More information can be obtained by referring the registers of Bank 2 in SMSC LAN91C111 data sheet See the Reference Documents section
Example Cypress Semiconductorrsquos CY7C67300 EZ-Host Programmable Embedded USB HostPeripheral Controller
The Cypress Semiconductorrsquos CY7C67300 EZ-Hosttrade Programmable Embedded USB HostPeripheral Controller is another example of a peripheral device supported by the OPB EPC Since the Cypress USB controller operates in asynchronous mode the OPB EPC must be configured to support asynchronous mode operation
Asynchronous Mode
Figure 7 illustrates the CY7C67300 USB Controller connection to the OPB EPC in asynchronous mode with non-multiplexed address and data buses
The following parameter settings apply for the connection shown in Figure 7
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 4
bull C_PRH0_DWIDTH = 16
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Configuration of CY7C67300 USB Controller
The CY7C67300 USB Controller is configured as a Host Processor Interface (HPI) The boot-up sequence code for the CY7C67300 USB Controller in this particular example is present on the external Compact Flash memory device and is accessed through the OPB SYSACE interface This code is downloaded to the CY7C67300 USB Controller through the HPI interface Once this boot-up sequence is executed by the CY7C67300 USB Controller it becomes ready to operate in normal HPI mode with the external host controller (OPB EPC)
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F
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 7 CY7C67300 USB Controller connection to OPB EPC in asynchronous mode
igure Top x-ref 7
SysACE_mpd_I[015]SysACE_mpd_O[015]SysACE_mpd_T[015]
SysACE_mpweSysACE_mpoe
SysACE_MPA[06]
SysACE_CEN
OPB SYS ACE Cntlr[150][150][150]
[60]
PRH_RstPRH_Rdy
PRH_CS_n
PRH_Data_I[015]PRH_Data_O[015]PRH_Data_T[015]
PRH_ADSPRH_RRNW
PRH_BurstPRH_Rd_nPRH_Wr_n
PRH_Addr[01]
OPB EPC
VCC
Ext
erna
l US
B P
orts
P
ort 1
A 1
B 2
AnCS
nRD
nWR
[D15D0]
[A1A0]
INT
CompactFLASH
TQFP144 SYSTEMACE
System ACE CompactFlash Controller
Ext
erna
l Glu
e Lo
gic
OPBINTC
US
B C
Y7C
6730
0
PP
C
OP
B B
us
FPGA
DS325_07_071406
Sysace_epc_data[150]
HPI interface
Sysace_epc_rd_n
Sysace_epc_wr_n
Sysace_epc_a[10]
DM1B
DP1B
DM2A
DP2A
DM1A
DP1A
External Glue Logic
In the interface diagram shown in Figure 7 the OPB EPC as well as the OPB SYSACE share the interface for data address and control lines on the board This requires external multiplex logic to be placed outside of IP cores in the FPGA The OPB EPC control signals PRH_RD_n and PRH_WR_n are muxed with the MEM_CEN and MEM_WEN signals of the OPB SYSACE When CY7C67300 USB Controller is accessed through the asynchronous mode the rising edge of sysace_epc_rd_n and sysace_epc_wr_n signals are used to control the read and the write operations respectively See the Reference Documents section for more information on OPB SYSACE
Design Constraints
Timing Constraints
Timing constraints must be placed on the system clock and the peripheral clock setting the frequency to meet the bus timing requirements An example is shown in Figure 8
Discontinued IP
ust 10 2007 wwwxilinxcom 25ecification
F
OPB External Peripheral Controller (EPC) v100a
26
Figure 8 EPC Timing Constraints
igure Top x-ref 8
Following constraint must be placed on the system clock
TIMESPEC TS_OPB_Clk = PERIOD OPB_Clk 10 ns HIGH 50
NET OPB_Clk TNM_NET = OPB_Clk
If C_PRH_CLK_SUPPORT=1 then the following constraint must be placed on the peripheral clock
TIMESPEC TS_PRH_Clk = PERIOD PRH_Clk 20 ns HIGH 50
NET PRH_Clk TNM_NET = PRH_Clk
DS325_08_071406
Design Implementation
Timing Diagrams
The timing diagrams in the figures below show various OPB transactions and the resulting access cycles on the peripheral interface Timing diagrams are not shown for all possible combinations of generics and the resulting access cycles However the timing diagrams shown are sufficient for the basic understanding of various access cycles supported by the OPB EPC
Figure 9 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 9
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
DS325_09_071206
8
4000000
004
04
Figure 10 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 10
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
04000000
20000004
8
00000000
004
04DS325_10_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 11 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 11
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000000
F
00010203
000 001 002 003
00 01 02 03DS325_11_071206
Figure 12 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 12
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
20000000
F
0000000000000000
000 001 002 003
00 01 02 03DS325_12_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 27ecification
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28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 29ecification
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN 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ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA 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ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
4
IPIC IF Decode Module
The IPIC IF Decode module implements the interface to the OPB_IPIF It also configures the EPC_CORE and interfaces to the Async Control module and Sync Control module by driving the necessary control signals based on user parameter settings
Sync Control and Async Control Modules
In Figure 2 the Sync Control and Async Control modules depict the synchronous and asynchronous paths of the EPC_ CORE This ensures that the read and write accesses to the external device(s) adheres to the specific timing parameters defined for the external device(s) Implementation of the Sync Control and Async Control modules is dependent on the parameter C_PRHx_SYNC If synchronous and asynchronous external peripheral devices exist simultaneously then both the Sync Control and Async Control modules will be implemented
The Sync Control module operates either on the OPB clock (OPB_Clk) or on the external peripheral clock (PRH_Clk) depending on the generic C_PRH_CLK_SUPPORT If C_PRH_CLK_SUPPORT = 1 then the Sync Control module operates on external device peripheral clock (PRH_Clk) that is different from the OPB clock If more than one device is synchronous then the frequency for the PRH_Clk should be chosen as the minimum of the operating frequencies of those devices The IPIC control signals that are inputs to the Sync Control module are synchronized to the PRH_Clk in the IPIC IF Decode module to indicate the start of a transaction Similarly the control signals from the Sync Control module to the IPIC interface such as data acknowledge are synchronized to the OPB clock in the IPIC IF Decode module If C_PRH_CLK_SUPPORT = 0 the Sync Control module operates on the OPB clock and the IPIC Decode module interface does not perform synchronization of control signals
The Async Control module operates on the OPB clock This module generates the control signals to the initiate read and write access cycles to the external peripheral device based on the asynchronous timing parameters set by the user
Data Steer and Address Generation Modules
The data bus of the external device must be less than or equal to the OPB data width and may be 8-bit 16-bit or 32-bit When the width of the external peripheral data bus is less than that of OPB and if C_PRHx_DWIDTH_MATCH = 1 for a particular device then the Data Steer Module will generate multiple read or write cycles to the external device to match a single access on the OPB
In order to map a single 32-bit OPB access to multiple 8-bit or 16-bit accesses the lower bits of the address bus are internally generated within the Address Generation module to provide the correct address to the external peripheral device The address bus increments as each transaction completes
For example if the external device is 8-bit wide then four read or write cycles to the device will be performed in order to match a single read or write transaction on the OPB For a write cycle the first byte of the OPB data bus (OPB_DBus[07]) is presented on the peripheral data bus (PRH_Data[07]) When the external device accepts the transaction a new write cycle is generated and the second byte of the OPB data bus (OPB_DBus[815]) is presented on the peripheral data bus (PRH_Data[07]) and so on When the last byte of the OPB data bus (OPB_DBus[2431]) is accepted by the peripheral the data acknowledge signal is generated to the OPB_IPIF interface to indicate that the access is complete on the peripheral interface
Similarly for a read cycle when the external device indicates it is ready to complete the transaction the data on the peripheral data bus (PRH_Data[07]) is internally registered as the first byte to be presented to OPB data bus (OPB_DBus[07]) followed by initiation of new read cycle on the peripheral interface The second read access on the peripheral data bus (PRH_Data[07]) is internally registered as the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
second byte to be presented to OPB data bus (OPB_DBus[815]) and so on When all four bytes are read from the external device an acknowledge is generated to the OPB_IPIF to indicate that the data is ready to be transferred to OPB data bus
When support for data width match is enabled for any of the external devices then the access to that device should respect data alignment ie a half word access should be aligned to a 16-bit boundary and a word access should be aligned to a 32-bit boundary
Access Mux Module
The interface to the external peripherals supports both multiplexed and non-multiplexed address and data bus to the external devices The Access Mux module controls the multiplexing of the peripheral address and data buses based on the parameter C_PRHx_BUS_MULTIPLEX If C_PRHx_BUS_MULTIPLEX = 1 the address and the data bus are multiplexed and presented to the corresponding external device on PRH_Data bus The address will be valid on the PRH_Data bus as long as the address strobe is active (PRH_ADS) This access will be performed in two phases (address phase and data phase) The data phase will be followed by the address phase If C_PRHx_BUS_MULTIPLEX = 0 then the address and the data are presented to the device on separate buses (PRH_Addr bus and PRH_Data bus) and the access cycle will contain only one phase
OPB EPC IO SignalsThe Table 1 provides a summary of all OPB EPC inputoutput (IO) signals
Table 1 OPB EPC IO Signal Description
Port Signal Name InterfaceSignal Type
Initial Status
Description
OPB Signals
P1OPB_ABus[0C_OPB_AWIDTH-1]
OPB I - OPB address bus
P2OPB_BE[0C_OPB_DWIDTH8-1]
OPB I - OPB byte enables
P3OPB_DBus[0C_OPB_DWIDTH-1]
OPB I - OPB data bus
P4 OPB_RNW OPB I - OPB read not write
P5 OPB_Select OPB I - OPB select
P6 OPB_seqAddr OPB I - OPB sequential address
P7Sln_DBus[0C_OPB_DWIDTH-1]
OPB O 0 OPB EPC data bus
P8 Sln_errAck OPB O 0 OPB EPC error acknowledge
P9 Sln_retry OPB O 0 OPB EPC retry
P10 Sln_toutSup OPB O 0 OPB EPC timeout suppress
P11 Sln_xferAck OPB O 0 OPB EPC transfer acknowledge
System Interface Signals
P12 OPB_Clk OPB I - OPB clock
P13 OPB_Rst OPB I - OPB reset
Discontinued IP
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OPB External Peripheral Controller (EPC) v100a
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OPB EPC Signals
P14 PRH_Clk(1) EPC I - External peripheral clock input
P15 PRH_Rst EPC I -External peripheral reset inputActive high input signal to the core
P16PRH_CS_n[0C_NUM_PERIPHERALS-1]
EPC O 1External peripheral chip selectActive low output signal from the core
P17PRH_Addr[0C_PRH_MAX_AWIDTH-1](2) EPC O - External peripheral address bus
P18 PRH_ADS EPC O 0
External peripheral address strobe in case of multiplexed address and data busActive high output signal from the core
P19PRH_BE[0C_PRH_MAX_DWIDTH8-1]
EPC O -External peripheral byte enablesActive high output signal from the core
P20 PRH_RNW EPC O 1
External peripheral readwrite signal for synchronous access modeActive high output signal from the core
P21 PRH_Rd_n EPC O 1
External peripheral read signal for asynchronous access modeActive low output signal from the core
P22 PRH_Wr_n EPC O 1
External peripheral write signal for asynchronous access modeActive low output signal from the core
P23 PRH_Burst EPC O 0
Burst cycle indication to external peripheralActive high output signal from the core
P24PRH_Rdy[0C_NUM_PERIPHERALS-1]
EPC I -
Peripheral ready signal This signal is used by the external peripheral to extend the transactionActive high input signal to the core
P25PRH_Data_I[0C_PRH_MAX_ADWIDTH-1]
EPC I - External peripheral input data bus
P26PRH_Data_O[0C_PRH_MAX_ADWIDTH-1] EPC O - External peripheral output data bus
Table 1 OPB EPC IO Signal Description (Contd)
Port Signal Name InterfaceSignal Type
Initial Status
Description
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
P27PRH_Data_T[0C_PRH_MAX_ADWIDTH-1]
EPC O -3-state control for external peripheral output data bus
Notes 1 PRH_Clk is utilized only when C_PRH_CLK_SUPPORT = 1 and the interface to the external peripheral is
synchronous2 External peripheral devices are considered as byte addressable irrespective of the data bus width
Table 1 OPB EPC IO Signal Description (Contd)
Port Signal Name InterfaceSignal Type
Initial Status
Description
Discontinued IP
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OPB External Peripheral Controller (EPC) v100a
8
OPB EPC Design ParametersTo allow a user to create the OPB EPC that is uniquely tailored for the system certain features can be parameterized in the OPB EPC design Some of these parameters control the interface to the OPB while others control the interface to the peripheral devices This allows the user to have a design that only utilizes the minimum resources required by the system and operating at the best possible performance
The features that could be parameterized in the OPB EPC are shown in Table 2
Table 2 OPB EPC Design Parameters
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
OPB EPC Features
G1OPB clock period
C_OPB_CLK_PERIOD_PS
Integer number of picoseconds
10000 integer
G2 Target FPGA family C_FAMILYvirtex2 virtex2p virtex4 virtex5 spartan3
virtex2p string
G3 OPB address width C_OPB_AWIDTH 32 32 integer
G4 OPB data width C_OPB_DWIDTH 32 32 integer
OPB EPC Interface Parameters
G5 Peripheral clock periodC_PRH_CLK_PERIOD_PS(1)
Integer number of picoseconds
20000 integer
G6 Number of peripheralsC_NUM_PERIPHERALS
1-4 1 integer
G7Maximum of address bus width of all external peripherals
C_PRH_MAX_AWIDTH 3-32 32integer
G8Maximum of data bus width of all external peripherals
C_PRH_MAX_DWIDTH 8 16 or 32 32 integer
G9
Maximum of data bus width of all peripherals and address bus with of peripherals employing addressdata multiplexing
C_PRH_MAX_ADWIDTH(2) 8-32 32 integer
G10 Peripheral clock supportC_PRH_CLK_SUPPORT(1)
0 = Peripheral device interface operates at the OPB clock 1 = Peripheral device interface operates at external peripheral clock
0 integer
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G11 OPB burst supportC_PRH_BURST_SUPPORT(24)
0 = No burst support from OPB 1 = Not supported
0 integer
OPB EPC Peripheral Address Space
G12External peripheral base address
C_PRHx_BASEADDR(3) Valid address(4 5)
User must set values(6)
std_logic_vector
G13External peripheral high address
C_PRHx_HIGHADDR(3) Valid address(4 5)
User must set values(6)
std_logic_vector
OPB EPC Peripheral Interface Parameters
G14Support for access to FIFO within the external peripheral
C_PRHx_FIFO_ACCESS(3)
0 = No support for the external peripheral FIFO access1 = Access to FIFO structures within the external peripheral device is supported
0 integer
G15External peripheral FIFO offset from peripheral base address
C_PRHx_FIFO_OFFSET(3 7 8)
Any valid offset within the base and high address range assigned to the peripheral device
0 integer
G16Address bus width of peripherals
C_PRHx_AWIDTH(3) 3-32 32 integer
G17Data bus width of peripherals
C_PRHx_DWIDTH(3) 8 16 or 32 32 integer
G18
Support for data width match when the peripheral device data width is less than the OPB data width
C_PRHx_DWIDTH_MATCH(3 9)
0 = No multiple cycles on the peripheral interface for single OPB read or write cycle 1 = Run multiple cycles on the peripheral interface for single OPB read or write cycle
0 integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
ust 10 2007 wwwxilinxcom 9ecification
OPB External Peripheral Controller (EPC) v100a
10
G19 Peripheral access mode C_PRHx_SYNC(1 3)
0 = External device is asynchronous 1 = External device is synchronous
1 integer
G20 Peripheral bus typeC_PRHx_BUS_MULTIPLEX(3)
0 = External device has separate address and data bus1 = External device has multiplexed address and data bus
0 integer
OPB EPC Timing Parameters
G21
Address bus (PRH_Addr) setup with respect to rising edge of address strobe (PRH_ADS) or falling edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_ADDR_TSU(3 10)
Integer number of picoseconds
User must set values(11)
integer
G22
Address bus (PRH_Addr) hold with respect to falling edge of address strobe (PRH_ADS) or rising edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_ADDR_TH(3 12 16 19)
Integer number of picoseconds
User must set values(11)
integer
G23Minimum pulse width of address strobe (PRH_ADS)
C_PRHx_ADS_WIDTH(3)
Integer number of picoseconds
User must set values(11)
integer
G24
Chip select (PRH_CS_n) setup with respect to falling edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_CSN_TSU(3 10)
Integer number of picoseconds
User must set values(13)
integer
G25
Chip select (PRH_CS_n) hold with respect to rising edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_CSN_TH(3 16 19)
Integer number of picoseconds
User must set values(13)
integer
G26Minimum pulse width of write signal (PRH_Wr_n)
C_PRHx_WRN_WIDTH(3 14 15 16)
Integer number of picoseconds
User must set values(13)
integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G27Cycle time of write signal (PRH_Wr_n)
C_PRHx_WR_CYCLE(3 15 16)
Integer number of picoseconds
User must set values(13)
integer
G28
Data bus (PRH_Data) setup with respect to falling edge of write signal (PRH_Wr_n)
C_PRHx_DATA_TSU(3 14)
Integer number of picoseconds
User must set values(13)
integer
G29
Data bus (PRH_Data) hold with respect to rising edge of write signal (PRH_Wr_n)
C_PRHx_DATA_TH(3 16)
Integer number of picoseconds
User must set values(13)
integer
G30Minimum pulse width of read signal (PRH_Rd_n)
C_PRHx_RDN_WIDTH(3 17 18 19)
Integer number of picoseconds
User must set values(13)
integer
G31Cycle time of read signal (PRH_Rd_n)
C_PRHx_RD_CYCLE(3 18 19)
Integer number of picoseconds
User must set values(13)
integer
G32
Data bus (PRH_Data) validity from falling edge of read signal (PRH_Rd_n)
C_PRHx_DATA_TOUT(3 17)
Integer number of picoseconds
User must set values(13)
integer
G33
Data bus (PRH_Data) high impedance from rising edge of read (PRH_Rd_n)
C_PRHx_DATA_TINV(3 19)
Integer number of picoseconds
User must set values(13)
integer
G34
Device ready (PRH_Rdy) validity from the falling edge of read or write (PRH_Rd_n PRH_Wr_n)
C_PRHx_RDY_TOUT(3 20 22)
Integer number of picoseconds
User must set values(13)
integer
G35
Maximum period of device ready signal (PRH_Rdy) to wait before device timeout
C_PRHx_RDY_WIDTH(3 21 22)
Integer number of picoseconds
User must set values(23)
integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
ust 10 2007 wwwxilinxcom 11ecification
OPB External Peripheral Controller (EPC) v100a
12
Notes 1 The generic C_PRH_CLK_SUPPORT is relevant only when the device is configured for synchronous access
ie C_PRHx_SYNC = 1 If more than one device is synchronous then the frequency for the peripheral clock (PRH_Clk) should be chosen as the minimum of the operating frequencies of those devices
2 The C_PRH_MAX_ADWIDTH determines the size of the data bus For all non multiplexed devices the C_PRH_MAX_ADWIDTH reflects the maximum of data bus width of all external devices ie C_PRH_MAX_ADWIDTH equals C_PRH_MAX_DWIDTH However if any of the devices is configured for multiplexed address and data bus then C_PRH_MAX_ADWIDTH should be set as the maximum of data bus of all external devices and the address bus of device(s) employing multiplexed address and data bus
3 rsquoxrsquo in the generic refers to the number of the peripheral device and takes a value in the range of 0 to C_NUM_PERIPHERALS - 1
4 OPB EPC design can accommodate up to four peripheral devices The address range for the devices are designated as C_PRH0_BASEADDR C_PRH0_HIGHADDR C_PRH1_BASEADDR C_PRH1_HIGHADDR etc
5 The range specified by C_PRHx_BASEADDR and C_PRHx_HIGHADDR must comprise a contiguous range and the size of the range must be a power of two ie size of range = 2m Further the rsquomrsquo least significant bits of C_PRHx_BASEADDR must be zero The base and high address range assigned to different peripherals must be mutually exclusive
6 No default value will be specified to ensure that the actual value is set ie if the value is not set a compiler error will be generated
7 C_PRHx_FIFO_ACCESS must be set to 1 if the support for access to FIFO within external peripheral device is to be included
8 C_PRHx_FIFO_OFFSET is the byte offset of the external peripheral FIFO from the base address (C_PRHx_BASEADDR) of the peripheral irrespective of the data width of the peripheral device If C_PRHx_FIFO_ACCESS = 1 then C_PRHx_FIFO_OFFSET must be set to a valid offset within the address range assigned to the peripheral
9 The generic C_PRHx_DWIDTH_MATCH is relevant only when the width of the peripheral data (PRH_Data) bus is less than the OPB data bus (OPB_DBus)
10Address setup time is with respect to falling edge of address strobe (PRH_ADS) if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 and must be set both in synchronous and asynchronous mode Address setup time is with respect to falling edge of readwrite signals (PRH_Wr_nPRH_Rd_n) if the device is non multiplexed and is relevant only if the access mode is asynchronous
11Value for the parameter must be assigned if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 This parameter assignment is appicalble for synchronous and asynchronous devices
12Address hold time is with respect to falling edge of address strobe (PRH_ADS) if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 and must be set both in synchronous and asynchronous mode Address hold time is with respect to rising edge of readwrite signals (PRH_Wr_nPRH_Rd_n) if the address and the data bus are separate and is relevant only if the access mode is asynchronous
13Value must be assigned if the access mode of the peripherals is asynchronous ie C_PRHx_SYNC = 0 If the access mode of the peripheral is synchronous ie C_PRHx_SYNC = 1 then the zero should be assigned to the parameter
14Write signal (PRH_Wr_n) low time is the maximum of C_PRHx_WRN_WIDTH and C_PRHx_DATA_TSU15The value of C_PRHx_WRN_WIDTH must be smaller than C_PRHx_WR_CYCLE16 In non-multiplexed address and data bus mode write recovery time will be maximum of C_PRHx_ADDR_TH
C_PRHx_CSN_TH C_PRHx_DATA_TH and PRH_Wr_n high time (ie C_PRHx_WR_CYCLE minus C_PRHx_WRN_WIDTH) If the peripheral uses multiplexed address and data bus then the write recovery time will be maximum of C_PRHx_CSN_TH C_PRHx_DATA_TH and PRH_Wr_n high time
17Read signal (PRH_Rd_n) low time is the maximum of C_PRHx_RDN_WIDTH and C_PRHx_DATA_TOUT18The value of C_PRHx_RDN_WIDTH must be smaller than C_PRHx_RD_CYCLE19 In non-multiplexed address and data bus mode read recovery time will be maximum of C_PRHx_ADDR_TH
C_PRHx_CSN_TH C_PRHx_DATA_TINV and PRH_Rd_n high time (ie C_PRHx_RD_CYCLE minus C_PRHx_RDN_WIDTH) If the peripheral uses multiplexed address and data bus then the read recovery time will be maximum of C_PRHx_CSN_TH C_PRHx_DATA_TINV and PRH_Rd_n high time
20Device ready validity period (C_PRHx_RDY_TOUT) must be set as the maximum of the values specified for read and write transactions
21Device ready pulse width (C_PRHx_RDY_WIDTH) must be set as the maximum of the values specified for read and write transactions
22Device ready validity (C_PRHx_RDY_TOUT) period must be less than the write strobe width (C_PRHx_WRN_WIDTH) read strobe width (C_PRHx_RDN_WIDTH) and device ready signal width (C_PRHx_RDY_WIDTH)
23Device ready signal width (C_PRHx_RDY_WIDTH) must be set for both synchronous and asynchronous
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
access mode in order to prevent the device from holding the OPB indefinitely24Current version of the OPB EPC do not support the burst transactions tofrom the OPB
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Allowable Parameter Combinations
When the peripheral devices are confugured in non multiplexed mode the C_PRH_MAX_AWIDTH should be the maximum of C_PRHx_AWIDTH of all peripherals in the system ie if C_NUM_PERIPHERALS is 2 then C_PRH_MAX_AWIDTH should be maximum of C_PRH0_AWIDTH and C_PRH1_AWIDTH
C_PRH_MAX_DWIDTH should be the maximum of C_PRHx_DWIDTH of all peripherals in the system ie if C_NUM_PERIPHERALS is 2 then C_PRH_MAX_DWIDTH should be maximum of C_PRH0_DWIDTH and C_PRH1_DWIDTH
If any of the peripheral devices are configured for a multiplexed address and data buses then the parameter C_PRH_MAX_ADWIDTH should be set as the maximum of the data bus and address bus of the device(s) employing a multiplexed address and data bus If all devices employ non-multiplexed address and data buses then C_PRH_MAX_ADWIDTH reflects the maximum of data bus width of all external devices Therefore for any configuration the parameter C_PRH_MAX_ADWIDTH should be greater than or equal to C_PRH_MAX_DWIDTH
The generic C_PRH_CLK_SUPPORT is relevant only when the devices are configured for the synchronous access ie C_PRHx_SYNC = 1 If more than one of the devices are synchronous then the frequency for the peripheral clock should be chosen as the minimum of the operating frequencies of those devices
The range specified by C_PRHx_BASEADDR and C_PRHx_HIGHADDR parameters must comprise a contiguous range and the size of the range must be a power of two ie size of range = 2m Furthermore the rsquomrsquo least significant bits of C_PRHx_BASEADDR must be zero The base and high address range assigned to different peripherals must be mutually exclusive No default value will be specified for C_PRHx_BASEADDR and C_PRHx_HIGHADDR in order to enforce that the user configures these parameters with the actual values If the values are not set for C_PRHx_BASEADDR and C_PRHx_HIGHADDR a compiler error will be generated
In order to access FIFO like structures within the external peripheral devices C_PRHx_FIFO_ACCESS must be set to rsquo1rsquo When FIFO access is enabled C_PRHx_FIFO_OFFSET specifies the offset of the FIFO in terms of number of byte locations from the base address (C_PRHx_BASEADDR) of the peripheral and should be set to an offset that lies within the address range assigned to the peripheral device ie C_PRHx_BASEADDR + C_PRHx_FIFO_OFFSET le C_PRHx_HIGHADDR Furthermore the FIFO offset should be within the range addressable by the address bus ie C_PRHx_FIFO_OFFSET lt 2n
where n = C_PRHx_AWIDTH
The width of the readwrite strobe must be less than the cycle time of the corresponding access ie C_PRHx_WRN_WIDTH lt C_PRHx_WR_CYCLE and C_PRHx_RDN_WIDTH lt C_PRHx_RD_CYCLE The value of device ready validity period must be less than the readwrite strobe width and the maximum pulse width of the device ready signal ie C_PRHx_RDY_TOUT lt minimum of C_PRHx_WRN_WIDTH C_PRHx_RDN_WIDTH and C_PRHx_RDY_WIDTH
Parameter - Port Dependencies
The dependencies between the OPB EPC design parameters and the IO ports are shown in Table 3 The width of the OPB EPC signals depend on some of the parameters In addition when certain features are parameterized away the related logic is removed
Discontinued IP
ust 10 2007 wwwxilinxcom 13ecification
OPB External Peripheral Controller (EPC) v100a
14
Table 3 Parameter - Port Dependencies
Generic or Port
Name Affects Depends Description
Design Parameters
G3 C_OPB_AWIDTH P1 -The OPB address width parameter sets the width of the OPB address bus
G4 C_OPB_DWIDTHP2 P3
P7-
The OPB data width parameter affects the number of byte enables configured for the OPB data bus width of the OPB data bus and the width of the OPB slave read data bus
G6C_NUM_PERIPHERALS
P16 P24-
The number of peripherals in the system determines the number of chip select signals driven and the number of device ready inputs decoded by the OPB external peripheral controller
G7C_PRH_MAX_AWIDTH
P17- The width of the peripheral address bus is set to
the maximum of address bus width of all peripheral devices
G8C_PRH_MAX_DWIDTH
P19- The number of byte enables for the peripheral data
bus is determined by the maximum of data bus width of the peripheral devices
G9C_PRH_MAX_ADWIDTH
P25 P26 P27
-
The width of the peripheral input data bus peripheral output data bus and the peripheral output data bus 3-state control are determined by the maximum of data bus width of all peripherals and the address bus width of peripherals employing address data bus multiplexing
G10C_PRH_CLK_SUPPORT
P14- If C_PRH_CLK_SUPPORT = 0 then all external
devices operate on OPB clock The input PRH_Clk must be driven high externally
G18C_PRHx_DWIDTH_MATCH
P23-
If the device is configured for synchronous mode with data width matching enabled then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G19 C_PRHx_SYNCP14 P20 P21 P22
P23
-
If the device is configured for asynchronous mode
bull With peripheral clock support the peripheral clock input (PRH_Clk) must be driven high externally
bull PRH_RNW is driven high as PRH_Rd_n and PRH_Wr_n should be used as read and write strobe
bull With data width matching enabled the OPB EPC drives PRH_Burst to its default low
If the device is configured for synchronous mode
bull The OPB EPC drives PRH_Rd_n and PRH_Wr_n outputs to their default state of high since PRH_RNW output is used as readwrite strobe
G20C_PRHx_BUS_MULTIPLEX
P18- PRH_ADS is driven low if the device does not use
multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
IO Signals
P1 OPB_ABus - G3The OPB address bus width is determined by the C_OPB_AWIDTH parameter
P2 OPB_BE - G4The number of byte enables for the OPB data bus is determined by the C_OPB_DWIDTH parameter
P3 OPB_DBus - G4The OPB data bus width is determined by the C_OPB_DWIDTH parameter
P7 Sln_DBus-
G4The width of the OPB slave read data bus is determined by the C_OPB_DWIDTH parameter
P14 PRH_Clk-
G10 G19
PRH_Clk is selected as operating clock only if the device is configured for synchronous mode with peripheral clock support ie C_PRHx_SYNC = 1 and C_PRH_CLK_SUPPORT = 1 Asynchronous interface always operates on OPB_Clk Therefore if no device is configured for synchronous mode with peripheral clock support enabled then the input PRH_Clk must be driven high
P16 PRH_CS_n-
G6The number of chip select signals driven by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P17 PRH_Addr-
G7The width of the peripheral address bus is determined by the C_PRH_MAX_AWIDTH parameter
P18 PRH_ADS-
G20PRH_ADS is driven low if the device does not use multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
Discontinued IP
ust 10 2007 wwwxilinxcom 15ecification
OPB External Peripheral Controller (EPC) v100a
16
OPB EPC Design Considerations
The OPB EPC is an OPB slave only device It receives read or write instructions from the processor and generates a corresponding access cycle on the peripheral interface Examples of read and write accesses are illustrated in the Timing Diagrams section The user must take the following considerations into account while designing with the OPB EPC
Device Ready Signal
The OPB EPC readwrite access cycles are executed only when the external device assert the device ready signal (PRH_Rdy) If the external peripheral device does not have a device ready signal then the PRH_Rdy input of the OPB EPC must be tied to logic high
P19 PRH_BE - G8The number of byte enables for the peripheral data bus is determined by the C_PRH_MAX_DWIDTH parameter
P20 PHR_RNW-
G19
If the device is synchronous ie C_PRHx_SYNC = 1 then PRH_RNW should be used as the readwrite control signal For asynchronous mode of operation PRH_RNW is driven high
P21 PRH_Rd_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Rd_n should be used as the read strobe For synchronous mode of operation PRH_Rd_n is driven high
P22 PRH_Wr_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Wr_n should be used as the write strobe For synchronous mode of operation PRH_Wr_n is driven high
P23 PRH_Burst-
G18 G19
If the device is synchronous with data width matching enabled ie C_PRHx_SYNC = 1 and C_PRHx_DWIDTH_MATCH = 1 then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
P24 PRH_Rdy-
G6The number of device ready inputs decoded by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P25 PRH_Data_I-
G9The peripheral input data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P26 PRH_Data_O - G9The peripheral output data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P27 PRH_Data_T - G9
The peripheral output data bus 3-state control width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
FIFO Transactions
When C_PRHx_FIFO_ACCESS = 1 the OPB EPC supports access to FIFOrsquos within the external peripheral devices When the FIFO within the external device is accessed then the peripheral address bus (PRH_Addr) must remain constant representing the FIFO address within the address range assigned to the peripheral device When data width matching is enabled and the access corresponds to the FIFO the OPB EPC does not increment the peripheral address (PRH_Addr) bus
Abnormal Terminations
If PRH_Rdy is de-asserted for more than the maximum period as specified by C_PRHx_RDY_WIDTH then the OPB EPC terminates the current access to the external device and signals an error to the OPB master by asserting Sln_errAck on the OPB Similarly when the OPB master terminates the current access (master abort on the OPB) OPB EPC terminates the access to the external device immediately In both cases the access to the external device is terminated abnormally Therefore the external device may be in an indeterminate state and the exceptions should be handled appropriately at the system level
Interrupt Handling
If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Peripheral Data Bus Mapping
The peripheral data bus (PRH_Data) uses big endian bit labelling (ie bit-0 is Most Significant Bit (MSB) and bit-31 is Least Significant Bit (LSB) for a 32-bit bus) and is sized according to the C_PRH_MAX_ADWIDTH parameter Peripherals that have smaller widths should connect to this bus starting at bit 0 (MSB) For example if three external devices are present in the system with data bus width of 8-bit 16-bit and 32-bit the 8-bit device should connect to PRH_Data[07] the 16-bit wide peripheral should connect to PRH_Data[015] and the 32-bit peripheral should connect to PRH_Data[031]
The bit and byte labeling for the big endian data types is shown in Figure 3
Discontinued IP
ust 10 2007 wwwxilinxcom 17ecification
F
OPB External Peripheral Controller (EPC) v100a
18
Figure 3 OPB EPC Big Endian Data Type
igure Top x-ref 3
2 3
n+2 n+3
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 15
Halfword
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 31
Word
Byte
MS Byte
LS BitMS Bit
0
nByte address
Byte label
Byte significance
Bit label
Bit significance
0 7
DS325_03_071406
Unsupported Features
Many peripheral devices have the device specific inputoutput ports such as status remote reset remote wakeup interrupts etc The OPB EPC does not have any provision to support these device specific inputoutput ports Therefore if the external device has any such device specific ports then these inputoutput ports may be connected directly to system general purpose input output controller or to the system interrupt controller If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Many peripheral devices support DMA capability However currently OPB EPC is an OPB slave only device and therefore does not support DMA operations from the external peripheral devices
Current version of the OPB EPC does not support burst transactions tofrom the OPB
OPB EPC Latency
The OPB EPC latency calculations are based on the OPB clock The OPB latency is defined as the number of OPB clock cycles elapsed from the time an access is initiated to the time the access is completed (Sln_xferAck is asserted) on the OPB Table 4 shows the latency calculations for asynchronous mode and Table 5 shows the latency calculations for synchronous mode of operation
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 4 Asynchronous Mode OPB EPC Latency
Transaction Type
ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation(1)
OPB Latency
50 MHz
OPB Latency 100 MHz
ReadWrite access to asynchronous device when addressdata bus is not multiplexed
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5)
9(7) 12(7)
1FIFO
Memory
5 + N(2) (T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5))
21(7) 33(7)
ReadWrite access to asynchronous device when addressdata bus is multiplexed (Register access)
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + (T_SETUP(3) + T_ADDR_HOLD(6) + 1 + CONTROL_WIDTH(4) + T_HOLD(5))
11(7) 14(7)
1 FIFO
5 + T_SETUP(3) + T_ADDR_HOLD(6) + 1 + N(2) (CONTROL_WIDTH(4) + T_HOLD(5))
20(7) 29(7)
1 Memory
4 + N(2) (T_SETUP(3) + T_ADDR_HOLD(6) + CONTROL_WIDTH(4) + T_HOLD(5) + 2)
32(7) 44(7)
Notes 1 Latency calculations assumes the device is always ready2 If C_PRHx_DWIDTH_MATCH = 1 then N = Access size on OPB (in bytes)width of peripheral data bus (in
bytes)3 T_SETUP is the setup time requirement on various control signals in terms of number of OPB clocks and is
device specific4 CONTROL_WIDTH represents the required width for readwrite signal in terms of number of OPB clocks and
is device specific 5 T_HOLD is the hold time requirement on various control signals in terms of number of OPB clocks and is
device specific6 T_ADDR_HOLD is the required hold time on the address bus (as specified by generic C_PRHx_ADDR_TH) in
terms of number of OPB clocks and is device specific 7 Calculation are made for typical values of various timing parameters with T_SETUP = 20ns T_HOLD = 10ns
T_ADDR_HOLD = 6ns and STROBE_WIDTH = 40ns
Discontinued IP
ust 10 2007 wwwxilinxcom 19ecification
OPB External Peripheral Controller (EPC) v100a
20
Table 5 Synchronous Mode OPB EPC Latency
Transaction Type ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory 9
1FIFO
Memory 8 + N(2)
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory 11
1 FIFO 10 + N(2)
1 Memory 6 + 5N(2)
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 7 peripheral clocks
1FIFO
Memory
7 OPB clocks + (6+N(2)) peripheral clocks
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 9 peripheral clocks
1 FIFO7 OPB clocks + (8+N(2)) peripheral clocks
1 Memory7 OPB clocks + (4+5N(2)) peripheral clocks
Notes 1 Latency calculations assumes the device is always ready2 N = Access size on the OPB (in bytes)width of peripheral data bus (in bytes) where access size on OPB
equals or less than C_OPB_DWIDTH expressed in terms of bytes3 Latency calculation assumes that the requirement on address setup (C_PRHx_ADDR_TSU) address hold
(C_PRHx_ADDR_TH) and ADS pulse width (C_PRHx_ADS_WIDTH) are all less than one OPB clock
OPB EPC External Peripheral ConnectionsThe OPB EPC interface to the external device is based upon the width of the OPB data bus address and data width of the peripheral subsystem number of peripherals in the system addressdata multiplex support mode of operation (synchronous or asynchronous) and if synchronous device the operating clock for the synchronous data path
Determining Address and Data Width
The address bus width of the peripheral subsystem is the maximum width of the address bus of all peripheral devices connected to the OPB EPC If all devices employ non-multiplexed address and data bus the data bus width of the peripheral subsystem is the maximum of the data bus width of all external devices If any of the devices are configured for multiplexed address and data bus then the data bus width of the peripheral subsystem should be set as the maximum of the data bus and the address bus of the device(s) employing a multiplexed address and data bus
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Endian Considerations
The peripheral address and data bus of the OPB EPC is labeled with big endian bit labeling (D0 is the MSB and D31 is the LSB for a 32-bit bus) while most peripheral devices are either endian agnostic ie they can be connected either way or little endian (D31 is the MSB and D0 is the LSB for a 32-bit bus) Caution must be exercised with the connection to the external peripheral devices to avoid incorrect data and address connections
Clock Generation
When connecting to a synchronous external device the OPB EPC may operate either on the OPB clock (OPB_Clk) or on a peripheral clock (PRH_Clk) The operating clock for the synchronous interface is based on the generic C_PRH_CLK_SUPPORT If C_PRH_CLK_SUPPORT = 1 the peripheral clock is used else the OPB clock is used The external devices connected to the OPB EPC will determine the operating frequency of the peripheral clock The minimum of the operating frequencies of various devices connected to OPB EPC should be used as the operating frequency of the peripheral clock (PRH_Clk)
Figure 4 illustrates a block diagram for generating a device specific clock source clock source using two DCMs The DCM modules are located within the FPGA but are external to the OPB EPC An external clock source is used to generate the OPB clock (OPB_Clk) to the OPB EPC The device clock source (PRH_Clk) is also generated from the same DCM (DCM0) using the CLKFX output and must be routed on the board to be fed back to the FPGA Another DCM (DCM1) is used to synchronize the device peripheral clock to the OPB EPC PRH_Clk
Figure 4 External Peripherals clocked by FPGA output with feedback
igure Top x-ref 4
DS325_04_071406
CLKFB CLK0
CLKFXCLKIN
DCM0
PRH_Clk_FB
PRH_Clk
OPB_Clk
CLKFB CLK0
CLKIN
DCM1
PRH_Clk
OPB_Clk
OPB EPCExternalDevice
CLK
FPGA
Example Peripheral Connections
Example SMSC LAN91C111 10100 non-PCI Ethernet Single Chip MAC + PHY
An example peripheral device supported by the OPB EPC is the SMSC 10100 non-PCI Ethernet Single Chip MAC + PHY LAN91C111 The OPB EPC allows OPB masters to access the device both in synchronous and asynchronous mode The device connections for synchronous and asynchronous mode of operations are outlined in the Asynchronous Mode and Synchronous Mode sections
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F
Asynchronous Mode
Figure 5 illustrates the SMSC LAN91C111 connections to the OPB EPC in asynchronous mode with non-multiplexed address and data buses In asynchronous mode the input clock source (PRH_Clk) to the external device must be tied to VCC When the SMSC LAN91C111 is accessed through the asynchronous mode the rising edge of PRH_Rd_n and PRH_Wr_n signals are used to control the read and the write operations respectively As the device uses Asynchronous Ready (ARDY) signal to indicate its readiness in asynchronous mode This signal is connected to the PRH_Rdy input of the OPB EPC Since the address and the data buses are not multiplexed PRH_ADS will be driven low by the OPB EPC
The following parameter settings apply for the connections shown in Figure 5
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 5 SMSC LAN91C111 Connection to OPB EPC in Asynchronous Mode
igure Top x-ref 5
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]
PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
To System Interrupt Controller
VCC
LCLKResetAENnADSA[151]
nBE[30]
ARDYnRdnWR
D[310]
INTRO
WnRnVLBUSnCYCLE
nRDYRTNnDADACS
nLDEVnSARDY
SMSC LAN91C111
ExternalGlue Logic
PPC
OP
B B
us
FPGA
DS325_05_071406
ExternalReset VCC
External Glue Logic
Special attention must be given while interfacing the OPB EPC to the SMSC LAN91C111 in asynchronous mode The OPB EPC drives the PRH_BE active high while the SMSC LAN91C111 requires the input byte enable to be active low To match this requirement external glue logic is required to invert the PRH_BE signals before they are interfaced with the byte enable signals of the SMSC LAN91C111
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Synchronous Mode
Figure 6 illustrates the SMSC LAN91C111 connection to the OPB EPC in synchronous VL Bus mode with non-multiplexed address and data buses In synchronous mode the device requires an input clock source to the LCLK pin with a maximum operating frequency of 50MHz The local clock generated by the DCM for the peripheral interface must be routed to the LCLK input of SMSC LAN91C111 and PRH_Clk of OPB EPC When the device is accessed PRH_RNW is used as the control signal to indicate a readwrite access When PRH_RNW is high it indicates a read operation and when low it indicates a write operation The SMSC LAN91C111 uses nSRDY signal to indicate the device readiness This signal is connected to PRH_Rdy input of the OPB_EPC As the address and the data bus are not multiplexed PRH_ADS will be driven low
The following parameter settings apply for the connections shown in Figure 6
bull C_PRH_CLK_SUPPORT = 1
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 1
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 6 SMSC LAN91C111 Connection to OPB EPC in Synchronous Mode
igure Top x-ref 6
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
LCLKResetAENnADSA[151]nBE[30]WnRnSRDY
D[310]
nCYCLEnRDYRTN
INTRO
nRdnWR
nDADACSnLDEVARDY
nVLBUS
SMSC LAN91C111
ExternalGlue Logic
DigitalClock
Manager
PP
C
OP
B B
us
FPGA
DS325_06_071406
External Reset
VCC
GND
To System Interrupt Controller
External Glue Logic
The SMSC LAN91C111 device requires two inputs nCYCLE and nRDYRTN to control synchronous operation The definition of these signals is outside the scope of this document and can be found in the documents listed in the Reference Documents section The nCYCLE and nRDYRTN signals are generated in external glue logic nCYCLE may be generated from PRH_CS_n and is driven low for a
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24
single clock cycle on a high to low transition on PRH_CS_n nRDYRTN is simply the registered value of the nSRDY signal
Design Considerations
When the OPB EPC is interfaced to the SMSC LAN91C111 with data width match enabled (C_PRHx_DWIDTH_MATCH = 1) and the internal SRAM of the peripheral is being accessed the device has to be configured in the address auto increment mode Address auto increment mode can be configured by setting AUTO INCR bit in the Bank 2 Pointer Register of SMSC LAN91C111 More information can be obtained by referring the registers of Bank 2 in SMSC LAN91C111 data sheet See the Reference Documents section
Example Cypress Semiconductorrsquos CY7C67300 EZ-Host Programmable Embedded USB HostPeripheral Controller
The Cypress Semiconductorrsquos CY7C67300 EZ-Hosttrade Programmable Embedded USB HostPeripheral Controller is another example of a peripheral device supported by the OPB EPC Since the Cypress USB controller operates in asynchronous mode the OPB EPC must be configured to support asynchronous mode operation
Asynchronous Mode
Figure 7 illustrates the CY7C67300 USB Controller connection to the OPB EPC in asynchronous mode with non-multiplexed address and data buses
The following parameter settings apply for the connection shown in Figure 7
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 4
bull C_PRH0_DWIDTH = 16
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Configuration of CY7C67300 USB Controller
The CY7C67300 USB Controller is configured as a Host Processor Interface (HPI) The boot-up sequence code for the CY7C67300 USB Controller in this particular example is present on the external Compact Flash memory device and is accessed through the OPB SYSACE interface This code is downloaded to the CY7C67300 USB Controller through the HPI interface Once this boot-up sequence is executed by the CY7C67300 USB Controller it becomes ready to operate in normal HPI mode with the external host controller (OPB EPC)
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OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 7 CY7C67300 USB Controller connection to OPB EPC in asynchronous mode
igure Top x-ref 7
SysACE_mpd_I[015]SysACE_mpd_O[015]SysACE_mpd_T[015]
SysACE_mpweSysACE_mpoe
SysACE_MPA[06]
SysACE_CEN
OPB SYS ACE Cntlr[150][150][150]
[60]
PRH_RstPRH_Rdy
PRH_CS_n
PRH_Data_I[015]PRH_Data_O[015]PRH_Data_T[015]
PRH_ADSPRH_RRNW
PRH_BurstPRH_Rd_nPRH_Wr_n
PRH_Addr[01]
OPB EPC
VCC
Ext
erna
l US
B P
orts
P
ort 1
A 1
B 2
AnCS
nRD
nWR
[D15D0]
[A1A0]
INT
CompactFLASH
TQFP144 SYSTEMACE
System ACE CompactFlash Controller
Ext
erna
l Glu
e Lo
gic
OPBINTC
US
B C
Y7C
6730
0
PP
C
OP
B B
us
FPGA
DS325_07_071406
Sysace_epc_data[150]
HPI interface
Sysace_epc_rd_n
Sysace_epc_wr_n
Sysace_epc_a[10]
DM1B
DP1B
DM2A
DP2A
DM1A
DP1A
External Glue Logic
In the interface diagram shown in Figure 7 the OPB EPC as well as the OPB SYSACE share the interface for data address and control lines on the board This requires external multiplex logic to be placed outside of IP cores in the FPGA The OPB EPC control signals PRH_RD_n and PRH_WR_n are muxed with the MEM_CEN and MEM_WEN signals of the OPB SYSACE When CY7C67300 USB Controller is accessed through the asynchronous mode the rising edge of sysace_epc_rd_n and sysace_epc_wr_n signals are used to control the read and the write operations respectively See the Reference Documents section for more information on OPB SYSACE
Design Constraints
Timing Constraints
Timing constraints must be placed on the system clock and the peripheral clock setting the frequency to meet the bus timing requirements An example is shown in Figure 8
Discontinued IP
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F
OPB External Peripheral Controller (EPC) v100a
26
Figure 8 EPC Timing Constraints
igure Top x-ref 8
Following constraint must be placed on the system clock
TIMESPEC TS_OPB_Clk = PERIOD OPB_Clk 10 ns HIGH 50
NET OPB_Clk TNM_NET = OPB_Clk
If C_PRH_CLK_SUPPORT=1 then the following constraint must be placed on the peripheral clock
TIMESPEC TS_PRH_Clk = PERIOD PRH_Clk 20 ns HIGH 50
NET PRH_Clk TNM_NET = PRH_Clk
DS325_08_071406
Design Implementation
Timing Diagrams
The timing diagrams in the figures below show various OPB transactions and the resulting access cycles on the peripheral interface Timing diagrams are not shown for all possible combinations of generics and the resulting access cycles However the timing diagrams shown are sufficient for the basic understanding of various access cycles supported by the OPB EPC
Figure 9 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 9
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
DS325_09_071206
8
4000000
004
04
Figure 10 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 10
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
04000000
20000004
8
00000000
004
04DS325_10_071206
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wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 11 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 11
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000000
F
00010203
000 001 002 003
00 01 02 03DS325_11_071206
Figure 12 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 12
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
20000000
F
0000000000000000
000 001 002 003
00 01 02 03DS325_12_071206
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28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
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wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
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Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
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wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
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32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU 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ESP 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FRA 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ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR 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ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO 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ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
second byte to be presented to OPB data bus (OPB_DBus[815]) and so on When all four bytes are read from the external device an acknowledge is generated to the OPB_IPIF to indicate that the data is ready to be transferred to OPB data bus
When support for data width match is enabled for any of the external devices then the access to that device should respect data alignment ie a half word access should be aligned to a 16-bit boundary and a word access should be aligned to a 32-bit boundary
Access Mux Module
The interface to the external peripherals supports both multiplexed and non-multiplexed address and data bus to the external devices The Access Mux module controls the multiplexing of the peripheral address and data buses based on the parameter C_PRHx_BUS_MULTIPLEX If C_PRHx_BUS_MULTIPLEX = 1 the address and the data bus are multiplexed and presented to the corresponding external device on PRH_Data bus The address will be valid on the PRH_Data bus as long as the address strobe is active (PRH_ADS) This access will be performed in two phases (address phase and data phase) The data phase will be followed by the address phase If C_PRHx_BUS_MULTIPLEX = 0 then the address and the data are presented to the device on separate buses (PRH_Addr bus and PRH_Data bus) and the access cycle will contain only one phase
OPB EPC IO SignalsThe Table 1 provides a summary of all OPB EPC inputoutput (IO) signals
Table 1 OPB EPC IO Signal Description
Port Signal Name InterfaceSignal Type
Initial Status
Description
OPB Signals
P1OPB_ABus[0C_OPB_AWIDTH-1]
OPB I - OPB address bus
P2OPB_BE[0C_OPB_DWIDTH8-1]
OPB I - OPB byte enables
P3OPB_DBus[0C_OPB_DWIDTH-1]
OPB I - OPB data bus
P4 OPB_RNW OPB I - OPB read not write
P5 OPB_Select OPB I - OPB select
P6 OPB_seqAddr OPB I - OPB sequential address
P7Sln_DBus[0C_OPB_DWIDTH-1]
OPB O 0 OPB EPC data bus
P8 Sln_errAck OPB O 0 OPB EPC error acknowledge
P9 Sln_retry OPB O 0 OPB EPC retry
P10 Sln_toutSup OPB O 0 OPB EPC timeout suppress
P11 Sln_xferAck OPB O 0 OPB EPC transfer acknowledge
System Interface Signals
P12 OPB_Clk OPB I - OPB clock
P13 OPB_Rst OPB I - OPB reset
Discontinued IP
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OPB External Peripheral Controller (EPC) v100a
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OPB EPC Signals
P14 PRH_Clk(1) EPC I - External peripheral clock input
P15 PRH_Rst EPC I -External peripheral reset inputActive high input signal to the core
P16PRH_CS_n[0C_NUM_PERIPHERALS-1]
EPC O 1External peripheral chip selectActive low output signal from the core
P17PRH_Addr[0C_PRH_MAX_AWIDTH-1](2) EPC O - External peripheral address bus
P18 PRH_ADS EPC O 0
External peripheral address strobe in case of multiplexed address and data busActive high output signal from the core
P19PRH_BE[0C_PRH_MAX_DWIDTH8-1]
EPC O -External peripheral byte enablesActive high output signal from the core
P20 PRH_RNW EPC O 1
External peripheral readwrite signal for synchronous access modeActive high output signal from the core
P21 PRH_Rd_n EPC O 1
External peripheral read signal for asynchronous access modeActive low output signal from the core
P22 PRH_Wr_n EPC O 1
External peripheral write signal for asynchronous access modeActive low output signal from the core
P23 PRH_Burst EPC O 0
Burst cycle indication to external peripheralActive high output signal from the core
P24PRH_Rdy[0C_NUM_PERIPHERALS-1]
EPC I -
Peripheral ready signal This signal is used by the external peripheral to extend the transactionActive high input signal to the core
P25PRH_Data_I[0C_PRH_MAX_ADWIDTH-1]
EPC I - External peripheral input data bus
P26PRH_Data_O[0C_PRH_MAX_ADWIDTH-1] EPC O - External peripheral output data bus
Table 1 OPB EPC IO Signal Description (Contd)
Port Signal Name InterfaceSignal Type
Initial Status
Description
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
P27PRH_Data_T[0C_PRH_MAX_ADWIDTH-1]
EPC O -3-state control for external peripheral output data bus
Notes 1 PRH_Clk is utilized only when C_PRH_CLK_SUPPORT = 1 and the interface to the external peripheral is
synchronous2 External peripheral devices are considered as byte addressable irrespective of the data bus width
Table 1 OPB EPC IO Signal Description (Contd)
Port Signal Name InterfaceSignal Type
Initial Status
Description
Discontinued IP
ust 10 2007 wwwxilinxcom 7ecification
OPB External Peripheral Controller (EPC) v100a
8
OPB EPC Design ParametersTo allow a user to create the OPB EPC that is uniquely tailored for the system certain features can be parameterized in the OPB EPC design Some of these parameters control the interface to the OPB while others control the interface to the peripheral devices This allows the user to have a design that only utilizes the minimum resources required by the system and operating at the best possible performance
The features that could be parameterized in the OPB EPC are shown in Table 2
Table 2 OPB EPC Design Parameters
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
OPB EPC Features
G1OPB clock period
C_OPB_CLK_PERIOD_PS
Integer number of picoseconds
10000 integer
G2 Target FPGA family C_FAMILYvirtex2 virtex2p virtex4 virtex5 spartan3
virtex2p string
G3 OPB address width C_OPB_AWIDTH 32 32 integer
G4 OPB data width C_OPB_DWIDTH 32 32 integer
OPB EPC Interface Parameters
G5 Peripheral clock periodC_PRH_CLK_PERIOD_PS(1)
Integer number of picoseconds
20000 integer
G6 Number of peripheralsC_NUM_PERIPHERALS
1-4 1 integer
G7Maximum of address bus width of all external peripherals
C_PRH_MAX_AWIDTH 3-32 32integer
G8Maximum of data bus width of all external peripherals
C_PRH_MAX_DWIDTH 8 16 or 32 32 integer
G9
Maximum of data bus width of all peripherals and address bus with of peripherals employing addressdata multiplexing
C_PRH_MAX_ADWIDTH(2) 8-32 32 integer
G10 Peripheral clock supportC_PRH_CLK_SUPPORT(1)
0 = Peripheral device interface operates at the OPB clock 1 = Peripheral device interface operates at external peripheral clock
0 integer
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G11 OPB burst supportC_PRH_BURST_SUPPORT(24)
0 = No burst support from OPB 1 = Not supported
0 integer
OPB EPC Peripheral Address Space
G12External peripheral base address
C_PRHx_BASEADDR(3) Valid address(4 5)
User must set values(6)
std_logic_vector
G13External peripheral high address
C_PRHx_HIGHADDR(3) Valid address(4 5)
User must set values(6)
std_logic_vector
OPB EPC Peripheral Interface Parameters
G14Support for access to FIFO within the external peripheral
C_PRHx_FIFO_ACCESS(3)
0 = No support for the external peripheral FIFO access1 = Access to FIFO structures within the external peripheral device is supported
0 integer
G15External peripheral FIFO offset from peripheral base address
C_PRHx_FIFO_OFFSET(3 7 8)
Any valid offset within the base and high address range assigned to the peripheral device
0 integer
G16Address bus width of peripherals
C_PRHx_AWIDTH(3) 3-32 32 integer
G17Data bus width of peripherals
C_PRHx_DWIDTH(3) 8 16 or 32 32 integer
G18
Support for data width match when the peripheral device data width is less than the OPB data width
C_PRHx_DWIDTH_MATCH(3 9)
0 = No multiple cycles on the peripheral interface for single OPB read or write cycle 1 = Run multiple cycles on the peripheral interface for single OPB read or write cycle
0 integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
ust 10 2007 wwwxilinxcom 9ecification
OPB External Peripheral Controller (EPC) v100a
10
G19 Peripheral access mode C_PRHx_SYNC(1 3)
0 = External device is asynchronous 1 = External device is synchronous
1 integer
G20 Peripheral bus typeC_PRHx_BUS_MULTIPLEX(3)
0 = External device has separate address and data bus1 = External device has multiplexed address and data bus
0 integer
OPB EPC Timing Parameters
G21
Address bus (PRH_Addr) setup with respect to rising edge of address strobe (PRH_ADS) or falling edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_ADDR_TSU(3 10)
Integer number of picoseconds
User must set values(11)
integer
G22
Address bus (PRH_Addr) hold with respect to falling edge of address strobe (PRH_ADS) or rising edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_ADDR_TH(3 12 16 19)
Integer number of picoseconds
User must set values(11)
integer
G23Minimum pulse width of address strobe (PRH_ADS)
C_PRHx_ADS_WIDTH(3)
Integer number of picoseconds
User must set values(11)
integer
G24
Chip select (PRH_CS_n) setup with respect to falling edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_CSN_TSU(3 10)
Integer number of picoseconds
User must set values(13)
integer
G25
Chip select (PRH_CS_n) hold with respect to rising edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_CSN_TH(3 16 19)
Integer number of picoseconds
User must set values(13)
integer
G26Minimum pulse width of write signal (PRH_Wr_n)
C_PRHx_WRN_WIDTH(3 14 15 16)
Integer number of picoseconds
User must set values(13)
integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G27Cycle time of write signal (PRH_Wr_n)
C_PRHx_WR_CYCLE(3 15 16)
Integer number of picoseconds
User must set values(13)
integer
G28
Data bus (PRH_Data) setup with respect to falling edge of write signal (PRH_Wr_n)
C_PRHx_DATA_TSU(3 14)
Integer number of picoseconds
User must set values(13)
integer
G29
Data bus (PRH_Data) hold with respect to rising edge of write signal (PRH_Wr_n)
C_PRHx_DATA_TH(3 16)
Integer number of picoseconds
User must set values(13)
integer
G30Minimum pulse width of read signal (PRH_Rd_n)
C_PRHx_RDN_WIDTH(3 17 18 19)
Integer number of picoseconds
User must set values(13)
integer
G31Cycle time of read signal (PRH_Rd_n)
C_PRHx_RD_CYCLE(3 18 19)
Integer number of picoseconds
User must set values(13)
integer
G32
Data bus (PRH_Data) validity from falling edge of read signal (PRH_Rd_n)
C_PRHx_DATA_TOUT(3 17)
Integer number of picoseconds
User must set values(13)
integer
G33
Data bus (PRH_Data) high impedance from rising edge of read (PRH_Rd_n)
C_PRHx_DATA_TINV(3 19)
Integer number of picoseconds
User must set values(13)
integer
G34
Device ready (PRH_Rdy) validity from the falling edge of read or write (PRH_Rd_n PRH_Wr_n)
C_PRHx_RDY_TOUT(3 20 22)
Integer number of picoseconds
User must set values(13)
integer
G35
Maximum period of device ready signal (PRH_Rdy) to wait before device timeout
C_PRHx_RDY_WIDTH(3 21 22)
Integer number of picoseconds
User must set values(23)
integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
ust 10 2007 wwwxilinxcom 11ecification
OPB External Peripheral Controller (EPC) v100a
12
Notes 1 The generic C_PRH_CLK_SUPPORT is relevant only when the device is configured for synchronous access
ie C_PRHx_SYNC = 1 If more than one device is synchronous then the frequency for the peripheral clock (PRH_Clk) should be chosen as the minimum of the operating frequencies of those devices
2 The C_PRH_MAX_ADWIDTH determines the size of the data bus For all non multiplexed devices the C_PRH_MAX_ADWIDTH reflects the maximum of data bus width of all external devices ie C_PRH_MAX_ADWIDTH equals C_PRH_MAX_DWIDTH However if any of the devices is configured for multiplexed address and data bus then C_PRH_MAX_ADWIDTH should be set as the maximum of data bus of all external devices and the address bus of device(s) employing multiplexed address and data bus
3 rsquoxrsquo in the generic refers to the number of the peripheral device and takes a value in the range of 0 to C_NUM_PERIPHERALS - 1
4 OPB EPC design can accommodate up to four peripheral devices The address range for the devices are designated as C_PRH0_BASEADDR C_PRH0_HIGHADDR C_PRH1_BASEADDR C_PRH1_HIGHADDR etc
5 The range specified by C_PRHx_BASEADDR and C_PRHx_HIGHADDR must comprise a contiguous range and the size of the range must be a power of two ie size of range = 2m Further the rsquomrsquo least significant bits of C_PRHx_BASEADDR must be zero The base and high address range assigned to different peripherals must be mutually exclusive
6 No default value will be specified to ensure that the actual value is set ie if the value is not set a compiler error will be generated
7 C_PRHx_FIFO_ACCESS must be set to 1 if the support for access to FIFO within external peripheral device is to be included
8 C_PRHx_FIFO_OFFSET is the byte offset of the external peripheral FIFO from the base address (C_PRHx_BASEADDR) of the peripheral irrespective of the data width of the peripheral device If C_PRHx_FIFO_ACCESS = 1 then C_PRHx_FIFO_OFFSET must be set to a valid offset within the address range assigned to the peripheral
9 The generic C_PRHx_DWIDTH_MATCH is relevant only when the width of the peripheral data (PRH_Data) bus is less than the OPB data bus (OPB_DBus)
10Address setup time is with respect to falling edge of address strobe (PRH_ADS) if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 and must be set both in synchronous and asynchronous mode Address setup time is with respect to falling edge of readwrite signals (PRH_Wr_nPRH_Rd_n) if the device is non multiplexed and is relevant only if the access mode is asynchronous
11Value for the parameter must be assigned if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 This parameter assignment is appicalble for synchronous and asynchronous devices
12Address hold time is with respect to falling edge of address strobe (PRH_ADS) if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 and must be set both in synchronous and asynchronous mode Address hold time is with respect to rising edge of readwrite signals (PRH_Wr_nPRH_Rd_n) if the address and the data bus are separate and is relevant only if the access mode is asynchronous
13Value must be assigned if the access mode of the peripherals is asynchronous ie C_PRHx_SYNC = 0 If the access mode of the peripheral is synchronous ie C_PRHx_SYNC = 1 then the zero should be assigned to the parameter
14Write signal (PRH_Wr_n) low time is the maximum of C_PRHx_WRN_WIDTH and C_PRHx_DATA_TSU15The value of C_PRHx_WRN_WIDTH must be smaller than C_PRHx_WR_CYCLE16 In non-multiplexed address and data bus mode write recovery time will be maximum of C_PRHx_ADDR_TH
C_PRHx_CSN_TH C_PRHx_DATA_TH and PRH_Wr_n high time (ie C_PRHx_WR_CYCLE minus C_PRHx_WRN_WIDTH) If the peripheral uses multiplexed address and data bus then the write recovery time will be maximum of C_PRHx_CSN_TH C_PRHx_DATA_TH and PRH_Wr_n high time
17Read signal (PRH_Rd_n) low time is the maximum of C_PRHx_RDN_WIDTH and C_PRHx_DATA_TOUT18The value of C_PRHx_RDN_WIDTH must be smaller than C_PRHx_RD_CYCLE19 In non-multiplexed address and data bus mode read recovery time will be maximum of C_PRHx_ADDR_TH
C_PRHx_CSN_TH C_PRHx_DATA_TINV and PRH_Rd_n high time (ie C_PRHx_RD_CYCLE minus C_PRHx_RDN_WIDTH) If the peripheral uses multiplexed address and data bus then the read recovery time will be maximum of C_PRHx_CSN_TH C_PRHx_DATA_TINV and PRH_Rd_n high time
20Device ready validity period (C_PRHx_RDY_TOUT) must be set as the maximum of the values specified for read and write transactions
21Device ready pulse width (C_PRHx_RDY_WIDTH) must be set as the maximum of the values specified for read and write transactions
22Device ready validity (C_PRHx_RDY_TOUT) period must be less than the write strobe width (C_PRHx_WRN_WIDTH) read strobe width (C_PRHx_RDN_WIDTH) and device ready signal width (C_PRHx_RDY_WIDTH)
23Device ready signal width (C_PRHx_RDY_WIDTH) must be set for both synchronous and asynchronous
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
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access mode in order to prevent the device from holding the OPB indefinitely24Current version of the OPB EPC do not support the burst transactions tofrom the OPB
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Allowable Parameter Combinations
When the peripheral devices are confugured in non multiplexed mode the C_PRH_MAX_AWIDTH should be the maximum of C_PRHx_AWIDTH of all peripherals in the system ie if C_NUM_PERIPHERALS is 2 then C_PRH_MAX_AWIDTH should be maximum of C_PRH0_AWIDTH and C_PRH1_AWIDTH
C_PRH_MAX_DWIDTH should be the maximum of C_PRHx_DWIDTH of all peripherals in the system ie if C_NUM_PERIPHERALS is 2 then C_PRH_MAX_DWIDTH should be maximum of C_PRH0_DWIDTH and C_PRH1_DWIDTH
If any of the peripheral devices are configured for a multiplexed address and data buses then the parameter C_PRH_MAX_ADWIDTH should be set as the maximum of the data bus and address bus of the device(s) employing a multiplexed address and data bus If all devices employ non-multiplexed address and data buses then C_PRH_MAX_ADWIDTH reflects the maximum of data bus width of all external devices Therefore for any configuration the parameter C_PRH_MAX_ADWIDTH should be greater than or equal to C_PRH_MAX_DWIDTH
The generic C_PRH_CLK_SUPPORT is relevant only when the devices are configured for the synchronous access ie C_PRHx_SYNC = 1 If more than one of the devices are synchronous then the frequency for the peripheral clock should be chosen as the minimum of the operating frequencies of those devices
The range specified by C_PRHx_BASEADDR and C_PRHx_HIGHADDR parameters must comprise a contiguous range and the size of the range must be a power of two ie size of range = 2m Furthermore the rsquomrsquo least significant bits of C_PRHx_BASEADDR must be zero The base and high address range assigned to different peripherals must be mutually exclusive No default value will be specified for C_PRHx_BASEADDR and C_PRHx_HIGHADDR in order to enforce that the user configures these parameters with the actual values If the values are not set for C_PRHx_BASEADDR and C_PRHx_HIGHADDR a compiler error will be generated
In order to access FIFO like structures within the external peripheral devices C_PRHx_FIFO_ACCESS must be set to rsquo1rsquo When FIFO access is enabled C_PRHx_FIFO_OFFSET specifies the offset of the FIFO in terms of number of byte locations from the base address (C_PRHx_BASEADDR) of the peripheral and should be set to an offset that lies within the address range assigned to the peripheral device ie C_PRHx_BASEADDR + C_PRHx_FIFO_OFFSET le C_PRHx_HIGHADDR Furthermore the FIFO offset should be within the range addressable by the address bus ie C_PRHx_FIFO_OFFSET lt 2n
where n = C_PRHx_AWIDTH
The width of the readwrite strobe must be less than the cycle time of the corresponding access ie C_PRHx_WRN_WIDTH lt C_PRHx_WR_CYCLE and C_PRHx_RDN_WIDTH lt C_PRHx_RD_CYCLE The value of device ready validity period must be less than the readwrite strobe width and the maximum pulse width of the device ready signal ie C_PRHx_RDY_TOUT lt minimum of C_PRHx_WRN_WIDTH C_PRHx_RDN_WIDTH and C_PRHx_RDY_WIDTH
Parameter - Port Dependencies
The dependencies between the OPB EPC design parameters and the IO ports are shown in Table 3 The width of the OPB EPC signals depend on some of the parameters In addition when certain features are parameterized away the related logic is removed
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ust 10 2007 wwwxilinxcom 13ecification
OPB External Peripheral Controller (EPC) v100a
14
Table 3 Parameter - Port Dependencies
Generic or Port
Name Affects Depends Description
Design Parameters
G3 C_OPB_AWIDTH P1 -The OPB address width parameter sets the width of the OPB address bus
G4 C_OPB_DWIDTHP2 P3
P7-
The OPB data width parameter affects the number of byte enables configured for the OPB data bus width of the OPB data bus and the width of the OPB slave read data bus
G6C_NUM_PERIPHERALS
P16 P24-
The number of peripherals in the system determines the number of chip select signals driven and the number of device ready inputs decoded by the OPB external peripheral controller
G7C_PRH_MAX_AWIDTH
P17- The width of the peripheral address bus is set to
the maximum of address bus width of all peripheral devices
G8C_PRH_MAX_DWIDTH
P19- The number of byte enables for the peripheral data
bus is determined by the maximum of data bus width of the peripheral devices
G9C_PRH_MAX_ADWIDTH
P25 P26 P27
-
The width of the peripheral input data bus peripheral output data bus and the peripheral output data bus 3-state control are determined by the maximum of data bus width of all peripherals and the address bus width of peripherals employing address data bus multiplexing
G10C_PRH_CLK_SUPPORT
P14- If C_PRH_CLK_SUPPORT = 0 then all external
devices operate on OPB clock The input PRH_Clk must be driven high externally
G18C_PRHx_DWIDTH_MATCH
P23-
If the device is configured for synchronous mode with data width matching enabled then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
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DS325 AugProduct Sp
G19 C_PRHx_SYNCP14 P20 P21 P22
P23
-
If the device is configured for asynchronous mode
bull With peripheral clock support the peripheral clock input (PRH_Clk) must be driven high externally
bull PRH_RNW is driven high as PRH_Rd_n and PRH_Wr_n should be used as read and write strobe
bull With data width matching enabled the OPB EPC drives PRH_Burst to its default low
If the device is configured for synchronous mode
bull The OPB EPC drives PRH_Rd_n and PRH_Wr_n outputs to their default state of high since PRH_RNW output is used as readwrite strobe
G20C_PRHx_BUS_MULTIPLEX
P18- PRH_ADS is driven low if the device does not use
multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
IO Signals
P1 OPB_ABus - G3The OPB address bus width is determined by the C_OPB_AWIDTH parameter
P2 OPB_BE - G4The number of byte enables for the OPB data bus is determined by the C_OPB_DWIDTH parameter
P3 OPB_DBus - G4The OPB data bus width is determined by the C_OPB_DWIDTH parameter
P7 Sln_DBus-
G4The width of the OPB slave read data bus is determined by the C_OPB_DWIDTH parameter
P14 PRH_Clk-
G10 G19
PRH_Clk is selected as operating clock only if the device is configured for synchronous mode with peripheral clock support ie C_PRHx_SYNC = 1 and C_PRH_CLK_SUPPORT = 1 Asynchronous interface always operates on OPB_Clk Therefore if no device is configured for synchronous mode with peripheral clock support enabled then the input PRH_Clk must be driven high
P16 PRH_CS_n-
G6The number of chip select signals driven by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P17 PRH_Addr-
G7The width of the peripheral address bus is determined by the C_PRH_MAX_AWIDTH parameter
P18 PRH_ADS-
G20PRH_ADS is driven low if the device does not use multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
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OPB External Peripheral Controller (EPC) v100a
16
OPB EPC Design Considerations
The OPB EPC is an OPB slave only device It receives read or write instructions from the processor and generates a corresponding access cycle on the peripheral interface Examples of read and write accesses are illustrated in the Timing Diagrams section The user must take the following considerations into account while designing with the OPB EPC
Device Ready Signal
The OPB EPC readwrite access cycles are executed only when the external device assert the device ready signal (PRH_Rdy) If the external peripheral device does not have a device ready signal then the PRH_Rdy input of the OPB EPC must be tied to logic high
P19 PRH_BE - G8The number of byte enables for the peripheral data bus is determined by the C_PRH_MAX_DWIDTH parameter
P20 PHR_RNW-
G19
If the device is synchronous ie C_PRHx_SYNC = 1 then PRH_RNW should be used as the readwrite control signal For asynchronous mode of operation PRH_RNW is driven high
P21 PRH_Rd_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Rd_n should be used as the read strobe For synchronous mode of operation PRH_Rd_n is driven high
P22 PRH_Wr_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Wr_n should be used as the write strobe For synchronous mode of operation PRH_Wr_n is driven high
P23 PRH_Burst-
G18 G19
If the device is synchronous with data width matching enabled ie C_PRHx_SYNC = 1 and C_PRHx_DWIDTH_MATCH = 1 then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
P24 PRH_Rdy-
G6The number of device ready inputs decoded by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P25 PRH_Data_I-
G9The peripheral input data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P26 PRH_Data_O - G9The peripheral output data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P27 PRH_Data_T - G9
The peripheral output data bus 3-state control width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
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OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
FIFO Transactions
When C_PRHx_FIFO_ACCESS = 1 the OPB EPC supports access to FIFOrsquos within the external peripheral devices When the FIFO within the external device is accessed then the peripheral address bus (PRH_Addr) must remain constant representing the FIFO address within the address range assigned to the peripheral device When data width matching is enabled and the access corresponds to the FIFO the OPB EPC does not increment the peripheral address (PRH_Addr) bus
Abnormal Terminations
If PRH_Rdy is de-asserted for more than the maximum period as specified by C_PRHx_RDY_WIDTH then the OPB EPC terminates the current access to the external device and signals an error to the OPB master by asserting Sln_errAck on the OPB Similarly when the OPB master terminates the current access (master abort on the OPB) OPB EPC terminates the access to the external device immediately In both cases the access to the external device is terminated abnormally Therefore the external device may be in an indeterminate state and the exceptions should be handled appropriately at the system level
Interrupt Handling
If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Peripheral Data Bus Mapping
The peripheral data bus (PRH_Data) uses big endian bit labelling (ie bit-0 is Most Significant Bit (MSB) and bit-31 is Least Significant Bit (LSB) for a 32-bit bus) and is sized according to the C_PRH_MAX_ADWIDTH parameter Peripherals that have smaller widths should connect to this bus starting at bit 0 (MSB) For example if three external devices are present in the system with data bus width of 8-bit 16-bit and 32-bit the 8-bit device should connect to PRH_Data[07] the 16-bit wide peripheral should connect to PRH_Data[015] and the 32-bit peripheral should connect to PRH_Data[031]
The bit and byte labeling for the big endian data types is shown in Figure 3
Discontinued IP
ust 10 2007 wwwxilinxcom 17ecification
F
OPB External Peripheral Controller (EPC) v100a
18
Figure 3 OPB EPC Big Endian Data Type
igure Top x-ref 3
2 3
n+2 n+3
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 15
Halfword
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 31
Word
Byte
MS Byte
LS BitMS Bit
0
nByte address
Byte label
Byte significance
Bit label
Bit significance
0 7
DS325_03_071406
Unsupported Features
Many peripheral devices have the device specific inputoutput ports such as status remote reset remote wakeup interrupts etc The OPB EPC does not have any provision to support these device specific inputoutput ports Therefore if the external device has any such device specific ports then these inputoutput ports may be connected directly to system general purpose input output controller or to the system interrupt controller If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Many peripheral devices support DMA capability However currently OPB EPC is an OPB slave only device and therefore does not support DMA operations from the external peripheral devices
Current version of the OPB EPC does not support burst transactions tofrom the OPB
OPB EPC Latency
The OPB EPC latency calculations are based on the OPB clock The OPB latency is defined as the number of OPB clock cycles elapsed from the time an access is initiated to the time the access is completed (Sln_xferAck is asserted) on the OPB Table 4 shows the latency calculations for asynchronous mode and Table 5 shows the latency calculations for synchronous mode of operation
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 4 Asynchronous Mode OPB EPC Latency
Transaction Type
ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation(1)
OPB Latency
50 MHz
OPB Latency 100 MHz
ReadWrite access to asynchronous device when addressdata bus is not multiplexed
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5)
9(7) 12(7)
1FIFO
Memory
5 + N(2) (T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5))
21(7) 33(7)
ReadWrite access to asynchronous device when addressdata bus is multiplexed (Register access)
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + (T_SETUP(3) + T_ADDR_HOLD(6) + 1 + CONTROL_WIDTH(4) + T_HOLD(5))
11(7) 14(7)
1 FIFO
5 + T_SETUP(3) + T_ADDR_HOLD(6) + 1 + N(2) (CONTROL_WIDTH(4) + T_HOLD(5))
20(7) 29(7)
1 Memory
4 + N(2) (T_SETUP(3) + T_ADDR_HOLD(6) + CONTROL_WIDTH(4) + T_HOLD(5) + 2)
32(7) 44(7)
Notes 1 Latency calculations assumes the device is always ready2 If C_PRHx_DWIDTH_MATCH = 1 then N = Access size on OPB (in bytes)width of peripheral data bus (in
bytes)3 T_SETUP is the setup time requirement on various control signals in terms of number of OPB clocks and is
device specific4 CONTROL_WIDTH represents the required width for readwrite signal in terms of number of OPB clocks and
is device specific 5 T_HOLD is the hold time requirement on various control signals in terms of number of OPB clocks and is
device specific6 T_ADDR_HOLD is the required hold time on the address bus (as specified by generic C_PRHx_ADDR_TH) in
terms of number of OPB clocks and is device specific 7 Calculation are made for typical values of various timing parameters with T_SETUP = 20ns T_HOLD = 10ns
T_ADDR_HOLD = 6ns and STROBE_WIDTH = 40ns
Discontinued IP
ust 10 2007 wwwxilinxcom 19ecification
OPB External Peripheral Controller (EPC) v100a
20
Table 5 Synchronous Mode OPB EPC Latency
Transaction Type ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory 9
1FIFO
Memory 8 + N(2)
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory 11
1 FIFO 10 + N(2)
1 Memory 6 + 5N(2)
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 7 peripheral clocks
1FIFO
Memory
7 OPB clocks + (6+N(2)) peripheral clocks
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 9 peripheral clocks
1 FIFO7 OPB clocks + (8+N(2)) peripheral clocks
1 Memory7 OPB clocks + (4+5N(2)) peripheral clocks
Notes 1 Latency calculations assumes the device is always ready2 N = Access size on the OPB (in bytes)width of peripheral data bus (in bytes) where access size on OPB
equals or less than C_OPB_DWIDTH expressed in terms of bytes3 Latency calculation assumes that the requirement on address setup (C_PRHx_ADDR_TSU) address hold
(C_PRHx_ADDR_TH) and ADS pulse width (C_PRHx_ADS_WIDTH) are all less than one OPB clock
OPB EPC External Peripheral ConnectionsThe OPB EPC interface to the external device is based upon the width of the OPB data bus address and data width of the peripheral subsystem number of peripherals in the system addressdata multiplex support mode of operation (synchronous or asynchronous) and if synchronous device the operating clock for the synchronous data path
Determining Address and Data Width
The address bus width of the peripheral subsystem is the maximum width of the address bus of all peripheral devices connected to the OPB EPC If all devices employ non-multiplexed address and data bus the data bus width of the peripheral subsystem is the maximum of the data bus width of all external devices If any of the devices are configured for multiplexed address and data bus then the data bus width of the peripheral subsystem should be set as the maximum of the data bus and the address bus of the device(s) employing a multiplexed address and data bus
Discontinued IP
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OPB External Peripheral Controller (EPC) v100a
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F
Endian Considerations
The peripheral address and data bus of the OPB EPC is labeled with big endian bit labeling (D0 is the MSB and D31 is the LSB for a 32-bit bus) while most peripheral devices are either endian agnostic ie they can be connected either way or little endian (D31 is the MSB and D0 is the LSB for a 32-bit bus) Caution must be exercised with the connection to the external peripheral devices to avoid incorrect data and address connections
Clock Generation
When connecting to a synchronous external device the OPB EPC may operate either on the OPB clock (OPB_Clk) or on a peripheral clock (PRH_Clk) The operating clock for the synchronous interface is based on the generic C_PRH_CLK_SUPPORT If C_PRH_CLK_SUPPORT = 1 the peripheral clock is used else the OPB clock is used The external devices connected to the OPB EPC will determine the operating frequency of the peripheral clock The minimum of the operating frequencies of various devices connected to OPB EPC should be used as the operating frequency of the peripheral clock (PRH_Clk)
Figure 4 illustrates a block diagram for generating a device specific clock source clock source using two DCMs The DCM modules are located within the FPGA but are external to the OPB EPC An external clock source is used to generate the OPB clock (OPB_Clk) to the OPB EPC The device clock source (PRH_Clk) is also generated from the same DCM (DCM0) using the CLKFX output and must be routed on the board to be fed back to the FPGA Another DCM (DCM1) is used to synchronize the device peripheral clock to the OPB EPC PRH_Clk
Figure 4 External Peripherals clocked by FPGA output with feedback
igure Top x-ref 4
DS325_04_071406
CLKFB CLK0
CLKFXCLKIN
DCM0
PRH_Clk_FB
PRH_Clk
OPB_Clk
CLKFB CLK0
CLKIN
DCM1
PRH_Clk
OPB_Clk
OPB EPCExternalDevice
CLK
FPGA
Example Peripheral Connections
Example SMSC LAN91C111 10100 non-PCI Ethernet Single Chip MAC + PHY
An example peripheral device supported by the OPB EPC is the SMSC 10100 non-PCI Ethernet Single Chip MAC + PHY LAN91C111 The OPB EPC allows OPB masters to access the device both in synchronous and asynchronous mode The device connections for synchronous and asynchronous mode of operations are outlined in the Asynchronous Mode and Synchronous Mode sections
Discontinued IP
ust 10 2007 wwwxilinxcom 21ecification
OPB External Peripheral Controller (EPC) v100a
22
F
Asynchronous Mode
Figure 5 illustrates the SMSC LAN91C111 connections to the OPB EPC in asynchronous mode with non-multiplexed address and data buses In asynchronous mode the input clock source (PRH_Clk) to the external device must be tied to VCC When the SMSC LAN91C111 is accessed through the asynchronous mode the rising edge of PRH_Rd_n and PRH_Wr_n signals are used to control the read and the write operations respectively As the device uses Asynchronous Ready (ARDY) signal to indicate its readiness in asynchronous mode This signal is connected to the PRH_Rdy input of the OPB EPC Since the address and the data buses are not multiplexed PRH_ADS will be driven low by the OPB EPC
The following parameter settings apply for the connections shown in Figure 5
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 5 SMSC LAN91C111 Connection to OPB EPC in Asynchronous Mode
igure Top x-ref 5
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]
PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
To System Interrupt Controller
VCC
LCLKResetAENnADSA[151]
nBE[30]
ARDYnRdnWR
D[310]
INTRO
WnRnVLBUSnCYCLE
nRDYRTNnDADACS
nLDEVnSARDY
SMSC LAN91C111
ExternalGlue Logic
PPC
OP
B B
us
FPGA
DS325_05_071406
ExternalReset VCC
External Glue Logic
Special attention must be given while interfacing the OPB EPC to the SMSC LAN91C111 in asynchronous mode The OPB EPC drives the PRH_BE active high while the SMSC LAN91C111 requires the input byte enable to be active low To match this requirement external glue logic is required to invert the PRH_BE signals before they are interfaced with the byte enable signals of the SMSC LAN91C111
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Synchronous Mode
Figure 6 illustrates the SMSC LAN91C111 connection to the OPB EPC in synchronous VL Bus mode with non-multiplexed address and data buses In synchronous mode the device requires an input clock source to the LCLK pin with a maximum operating frequency of 50MHz The local clock generated by the DCM for the peripheral interface must be routed to the LCLK input of SMSC LAN91C111 and PRH_Clk of OPB EPC When the device is accessed PRH_RNW is used as the control signal to indicate a readwrite access When PRH_RNW is high it indicates a read operation and when low it indicates a write operation The SMSC LAN91C111 uses nSRDY signal to indicate the device readiness This signal is connected to PRH_Rdy input of the OPB_EPC As the address and the data bus are not multiplexed PRH_ADS will be driven low
The following parameter settings apply for the connections shown in Figure 6
bull C_PRH_CLK_SUPPORT = 1
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 1
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 6 SMSC LAN91C111 Connection to OPB EPC in Synchronous Mode
igure Top x-ref 6
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
LCLKResetAENnADSA[151]nBE[30]WnRnSRDY
D[310]
nCYCLEnRDYRTN
INTRO
nRdnWR
nDADACSnLDEVARDY
nVLBUS
SMSC LAN91C111
ExternalGlue Logic
DigitalClock
Manager
PP
C
OP
B B
us
FPGA
DS325_06_071406
External Reset
VCC
GND
To System Interrupt Controller
External Glue Logic
The SMSC LAN91C111 device requires two inputs nCYCLE and nRDYRTN to control synchronous operation The definition of these signals is outside the scope of this document and can be found in the documents listed in the Reference Documents section The nCYCLE and nRDYRTN signals are generated in external glue logic nCYCLE may be generated from PRH_CS_n and is driven low for a
Discontinued IP
ust 10 2007 wwwxilinxcom 23ecification
OPB External Peripheral Controller (EPC) v100a
24
single clock cycle on a high to low transition on PRH_CS_n nRDYRTN is simply the registered value of the nSRDY signal
Design Considerations
When the OPB EPC is interfaced to the SMSC LAN91C111 with data width match enabled (C_PRHx_DWIDTH_MATCH = 1) and the internal SRAM of the peripheral is being accessed the device has to be configured in the address auto increment mode Address auto increment mode can be configured by setting AUTO INCR bit in the Bank 2 Pointer Register of SMSC LAN91C111 More information can be obtained by referring the registers of Bank 2 in SMSC LAN91C111 data sheet See the Reference Documents section
Example Cypress Semiconductorrsquos CY7C67300 EZ-Host Programmable Embedded USB HostPeripheral Controller
The Cypress Semiconductorrsquos CY7C67300 EZ-Hosttrade Programmable Embedded USB HostPeripheral Controller is another example of a peripheral device supported by the OPB EPC Since the Cypress USB controller operates in asynchronous mode the OPB EPC must be configured to support asynchronous mode operation
Asynchronous Mode
Figure 7 illustrates the CY7C67300 USB Controller connection to the OPB EPC in asynchronous mode with non-multiplexed address and data buses
The following parameter settings apply for the connection shown in Figure 7
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 4
bull C_PRH0_DWIDTH = 16
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Configuration of CY7C67300 USB Controller
The CY7C67300 USB Controller is configured as a Host Processor Interface (HPI) The boot-up sequence code for the CY7C67300 USB Controller in this particular example is present on the external Compact Flash memory device and is accessed through the OPB SYSACE interface This code is downloaded to the CY7C67300 USB Controller through the HPI interface Once this boot-up sequence is executed by the CY7C67300 USB Controller it becomes ready to operate in normal HPI mode with the external host controller (OPB EPC)
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
F
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 7 CY7C67300 USB Controller connection to OPB EPC in asynchronous mode
igure Top x-ref 7
SysACE_mpd_I[015]SysACE_mpd_O[015]SysACE_mpd_T[015]
SysACE_mpweSysACE_mpoe
SysACE_MPA[06]
SysACE_CEN
OPB SYS ACE Cntlr[150][150][150]
[60]
PRH_RstPRH_Rdy
PRH_CS_n
PRH_Data_I[015]PRH_Data_O[015]PRH_Data_T[015]
PRH_ADSPRH_RRNW
PRH_BurstPRH_Rd_nPRH_Wr_n
PRH_Addr[01]
OPB EPC
VCC
Ext
erna
l US
B P
orts
P
ort 1
A 1
B 2
AnCS
nRD
nWR
[D15D0]
[A1A0]
INT
CompactFLASH
TQFP144 SYSTEMACE
System ACE CompactFlash Controller
Ext
erna
l Glu
e Lo
gic
OPBINTC
US
B C
Y7C
6730
0
PP
C
OP
B B
us
FPGA
DS325_07_071406
Sysace_epc_data[150]
HPI interface
Sysace_epc_rd_n
Sysace_epc_wr_n
Sysace_epc_a[10]
DM1B
DP1B
DM2A
DP2A
DM1A
DP1A
External Glue Logic
In the interface diagram shown in Figure 7 the OPB EPC as well as the OPB SYSACE share the interface for data address and control lines on the board This requires external multiplex logic to be placed outside of IP cores in the FPGA The OPB EPC control signals PRH_RD_n and PRH_WR_n are muxed with the MEM_CEN and MEM_WEN signals of the OPB SYSACE When CY7C67300 USB Controller is accessed through the asynchronous mode the rising edge of sysace_epc_rd_n and sysace_epc_wr_n signals are used to control the read and the write operations respectively See the Reference Documents section for more information on OPB SYSACE
Design Constraints
Timing Constraints
Timing constraints must be placed on the system clock and the peripheral clock setting the frequency to meet the bus timing requirements An example is shown in Figure 8
Discontinued IP
ust 10 2007 wwwxilinxcom 25ecification
F
OPB External Peripheral Controller (EPC) v100a
26
Figure 8 EPC Timing Constraints
igure Top x-ref 8
Following constraint must be placed on the system clock
TIMESPEC TS_OPB_Clk = PERIOD OPB_Clk 10 ns HIGH 50
NET OPB_Clk TNM_NET = OPB_Clk
If C_PRH_CLK_SUPPORT=1 then the following constraint must be placed on the peripheral clock
TIMESPEC TS_PRH_Clk = PERIOD PRH_Clk 20 ns HIGH 50
NET PRH_Clk TNM_NET = PRH_Clk
DS325_08_071406
Design Implementation
Timing Diagrams
The timing diagrams in the figures below show various OPB transactions and the resulting access cycles on the peripheral interface Timing diagrams are not shown for all possible combinations of generics and the resulting access cycles However the timing diagrams shown are sufficient for the basic understanding of various access cycles supported by the OPB EPC
Figure 9 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 9
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
DS325_09_071206
8
4000000
004
04
Figure 10 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 10
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
04000000
20000004
8
00000000
004
04DS325_10_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 11 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 11
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000000
F
00010203
000 001 002 003
00 01 02 03DS325_11_071206
Figure 12 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 12
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
20000000
F
0000000000000000
000 001 002 003
00 01 02 03DS325_12_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 27ecification
OPB External Peripheral Controller (EPC) v100a
28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
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wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 29ecification
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
Discontinued IP
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OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
6
OPB EPC Signals
P14 PRH_Clk(1) EPC I - External peripheral clock input
P15 PRH_Rst EPC I -External peripheral reset inputActive high input signal to the core
P16PRH_CS_n[0C_NUM_PERIPHERALS-1]
EPC O 1External peripheral chip selectActive low output signal from the core
P17PRH_Addr[0C_PRH_MAX_AWIDTH-1](2) EPC O - External peripheral address bus
P18 PRH_ADS EPC O 0
External peripheral address strobe in case of multiplexed address and data busActive high output signal from the core
P19PRH_BE[0C_PRH_MAX_DWIDTH8-1]
EPC O -External peripheral byte enablesActive high output signal from the core
P20 PRH_RNW EPC O 1
External peripheral readwrite signal for synchronous access modeActive high output signal from the core
P21 PRH_Rd_n EPC O 1
External peripheral read signal for asynchronous access modeActive low output signal from the core
P22 PRH_Wr_n EPC O 1
External peripheral write signal for asynchronous access modeActive low output signal from the core
P23 PRH_Burst EPC O 0
Burst cycle indication to external peripheralActive high output signal from the core
P24PRH_Rdy[0C_NUM_PERIPHERALS-1]
EPC I -
Peripheral ready signal This signal is used by the external peripheral to extend the transactionActive high input signal to the core
P25PRH_Data_I[0C_PRH_MAX_ADWIDTH-1]
EPC I - External peripheral input data bus
P26PRH_Data_O[0C_PRH_MAX_ADWIDTH-1] EPC O - External peripheral output data bus
Table 1 OPB EPC IO Signal Description (Contd)
Port Signal Name InterfaceSignal Type
Initial Status
Description
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
P27PRH_Data_T[0C_PRH_MAX_ADWIDTH-1]
EPC O -3-state control for external peripheral output data bus
Notes 1 PRH_Clk is utilized only when C_PRH_CLK_SUPPORT = 1 and the interface to the external peripheral is
synchronous2 External peripheral devices are considered as byte addressable irrespective of the data bus width
Table 1 OPB EPC IO Signal Description (Contd)
Port Signal Name InterfaceSignal Type
Initial Status
Description
Discontinued IP
ust 10 2007 wwwxilinxcom 7ecification
OPB External Peripheral Controller (EPC) v100a
8
OPB EPC Design ParametersTo allow a user to create the OPB EPC that is uniquely tailored for the system certain features can be parameterized in the OPB EPC design Some of these parameters control the interface to the OPB while others control the interface to the peripheral devices This allows the user to have a design that only utilizes the minimum resources required by the system and operating at the best possible performance
The features that could be parameterized in the OPB EPC are shown in Table 2
Table 2 OPB EPC Design Parameters
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
OPB EPC Features
G1OPB clock period
C_OPB_CLK_PERIOD_PS
Integer number of picoseconds
10000 integer
G2 Target FPGA family C_FAMILYvirtex2 virtex2p virtex4 virtex5 spartan3
virtex2p string
G3 OPB address width C_OPB_AWIDTH 32 32 integer
G4 OPB data width C_OPB_DWIDTH 32 32 integer
OPB EPC Interface Parameters
G5 Peripheral clock periodC_PRH_CLK_PERIOD_PS(1)
Integer number of picoseconds
20000 integer
G6 Number of peripheralsC_NUM_PERIPHERALS
1-4 1 integer
G7Maximum of address bus width of all external peripherals
C_PRH_MAX_AWIDTH 3-32 32integer
G8Maximum of data bus width of all external peripherals
C_PRH_MAX_DWIDTH 8 16 or 32 32 integer
G9
Maximum of data bus width of all peripherals and address bus with of peripherals employing addressdata multiplexing
C_PRH_MAX_ADWIDTH(2) 8-32 32 integer
G10 Peripheral clock supportC_PRH_CLK_SUPPORT(1)
0 = Peripheral device interface operates at the OPB clock 1 = Peripheral device interface operates at external peripheral clock
0 integer
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G11 OPB burst supportC_PRH_BURST_SUPPORT(24)
0 = No burst support from OPB 1 = Not supported
0 integer
OPB EPC Peripheral Address Space
G12External peripheral base address
C_PRHx_BASEADDR(3) Valid address(4 5)
User must set values(6)
std_logic_vector
G13External peripheral high address
C_PRHx_HIGHADDR(3) Valid address(4 5)
User must set values(6)
std_logic_vector
OPB EPC Peripheral Interface Parameters
G14Support for access to FIFO within the external peripheral
C_PRHx_FIFO_ACCESS(3)
0 = No support for the external peripheral FIFO access1 = Access to FIFO structures within the external peripheral device is supported
0 integer
G15External peripheral FIFO offset from peripheral base address
C_PRHx_FIFO_OFFSET(3 7 8)
Any valid offset within the base and high address range assigned to the peripheral device
0 integer
G16Address bus width of peripherals
C_PRHx_AWIDTH(3) 3-32 32 integer
G17Data bus width of peripherals
C_PRHx_DWIDTH(3) 8 16 or 32 32 integer
G18
Support for data width match when the peripheral device data width is less than the OPB data width
C_PRHx_DWIDTH_MATCH(3 9)
0 = No multiple cycles on the peripheral interface for single OPB read or write cycle 1 = Run multiple cycles on the peripheral interface for single OPB read or write cycle
0 integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
ust 10 2007 wwwxilinxcom 9ecification
OPB External Peripheral Controller (EPC) v100a
10
G19 Peripheral access mode C_PRHx_SYNC(1 3)
0 = External device is asynchronous 1 = External device is synchronous
1 integer
G20 Peripheral bus typeC_PRHx_BUS_MULTIPLEX(3)
0 = External device has separate address and data bus1 = External device has multiplexed address and data bus
0 integer
OPB EPC Timing Parameters
G21
Address bus (PRH_Addr) setup with respect to rising edge of address strobe (PRH_ADS) or falling edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_ADDR_TSU(3 10)
Integer number of picoseconds
User must set values(11)
integer
G22
Address bus (PRH_Addr) hold with respect to falling edge of address strobe (PRH_ADS) or rising edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_ADDR_TH(3 12 16 19)
Integer number of picoseconds
User must set values(11)
integer
G23Minimum pulse width of address strobe (PRH_ADS)
C_PRHx_ADS_WIDTH(3)
Integer number of picoseconds
User must set values(11)
integer
G24
Chip select (PRH_CS_n) setup with respect to falling edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_CSN_TSU(3 10)
Integer number of picoseconds
User must set values(13)
integer
G25
Chip select (PRH_CS_n) hold with respect to rising edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_CSN_TH(3 16 19)
Integer number of picoseconds
User must set values(13)
integer
G26Minimum pulse width of write signal (PRH_Wr_n)
C_PRHx_WRN_WIDTH(3 14 15 16)
Integer number of picoseconds
User must set values(13)
integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G27Cycle time of write signal (PRH_Wr_n)
C_PRHx_WR_CYCLE(3 15 16)
Integer number of picoseconds
User must set values(13)
integer
G28
Data bus (PRH_Data) setup with respect to falling edge of write signal (PRH_Wr_n)
C_PRHx_DATA_TSU(3 14)
Integer number of picoseconds
User must set values(13)
integer
G29
Data bus (PRH_Data) hold with respect to rising edge of write signal (PRH_Wr_n)
C_PRHx_DATA_TH(3 16)
Integer number of picoseconds
User must set values(13)
integer
G30Minimum pulse width of read signal (PRH_Rd_n)
C_PRHx_RDN_WIDTH(3 17 18 19)
Integer number of picoseconds
User must set values(13)
integer
G31Cycle time of read signal (PRH_Rd_n)
C_PRHx_RD_CYCLE(3 18 19)
Integer number of picoseconds
User must set values(13)
integer
G32
Data bus (PRH_Data) validity from falling edge of read signal (PRH_Rd_n)
C_PRHx_DATA_TOUT(3 17)
Integer number of picoseconds
User must set values(13)
integer
G33
Data bus (PRH_Data) high impedance from rising edge of read (PRH_Rd_n)
C_PRHx_DATA_TINV(3 19)
Integer number of picoseconds
User must set values(13)
integer
G34
Device ready (PRH_Rdy) validity from the falling edge of read or write (PRH_Rd_n PRH_Wr_n)
C_PRHx_RDY_TOUT(3 20 22)
Integer number of picoseconds
User must set values(13)
integer
G35
Maximum period of device ready signal (PRH_Rdy) to wait before device timeout
C_PRHx_RDY_WIDTH(3 21 22)
Integer number of picoseconds
User must set values(23)
integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
ust 10 2007 wwwxilinxcom 11ecification
OPB External Peripheral Controller (EPC) v100a
12
Notes 1 The generic C_PRH_CLK_SUPPORT is relevant only when the device is configured for synchronous access
ie C_PRHx_SYNC = 1 If more than one device is synchronous then the frequency for the peripheral clock (PRH_Clk) should be chosen as the minimum of the operating frequencies of those devices
2 The C_PRH_MAX_ADWIDTH determines the size of the data bus For all non multiplexed devices the C_PRH_MAX_ADWIDTH reflects the maximum of data bus width of all external devices ie C_PRH_MAX_ADWIDTH equals C_PRH_MAX_DWIDTH However if any of the devices is configured for multiplexed address and data bus then C_PRH_MAX_ADWIDTH should be set as the maximum of data bus of all external devices and the address bus of device(s) employing multiplexed address and data bus
3 rsquoxrsquo in the generic refers to the number of the peripheral device and takes a value in the range of 0 to C_NUM_PERIPHERALS - 1
4 OPB EPC design can accommodate up to four peripheral devices The address range for the devices are designated as C_PRH0_BASEADDR C_PRH0_HIGHADDR C_PRH1_BASEADDR C_PRH1_HIGHADDR etc
5 The range specified by C_PRHx_BASEADDR and C_PRHx_HIGHADDR must comprise a contiguous range and the size of the range must be a power of two ie size of range = 2m Further the rsquomrsquo least significant bits of C_PRHx_BASEADDR must be zero The base and high address range assigned to different peripherals must be mutually exclusive
6 No default value will be specified to ensure that the actual value is set ie if the value is not set a compiler error will be generated
7 C_PRHx_FIFO_ACCESS must be set to 1 if the support for access to FIFO within external peripheral device is to be included
8 C_PRHx_FIFO_OFFSET is the byte offset of the external peripheral FIFO from the base address (C_PRHx_BASEADDR) of the peripheral irrespective of the data width of the peripheral device If C_PRHx_FIFO_ACCESS = 1 then C_PRHx_FIFO_OFFSET must be set to a valid offset within the address range assigned to the peripheral
9 The generic C_PRHx_DWIDTH_MATCH is relevant only when the width of the peripheral data (PRH_Data) bus is less than the OPB data bus (OPB_DBus)
10Address setup time is with respect to falling edge of address strobe (PRH_ADS) if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 and must be set both in synchronous and asynchronous mode Address setup time is with respect to falling edge of readwrite signals (PRH_Wr_nPRH_Rd_n) if the device is non multiplexed and is relevant only if the access mode is asynchronous
11Value for the parameter must be assigned if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 This parameter assignment is appicalble for synchronous and asynchronous devices
12Address hold time is with respect to falling edge of address strobe (PRH_ADS) if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 and must be set both in synchronous and asynchronous mode Address hold time is with respect to rising edge of readwrite signals (PRH_Wr_nPRH_Rd_n) if the address and the data bus are separate and is relevant only if the access mode is asynchronous
13Value must be assigned if the access mode of the peripherals is asynchronous ie C_PRHx_SYNC = 0 If the access mode of the peripheral is synchronous ie C_PRHx_SYNC = 1 then the zero should be assigned to the parameter
14Write signal (PRH_Wr_n) low time is the maximum of C_PRHx_WRN_WIDTH and C_PRHx_DATA_TSU15The value of C_PRHx_WRN_WIDTH must be smaller than C_PRHx_WR_CYCLE16 In non-multiplexed address and data bus mode write recovery time will be maximum of C_PRHx_ADDR_TH
C_PRHx_CSN_TH C_PRHx_DATA_TH and PRH_Wr_n high time (ie C_PRHx_WR_CYCLE minus C_PRHx_WRN_WIDTH) If the peripheral uses multiplexed address and data bus then the write recovery time will be maximum of C_PRHx_CSN_TH C_PRHx_DATA_TH and PRH_Wr_n high time
17Read signal (PRH_Rd_n) low time is the maximum of C_PRHx_RDN_WIDTH and C_PRHx_DATA_TOUT18The value of C_PRHx_RDN_WIDTH must be smaller than C_PRHx_RD_CYCLE19 In non-multiplexed address and data bus mode read recovery time will be maximum of C_PRHx_ADDR_TH
C_PRHx_CSN_TH C_PRHx_DATA_TINV and PRH_Rd_n high time (ie C_PRHx_RD_CYCLE minus C_PRHx_RDN_WIDTH) If the peripheral uses multiplexed address and data bus then the read recovery time will be maximum of C_PRHx_CSN_TH C_PRHx_DATA_TINV and PRH_Rd_n high time
20Device ready validity period (C_PRHx_RDY_TOUT) must be set as the maximum of the values specified for read and write transactions
21Device ready pulse width (C_PRHx_RDY_WIDTH) must be set as the maximum of the values specified for read and write transactions
22Device ready validity (C_PRHx_RDY_TOUT) period must be less than the write strobe width (C_PRHx_WRN_WIDTH) read strobe width (C_PRHx_RDN_WIDTH) and device ready signal width (C_PRHx_RDY_WIDTH)
23Device ready signal width (C_PRHx_RDY_WIDTH) must be set for both synchronous and asynchronous
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
access mode in order to prevent the device from holding the OPB indefinitely24Current version of the OPB EPC do not support the burst transactions tofrom the OPB
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Allowable Parameter Combinations
When the peripheral devices are confugured in non multiplexed mode the C_PRH_MAX_AWIDTH should be the maximum of C_PRHx_AWIDTH of all peripherals in the system ie if C_NUM_PERIPHERALS is 2 then C_PRH_MAX_AWIDTH should be maximum of C_PRH0_AWIDTH and C_PRH1_AWIDTH
C_PRH_MAX_DWIDTH should be the maximum of C_PRHx_DWIDTH of all peripherals in the system ie if C_NUM_PERIPHERALS is 2 then C_PRH_MAX_DWIDTH should be maximum of C_PRH0_DWIDTH and C_PRH1_DWIDTH
If any of the peripheral devices are configured for a multiplexed address and data buses then the parameter C_PRH_MAX_ADWIDTH should be set as the maximum of the data bus and address bus of the device(s) employing a multiplexed address and data bus If all devices employ non-multiplexed address and data buses then C_PRH_MAX_ADWIDTH reflects the maximum of data bus width of all external devices Therefore for any configuration the parameter C_PRH_MAX_ADWIDTH should be greater than or equal to C_PRH_MAX_DWIDTH
The generic C_PRH_CLK_SUPPORT is relevant only when the devices are configured for the synchronous access ie C_PRHx_SYNC = 1 If more than one of the devices are synchronous then the frequency for the peripheral clock should be chosen as the minimum of the operating frequencies of those devices
The range specified by C_PRHx_BASEADDR and C_PRHx_HIGHADDR parameters must comprise a contiguous range and the size of the range must be a power of two ie size of range = 2m Furthermore the rsquomrsquo least significant bits of C_PRHx_BASEADDR must be zero The base and high address range assigned to different peripherals must be mutually exclusive No default value will be specified for C_PRHx_BASEADDR and C_PRHx_HIGHADDR in order to enforce that the user configures these parameters with the actual values If the values are not set for C_PRHx_BASEADDR and C_PRHx_HIGHADDR a compiler error will be generated
In order to access FIFO like structures within the external peripheral devices C_PRHx_FIFO_ACCESS must be set to rsquo1rsquo When FIFO access is enabled C_PRHx_FIFO_OFFSET specifies the offset of the FIFO in terms of number of byte locations from the base address (C_PRHx_BASEADDR) of the peripheral and should be set to an offset that lies within the address range assigned to the peripheral device ie C_PRHx_BASEADDR + C_PRHx_FIFO_OFFSET le C_PRHx_HIGHADDR Furthermore the FIFO offset should be within the range addressable by the address bus ie C_PRHx_FIFO_OFFSET lt 2n
where n = C_PRHx_AWIDTH
The width of the readwrite strobe must be less than the cycle time of the corresponding access ie C_PRHx_WRN_WIDTH lt C_PRHx_WR_CYCLE and C_PRHx_RDN_WIDTH lt C_PRHx_RD_CYCLE The value of device ready validity period must be less than the readwrite strobe width and the maximum pulse width of the device ready signal ie C_PRHx_RDY_TOUT lt minimum of C_PRHx_WRN_WIDTH C_PRHx_RDN_WIDTH and C_PRHx_RDY_WIDTH
Parameter - Port Dependencies
The dependencies between the OPB EPC design parameters and the IO ports are shown in Table 3 The width of the OPB EPC signals depend on some of the parameters In addition when certain features are parameterized away the related logic is removed
Discontinued IP
ust 10 2007 wwwxilinxcom 13ecification
OPB External Peripheral Controller (EPC) v100a
14
Table 3 Parameter - Port Dependencies
Generic or Port
Name Affects Depends Description
Design Parameters
G3 C_OPB_AWIDTH P1 -The OPB address width parameter sets the width of the OPB address bus
G4 C_OPB_DWIDTHP2 P3
P7-
The OPB data width parameter affects the number of byte enables configured for the OPB data bus width of the OPB data bus and the width of the OPB slave read data bus
G6C_NUM_PERIPHERALS
P16 P24-
The number of peripherals in the system determines the number of chip select signals driven and the number of device ready inputs decoded by the OPB external peripheral controller
G7C_PRH_MAX_AWIDTH
P17- The width of the peripheral address bus is set to
the maximum of address bus width of all peripheral devices
G8C_PRH_MAX_DWIDTH
P19- The number of byte enables for the peripheral data
bus is determined by the maximum of data bus width of the peripheral devices
G9C_PRH_MAX_ADWIDTH
P25 P26 P27
-
The width of the peripheral input data bus peripheral output data bus and the peripheral output data bus 3-state control are determined by the maximum of data bus width of all peripherals and the address bus width of peripherals employing address data bus multiplexing
G10C_PRH_CLK_SUPPORT
P14- If C_PRH_CLK_SUPPORT = 0 then all external
devices operate on OPB clock The input PRH_Clk must be driven high externally
G18C_PRHx_DWIDTH_MATCH
P23-
If the device is configured for synchronous mode with data width matching enabled then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G19 C_PRHx_SYNCP14 P20 P21 P22
P23
-
If the device is configured for asynchronous mode
bull With peripheral clock support the peripheral clock input (PRH_Clk) must be driven high externally
bull PRH_RNW is driven high as PRH_Rd_n and PRH_Wr_n should be used as read and write strobe
bull With data width matching enabled the OPB EPC drives PRH_Burst to its default low
If the device is configured for synchronous mode
bull The OPB EPC drives PRH_Rd_n and PRH_Wr_n outputs to their default state of high since PRH_RNW output is used as readwrite strobe
G20C_PRHx_BUS_MULTIPLEX
P18- PRH_ADS is driven low if the device does not use
multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
IO Signals
P1 OPB_ABus - G3The OPB address bus width is determined by the C_OPB_AWIDTH parameter
P2 OPB_BE - G4The number of byte enables for the OPB data bus is determined by the C_OPB_DWIDTH parameter
P3 OPB_DBus - G4The OPB data bus width is determined by the C_OPB_DWIDTH parameter
P7 Sln_DBus-
G4The width of the OPB slave read data bus is determined by the C_OPB_DWIDTH parameter
P14 PRH_Clk-
G10 G19
PRH_Clk is selected as operating clock only if the device is configured for synchronous mode with peripheral clock support ie C_PRHx_SYNC = 1 and C_PRH_CLK_SUPPORT = 1 Asynchronous interface always operates on OPB_Clk Therefore if no device is configured for synchronous mode with peripheral clock support enabled then the input PRH_Clk must be driven high
P16 PRH_CS_n-
G6The number of chip select signals driven by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P17 PRH_Addr-
G7The width of the peripheral address bus is determined by the C_PRH_MAX_AWIDTH parameter
P18 PRH_ADS-
G20PRH_ADS is driven low if the device does not use multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
Discontinued IP
ust 10 2007 wwwxilinxcom 15ecification
OPB External Peripheral Controller (EPC) v100a
16
OPB EPC Design Considerations
The OPB EPC is an OPB slave only device It receives read or write instructions from the processor and generates a corresponding access cycle on the peripheral interface Examples of read and write accesses are illustrated in the Timing Diagrams section The user must take the following considerations into account while designing with the OPB EPC
Device Ready Signal
The OPB EPC readwrite access cycles are executed only when the external device assert the device ready signal (PRH_Rdy) If the external peripheral device does not have a device ready signal then the PRH_Rdy input of the OPB EPC must be tied to logic high
P19 PRH_BE - G8The number of byte enables for the peripheral data bus is determined by the C_PRH_MAX_DWIDTH parameter
P20 PHR_RNW-
G19
If the device is synchronous ie C_PRHx_SYNC = 1 then PRH_RNW should be used as the readwrite control signal For asynchronous mode of operation PRH_RNW is driven high
P21 PRH_Rd_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Rd_n should be used as the read strobe For synchronous mode of operation PRH_Rd_n is driven high
P22 PRH_Wr_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Wr_n should be used as the write strobe For synchronous mode of operation PRH_Wr_n is driven high
P23 PRH_Burst-
G18 G19
If the device is synchronous with data width matching enabled ie C_PRHx_SYNC = 1 and C_PRHx_DWIDTH_MATCH = 1 then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
P24 PRH_Rdy-
G6The number of device ready inputs decoded by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P25 PRH_Data_I-
G9The peripheral input data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P26 PRH_Data_O - G9The peripheral output data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P27 PRH_Data_T - G9
The peripheral output data bus 3-state control width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
FIFO Transactions
When C_PRHx_FIFO_ACCESS = 1 the OPB EPC supports access to FIFOrsquos within the external peripheral devices When the FIFO within the external device is accessed then the peripheral address bus (PRH_Addr) must remain constant representing the FIFO address within the address range assigned to the peripheral device When data width matching is enabled and the access corresponds to the FIFO the OPB EPC does not increment the peripheral address (PRH_Addr) bus
Abnormal Terminations
If PRH_Rdy is de-asserted for more than the maximum period as specified by C_PRHx_RDY_WIDTH then the OPB EPC terminates the current access to the external device and signals an error to the OPB master by asserting Sln_errAck on the OPB Similarly when the OPB master terminates the current access (master abort on the OPB) OPB EPC terminates the access to the external device immediately In both cases the access to the external device is terminated abnormally Therefore the external device may be in an indeterminate state and the exceptions should be handled appropriately at the system level
Interrupt Handling
If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Peripheral Data Bus Mapping
The peripheral data bus (PRH_Data) uses big endian bit labelling (ie bit-0 is Most Significant Bit (MSB) and bit-31 is Least Significant Bit (LSB) for a 32-bit bus) and is sized according to the C_PRH_MAX_ADWIDTH parameter Peripherals that have smaller widths should connect to this bus starting at bit 0 (MSB) For example if three external devices are present in the system with data bus width of 8-bit 16-bit and 32-bit the 8-bit device should connect to PRH_Data[07] the 16-bit wide peripheral should connect to PRH_Data[015] and the 32-bit peripheral should connect to PRH_Data[031]
The bit and byte labeling for the big endian data types is shown in Figure 3
Discontinued IP
ust 10 2007 wwwxilinxcom 17ecification
F
OPB External Peripheral Controller (EPC) v100a
18
Figure 3 OPB EPC Big Endian Data Type
igure Top x-ref 3
2 3
n+2 n+3
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 15
Halfword
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 31
Word
Byte
MS Byte
LS BitMS Bit
0
nByte address
Byte label
Byte significance
Bit label
Bit significance
0 7
DS325_03_071406
Unsupported Features
Many peripheral devices have the device specific inputoutput ports such as status remote reset remote wakeup interrupts etc The OPB EPC does not have any provision to support these device specific inputoutput ports Therefore if the external device has any such device specific ports then these inputoutput ports may be connected directly to system general purpose input output controller or to the system interrupt controller If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Many peripheral devices support DMA capability However currently OPB EPC is an OPB slave only device and therefore does not support DMA operations from the external peripheral devices
Current version of the OPB EPC does not support burst transactions tofrom the OPB
OPB EPC Latency
The OPB EPC latency calculations are based on the OPB clock The OPB latency is defined as the number of OPB clock cycles elapsed from the time an access is initiated to the time the access is completed (Sln_xferAck is asserted) on the OPB Table 4 shows the latency calculations for asynchronous mode and Table 5 shows the latency calculations for synchronous mode of operation
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 4 Asynchronous Mode OPB EPC Latency
Transaction Type
ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation(1)
OPB Latency
50 MHz
OPB Latency 100 MHz
ReadWrite access to asynchronous device when addressdata bus is not multiplexed
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5)
9(7) 12(7)
1FIFO
Memory
5 + N(2) (T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5))
21(7) 33(7)
ReadWrite access to asynchronous device when addressdata bus is multiplexed (Register access)
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + (T_SETUP(3) + T_ADDR_HOLD(6) + 1 + CONTROL_WIDTH(4) + T_HOLD(5))
11(7) 14(7)
1 FIFO
5 + T_SETUP(3) + T_ADDR_HOLD(6) + 1 + N(2) (CONTROL_WIDTH(4) + T_HOLD(5))
20(7) 29(7)
1 Memory
4 + N(2) (T_SETUP(3) + T_ADDR_HOLD(6) + CONTROL_WIDTH(4) + T_HOLD(5) + 2)
32(7) 44(7)
Notes 1 Latency calculations assumes the device is always ready2 If C_PRHx_DWIDTH_MATCH = 1 then N = Access size on OPB (in bytes)width of peripheral data bus (in
bytes)3 T_SETUP is the setup time requirement on various control signals in terms of number of OPB clocks and is
device specific4 CONTROL_WIDTH represents the required width for readwrite signal in terms of number of OPB clocks and
is device specific 5 T_HOLD is the hold time requirement on various control signals in terms of number of OPB clocks and is
device specific6 T_ADDR_HOLD is the required hold time on the address bus (as specified by generic C_PRHx_ADDR_TH) in
terms of number of OPB clocks and is device specific 7 Calculation are made for typical values of various timing parameters with T_SETUP = 20ns T_HOLD = 10ns
T_ADDR_HOLD = 6ns and STROBE_WIDTH = 40ns
Discontinued IP
ust 10 2007 wwwxilinxcom 19ecification
OPB External Peripheral Controller (EPC) v100a
20
Table 5 Synchronous Mode OPB EPC Latency
Transaction Type ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory 9
1FIFO
Memory 8 + N(2)
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory 11
1 FIFO 10 + N(2)
1 Memory 6 + 5N(2)
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 7 peripheral clocks
1FIFO
Memory
7 OPB clocks + (6+N(2)) peripheral clocks
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 9 peripheral clocks
1 FIFO7 OPB clocks + (8+N(2)) peripheral clocks
1 Memory7 OPB clocks + (4+5N(2)) peripheral clocks
Notes 1 Latency calculations assumes the device is always ready2 N = Access size on the OPB (in bytes)width of peripheral data bus (in bytes) where access size on OPB
equals or less than C_OPB_DWIDTH expressed in terms of bytes3 Latency calculation assumes that the requirement on address setup (C_PRHx_ADDR_TSU) address hold
(C_PRHx_ADDR_TH) and ADS pulse width (C_PRHx_ADS_WIDTH) are all less than one OPB clock
OPB EPC External Peripheral ConnectionsThe OPB EPC interface to the external device is based upon the width of the OPB data bus address and data width of the peripheral subsystem number of peripherals in the system addressdata multiplex support mode of operation (synchronous or asynchronous) and if synchronous device the operating clock for the synchronous data path
Determining Address and Data Width
The address bus width of the peripheral subsystem is the maximum width of the address bus of all peripheral devices connected to the OPB EPC If all devices employ non-multiplexed address and data bus the data bus width of the peripheral subsystem is the maximum of the data bus width of all external devices If any of the devices are configured for multiplexed address and data bus then the data bus width of the peripheral subsystem should be set as the maximum of the data bus and the address bus of the device(s) employing a multiplexed address and data bus
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Endian Considerations
The peripheral address and data bus of the OPB EPC is labeled with big endian bit labeling (D0 is the MSB and D31 is the LSB for a 32-bit bus) while most peripheral devices are either endian agnostic ie they can be connected either way or little endian (D31 is the MSB and D0 is the LSB for a 32-bit bus) Caution must be exercised with the connection to the external peripheral devices to avoid incorrect data and address connections
Clock Generation
When connecting to a synchronous external device the OPB EPC may operate either on the OPB clock (OPB_Clk) or on a peripheral clock (PRH_Clk) The operating clock for the synchronous interface is based on the generic C_PRH_CLK_SUPPORT If C_PRH_CLK_SUPPORT = 1 the peripheral clock is used else the OPB clock is used The external devices connected to the OPB EPC will determine the operating frequency of the peripheral clock The minimum of the operating frequencies of various devices connected to OPB EPC should be used as the operating frequency of the peripheral clock (PRH_Clk)
Figure 4 illustrates a block diagram for generating a device specific clock source clock source using two DCMs The DCM modules are located within the FPGA but are external to the OPB EPC An external clock source is used to generate the OPB clock (OPB_Clk) to the OPB EPC The device clock source (PRH_Clk) is also generated from the same DCM (DCM0) using the CLKFX output and must be routed on the board to be fed back to the FPGA Another DCM (DCM1) is used to synchronize the device peripheral clock to the OPB EPC PRH_Clk
Figure 4 External Peripherals clocked by FPGA output with feedback
igure Top x-ref 4
DS325_04_071406
CLKFB CLK0
CLKFXCLKIN
DCM0
PRH_Clk_FB
PRH_Clk
OPB_Clk
CLKFB CLK0
CLKIN
DCM1
PRH_Clk
OPB_Clk
OPB EPCExternalDevice
CLK
FPGA
Example Peripheral Connections
Example SMSC LAN91C111 10100 non-PCI Ethernet Single Chip MAC + PHY
An example peripheral device supported by the OPB EPC is the SMSC 10100 non-PCI Ethernet Single Chip MAC + PHY LAN91C111 The OPB EPC allows OPB masters to access the device both in synchronous and asynchronous mode The device connections for synchronous and asynchronous mode of operations are outlined in the Asynchronous Mode and Synchronous Mode sections
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ust 10 2007 wwwxilinxcom 21ecification
OPB External Peripheral Controller (EPC) v100a
22
F
Asynchronous Mode
Figure 5 illustrates the SMSC LAN91C111 connections to the OPB EPC in asynchronous mode with non-multiplexed address and data buses In asynchronous mode the input clock source (PRH_Clk) to the external device must be tied to VCC When the SMSC LAN91C111 is accessed through the asynchronous mode the rising edge of PRH_Rd_n and PRH_Wr_n signals are used to control the read and the write operations respectively As the device uses Asynchronous Ready (ARDY) signal to indicate its readiness in asynchronous mode This signal is connected to the PRH_Rdy input of the OPB EPC Since the address and the data buses are not multiplexed PRH_ADS will be driven low by the OPB EPC
The following parameter settings apply for the connections shown in Figure 5
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 5 SMSC LAN91C111 Connection to OPB EPC in Asynchronous Mode
igure Top x-ref 5
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]
PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
To System Interrupt Controller
VCC
LCLKResetAENnADSA[151]
nBE[30]
ARDYnRdnWR
D[310]
INTRO
WnRnVLBUSnCYCLE
nRDYRTNnDADACS
nLDEVnSARDY
SMSC LAN91C111
ExternalGlue Logic
PPC
OP
B B
us
FPGA
DS325_05_071406
ExternalReset VCC
External Glue Logic
Special attention must be given while interfacing the OPB EPC to the SMSC LAN91C111 in asynchronous mode The OPB EPC drives the PRH_BE active high while the SMSC LAN91C111 requires the input byte enable to be active low To match this requirement external glue logic is required to invert the PRH_BE signals before they are interfaced with the byte enable signals of the SMSC LAN91C111
Discontinued IP
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OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Synchronous Mode
Figure 6 illustrates the SMSC LAN91C111 connection to the OPB EPC in synchronous VL Bus mode with non-multiplexed address and data buses In synchronous mode the device requires an input clock source to the LCLK pin with a maximum operating frequency of 50MHz The local clock generated by the DCM for the peripheral interface must be routed to the LCLK input of SMSC LAN91C111 and PRH_Clk of OPB EPC When the device is accessed PRH_RNW is used as the control signal to indicate a readwrite access When PRH_RNW is high it indicates a read operation and when low it indicates a write operation The SMSC LAN91C111 uses nSRDY signal to indicate the device readiness This signal is connected to PRH_Rdy input of the OPB_EPC As the address and the data bus are not multiplexed PRH_ADS will be driven low
The following parameter settings apply for the connections shown in Figure 6
bull C_PRH_CLK_SUPPORT = 1
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 1
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 6 SMSC LAN91C111 Connection to OPB EPC in Synchronous Mode
igure Top x-ref 6
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
LCLKResetAENnADSA[151]nBE[30]WnRnSRDY
D[310]
nCYCLEnRDYRTN
INTRO
nRdnWR
nDADACSnLDEVARDY
nVLBUS
SMSC LAN91C111
ExternalGlue Logic
DigitalClock
Manager
PP
C
OP
B B
us
FPGA
DS325_06_071406
External Reset
VCC
GND
To System Interrupt Controller
External Glue Logic
The SMSC LAN91C111 device requires two inputs nCYCLE and nRDYRTN to control synchronous operation The definition of these signals is outside the scope of this document and can be found in the documents listed in the Reference Documents section The nCYCLE and nRDYRTN signals are generated in external glue logic nCYCLE may be generated from PRH_CS_n and is driven low for a
Discontinued IP
ust 10 2007 wwwxilinxcom 23ecification
OPB External Peripheral Controller (EPC) v100a
24
single clock cycle on a high to low transition on PRH_CS_n nRDYRTN is simply the registered value of the nSRDY signal
Design Considerations
When the OPB EPC is interfaced to the SMSC LAN91C111 with data width match enabled (C_PRHx_DWIDTH_MATCH = 1) and the internal SRAM of the peripheral is being accessed the device has to be configured in the address auto increment mode Address auto increment mode can be configured by setting AUTO INCR bit in the Bank 2 Pointer Register of SMSC LAN91C111 More information can be obtained by referring the registers of Bank 2 in SMSC LAN91C111 data sheet See the Reference Documents section
Example Cypress Semiconductorrsquos CY7C67300 EZ-Host Programmable Embedded USB HostPeripheral Controller
The Cypress Semiconductorrsquos CY7C67300 EZ-Hosttrade Programmable Embedded USB HostPeripheral Controller is another example of a peripheral device supported by the OPB EPC Since the Cypress USB controller operates in asynchronous mode the OPB EPC must be configured to support asynchronous mode operation
Asynchronous Mode
Figure 7 illustrates the CY7C67300 USB Controller connection to the OPB EPC in asynchronous mode with non-multiplexed address and data buses
The following parameter settings apply for the connection shown in Figure 7
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 4
bull C_PRH0_DWIDTH = 16
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Configuration of CY7C67300 USB Controller
The CY7C67300 USB Controller is configured as a Host Processor Interface (HPI) The boot-up sequence code for the CY7C67300 USB Controller in this particular example is present on the external Compact Flash memory device and is accessed through the OPB SYSACE interface This code is downloaded to the CY7C67300 USB Controller through the HPI interface Once this boot-up sequence is executed by the CY7C67300 USB Controller it becomes ready to operate in normal HPI mode with the external host controller (OPB EPC)
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
F
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 7 CY7C67300 USB Controller connection to OPB EPC in asynchronous mode
igure Top x-ref 7
SysACE_mpd_I[015]SysACE_mpd_O[015]SysACE_mpd_T[015]
SysACE_mpweSysACE_mpoe
SysACE_MPA[06]
SysACE_CEN
OPB SYS ACE Cntlr[150][150][150]
[60]
PRH_RstPRH_Rdy
PRH_CS_n
PRH_Data_I[015]PRH_Data_O[015]PRH_Data_T[015]
PRH_ADSPRH_RRNW
PRH_BurstPRH_Rd_nPRH_Wr_n
PRH_Addr[01]
OPB EPC
VCC
Ext
erna
l US
B P
orts
P
ort 1
A 1
B 2
AnCS
nRD
nWR
[D15D0]
[A1A0]
INT
CompactFLASH
TQFP144 SYSTEMACE
System ACE CompactFlash Controller
Ext
erna
l Glu
e Lo
gic
OPBINTC
US
B C
Y7C
6730
0
PP
C
OP
B B
us
FPGA
DS325_07_071406
Sysace_epc_data[150]
HPI interface
Sysace_epc_rd_n
Sysace_epc_wr_n
Sysace_epc_a[10]
DM1B
DP1B
DM2A
DP2A
DM1A
DP1A
External Glue Logic
In the interface diagram shown in Figure 7 the OPB EPC as well as the OPB SYSACE share the interface for data address and control lines on the board This requires external multiplex logic to be placed outside of IP cores in the FPGA The OPB EPC control signals PRH_RD_n and PRH_WR_n are muxed with the MEM_CEN and MEM_WEN signals of the OPB SYSACE When CY7C67300 USB Controller is accessed through the asynchronous mode the rising edge of sysace_epc_rd_n and sysace_epc_wr_n signals are used to control the read and the write operations respectively See the Reference Documents section for more information on OPB SYSACE
Design Constraints
Timing Constraints
Timing constraints must be placed on the system clock and the peripheral clock setting the frequency to meet the bus timing requirements An example is shown in Figure 8
Discontinued IP
ust 10 2007 wwwxilinxcom 25ecification
F
OPB External Peripheral Controller (EPC) v100a
26
Figure 8 EPC Timing Constraints
igure Top x-ref 8
Following constraint must be placed on the system clock
TIMESPEC TS_OPB_Clk = PERIOD OPB_Clk 10 ns HIGH 50
NET OPB_Clk TNM_NET = OPB_Clk
If C_PRH_CLK_SUPPORT=1 then the following constraint must be placed on the peripheral clock
TIMESPEC TS_PRH_Clk = PERIOD PRH_Clk 20 ns HIGH 50
NET PRH_Clk TNM_NET = PRH_Clk
DS325_08_071406
Design Implementation
Timing Diagrams
The timing diagrams in the figures below show various OPB transactions and the resulting access cycles on the peripheral interface Timing diagrams are not shown for all possible combinations of generics and the resulting access cycles However the timing diagrams shown are sufficient for the basic understanding of various access cycles supported by the OPB EPC
Figure 9 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 9
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
DS325_09_071206
8
4000000
004
04
Figure 10 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 10
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
04000000
20000004
8
00000000
004
04DS325_10_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 11 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 11
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000000
F
00010203
000 001 002 003
00 01 02 03DS325_11_071206
Figure 12 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 12
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
20000000
F
0000000000000000
000 001 002 003
00 01 02 03DS325_12_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 27ecification
OPB External Peripheral Controller (EPC) v100a
28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 29ecification
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
P27PRH_Data_T[0C_PRH_MAX_ADWIDTH-1]
EPC O -3-state control for external peripheral output data bus
Notes 1 PRH_Clk is utilized only when C_PRH_CLK_SUPPORT = 1 and the interface to the external peripheral is
synchronous2 External peripheral devices are considered as byte addressable irrespective of the data bus width
Table 1 OPB EPC IO Signal Description (Contd)
Port Signal Name InterfaceSignal Type
Initial Status
Description
Discontinued IP
ust 10 2007 wwwxilinxcom 7ecification
OPB External Peripheral Controller (EPC) v100a
8
OPB EPC Design ParametersTo allow a user to create the OPB EPC that is uniquely tailored for the system certain features can be parameterized in the OPB EPC design Some of these parameters control the interface to the OPB while others control the interface to the peripheral devices This allows the user to have a design that only utilizes the minimum resources required by the system and operating at the best possible performance
The features that could be parameterized in the OPB EPC are shown in Table 2
Table 2 OPB EPC Design Parameters
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
OPB EPC Features
G1OPB clock period
C_OPB_CLK_PERIOD_PS
Integer number of picoseconds
10000 integer
G2 Target FPGA family C_FAMILYvirtex2 virtex2p virtex4 virtex5 spartan3
virtex2p string
G3 OPB address width C_OPB_AWIDTH 32 32 integer
G4 OPB data width C_OPB_DWIDTH 32 32 integer
OPB EPC Interface Parameters
G5 Peripheral clock periodC_PRH_CLK_PERIOD_PS(1)
Integer number of picoseconds
20000 integer
G6 Number of peripheralsC_NUM_PERIPHERALS
1-4 1 integer
G7Maximum of address bus width of all external peripherals
C_PRH_MAX_AWIDTH 3-32 32integer
G8Maximum of data bus width of all external peripherals
C_PRH_MAX_DWIDTH 8 16 or 32 32 integer
G9
Maximum of data bus width of all peripherals and address bus with of peripherals employing addressdata multiplexing
C_PRH_MAX_ADWIDTH(2) 8-32 32 integer
G10 Peripheral clock supportC_PRH_CLK_SUPPORT(1)
0 = Peripheral device interface operates at the OPB clock 1 = Peripheral device interface operates at external peripheral clock
0 integer
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G11 OPB burst supportC_PRH_BURST_SUPPORT(24)
0 = No burst support from OPB 1 = Not supported
0 integer
OPB EPC Peripheral Address Space
G12External peripheral base address
C_PRHx_BASEADDR(3) Valid address(4 5)
User must set values(6)
std_logic_vector
G13External peripheral high address
C_PRHx_HIGHADDR(3) Valid address(4 5)
User must set values(6)
std_logic_vector
OPB EPC Peripheral Interface Parameters
G14Support for access to FIFO within the external peripheral
C_PRHx_FIFO_ACCESS(3)
0 = No support for the external peripheral FIFO access1 = Access to FIFO structures within the external peripheral device is supported
0 integer
G15External peripheral FIFO offset from peripheral base address
C_PRHx_FIFO_OFFSET(3 7 8)
Any valid offset within the base and high address range assigned to the peripheral device
0 integer
G16Address bus width of peripherals
C_PRHx_AWIDTH(3) 3-32 32 integer
G17Data bus width of peripherals
C_PRHx_DWIDTH(3) 8 16 or 32 32 integer
G18
Support for data width match when the peripheral device data width is less than the OPB data width
C_PRHx_DWIDTH_MATCH(3 9)
0 = No multiple cycles on the peripheral interface for single OPB read or write cycle 1 = Run multiple cycles on the peripheral interface for single OPB read or write cycle
0 integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
ust 10 2007 wwwxilinxcom 9ecification
OPB External Peripheral Controller (EPC) v100a
10
G19 Peripheral access mode C_PRHx_SYNC(1 3)
0 = External device is asynchronous 1 = External device is synchronous
1 integer
G20 Peripheral bus typeC_PRHx_BUS_MULTIPLEX(3)
0 = External device has separate address and data bus1 = External device has multiplexed address and data bus
0 integer
OPB EPC Timing Parameters
G21
Address bus (PRH_Addr) setup with respect to rising edge of address strobe (PRH_ADS) or falling edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_ADDR_TSU(3 10)
Integer number of picoseconds
User must set values(11)
integer
G22
Address bus (PRH_Addr) hold with respect to falling edge of address strobe (PRH_ADS) or rising edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_ADDR_TH(3 12 16 19)
Integer number of picoseconds
User must set values(11)
integer
G23Minimum pulse width of address strobe (PRH_ADS)
C_PRHx_ADS_WIDTH(3)
Integer number of picoseconds
User must set values(11)
integer
G24
Chip select (PRH_CS_n) setup with respect to falling edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_CSN_TSU(3 10)
Integer number of picoseconds
User must set values(13)
integer
G25
Chip select (PRH_CS_n) hold with respect to rising edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_CSN_TH(3 16 19)
Integer number of picoseconds
User must set values(13)
integer
G26Minimum pulse width of write signal (PRH_Wr_n)
C_PRHx_WRN_WIDTH(3 14 15 16)
Integer number of picoseconds
User must set values(13)
integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G27Cycle time of write signal (PRH_Wr_n)
C_PRHx_WR_CYCLE(3 15 16)
Integer number of picoseconds
User must set values(13)
integer
G28
Data bus (PRH_Data) setup with respect to falling edge of write signal (PRH_Wr_n)
C_PRHx_DATA_TSU(3 14)
Integer number of picoseconds
User must set values(13)
integer
G29
Data bus (PRH_Data) hold with respect to rising edge of write signal (PRH_Wr_n)
C_PRHx_DATA_TH(3 16)
Integer number of picoseconds
User must set values(13)
integer
G30Minimum pulse width of read signal (PRH_Rd_n)
C_PRHx_RDN_WIDTH(3 17 18 19)
Integer number of picoseconds
User must set values(13)
integer
G31Cycle time of read signal (PRH_Rd_n)
C_PRHx_RD_CYCLE(3 18 19)
Integer number of picoseconds
User must set values(13)
integer
G32
Data bus (PRH_Data) validity from falling edge of read signal (PRH_Rd_n)
C_PRHx_DATA_TOUT(3 17)
Integer number of picoseconds
User must set values(13)
integer
G33
Data bus (PRH_Data) high impedance from rising edge of read (PRH_Rd_n)
C_PRHx_DATA_TINV(3 19)
Integer number of picoseconds
User must set values(13)
integer
G34
Device ready (PRH_Rdy) validity from the falling edge of read or write (PRH_Rd_n PRH_Wr_n)
C_PRHx_RDY_TOUT(3 20 22)
Integer number of picoseconds
User must set values(13)
integer
G35
Maximum period of device ready signal (PRH_Rdy) to wait before device timeout
C_PRHx_RDY_WIDTH(3 21 22)
Integer number of picoseconds
User must set values(23)
integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
ust 10 2007 wwwxilinxcom 11ecification
OPB External Peripheral Controller (EPC) v100a
12
Notes 1 The generic C_PRH_CLK_SUPPORT is relevant only when the device is configured for synchronous access
ie C_PRHx_SYNC = 1 If more than one device is synchronous then the frequency for the peripheral clock (PRH_Clk) should be chosen as the minimum of the operating frequencies of those devices
2 The C_PRH_MAX_ADWIDTH determines the size of the data bus For all non multiplexed devices the C_PRH_MAX_ADWIDTH reflects the maximum of data bus width of all external devices ie C_PRH_MAX_ADWIDTH equals C_PRH_MAX_DWIDTH However if any of the devices is configured for multiplexed address and data bus then C_PRH_MAX_ADWIDTH should be set as the maximum of data bus of all external devices and the address bus of device(s) employing multiplexed address and data bus
3 rsquoxrsquo in the generic refers to the number of the peripheral device and takes a value in the range of 0 to C_NUM_PERIPHERALS - 1
4 OPB EPC design can accommodate up to four peripheral devices The address range for the devices are designated as C_PRH0_BASEADDR C_PRH0_HIGHADDR C_PRH1_BASEADDR C_PRH1_HIGHADDR etc
5 The range specified by C_PRHx_BASEADDR and C_PRHx_HIGHADDR must comprise a contiguous range and the size of the range must be a power of two ie size of range = 2m Further the rsquomrsquo least significant bits of C_PRHx_BASEADDR must be zero The base and high address range assigned to different peripherals must be mutually exclusive
6 No default value will be specified to ensure that the actual value is set ie if the value is not set a compiler error will be generated
7 C_PRHx_FIFO_ACCESS must be set to 1 if the support for access to FIFO within external peripheral device is to be included
8 C_PRHx_FIFO_OFFSET is the byte offset of the external peripheral FIFO from the base address (C_PRHx_BASEADDR) of the peripheral irrespective of the data width of the peripheral device If C_PRHx_FIFO_ACCESS = 1 then C_PRHx_FIFO_OFFSET must be set to a valid offset within the address range assigned to the peripheral
9 The generic C_PRHx_DWIDTH_MATCH is relevant only when the width of the peripheral data (PRH_Data) bus is less than the OPB data bus (OPB_DBus)
10Address setup time is with respect to falling edge of address strobe (PRH_ADS) if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 and must be set both in synchronous and asynchronous mode Address setup time is with respect to falling edge of readwrite signals (PRH_Wr_nPRH_Rd_n) if the device is non multiplexed and is relevant only if the access mode is asynchronous
11Value for the parameter must be assigned if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 This parameter assignment is appicalble for synchronous and asynchronous devices
12Address hold time is with respect to falling edge of address strobe (PRH_ADS) if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 and must be set both in synchronous and asynchronous mode Address hold time is with respect to rising edge of readwrite signals (PRH_Wr_nPRH_Rd_n) if the address and the data bus are separate and is relevant only if the access mode is asynchronous
13Value must be assigned if the access mode of the peripherals is asynchronous ie C_PRHx_SYNC = 0 If the access mode of the peripheral is synchronous ie C_PRHx_SYNC = 1 then the zero should be assigned to the parameter
14Write signal (PRH_Wr_n) low time is the maximum of C_PRHx_WRN_WIDTH and C_PRHx_DATA_TSU15The value of C_PRHx_WRN_WIDTH must be smaller than C_PRHx_WR_CYCLE16 In non-multiplexed address and data bus mode write recovery time will be maximum of C_PRHx_ADDR_TH
C_PRHx_CSN_TH C_PRHx_DATA_TH and PRH_Wr_n high time (ie C_PRHx_WR_CYCLE minus C_PRHx_WRN_WIDTH) If the peripheral uses multiplexed address and data bus then the write recovery time will be maximum of C_PRHx_CSN_TH C_PRHx_DATA_TH and PRH_Wr_n high time
17Read signal (PRH_Rd_n) low time is the maximum of C_PRHx_RDN_WIDTH and C_PRHx_DATA_TOUT18The value of C_PRHx_RDN_WIDTH must be smaller than C_PRHx_RD_CYCLE19 In non-multiplexed address and data bus mode read recovery time will be maximum of C_PRHx_ADDR_TH
C_PRHx_CSN_TH C_PRHx_DATA_TINV and PRH_Rd_n high time (ie C_PRHx_RD_CYCLE minus C_PRHx_RDN_WIDTH) If the peripheral uses multiplexed address and data bus then the read recovery time will be maximum of C_PRHx_CSN_TH C_PRHx_DATA_TINV and PRH_Rd_n high time
20Device ready validity period (C_PRHx_RDY_TOUT) must be set as the maximum of the values specified for read and write transactions
21Device ready pulse width (C_PRHx_RDY_WIDTH) must be set as the maximum of the values specified for read and write transactions
22Device ready validity (C_PRHx_RDY_TOUT) period must be less than the write strobe width (C_PRHx_WRN_WIDTH) read strobe width (C_PRHx_RDN_WIDTH) and device ready signal width (C_PRHx_RDY_WIDTH)
23Device ready signal width (C_PRHx_RDY_WIDTH) must be set for both synchronous and asynchronous
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
access mode in order to prevent the device from holding the OPB indefinitely24Current version of the OPB EPC do not support the burst transactions tofrom the OPB
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Allowable Parameter Combinations
When the peripheral devices are confugured in non multiplexed mode the C_PRH_MAX_AWIDTH should be the maximum of C_PRHx_AWIDTH of all peripherals in the system ie if C_NUM_PERIPHERALS is 2 then C_PRH_MAX_AWIDTH should be maximum of C_PRH0_AWIDTH and C_PRH1_AWIDTH
C_PRH_MAX_DWIDTH should be the maximum of C_PRHx_DWIDTH of all peripherals in the system ie if C_NUM_PERIPHERALS is 2 then C_PRH_MAX_DWIDTH should be maximum of C_PRH0_DWIDTH and C_PRH1_DWIDTH
If any of the peripheral devices are configured for a multiplexed address and data buses then the parameter C_PRH_MAX_ADWIDTH should be set as the maximum of the data bus and address bus of the device(s) employing a multiplexed address and data bus If all devices employ non-multiplexed address and data buses then C_PRH_MAX_ADWIDTH reflects the maximum of data bus width of all external devices Therefore for any configuration the parameter C_PRH_MAX_ADWIDTH should be greater than or equal to C_PRH_MAX_DWIDTH
The generic C_PRH_CLK_SUPPORT is relevant only when the devices are configured for the synchronous access ie C_PRHx_SYNC = 1 If more than one of the devices are synchronous then the frequency for the peripheral clock should be chosen as the minimum of the operating frequencies of those devices
The range specified by C_PRHx_BASEADDR and C_PRHx_HIGHADDR parameters must comprise a contiguous range and the size of the range must be a power of two ie size of range = 2m Furthermore the rsquomrsquo least significant bits of C_PRHx_BASEADDR must be zero The base and high address range assigned to different peripherals must be mutually exclusive No default value will be specified for C_PRHx_BASEADDR and C_PRHx_HIGHADDR in order to enforce that the user configures these parameters with the actual values If the values are not set for C_PRHx_BASEADDR and C_PRHx_HIGHADDR a compiler error will be generated
In order to access FIFO like structures within the external peripheral devices C_PRHx_FIFO_ACCESS must be set to rsquo1rsquo When FIFO access is enabled C_PRHx_FIFO_OFFSET specifies the offset of the FIFO in terms of number of byte locations from the base address (C_PRHx_BASEADDR) of the peripheral and should be set to an offset that lies within the address range assigned to the peripheral device ie C_PRHx_BASEADDR + C_PRHx_FIFO_OFFSET le C_PRHx_HIGHADDR Furthermore the FIFO offset should be within the range addressable by the address bus ie C_PRHx_FIFO_OFFSET lt 2n
where n = C_PRHx_AWIDTH
The width of the readwrite strobe must be less than the cycle time of the corresponding access ie C_PRHx_WRN_WIDTH lt C_PRHx_WR_CYCLE and C_PRHx_RDN_WIDTH lt C_PRHx_RD_CYCLE The value of device ready validity period must be less than the readwrite strobe width and the maximum pulse width of the device ready signal ie C_PRHx_RDY_TOUT lt minimum of C_PRHx_WRN_WIDTH C_PRHx_RDN_WIDTH and C_PRHx_RDY_WIDTH
Parameter - Port Dependencies
The dependencies between the OPB EPC design parameters and the IO ports are shown in Table 3 The width of the OPB EPC signals depend on some of the parameters In addition when certain features are parameterized away the related logic is removed
Discontinued IP
ust 10 2007 wwwxilinxcom 13ecification
OPB External Peripheral Controller (EPC) v100a
14
Table 3 Parameter - Port Dependencies
Generic or Port
Name Affects Depends Description
Design Parameters
G3 C_OPB_AWIDTH P1 -The OPB address width parameter sets the width of the OPB address bus
G4 C_OPB_DWIDTHP2 P3
P7-
The OPB data width parameter affects the number of byte enables configured for the OPB data bus width of the OPB data bus and the width of the OPB slave read data bus
G6C_NUM_PERIPHERALS
P16 P24-
The number of peripherals in the system determines the number of chip select signals driven and the number of device ready inputs decoded by the OPB external peripheral controller
G7C_PRH_MAX_AWIDTH
P17- The width of the peripheral address bus is set to
the maximum of address bus width of all peripheral devices
G8C_PRH_MAX_DWIDTH
P19- The number of byte enables for the peripheral data
bus is determined by the maximum of data bus width of the peripheral devices
G9C_PRH_MAX_ADWIDTH
P25 P26 P27
-
The width of the peripheral input data bus peripheral output data bus and the peripheral output data bus 3-state control are determined by the maximum of data bus width of all peripherals and the address bus width of peripherals employing address data bus multiplexing
G10C_PRH_CLK_SUPPORT
P14- If C_PRH_CLK_SUPPORT = 0 then all external
devices operate on OPB clock The input PRH_Clk must be driven high externally
G18C_PRHx_DWIDTH_MATCH
P23-
If the device is configured for synchronous mode with data width matching enabled then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G19 C_PRHx_SYNCP14 P20 P21 P22
P23
-
If the device is configured for asynchronous mode
bull With peripheral clock support the peripheral clock input (PRH_Clk) must be driven high externally
bull PRH_RNW is driven high as PRH_Rd_n and PRH_Wr_n should be used as read and write strobe
bull With data width matching enabled the OPB EPC drives PRH_Burst to its default low
If the device is configured for synchronous mode
bull The OPB EPC drives PRH_Rd_n and PRH_Wr_n outputs to their default state of high since PRH_RNW output is used as readwrite strobe
G20C_PRHx_BUS_MULTIPLEX
P18- PRH_ADS is driven low if the device does not use
multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
IO Signals
P1 OPB_ABus - G3The OPB address bus width is determined by the C_OPB_AWIDTH parameter
P2 OPB_BE - G4The number of byte enables for the OPB data bus is determined by the C_OPB_DWIDTH parameter
P3 OPB_DBus - G4The OPB data bus width is determined by the C_OPB_DWIDTH parameter
P7 Sln_DBus-
G4The width of the OPB slave read data bus is determined by the C_OPB_DWIDTH parameter
P14 PRH_Clk-
G10 G19
PRH_Clk is selected as operating clock only if the device is configured for synchronous mode with peripheral clock support ie C_PRHx_SYNC = 1 and C_PRH_CLK_SUPPORT = 1 Asynchronous interface always operates on OPB_Clk Therefore if no device is configured for synchronous mode with peripheral clock support enabled then the input PRH_Clk must be driven high
P16 PRH_CS_n-
G6The number of chip select signals driven by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P17 PRH_Addr-
G7The width of the peripheral address bus is determined by the C_PRH_MAX_AWIDTH parameter
P18 PRH_ADS-
G20PRH_ADS is driven low if the device does not use multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
Discontinued IP
ust 10 2007 wwwxilinxcom 15ecification
OPB External Peripheral Controller (EPC) v100a
16
OPB EPC Design Considerations
The OPB EPC is an OPB slave only device It receives read or write instructions from the processor and generates a corresponding access cycle on the peripheral interface Examples of read and write accesses are illustrated in the Timing Diagrams section The user must take the following considerations into account while designing with the OPB EPC
Device Ready Signal
The OPB EPC readwrite access cycles are executed only when the external device assert the device ready signal (PRH_Rdy) If the external peripheral device does not have a device ready signal then the PRH_Rdy input of the OPB EPC must be tied to logic high
P19 PRH_BE - G8The number of byte enables for the peripheral data bus is determined by the C_PRH_MAX_DWIDTH parameter
P20 PHR_RNW-
G19
If the device is synchronous ie C_PRHx_SYNC = 1 then PRH_RNW should be used as the readwrite control signal For asynchronous mode of operation PRH_RNW is driven high
P21 PRH_Rd_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Rd_n should be used as the read strobe For synchronous mode of operation PRH_Rd_n is driven high
P22 PRH_Wr_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Wr_n should be used as the write strobe For synchronous mode of operation PRH_Wr_n is driven high
P23 PRH_Burst-
G18 G19
If the device is synchronous with data width matching enabled ie C_PRHx_SYNC = 1 and C_PRHx_DWIDTH_MATCH = 1 then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
P24 PRH_Rdy-
G6The number of device ready inputs decoded by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P25 PRH_Data_I-
G9The peripheral input data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P26 PRH_Data_O - G9The peripheral output data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P27 PRH_Data_T - G9
The peripheral output data bus 3-state control width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
FIFO Transactions
When C_PRHx_FIFO_ACCESS = 1 the OPB EPC supports access to FIFOrsquos within the external peripheral devices When the FIFO within the external device is accessed then the peripheral address bus (PRH_Addr) must remain constant representing the FIFO address within the address range assigned to the peripheral device When data width matching is enabled and the access corresponds to the FIFO the OPB EPC does not increment the peripheral address (PRH_Addr) bus
Abnormal Terminations
If PRH_Rdy is de-asserted for more than the maximum period as specified by C_PRHx_RDY_WIDTH then the OPB EPC terminates the current access to the external device and signals an error to the OPB master by asserting Sln_errAck on the OPB Similarly when the OPB master terminates the current access (master abort on the OPB) OPB EPC terminates the access to the external device immediately In both cases the access to the external device is terminated abnormally Therefore the external device may be in an indeterminate state and the exceptions should be handled appropriately at the system level
Interrupt Handling
If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Peripheral Data Bus Mapping
The peripheral data bus (PRH_Data) uses big endian bit labelling (ie bit-0 is Most Significant Bit (MSB) and bit-31 is Least Significant Bit (LSB) for a 32-bit bus) and is sized according to the C_PRH_MAX_ADWIDTH parameter Peripherals that have smaller widths should connect to this bus starting at bit 0 (MSB) For example if three external devices are present in the system with data bus width of 8-bit 16-bit and 32-bit the 8-bit device should connect to PRH_Data[07] the 16-bit wide peripheral should connect to PRH_Data[015] and the 32-bit peripheral should connect to PRH_Data[031]
The bit and byte labeling for the big endian data types is shown in Figure 3
Discontinued IP
ust 10 2007 wwwxilinxcom 17ecification
F
OPB External Peripheral Controller (EPC) v100a
18
Figure 3 OPB EPC Big Endian Data Type
igure Top x-ref 3
2 3
n+2 n+3
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 15
Halfword
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 31
Word
Byte
MS Byte
LS BitMS Bit
0
nByte address
Byte label
Byte significance
Bit label
Bit significance
0 7
DS325_03_071406
Unsupported Features
Many peripheral devices have the device specific inputoutput ports such as status remote reset remote wakeup interrupts etc The OPB EPC does not have any provision to support these device specific inputoutput ports Therefore if the external device has any such device specific ports then these inputoutput ports may be connected directly to system general purpose input output controller or to the system interrupt controller If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Many peripheral devices support DMA capability However currently OPB EPC is an OPB slave only device and therefore does not support DMA operations from the external peripheral devices
Current version of the OPB EPC does not support burst transactions tofrom the OPB
OPB EPC Latency
The OPB EPC latency calculations are based on the OPB clock The OPB latency is defined as the number of OPB clock cycles elapsed from the time an access is initiated to the time the access is completed (Sln_xferAck is asserted) on the OPB Table 4 shows the latency calculations for asynchronous mode and Table 5 shows the latency calculations for synchronous mode of operation
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 4 Asynchronous Mode OPB EPC Latency
Transaction Type
ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation(1)
OPB Latency
50 MHz
OPB Latency 100 MHz
ReadWrite access to asynchronous device when addressdata bus is not multiplexed
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5)
9(7) 12(7)
1FIFO
Memory
5 + N(2) (T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5))
21(7) 33(7)
ReadWrite access to asynchronous device when addressdata bus is multiplexed (Register access)
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + (T_SETUP(3) + T_ADDR_HOLD(6) + 1 + CONTROL_WIDTH(4) + T_HOLD(5))
11(7) 14(7)
1 FIFO
5 + T_SETUP(3) + T_ADDR_HOLD(6) + 1 + N(2) (CONTROL_WIDTH(4) + T_HOLD(5))
20(7) 29(7)
1 Memory
4 + N(2) (T_SETUP(3) + T_ADDR_HOLD(6) + CONTROL_WIDTH(4) + T_HOLD(5) + 2)
32(7) 44(7)
Notes 1 Latency calculations assumes the device is always ready2 If C_PRHx_DWIDTH_MATCH = 1 then N = Access size on OPB (in bytes)width of peripheral data bus (in
bytes)3 T_SETUP is the setup time requirement on various control signals in terms of number of OPB clocks and is
device specific4 CONTROL_WIDTH represents the required width for readwrite signal in terms of number of OPB clocks and
is device specific 5 T_HOLD is the hold time requirement on various control signals in terms of number of OPB clocks and is
device specific6 T_ADDR_HOLD is the required hold time on the address bus (as specified by generic C_PRHx_ADDR_TH) in
terms of number of OPB clocks and is device specific 7 Calculation are made for typical values of various timing parameters with T_SETUP = 20ns T_HOLD = 10ns
T_ADDR_HOLD = 6ns and STROBE_WIDTH = 40ns
Discontinued IP
ust 10 2007 wwwxilinxcom 19ecification
OPB External Peripheral Controller (EPC) v100a
20
Table 5 Synchronous Mode OPB EPC Latency
Transaction Type ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory 9
1FIFO
Memory 8 + N(2)
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory 11
1 FIFO 10 + N(2)
1 Memory 6 + 5N(2)
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 7 peripheral clocks
1FIFO
Memory
7 OPB clocks + (6+N(2)) peripheral clocks
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 9 peripheral clocks
1 FIFO7 OPB clocks + (8+N(2)) peripheral clocks
1 Memory7 OPB clocks + (4+5N(2)) peripheral clocks
Notes 1 Latency calculations assumes the device is always ready2 N = Access size on the OPB (in bytes)width of peripheral data bus (in bytes) where access size on OPB
equals or less than C_OPB_DWIDTH expressed in terms of bytes3 Latency calculation assumes that the requirement on address setup (C_PRHx_ADDR_TSU) address hold
(C_PRHx_ADDR_TH) and ADS pulse width (C_PRHx_ADS_WIDTH) are all less than one OPB clock
OPB EPC External Peripheral ConnectionsThe OPB EPC interface to the external device is based upon the width of the OPB data bus address and data width of the peripheral subsystem number of peripherals in the system addressdata multiplex support mode of operation (synchronous or asynchronous) and if synchronous device the operating clock for the synchronous data path
Determining Address and Data Width
The address bus width of the peripheral subsystem is the maximum width of the address bus of all peripheral devices connected to the OPB EPC If all devices employ non-multiplexed address and data bus the data bus width of the peripheral subsystem is the maximum of the data bus width of all external devices If any of the devices are configured for multiplexed address and data bus then the data bus width of the peripheral subsystem should be set as the maximum of the data bus and the address bus of the device(s) employing a multiplexed address and data bus
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Endian Considerations
The peripheral address and data bus of the OPB EPC is labeled with big endian bit labeling (D0 is the MSB and D31 is the LSB for a 32-bit bus) while most peripheral devices are either endian agnostic ie they can be connected either way or little endian (D31 is the MSB and D0 is the LSB for a 32-bit bus) Caution must be exercised with the connection to the external peripheral devices to avoid incorrect data and address connections
Clock Generation
When connecting to a synchronous external device the OPB EPC may operate either on the OPB clock (OPB_Clk) or on a peripheral clock (PRH_Clk) The operating clock for the synchronous interface is based on the generic C_PRH_CLK_SUPPORT If C_PRH_CLK_SUPPORT = 1 the peripheral clock is used else the OPB clock is used The external devices connected to the OPB EPC will determine the operating frequency of the peripheral clock The minimum of the operating frequencies of various devices connected to OPB EPC should be used as the operating frequency of the peripheral clock (PRH_Clk)
Figure 4 illustrates a block diagram for generating a device specific clock source clock source using two DCMs The DCM modules are located within the FPGA but are external to the OPB EPC An external clock source is used to generate the OPB clock (OPB_Clk) to the OPB EPC The device clock source (PRH_Clk) is also generated from the same DCM (DCM0) using the CLKFX output and must be routed on the board to be fed back to the FPGA Another DCM (DCM1) is used to synchronize the device peripheral clock to the OPB EPC PRH_Clk
Figure 4 External Peripherals clocked by FPGA output with feedback
igure Top x-ref 4
DS325_04_071406
CLKFB CLK0
CLKFXCLKIN
DCM0
PRH_Clk_FB
PRH_Clk
OPB_Clk
CLKFB CLK0
CLKIN
DCM1
PRH_Clk
OPB_Clk
OPB EPCExternalDevice
CLK
FPGA
Example Peripheral Connections
Example SMSC LAN91C111 10100 non-PCI Ethernet Single Chip MAC + PHY
An example peripheral device supported by the OPB EPC is the SMSC 10100 non-PCI Ethernet Single Chip MAC + PHY LAN91C111 The OPB EPC allows OPB masters to access the device both in synchronous and asynchronous mode The device connections for synchronous and asynchronous mode of operations are outlined in the Asynchronous Mode and Synchronous Mode sections
Discontinued IP
ust 10 2007 wwwxilinxcom 21ecification
OPB External Peripheral Controller (EPC) v100a
22
F
Asynchronous Mode
Figure 5 illustrates the SMSC LAN91C111 connections to the OPB EPC in asynchronous mode with non-multiplexed address and data buses In asynchronous mode the input clock source (PRH_Clk) to the external device must be tied to VCC When the SMSC LAN91C111 is accessed through the asynchronous mode the rising edge of PRH_Rd_n and PRH_Wr_n signals are used to control the read and the write operations respectively As the device uses Asynchronous Ready (ARDY) signal to indicate its readiness in asynchronous mode This signal is connected to the PRH_Rdy input of the OPB EPC Since the address and the data buses are not multiplexed PRH_ADS will be driven low by the OPB EPC
The following parameter settings apply for the connections shown in Figure 5
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 5 SMSC LAN91C111 Connection to OPB EPC in Asynchronous Mode
igure Top x-ref 5
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]
PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
To System Interrupt Controller
VCC
LCLKResetAENnADSA[151]
nBE[30]
ARDYnRdnWR
D[310]
INTRO
WnRnVLBUSnCYCLE
nRDYRTNnDADACS
nLDEVnSARDY
SMSC LAN91C111
ExternalGlue Logic
PPC
OP
B B
us
FPGA
DS325_05_071406
ExternalReset VCC
External Glue Logic
Special attention must be given while interfacing the OPB EPC to the SMSC LAN91C111 in asynchronous mode The OPB EPC drives the PRH_BE active high while the SMSC LAN91C111 requires the input byte enable to be active low To match this requirement external glue logic is required to invert the PRH_BE signals before they are interfaced with the byte enable signals of the SMSC LAN91C111
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Synchronous Mode
Figure 6 illustrates the SMSC LAN91C111 connection to the OPB EPC in synchronous VL Bus mode with non-multiplexed address and data buses In synchronous mode the device requires an input clock source to the LCLK pin with a maximum operating frequency of 50MHz The local clock generated by the DCM for the peripheral interface must be routed to the LCLK input of SMSC LAN91C111 and PRH_Clk of OPB EPC When the device is accessed PRH_RNW is used as the control signal to indicate a readwrite access When PRH_RNW is high it indicates a read operation and when low it indicates a write operation The SMSC LAN91C111 uses nSRDY signal to indicate the device readiness This signal is connected to PRH_Rdy input of the OPB_EPC As the address and the data bus are not multiplexed PRH_ADS will be driven low
The following parameter settings apply for the connections shown in Figure 6
bull C_PRH_CLK_SUPPORT = 1
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 1
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 6 SMSC LAN91C111 Connection to OPB EPC in Synchronous Mode
igure Top x-ref 6
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
LCLKResetAENnADSA[151]nBE[30]WnRnSRDY
D[310]
nCYCLEnRDYRTN
INTRO
nRdnWR
nDADACSnLDEVARDY
nVLBUS
SMSC LAN91C111
ExternalGlue Logic
DigitalClock
Manager
PP
C
OP
B B
us
FPGA
DS325_06_071406
External Reset
VCC
GND
To System Interrupt Controller
External Glue Logic
The SMSC LAN91C111 device requires two inputs nCYCLE and nRDYRTN to control synchronous operation The definition of these signals is outside the scope of this document and can be found in the documents listed in the Reference Documents section The nCYCLE and nRDYRTN signals are generated in external glue logic nCYCLE may be generated from PRH_CS_n and is driven low for a
Discontinued IP
ust 10 2007 wwwxilinxcom 23ecification
OPB External Peripheral Controller (EPC) v100a
24
single clock cycle on a high to low transition on PRH_CS_n nRDYRTN is simply the registered value of the nSRDY signal
Design Considerations
When the OPB EPC is interfaced to the SMSC LAN91C111 with data width match enabled (C_PRHx_DWIDTH_MATCH = 1) and the internal SRAM of the peripheral is being accessed the device has to be configured in the address auto increment mode Address auto increment mode can be configured by setting AUTO INCR bit in the Bank 2 Pointer Register of SMSC LAN91C111 More information can be obtained by referring the registers of Bank 2 in SMSC LAN91C111 data sheet See the Reference Documents section
Example Cypress Semiconductorrsquos CY7C67300 EZ-Host Programmable Embedded USB HostPeripheral Controller
The Cypress Semiconductorrsquos CY7C67300 EZ-Hosttrade Programmable Embedded USB HostPeripheral Controller is another example of a peripheral device supported by the OPB EPC Since the Cypress USB controller operates in asynchronous mode the OPB EPC must be configured to support asynchronous mode operation
Asynchronous Mode
Figure 7 illustrates the CY7C67300 USB Controller connection to the OPB EPC in asynchronous mode with non-multiplexed address and data buses
The following parameter settings apply for the connection shown in Figure 7
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 4
bull C_PRH0_DWIDTH = 16
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Configuration of CY7C67300 USB Controller
The CY7C67300 USB Controller is configured as a Host Processor Interface (HPI) The boot-up sequence code for the CY7C67300 USB Controller in this particular example is present on the external Compact Flash memory device and is accessed through the OPB SYSACE interface This code is downloaded to the CY7C67300 USB Controller through the HPI interface Once this boot-up sequence is executed by the CY7C67300 USB Controller it becomes ready to operate in normal HPI mode with the external host controller (OPB EPC)
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
F
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 7 CY7C67300 USB Controller connection to OPB EPC in asynchronous mode
igure Top x-ref 7
SysACE_mpd_I[015]SysACE_mpd_O[015]SysACE_mpd_T[015]
SysACE_mpweSysACE_mpoe
SysACE_MPA[06]
SysACE_CEN
OPB SYS ACE Cntlr[150][150][150]
[60]
PRH_RstPRH_Rdy
PRH_CS_n
PRH_Data_I[015]PRH_Data_O[015]PRH_Data_T[015]
PRH_ADSPRH_RRNW
PRH_BurstPRH_Rd_nPRH_Wr_n
PRH_Addr[01]
OPB EPC
VCC
Ext
erna
l US
B P
orts
P
ort 1
A 1
B 2
AnCS
nRD
nWR
[D15D0]
[A1A0]
INT
CompactFLASH
TQFP144 SYSTEMACE
System ACE CompactFlash Controller
Ext
erna
l Glu
e Lo
gic
OPBINTC
US
B C
Y7C
6730
0
PP
C
OP
B B
us
FPGA
DS325_07_071406
Sysace_epc_data[150]
HPI interface
Sysace_epc_rd_n
Sysace_epc_wr_n
Sysace_epc_a[10]
DM1B
DP1B
DM2A
DP2A
DM1A
DP1A
External Glue Logic
In the interface diagram shown in Figure 7 the OPB EPC as well as the OPB SYSACE share the interface for data address and control lines on the board This requires external multiplex logic to be placed outside of IP cores in the FPGA The OPB EPC control signals PRH_RD_n and PRH_WR_n are muxed with the MEM_CEN and MEM_WEN signals of the OPB SYSACE When CY7C67300 USB Controller is accessed through the asynchronous mode the rising edge of sysace_epc_rd_n and sysace_epc_wr_n signals are used to control the read and the write operations respectively See the Reference Documents section for more information on OPB SYSACE
Design Constraints
Timing Constraints
Timing constraints must be placed on the system clock and the peripheral clock setting the frequency to meet the bus timing requirements An example is shown in Figure 8
Discontinued IP
ust 10 2007 wwwxilinxcom 25ecification
F
OPB External Peripheral Controller (EPC) v100a
26
Figure 8 EPC Timing Constraints
igure Top x-ref 8
Following constraint must be placed on the system clock
TIMESPEC TS_OPB_Clk = PERIOD OPB_Clk 10 ns HIGH 50
NET OPB_Clk TNM_NET = OPB_Clk
If C_PRH_CLK_SUPPORT=1 then the following constraint must be placed on the peripheral clock
TIMESPEC TS_PRH_Clk = PERIOD PRH_Clk 20 ns HIGH 50
NET PRH_Clk TNM_NET = PRH_Clk
DS325_08_071406
Design Implementation
Timing Diagrams
The timing diagrams in the figures below show various OPB transactions and the resulting access cycles on the peripheral interface Timing diagrams are not shown for all possible combinations of generics and the resulting access cycles However the timing diagrams shown are sufficient for the basic understanding of various access cycles supported by the OPB EPC
Figure 9 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 9
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
DS325_09_071206
8
4000000
004
04
Figure 10 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 10
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
04000000
20000004
8
00000000
004
04DS325_10_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 11 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 11
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000000
F
00010203
000 001 002 003
00 01 02 03DS325_11_071206
Figure 12 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 12
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
20000000
F
0000000000000000
000 001 002 003
00 01 02 03DS325_12_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 27ecification
OPB External Peripheral Controller (EPC) v100a
28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 29ecification
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
8
OPB EPC Design ParametersTo allow a user to create the OPB EPC that is uniquely tailored for the system certain features can be parameterized in the OPB EPC design Some of these parameters control the interface to the OPB while others control the interface to the peripheral devices This allows the user to have a design that only utilizes the minimum resources required by the system and operating at the best possible performance
The features that could be parameterized in the OPB EPC are shown in Table 2
Table 2 OPB EPC Design Parameters
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
OPB EPC Features
G1OPB clock period
C_OPB_CLK_PERIOD_PS
Integer number of picoseconds
10000 integer
G2 Target FPGA family C_FAMILYvirtex2 virtex2p virtex4 virtex5 spartan3
virtex2p string
G3 OPB address width C_OPB_AWIDTH 32 32 integer
G4 OPB data width C_OPB_DWIDTH 32 32 integer
OPB EPC Interface Parameters
G5 Peripheral clock periodC_PRH_CLK_PERIOD_PS(1)
Integer number of picoseconds
20000 integer
G6 Number of peripheralsC_NUM_PERIPHERALS
1-4 1 integer
G7Maximum of address bus width of all external peripherals
C_PRH_MAX_AWIDTH 3-32 32integer
G8Maximum of data bus width of all external peripherals
C_PRH_MAX_DWIDTH 8 16 or 32 32 integer
G9
Maximum of data bus width of all peripherals and address bus with of peripherals employing addressdata multiplexing
C_PRH_MAX_ADWIDTH(2) 8-32 32 integer
G10 Peripheral clock supportC_PRH_CLK_SUPPORT(1)
0 = Peripheral device interface operates at the OPB clock 1 = Peripheral device interface operates at external peripheral clock
0 integer
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G11 OPB burst supportC_PRH_BURST_SUPPORT(24)
0 = No burst support from OPB 1 = Not supported
0 integer
OPB EPC Peripheral Address Space
G12External peripheral base address
C_PRHx_BASEADDR(3) Valid address(4 5)
User must set values(6)
std_logic_vector
G13External peripheral high address
C_PRHx_HIGHADDR(3) Valid address(4 5)
User must set values(6)
std_logic_vector
OPB EPC Peripheral Interface Parameters
G14Support for access to FIFO within the external peripheral
C_PRHx_FIFO_ACCESS(3)
0 = No support for the external peripheral FIFO access1 = Access to FIFO structures within the external peripheral device is supported
0 integer
G15External peripheral FIFO offset from peripheral base address
C_PRHx_FIFO_OFFSET(3 7 8)
Any valid offset within the base and high address range assigned to the peripheral device
0 integer
G16Address bus width of peripherals
C_PRHx_AWIDTH(3) 3-32 32 integer
G17Data bus width of peripherals
C_PRHx_DWIDTH(3) 8 16 or 32 32 integer
G18
Support for data width match when the peripheral device data width is less than the OPB data width
C_PRHx_DWIDTH_MATCH(3 9)
0 = No multiple cycles on the peripheral interface for single OPB read or write cycle 1 = Run multiple cycles on the peripheral interface for single OPB read or write cycle
0 integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
ust 10 2007 wwwxilinxcom 9ecification
OPB External Peripheral Controller (EPC) v100a
10
G19 Peripheral access mode C_PRHx_SYNC(1 3)
0 = External device is asynchronous 1 = External device is synchronous
1 integer
G20 Peripheral bus typeC_PRHx_BUS_MULTIPLEX(3)
0 = External device has separate address and data bus1 = External device has multiplexed address and data bus
0 integer
OPB EPC Timing Parameters
G21
Address bus (PRH_Addr) setup with respect to rising edge of address strobe (PRH_ADS) or falling edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_ADDR_TSU(3 10)
Integer number of picoseconds
User must set values(11)
integer
G22
Address bus (PRH_Addr) hold with respect to falling edge of address strobe (PRH_ADS) or rising edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_ADDR_TH(3 12 16 19)
Integer number of picoseconds
User must set values(11)
integer
G23Minimum pulse width of address strobe (PRH_ADS)
C_PRHx_ADS_WIDTH(3)
Integer number of picoseconds
User must set values(11)
integer
G24
Chip select (PRH_CS_n) setup with respect to falling edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_CSN_TSU(3 10)
Integer number of picoseconds
User must set values(13)
integer
G25
Chip select (PRH_CS_n) hold with respect to rising edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_CSN_TH(3 16 19)
Integer number of picoseconds
User must set values(13)
integer
G26Minimum pulse width of write signal (PRH_Wr_n)
C_PRHx_WRN_WIDTH(3 14 15 16)
Integer number of picoseconds
User must set values(13)
integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G27Cycle time of write signal (PRH_Wr_n)
C_PRHx_WR_CYCLE(3 15 16)
Integer number of picoseconds
User must set values(13)
integer
G28
Data bus (PRH_Data) setup with respect to falling edge of write signal (PRH_Wr_n)
C_PRHx_DATA_TSU(3 14)
Integer number of picoseconds
User must set values(13)
integer
G29
Data bus (PRH_Data) hold with respect to rising edge of write signal (PRH_Wr_n)
C_PRHx_DATA_TH(3 16)
Integer number of picoseconds
User must set values(13)
integer
G30Minimum pulse width of read signal (PRH_Rd_n)
C_PRHx_RDN_WIDTH(3 17 18 19)
Integer number of picoseconds
User must set values(13)
integer
G31Cycle time of read signal (PRH_Rd_n)
C_PRHx_RD_CYCLE(3 18 19)
Integer number of picoseconds
User must set values(13)
integer
G32
Data bus (PRH_Data) validity from falling edge of read signal (PRH_Rd_n)
C_PRHx_DATA_TOUT(3 17)
Integer number of picoseconds
User must set values(13)
integer
G33
Data bus (PRH_Data) high impedance from rising edge of read (PRH_Rd_n)
C_PRHx_DATA_TINV(3 19)
Integer number of picoseconds
User must set values(13)
integer
G34
Device ready (PRH_Rdy) validity from the falling edge of read or write (PRH_Rd_n PRH_Wr_n)
C_PRHx_RDY_TOUT(3 20 22)
Integer number of picoseconds
User must set values(13)
integer
G35
Maximum period of device ready signal (PRH_Rdy) to wait before device timeout
C_PRHx_RDY_WIDTH(3 21 22)
Integer number of picoseconds
User must set values(23)
integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
ust 10 2007 wwwxilinxcom 11ecification
OPB External Peripheral Controller (EPC) v100a
12
Notes 1 The generic C_PRH_CLK_SUPPORT is relevant only when the device is configured for synchronous access
ie C_PRHx_SYNC = 1 If more than one device is synchronous then the frequency for the peripheral clock (PRH_Clk) should be chosen as the minimum of the operating frequencies of those devices
2 The C_PRH_MAX_ADWIDTH determines the size of the data bus For all non multiplexed devices the C_PRH_MAX_ADWIDTH reflects the maximum of data bus width of all external devices ie C_PRH_MAX_ADWIDTH equals C_PRH_MAX_DWIDTH However if any of the devices is configured for multiplexed address and data bus then C_PRH_MAX_ADWIDTH should be set as the maximum of data bus of all external devices and the address bus of device(s) employing multiplexed address and data bus
3 rsquoxrsquo in the generic refers to the number of the peripheral device and takes a value in the range of 0 to C_NUM_PERIPHERALS - 1
4 OPB EPC design can accommodate up to four peripheral devices The address range for the devices are designated as C_PRH0_BASEADDR C_PRH0_HIGHADDR C_PRH1_BASEADDR C_PRH1_HIGHADDR etc
5 The range specified by C_PRHx_BASEADDR and C_PRHx_HIGHADDR must comprise a contiguous range and the size of the range must be a power of two ie size of range = 2m Further the rsquomrsquo least significant bits of C_PRHx_BASEADDR must be zero The base and high address range assigned to different peripherals must be mutually exclusive
6 No default value will be specified to ensure that the actual value is set ie if the value is not set a compiler error will be generated
7 C_PRHx_FIFO_ACCESS must be set to 1 if the support for access to FIFO within external peripheral device is to be included
8 C_PRHx_FIFO_OFFSET is the byte offset of the external peripheral FIFO from the base address (C_PRHx_BASEADDR) of the peripheral irrespective of the data width of the peripheral device If C_PRHx_FIFO_ACCESS = 1 then C_PRHx_FIFO_OFFSET must be set to a valid offset within the address range assigned to the peripheral
9 The generic C_PRHx_DWIDTH_MATCH is relevant only when the width of the peripheral data (PRH_Data) bus is less than the OPB data bus (OPB_DBus)
10Address setup time is with respect to falling edge of address strobe (PRH_ADS) if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 and must be set both in synchronous and asynchronous mode Address setup time is with respect to falling edge of readwrite signals (PRH_Wr_nPRH_Rd_n) if the device is non multiplexed and is relevant only if the access mode is asynchronous
11Value for the parameter must be assigned if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 This parameter assignment is appicalble for synchronous and asynchronous devices
12Address hold time is with respect to falling edge of address strobe (PRH_ADS) if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 and must be set both in synchronous and asynchronous mode Address hold time is with respect to rising edge of readwrite signals (PRH_Wr_nPRH_Rd_n) if the address and the data bus are separate and is relevant only if the access mode is asynchronous
13Value must be assigned if the access mode of the peripherals is asynchronous ie C_PRHx_SYNC = 0 If the access mode of the peripheral is synchronous ie C_PRHx_SYNC = 1 then the zero should be assigned to the parameter
14Write signal (PRH_Wr_n) low time is the maximum of C_PRHx_WRN_WIDTH and C_PRHx_DATA_TSU15The value of C_PRHx_WRN_WIDTH must be smaller than C_PRHx_WR_CYCLE16 In non-multiplexed address and data bus mode write recovery time will be maximum of C_PRHx_ADDR_TH
C_PRHx_CSN_TH C_PRHx_DATA_TH and PRH_Wr_n high time (ie C_PRHx_WR_CYCLE minus C_PRHx_WRN_WIDTH) If the peripheral uses multiplexed address and data bus then the write recovery time will be maximum of C_PRHx_CSN_TH C_PRHx_DATA_TH and PRH_Wr_n high time
17Read signal (PRH_Rd_n) low time is the maximum of C_PRHx_RDN_WIDTH and C_PRHx_DATA_TOUT18The value of C_PRHx_RDN_WIDTH must be smaller than C_PRHx_RD_CYCLE19 In non-multiplexed address and data bus mode read recovery time will be maximum of C_PRHx_ADDR_TH
C_PRHx_CSN_TH C_PRHx_DATA_TINV and PRH_Rd_n high time (ie C_PRHx_RD_CYCLE minus C_PRHx_RDN_WIDTH) If the peripheral uses multiplexed address and data bus then the read recovery time will be maximum of C_PRHx_CSN_TH C_PRHx_DATA_TINV and PRH_Rd_n high time
20Device ready validity period (C_PRHx_RDY_TOUT) must be set as the maximum of the values specified for read and write transactions
21Device ready pulse width (C_PRHx_RDY_WIDTH) must be set as the maximum of the values specified for read and write transactions
22Device ready validity (C_PRHx_RDY_TOUT) period must be less than the write strobe width (C_PRHx_WRN_WIDTH) read strobe width (C_PRHx_RDN_WIDTH) and device ready signal width (C_PRHx_RDY_WIDTH)
23Device ready signal width (C_PRHx_RDY_WIDTH) must be set for both synchronous and asynchronous
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
access mode in order to prevent the device from holding the OPB indefinitely24Current version of the OPB EPC do not support the burst transactions tofrom the OPB
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Allowable Parameter Combinations
When the peripheral devices are confugured in non multiplexed mode the C_PRH_MAX_AWIDTH should be the maximum of C_PRHx_AWIDTH of all peripherals in the system ie if C_NUM_PERIPHERALS is 2 then C_PRH_MAX_AWIDTH should be maximum of C_PRH0_AWIDTH and C_PRH1_AWIDTH
C_PRH_MAX_DWIDTH should be the maximum of C_PRHx_DWIDTH of all peripherals in the system ie if C_NUM_PERIPHERALS is 2 then C_PRH_MAX_DWIDTH should be maximum of C_PRH0_DWIDTH and C_PRH1_DWIDTH
If any of the peripheral devices are configured for a multiplexed address and data buses then the parameter C_PRH_MAX_ADWIDTH should be set as the maximum of the data bus and address bus of the device(s) employing a multiplexed address and data bus If all devices employ non-multiplexed address and data buses then C_PRH_MAX_ADWIDTH reflects the maximum of data bus width of all external devices Therefore for any configuration the parameter C_PRH_MAX_ADWIDTH should be greater than or equal to C_PRH_MAX_DWIDTH
The generic C_PRH_CLK_SUPPORT is relevant only when the devices are configured for the synchronous access ie C_PRHx_SYNC = 1 If more than one of the devices are synchronous then the frequency for the peripheral clock should be chosen as the minimum of the operating frequencies of those devices
The range specified by C_PRHx_BASEADDR and C_PRHx_HIGHADDR parameters must comprise a contiguous range and the size of the range must be a power of two ie size of range = 2m Furthermore the rsquomrsquo least significant bits of C_PRHx_BASEADDR must be zero The base and high address range assigned to different peripherals must be mutually exclusive No default value will be specified for C_PRHx_BASEADDR and C_PRHx_HIGHADDR in order to enforce that the user configures these parameters with the actual values If the values are not set for C_PRHx_BASEADDR and C_PRHx_HIGHADDR a compiler error will be generated
In order to access FIFO like structures within the external peripheral devices C_PRHx_FIFO_ACCESS must be set to rsquo1rsquo When FIFO access is enabled C_PRHx_FIFO_OFFSET specifies the offset of the FIFO in terms of number of byte locations from the base address (C_PRHx_BASEADDR) of the peripheral and should be set to an offset that lies within the address range assigned to the peripheral device ie C_PRHx_BASEADDR + C_PRHx_FIFO_OFFSET le C_PRHx_HIGHADDR Furthermore the FIFO offset should be within the range addressable by the address bus ie C_PRHx_FIFO_OFFSET lt 2n
where n = C_PRHx_AWIDTH
The width of the readwrite strobe must be less than the cycle time of the corresponding access ie C_PRHx_WRN_WIDTH lt C_PRHx_WR_CYCLE and C_PRHx_RDN_WIDTH lt C_PRHx_RD_CYCLE The value of device ready validity period must be less than the readwrite strobe width and the maximum pulse width of the device ready signal ie C_PRHx_RDY_TOUT lt minimum of C_PRHx_WRN_WIDTH C_PRHx_RDN_WIDTH and C_PRHx_RDY_WIDTH
Parameter - Port Dependencies
The dependencies between the OPB EPC design parameters and the IO ports are shown in Table 3 The width of the OPB EPC signals depend on some of the parameters In addition when certain features are parameterized away the related logic is removed
Discontinued IP
ust 10 2007 wwwxilinxcom 13ecification
OPB External Peripheral Controller (EPC) v100a
14
Table 3 Parameter - Port Dependencies
Generic or Port
Name Affects Depends Description
Design Parameters
G3 C_OPB_AWIDTH P1 -The OPB address width parameter sets the width of the OPB address bus
G4 C_OPB_DWIDTHP2 P3
P7-
The OPB data width parameter affects the number of byte enables configured for the OPB data bus width of the OPB data bus and the width of the OPB slave read data bus
G6C_NUM_PERIPHERALS
P16 P24-
The number of peripherals in the system determines the number of chip select signals driven and the number of device ready inputs decoded by the OPB external peripheral controller
G7C_PRH_MAX_AWIDTH
P17- The width of the peripheral address bus is set to
the maximum of address bus width of all peripheral devices
G8C_PRH_MAX_DWIDTH
P19- The number of byte enables for the peripheral data
bus is determined by the maximum of data bus width of the peripheral devices
G9C_PRH_MAX_ADWIDTH
P25 P26 P27
-
The width of the peripheral input data bus peripheral output data bus and the peripheral output data bus 3-state control are determined by the maximum of data bus width of all peripherals and the address bus width of peripherals employing address data bus multiplexing
G10C_PRH_CLK_SUPPORT
P14- If C_PRH_CLK_SUPPORT = 0 then all external
devices operate on OPB clock The input PRH_Clk must be driven high externally
G18C_PRHx_DWIDTH_MATCH
P23-
If the device is configured for synchronous mode with data width matching enabled then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G19 C_PRHx_SYNCP14 P20 P21 P22
P23
-
If the device is configured for asynchronous mode
bull With peripheral clock support the peripheral clock input (PRH_Clk) must be driven high externally
bull PRH_RNW is driven high as PRH_Rd_n and PRH_Wr_n should be used as read and write strobe
bull With data width matching enabled the OPB EPC drives PRH_Burst to its default low
If the device is configured for synchronous mode
bull The OPB EPC drives PRH_Rd_n and PRH_Wr_n outputs to their default state of high since PRH_RNW output is used as readwrite strobe
G20C_PRHx_BUS_MULTIPLEX
P18- PRH_ADS is driven low if the device does not use
multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
IO Signals
P1 OPB_ABus - G3The OPB address bus width is determined by the C_OPB_AWIDTH parameter
P2 OPB_BE - G4The number of byte enables for the OPB data bus is determined by the C_OPB_DWIDTH parameter
P3 OPB_DBus - G4The OPB data bus width is determined by the C_OPB_DWIDTH parameter
P7 Sln_DBus-
G4The width of the OPB slave read data bus is determined by the C_OPB_DWIDTH parameter
P14 PRH_Clk-
G10 G19
PRH_Clk is selected as operating clock only if the device is configured for synchronous mode with peripheral clock support ie C_PRHx_SYNC = 1 and C_PRH_CLK_SUPPORT = 1 Asynchronous interface always operates on OPB_Clk Therefore if no device is configured for synchronous mode with peripheral clock support enabled then the input PRH_Clk must be driven high
P16 PRH_CS_n-
G6The number of chip select signals driven by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P17 PRH_Addr-
G7The width of the peripheral address bus is determined by the C_PRH_MAX_AWIDTH parameter
P18 PRH_ADS-
G20PRH_ADS is driven low if the device does not use multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
Discontinued IP
ust 10 2007 wwwxilinxcom 15ecification
OPB External Peripheral Controller (EPC) v100a
16
OPB EPC Design Considerations
The OPB EPC is an OPB slave only device It receives read or write instructions from the processor and generates a corresponding access cycle on the peripheral interface Examples of read and write accesses are illustrated in the Timing Diagrams section The user must take the following considerations into account while designing with the OPB EPC
Device Ready Signal
The OPB EPC readwrite access cycles are executed only when the external device assert the device ready signal (PRH_Rdy) If the external peripheral device does not have a device ready signal then the PRH_Rdy input of the OPB EPC must be tied to logic high
P19 PRH_BE - G8The number of byte enables for the peripheral data bus is determined by the C_PRH_MAX_DWIDTH parameter
P20 PHR_RNW-
G19
If the device is synchronous ie C_PRHx_SYNC = 1 then PRH_RNW should be used as the readwrite control signal For asynchronous mode of operation PRH_RNW is driven high
P21 PRH_Rd_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Rd_n should be used as the read strobe For synchronous mode of operation PRH_Rd_n is driven high
P22 PRH_Wr_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Wr_n should be used as the write strobe For synchronous mode of operation PRH_Wr_n is driven high
P23 PRH_Burst-
G18 G19
If the device is synchronous with data width matching enabled ie C_PRHx_SYNC = 1 and C_PRHx_DWIDTH_MATCH = 1 then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
P24 PRH_Rdy-
G6The number of device ready inputs decoded by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P25 PRH_Data_I-
G9The peripheral input data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P26 PRH_Data_O - G9The peripheral output data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P27 PRH_Data_T - G9
The peripheral output data bus 3-state control width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
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wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
FIFO Transactions
When C_PRHx_FIFO_ACCESS = 1 the OPB EPC supports access to FIFOrsquos within the external peripheral devices When the FIFO within the external device is accessed then the peripheral address bus (PRH_Addr) must remain constant representing the FIFO address within the address range assigned to the peripheral device When data width matching is enabled and the access corresponds to the FIFO the OPB EPC does not increment the peripheral address (PRH_Addr) bus
Abnormal Terminations
If PRH_Rdy is de-asserted for more than the maximum period as specified by C_PRHx_RDY_WIDTH then the OPB EPC terminates the current access to the external device and signals an error to the OPB master by asserting Sln_errAck on the OPB Similarly when the OPB master terminates the current access (master abort on the OPB) OPB EPC terminates the access to the external device immediately In both cases the access to the external device is terminated abnormally Therefore the external device may be in an indeterminate state and the exceptions should be handled appropriately at the system level
Interrupt Handling
If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Peripheral Data Bus Mapping
The peripheral data bus (PRH_Data) uses big endian bit labelling (ie bit-0 is Most Significant Bit (MSB) and bit-31 is Least Significant Bit (LSB) for a 32-bit bus) and is sized according to the C_PRH_MAX_ADWIDTH parameter Peripherals that have smaller widths should connect to this bus starting at bit 0 (MSB) For example if three external devices are present in the system with data bus width of 8-bit 16-bit and 32-bit the 8-bit device should connect to PRH_Data[07] the 16-bit wide peripheral should connect to PRH_Data[015] and the 32-bit peripheral should connect to PRH_Data[031]
The bit and byte labeling for the big endian data types is shown in Figure 3
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F
OPB External Peripheral Controller (EPC) v100a
18
Figure 3 OPB EPC Big Endian Data Type
igure Top x-ref 3
2 3
n+2 n+3
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 15
Halfword
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 31
Word
Byte
MS Byte
LS BitMS Bit
0
nByte address
Byte label
Byte significance
Bit label
Bit significance
0 7
DS325_03_071406
Unsupported Features
Many peripheral devices have the device specific inputoutput ports such as status remote reset remote wakeup interrupts etc The OPB EPC does not have any provision to support these device specific inputoutput ports Therefore if the external device has any such device specific ports then these inputoutput ports may be connected directly to system general purpose input output controller or to the system interrupt controller If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Many peripheral devices support DMA capability However currently OPB EPC is an OPB slave only device and therefore does not support DMA operations from the external peripheral devices
Current version of the OPB EPC does not support burst transactions tofrom the OPB
OPB EPC Latency
The OPB EPC latency calculations are based on the OPB clock The OPB latency is defined as the number of OPB clock cycles elapsed from the time an access is initiated to the time the access is completed (Sln_xferAck is asserted) on the OPB Table 4 shows the latency calculations for asynchronous mode and Table 5 shows the latency calculations for synchronous mode of operation
Discontinued IP
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OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 4 Asynchronous Mode OPB EPC Latency
Transaction Type
ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation(1)
OPB Latency
50 MHz
OPB Latency 100 MHz
ReadWrite access to asynchronous device when addressdata bus is not multiplexed
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5)
9(7) 12(7)
1FIFO
Memory
5 + N(2) (T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5))
21(7) 33(7)
ReadWrite access to asynchronous device when addressdata bus is multiplexed (Register access)
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + (T_SETUP(3) + T_ADDR_HOLD(6) + 1 + CONTROL_WIDTH(4) + T_HOLD(5))
11(7) 14(7)
1 FIFO
5 + T_SETUP(3) + T_ADDR_HOLD(6) + 1 + N(2) (CONTROL_WIDTH(4) + T_HOLD(5))
20(7) 29(7)
1 Memory
4 + N(2) (T_SETUP(3) + T_ADDR_HOLD(6) + CONTROL_WIDTH(4) + T_HOLD(5) + 2)
32(7) 44(7)
Notes 1 Latency calculations assumes the device is always ready2 If C_PRHx_DWIDTH_MATCH = 1 then N = Access size on OPB (in bytes)width of peripheral data bus (in
bytes)3 T_SETUP is the setup time requirement on various control signals in terms of number of OPB clocks and is
device specific4 CONTROL_WIDTH represents the required width for readwrite signal in terms of number of OPB clocks and
is device specific 5 T_HOLD is the hold time requirement on various control signals in terms of number of OPB clocks and is
device specific6 T_ADDR_HOLD is the required hold time on the address bus (as specified by generic C_PRHx_ADDR_TH) in
terms of number of OPB clocks and is device specific 7 Calculation are made for typical values of various timing parameters with T_SETUP = 20ns T_HOLD = 10ns
T_ADDR_HOLD = 6ns and STROBE_WIDTH = 40ns
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OPB External Peripheral Controller (EPC) v100a
20
Table 5 Synchronous Mode OPB EPC Latency
Transaction Type ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory 9
1FIFO
Memory 8 + N(2)
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory 11
1 FIFO 10 + N(2)
1 Memory 6 + 5N(2)
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 7 peripheral clocks
1FIFO
Memory
7 OPB clocks + (6+N(2)) peripheral clocks
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 9 peripheral clocks
1 FIFO7 OPB clocks + (8+N(2)) peripheral clocks
1 Memory7 OPB clocks + (4+5N(2)) peripheral clocks
Notes 1 Latency calculations assumes the device is always ready2 N = Access size on the OPB (in bytes)width of peripheral data bus (in bytes) where access size on OPB
equals or less than C_OPB_DWIDTH expressed in terms of bytes3 Latency calculation assumes that the requirement on address setup (C_PRHx_ADDR_TSU) address hold
(C_PRHx_ADDR_TH) and ADS pulse width (C_PRHx_ADS_WIDTH) are all less than one OPB clock
OPB EPC External Peripheral ConnectionsThe OPB EPC interface to the external device is based upon the width of the OPB data bus address and data width of the peripheral subsystem number of peripherals in the system addressdata multiplex support mode of operation (synchronous or asynchronous) and if synchronous device the operating clock for the synchronous data path
Determining Address and Data Width
The address bus width of the peripheral subsystem is the maximum width of the address bus of all peripheral devices connected to the OPB EPC If all devices employ non-multiplexed address and data bus the data bus width of the peripheral subsystem is the maximum of the data bus width of all external devices If any of the devices are configured for multiplexed address and data bus then the data bus width of the peripheral subsystem should be set as the maximum of the data bus and the address bus of the device(s) employing a multiplexed address and data bus
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OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Endian Considerations
The peripheral address and data bus of the OPB EPC is labeled with big endian bit labeling (D0 is the MSB and D31 is the LSB for a 32-bit bus) while most peripheral devices are either endian agnostic ie they can be connected either way or little endian (D31 is the MSB and D0 is the LSB for a 32-bit bus) Caution must be exercised with the connection to the external peripheral devices to avoid incorrect data and address connections
Clock Generation
When connecting to a synchronous external device the OPB EPC may operate either on the OPB clock (OPB_Clk) or on a peripheral clock (PRH_Clk) The operating clock for the synchronous interface is based on the generic C_PRH_CLK_SUPPORT If C_PRH_CLK_SUPPORT = 1 the peripheral clock is used else the OPB clock is used The external devices connected to the OPB EPC will determine the operating frequency of the peripheral clock The minimum of the operating frequencies of various devices connected to OPB EPC should be used as the operating frequency of the peripheral clock (PRH_Clk)
Figure 4 illustrates a block diagram for generating a device specific clock source clock source using two DCMs The DCM modules are located within the FPGA but are external to the OPB EPC An external clock source is used to generate the OPB clock (OPB_Clk) to the OPB EPC The device clock source (PRH_Clk) is also generated from the same DCM (DCM0) using the CLKFX output and must be routed on the board to be fed back to the FPGA Another DCM (DCM1) is used to synchronize the device peripheral clock to the OPB EPC PRH_Clk
Figure 4 External Peripherals clocked by FPGA output with feedback
igure Top x-ref 4
DS325_04_071406
CLKFB CLK0
CLKFXCLKIN
DCM0
PRH_Clk_FB
PRH_Clk
OPB_Clk
CLKFB CLK0
CLKIN
DCM1
PRH_Clk
OPB_Clk
OPB EPCExternalDevice
CLK
FPGA
Example Peripheral Connections
Example SMSC LAN91C111 10100 non-PCI Ethernet Single Chip MAC + PHY
An example peripheral device supported by the OPB EPC is the SMSC 10100 non-PCI Ethernet Single Chip MAC + PHY LAN91C111 The OPB EPC allows OPB masters to access the device both in synchronous and asynchronous mode The device connections for synchronous and asynchronous mode of operations are outlined in the Asynchronous Mode and Synchronous Mode sections
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OPB External Peripheral Controller (EPC) v100a
22
F
Asynchronous Mode
Figure 5 illustrates the SMSC LAN91C111 connections to the OPB EPC in asynchronous mode with non-multiplexed address and data buses In asynchronous mode the input clock source (PRH_Clk) to the external device must be tied to VCC When the SMSC LAN91C111 is accessed through the asynchronous mode the rising edge of PRH_Rd_n and PRH_Wr_n signals are used to control the read and the write operations respectively As the device uses Asynchronous Ready (ARDY) signal to indicate its readiness in asynchronous mode This signal is connected to the PRH_Rdy input of the OPB EPC Since the address and the data buses are not multiplexed PRH_ADS will be driven low by the OPB EPC
The following parameter settings apply for the connections shown in Figure 5
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 5 SMSC LAN91C111 Connection to OPB EPC in Asynchronous Mode
igure Top x-ref 5
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]
PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
To System Interrupt Controller
VCC
LCLKResetAENnADSA[151]
nBE[30]
ARDYnRdnWR
D[310]
INTRO
WnRnVLBUSnCYCLE
nRDYRTNnDADACS
nLDEVnSARDY
SMSC LAN91C111
ExternalGlue Logic
PPC
OP
B B
us
FPGA
DS325_05_071406
ExternalReset VCC
External Glue Logic
Special attention must be given while interfacing the OPB EPC to the SMSC LAN91C111 in asynchronous mode The OPB EPC drives the PRH_BE active high while the SMSC LAN91C111 requires the input byte enable to be active low To match this requirement external glue logic is required to invert the PRH_BE signals before they are interfaced with the byte enable signals of the SMSC LAN91C111
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OPB External Peripheral Controller (EPC) v100a
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F
Synchronous Mode
Figure 6 illustrates the SMSC LAN91C111 connection to the OPB EPC in synchronous VL Bus mode with non-multiplexed address and data buses In synchronous mode the device requires an input clock source to the LCLK pin with a maximum operating frequency of 50MHz The local clock generated by the DCM for the peripheral interface must be routed to the LCLK input of SMSC LAN91C111 and PRH_Clk of OPB EPC When the device is accessed PRH_RNW is used as the control signal to indicate a readwrite access When PRH_RNW is high it indicates a read operation and when low it indicates a write operation The SMSC LAN91C111 uses nSRDY signal to indicate the device readiness This signal is connected to PRH_Rdy input of the OPB_EPC As the address and the data bus are not multiplexed PRH_ADS will be driven low
The following parameter settings apply for the connections shown in Figure 6
bull C_PRH_CLK_SUPPORT = 1
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 1
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 6 SMSC LAN91C111 Connection to OPB EPC in Synchronous Mode
igure Top x-ref 6
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
LCLKResetAENnADSA[151]nBE[30]WnRnSRDY
D[310]
nCYCLEnRDYRTN
INTRO
nRdnWR
nDADACSnLDEVARDY
nVLBUS
SMSC LAN91C111
ExternalGlue Logic
DigitalClock
Manager
PP
C
OP
B B
us
FPGA
DS325_06_071406
External Reset
VCC
GND
To System Interrupt Controller
External Glue Logic
The SMSC LAN91C111 device requires two inputs nCYCLE and nRDYRTN to control synchronous operation The definition of these signals is outside the scope of this document and can be found in the documents listed in the Reference Documents section The nCYCLE and nRDYRTN signals are generated in external glue logic nCYCLE may be generated from PRH_CS_n and is driven low for a
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OPB External Peripheral Controller (EPC) v100a
24
single clock cycle on a high to low transition on PRH_CS_n nRDYRTN is simply the registered value of the nSRDY signal
Design Considerations
When the OPB EPC is interfaced to the SMSC LAN91C111 with data width match enabled (C_PRHx_DWIDTH_MATCH = 1) and the internal SRAM of the peripheral is being accessed the device has to be configured in the address auto increment mode Address auto increment mode can be configured by setting AUTO INCR bit in the Bank 2 Pointer Register of SMSC LAN91C111 More information can be obtained by referring the registers of Bank 2 in SMSC LAN91C111 data sheet See the Reference Documents section
Example Cypress Semiconductorrsquos CY7C67300 EZ-Host Programmable Embedded USB HostPeripheral Controller
The Cypress Semiconductorrsquos CY7C67300 EZ-Hosttrade Programmable Embedded USB HostPeripheral Controller is another example of a peripheral device supported by the OPB EPC Since the Cypress USB controller operates in asynchronous mode the OPB EPC must be configured to support asynchronous mode operation
Asynchronous Mode
Figure 7 illustrates the CY7C67300 USB Controller connection to the OPB EPC in asynchronous mode with non-multiplexed address and data buses
The following parameter settings apply for the connection shown in Figure 7
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 4
bull C_PRH0_DWIDTH = 16
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Configuration of CY7C67300 USB Controller
The CY7C67300 USB Controller is configured as a Host Processor Interface (HPI) The boot-up sequence code for the CY7C67300 USB Controller in this particular example is present on the external Compact Flash memory device and is accessed through the OPB SYSACE interface This code is downloaded to the CY7C67300 USB Controller through the HPI interface Once this boot-up sequence is executed by the CY7C67300 USB Controller it becomes ready to operate in normal HPI mode with the external host controller (OPB EPC)
Discontinued IP
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F
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 7 CY7C67300 USB Controller connection to OPB EPC in asynchronous mode
igure Top x-ref 7
SysACE_mpd_I[015]SysACE_mpd_O[015]SysACE_mpd_T[015]
SysACE_mpweSysACE_mpoe
SysACE_MPA[06]
SysACE_CEN
OPB SYS ACE Cntlr[150][150][150]
[60]
PRH_RstPRH_Rdy
PRH_CS_n
PRH_Data_I[015]PRH_Data_O[015]PRH_Data_T[015]
PRH_ADSPRH_RRNW
PRH_BurstPRH_Rd_nPRH_Wr_n
PRH_Addr[01]
OPB EPC
VCC
Ext
erna
l US
B P
orts
P
ort 1
A 1
B 2
AnCS
nRD
nWR
[D15D0]
[A1A0]
INT
CompactFLASH
TQFP144 SYSTEMACE
System ACE CompactFlash Controller
Ext
erna
l Glu
e Lo
gic
OPBINTC
US
B C
Y7C
6730
0
PP
C
OP
B B
us
FPGA
DS325_07_071406
Sysace_epc_data[150]
HPI interface
Sysace_epc_rd_n
Sysace_epc_wr_n
Sysace_epc_a[10]
DM1B
DP1B
DM2A
DP2A
DM1A
DP1A
External Glue Logic
In the interface diagram shown in Figure 7 the OPB EPC as well as the OPB SYSACE share the interface for data address and control lines on the board This requires external multiplex logic to be placed outside of IP cores in the FPGA The OPB EPC control signals PRH_RD_n and PRH_WR_n are muxed with the MEM_CEN and MEM_WEN signals of the OPB SYSACE When CY7C67300 USB Controller is accessed through the asynchronous mode the rising edge of sysace_epc_rd_n and sysace_epc_wr_n signals are used to control the read and the write operations respectively See the Reference Documents section for more information on OPB SYSACE
Design Constraints
Timing Constraints
Timing constraints must be placed on the system clock and the peripheral clock setting the frequency to meet the bus timing requirements An example is shown in Figure 8
Discontinued IP
ust 10 2007 wwwxilinxcom 25ecification
F
OPB External Peripheral Controller (EPC) v100a
26
Figure 8 EPC Timing Constraints
igure Top x-ref 8
Following constraint must be placed on the system clock
TIMESPEC TS_OPB_Clk = PERIOD OPB_Clk 10 ns HIGH 50
NET OPB_Clk TNM_NET = OPB_Clk
If C_PRH_CLK_SUPPORT=1 then the following constraint must be placed on the peripheral clock
TIMESPEC TS_PRH_Clk = PERIOD PRH_Clk 20 ns HIGH 50
NET PRH_Clk TNM_NET = PRH_Clk
DS325_08_071406
Design Implementation
Timing Diagrams
The timing diagrams in the figures below show various OPB transactions and the resulting access cycles on the peripheral interface Timing diagrams are not shown for all possible combinations of generics and the resulting access cycles However the timing diagrams shown are sufficient for the basic understanding of various access cycles supported by the OPB EPC
Figure 9 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 9
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
DS325_09_071206
8
4000000
004
04
Figure 10 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 10
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
04000000
20000004
8
00000000
004
04DS325_10_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 11 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 11
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000000
F
00010203
000 001 002 003
00 01 02 03DS325_11_071206
Figure 12 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 12
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
20000000
F
0000000000000000
000 001 002 003
00 01 02 03DS325_12_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 27ecification
OPB External Peripheral Controller (EPC) v100a
28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
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wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 29ecification
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
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wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G11 OPB burst supportC_PRH_BURST_SUPPORT(24)
0 = No burst support from OPB 1 = Not supported
0 integer
OPB EPC Peripheral Address Space
G12External peripheral base address
C_PRHx_BASEADDR(3) Valid address(4 5)
User must set values(6)
std_logic_vector
G13External peripheral high address
C_PRHx_HIGHADDR(3) Valid address(4 5)
User must set values(6)
std_logic_vector
OPB EPC Peripheral Interface Parameters
G14Support for access to FIFO within the external peripheral
C_PRHx_FIFO_ACCESS(3)
0 = No support for the external peripheral FIFO access1 = Access to FIFO structures within the external peripheral device is supported
0 integer
G15External peripheral FIFO offset from peripheral base address
C_PRHx_FIFO_OFFSET(3 7 8)
Any valid offset within the base and high address range assigned to the peripheral device
0 integer
G16Address bus width of peripherals
C_PRHx_AWIDTH(3) 3-32 32 integer
G17Data bus width of peripherals
C_PRHx_DWIDTH(3) 8 16 or 32 32 integer
G18
Support for data width match when the peripheral device data width is less than the OPB data width
C_PRHx_DWIDTH_MATCH(3 9)
0 = No multiple cycles on the peripheral interface for single OPB read or write cycle 1 = Run multiple cycles on the peripheral interface for single OPB read or write cycle
0 integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
ust 10 2007 wwwxilinxcom 9ecification
OPB External Peripheral Controller (EPC) v100a
10
G19 Peripheral access mode C_PRHx_SYNC(1 3)
0 = External device is asynchronous 1 = External device is synchronous
1 integer
G20 Peripheral bus typeC_PRHx_BUS_MULTIPLEX(3)
0 = External device has separate address and data bus1 = External device has multiplexed address and data bus
0 integer
OPB EPC Timing Parameters
G21
Address bus (PRH_Addr) setup with respect to rising edge of address strobe (PRH_ADS) or falling edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_ADDR_TSU(3 10)
Integer number of picoseconds
User must set values(11)
integer
G22
Address bus (PRH_Addr) hold with respect to falling edge of address strobe (PRH_ADS) or rising edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_ADDR_TH(3 12 16 19)
Integer number of picoseconds
User must set values(11)
integer
G23Minimum pulse width of address strobe (PRH_ADS)
C_PRHx_ADS_WIDTH(3)
Integer number of picoseconds
User must set values(11)
integer
G24
Chip select (PRH_CS_n) setup with respect to falling edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_CSN_TSU(3 10)
Integer number of picoseconds
User must set values(13)
integer
G25
Chip select (PRH_CS_n) hold with respect to rising edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_CSN_TH(3 16 19)
Integer number of picoseconds
User must set values(13)
integer
G26Minimum pulse width of write signal (PRH_Wr_n)
C_PRHx_WRN_WIDTH(3 14 15 16)
Integer number of picoseconds
User must set values(13)
integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G27Cycle time of write signal (PRH_Wr_n)
C_PRHx_WR_CYCLE(3 15 16)
Integer number of picoseconds
User must set values(13)
integer
G28
Data bus (PRH_Data) setup with respect to falling edge of write signal (PRH_Wr_n)
C_PRHx_DATA_TSU(3 14)
Integer number of picoseconds
User must set values(13)
integer
G29
Data bus (PRH_Data) hold with respect to rising edge of write signal (PRH_Wr_n)
C_PRHx_DATA_TH(3 16)
Integer number of picoseconds
User must set values(13)
integer
G30Minimum pulse width of read signal (PRH_Rd_n)
C_PRHx_RDN_WIDTH(3 17 18 19)
Integer number of picoseconds
User must set values(13)
integer
G31Cycle time of read signal (PRH_Rd_n)
C_PRHx_RD_CYCLE(3 18 19)
Integer number of picoseconds
User must set values(13)
integer
G32
Data bus (PRH_Data) validity from falling edge of read signal (PRH_Rd_n)
C_PRHx_DATA_TOUT(3 17)
Integer number of picoseconds
User must set values(13)
integer
G33
Data bus (PRH_Data) high impedance from rising edge of read (PRH_Rd_n)
C_PRHx_DATA_TINV(3 19)
Integer number of picoseconds
User must set values(13)
integer
G34
Device ready (PRH_Rdy) validity from the falling edge of read or write (PRH_Rd_n PRH_Wr_n)
C_PRHx_RDY_TOUT(3 20 22)
Integer number of picoseconds
User must set values(13)
integer
G35
Maximum period of device ready signal (PRH_Rdy) to wait before device timeout
C_PRHx_RDY_WIDTH(3 21 22)
Integer number of picoseconds
User must set values(23)
integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
ust 10 2007 wwwxilinxcom 11ecification
OPB External Peripheral Controller (EPC) v100a
12
Notes 1 The generic C_PRH_CLK_SUPPORT is relevant only when the device is configured for synchronous access
ie C_PRHx_SYNC = 1 If more than one device is synchronous then the frequency for the peripheral clock (PRH_Clk) should be chosen as the minimum of the operating frequencies of those devices
2 The C_PRH_MAX_ADWIDTH determines the size of the data bus For all non multiplexed devices the C_PRH_MAX_ADWIDTH reflects the maximum of data bus width of all external devices ie C_PRH_MAX_ADWIDTH equals C_PRH_MAX_DWIDTH However if any of the devices is configured for multiplexed address and data bus then C_PRH_MAX_ADWIDTH should be set as the maximum of data bus of all external devices and the address bus of device(s) employing multiplexed address and data bus
3 rsquoxrsquo in the generic refers to the number of the peripheral device and takes a value in the range of 0 to C_NUM_PERIPHERALS - 1
4 OPB EPC design can accommodate up to four peripheral devices The address range for the devices are designated as C_PRH0_BASEADDR C_PRH0_HIGHADDR C_PRH1_BASEADDR C_PRH1_HIGHADDR etc
5 The range specified by C_PRHx_BASEADDR and C_PRHx_HIGHADDR must comprise a contiguous range and the size of the range must be a power of two ie size of range = 2m Further the rsquomrsquo least significant bits of C_PRHx_BASEADDR must be zero The base and high address range assigned to different peripherals must be mutually exclusive
6 No default value will be specified to ensure that the actual value is set ie if the value is not set a compiler error will be generated
7 C_PRHx_FIFO_ACCESS must be set to 1 if the support for access to FIFO within external peripheral device is to be included
8 C_PRHx_FIFO_OFFSET is the byte offset of the external peripheral FIFO from the base address (C_PRHx_BASEADDR) of the peripheral irrespective of the data width of the peripheral device If C_PRHx_FIFO_ACCESS = 1 then C_PRHx_FIFO_OFFSET must be set to a valid offset within the address range assigned to the peripheral
9 The generic C_PRHx_DWIDTH_MATCH is relevant only when the width of the peripheral data (PRH_Data) bus is less than the OPB data bus (OPB_DBus)
10Address setup time is with respect to falling edge of address strobe (PRH_ADS) if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 and must be set both in synchronous and asynchronous mode Address setup time is with respect to falling edge of readwrite signals (PRH_Wr_nPRH_Rd_n) if the device is non multiplexed and is relevant only if the access mode is asynchronous
11Value for the parameter must be assigned if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 This parameter assignment is appicalble for synchronous and asynchronous devices
12Address hold time is with respect to falling edge of address strobe (PRH_ADS) if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 and must be set both in synchronous and asynchronous mode Address hold time is with respect to rising edge of readwrite signals (PRH_Wr_nPRH_Rd_n) if the address and the data bus are separate and is relevant only if the access mode is asynchronous
13Value must be assigned if the access mode of the peripherals is asynchronous ie C_PRHx_SYNC = 0 If the access mode of the peripheral is synchronous ie C_PRHx_SYNC = 1 then the zero should be assigned to the parameter
14Write signal (PRH_Wr_n) low time is the maximum of C_PRHx_WRN_WIDTH and C_PRHx_DATA_TSU15The value of C_PRHx_WRN_WIDTH must be smaller than C_PRHx_WR_CYCLE16 In non-multiplexed address and data bus mode write recovery time will be maximum of C_PRHx_ADDR_TH
C_PRHx_CSN_TH C_PRHx_DATA_TH and PRH_Wr_n high time (ie C_PRHx_WR_CYCLE minus C_PRHx_WRN_WIDTH) If the peripheral uses multiplexed address and data bus then the write recovery time will be maximum of C_PRHx_CSN_TH C_PRHx_DATA_TH and PRH_Wr_n high time
17Read signal (PRH_Rd_n) low time is the maximum of C_PRHx_RDN_WIDTH and C_PRHx_DATA_TOUT18The value of C_PRHx_RDN_WIDTH must be smaller than C_PRHx_RD_CYCLE19 In non-multiplexed address and data bus mode read recovery time will be maximum of C_PRHx_ADDR_TH
C_PRHx_CSN_TH C_PRHx_DATA_TINV and PRH_Rd_n high time (ie C_PRHx_RD_CYCLE minus C_PRHx_RDN_WIDTH) If the peripheral uses multiplexed address and data bus then the read recovery time will be maximum of C_PRHx_CSN_TH C_PRHx_DATA_TINV and PRH_Rd_n high time
20Device ready validity period (C_PRHx_RDY_TOUT) must be set as the maximum of the values specified for read and write transactions
21Device ready pulse width (C_PRHx_RDY_WIDTH) must be set as the maximum of the values specified for read and write transactions
22Device ready validity (C_PRHx_RDY_TOUT) period must be less than the write strobe width (C_PRHx_WRN_WIDTH) read strobe width (C_PRHx_RDN_WIDTH) and device ready signal width (C_PRHx_RDY_WIDTH)
23Device ready signal width (C_PRHx_RDY_WIDTH) must be set for both synchronous and asynchronous
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
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access mode in order to prevent the device from holding the OPB indefinitely24Current version of the OPB EPC do not support the burst transactions tofrom the OPB
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Allowable Parameter Combinations
When the peripheral devices are confugured in non multiplexed mode the C_PRH_MAX_AWIDTH should be the maximum of C_PRHx_AWIDTH of all peripherals in the system ie if C_NUM_PERIPHERALS is 2 then C_PRH_MAX_AWIDTH should be maximum of C_PRH0_AWIDTH and C_PRH1_AWIDTH
C_PRH_MAX_DWIDTH should be the maximum of C_PRHx_DWIDTH of all peripherals in the system ie if C_NUM_PERIPHERALS is 2 then C_PRH_MAX_DWIDTH should be maximum of C_PRH0_DWIDTH and C_PRH1_DWIDTH
If any of the peripheral devices are configured for a multiplexed address and data buses then the parameter C_PRH_MAX_ADWIDTH should be set as the maximum of the data bus and address bus of the device(s) employing a multiplexed address and data bus If all devices employ non-multiplexed address and data buses then C_PRH_MAX_ADWIDTH reflects the maximum of data bus width of all external devices Therefore for any configuration the parameter C_PRH_MAX_ADWIDTH should be greater than or equal to C_PRH_MAX_DWIDTH
The generic C_PRH_CLK_SUPPORT is relevant only when the devices are configured for the synchronous access ie C_PRHx_SYNC = 1 If more than one of the devices are synchronous then the frequency for the peripheral clock should be chosen as the minimum of the operating frequencies of those devices
The range specified by C_PRHx_BASEADDR and C_PRHx_HIGHADDR parameters must comprise a contiguous range and the size of the range must be a power of two ie size of range = 2m Furthermore the rsquomrsquo least significant bits of C_PRHx_BASEADDR must be zero The base and high address range assigned to different peripherals must be mutually exclusive No default value will be specified for C_PRHx_BASEADDR and C_PRHx_HIGHADDR in order to enforce that the user configures these parameters with the actual values If the values are not set for C_PRHx_BASEADDR and C_PRHx_HIGHADDR a compiler error will be generated
In order to access FIFO like structures within the external peripheral devices C_PRHx_FIFO_ACCESS must be set to rsquo1rsquo When FIFO access is enabled C_PRHx_FIFO_OFFSET specifies the offset of the FIFO in terms of number of byte locations from the base address (C_PRHx_BASEADDR) of the peripheral and should be set to an offset that lies within the address range assigned to the peripheral device ie C_PRHx_BASEADDR + C_PRHx_FIFO_OFFSET le C_PRHx_HIGHADDR Furthermore the FIFO offset should be within the range addressable by the address bus ie C_PRHx_FIFO_OFFSET lt 2n
where n = C_PRHx_AWIDTH
The width of the readwrite strobe must be less than the cycle time of the corresponding access ie C_PRHx_WRN_WIDTH lt C_PRHx_WR_CYCLE and C_PRHx_RDN_WIDTH lt C_PRHx_RD_CYCLE The value of device ready validity period must be less than the readwrite strobe width and the maximum pulse width of the device ready signal ie C_PRHx_RDY_TOUT lt minimum of C_PRHx_WRN_WIDTH C_PRHx_RDN_WIDTH and C_PRHx_RDY_WIDTH
Parameter - Port Dependencies
The dependencies between the OPB EPC design parameters and the IO ports are shown in Table 3 The width of the OPB EPC signals depend on some of the parameters In addition when certain features are parameterized away the related logic is removed
Discontinued IP
ust 10 2007 wwwxilinxcom 13ecification
OPB External Peripheral Controller (EPC) v100a
14
Table 3 Parameter - Port Dependencies
Generic or Port
Name Affects Depends Description
Design Parameters
G3 C_OPB_AWIDTH P1 -The OPB address width parameter sets the width of the OPB address bus
G4 C_OPB_DWIDTHP2 P3
P7-
The OPB data width parameter affects the number of byte enables configured for the OPB data bus width of the OPB data bus and the width of the OPB slave read data bus
G6C_NUM_PERIPHERALS
P16 P24-
The number of peripherals in the system determines the number of chip select signals driven and the number of device ready inputs decoded by the OPB external peripheral controller
G7C_PRH_MAX_AWIDTH
P17- The width of the peripheral address bus is set to
the maximum of address bus width of all peripheral devices
G8C_PRH_MAX_DWIDTH
P19- The number of byte enables for the peripheral data
bus is determined by the maximum of data bus width of the peripheral devices
G9C_PRH_MAX_ADWIDTH
P25 P26 P27
-
The width of the peripheral input data bus peripheral output data bus and the peripheral output data bus 3-state control are determined by the maximum of data bus width of all peripherals and the address bus width of peripherals employing address data bus multiplexing
G10C_PRH_CLK_SUPPORT
P14- If C_PRH_CLK_SUPPORT = 0 then all external
devices operate on OPB clock The input PRH_Clk must be driven high externally
G18C_PRHx_DWIDTH_MATCH
P23-
If the device is configured for synchronous mode with data width matching enabled then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
Discontinued IP
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OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G19 C_PRHx_SYNCP14 P20 P21 P22
P23
-
If the device is configured for asynchronous mode
bull With peripheral clock support the peripheral clock input (PRH_Clk) must be driven high externally
bull PRH_RNW is driven high as PRH_Rd_n and PRH_Wr_n should be used as read and write strobe
bull With data width matching enabled the OPB EPC drives PRH_Burst to its default low
If the device is configured for synchronous mode
bull The OPB EPC drives PRH_Rd_n and PRH_Wr_n outputs to their default state of high since PRH_RNW output is used as readwrite strobe
G20C_PRHx_BUS_MULTIPLEX
P18- PRH_ADS is driven low if the device does not use
multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
IO Signals
P1 OPB_ABus - G3The OPB address bus width is determined by the C_OPB_AWIDTH parameter
P2 OPB_BE - G4The number of byte enables for the OPB data bus is determined by the C_OPB_DWIDTH parameter
P3 OPB_DBus - G4The OPB data bus width is determined by the C_OPB_DWIDTH parameter
P7 Sln_DBus-
G4The width of the OPB slave read data bus is determined by the C_OPB_DWIDTH parameter
P14 PRH_Clk-
G10 G19
PRH_Clk is selected as operating clock only if the device is configured for synchronous mode with peripheral clock support ie C_PRHx_SYNC = 1 and C_PRH_CLK_SUPPORT = 1 Asynchronous interface always operates on OPB_Clk Therefore if no device is configured for synchronous mode with peripheral clock support enabled then the input PRH_Clk must be driven high
P16 PRH_CS_n-
G6The number of chip select signals driven by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P17 PRH_Addr-
G7The width of the peripheral address bus is determined by the C_PRH_MAX_AWIDTH parameter
P18 PRH_ADS-
G20PRH_ADS is driven low if the device does not use multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
Discontinued IP
ust 10 2007 wwwxilinxcom 15ecification
OPB External Peripheral Controller (EPC) v100a
16
OPB EPC Design Considerations
The OPB EPC is an OPB slave only device It receives read or write instructions from the processor and generates a corresponding access cycle on the peripheral interface Examples of read and write accesses are illustrated in the Timing Diagrams section The user must take the following considerations into account while designing with the OPB EPC
Device Ready Signal
The OPB EPC readwrite access cycles are executed only when the external device assert the device ready signal (PRH_Rdy) If the external peripheral device does not have a device ready signal then the PRH_Rdy input of the OPB EPC must be tied to logic high
P19 PRH_BE - G8The number of byte enables for the peripheral data bus is determined by the C_PRH_MAX_DWIDTH parameter
P20 PHR_RNW-
G19
If the device is synchronous ie C_PRHx_SYNC = 1 then PRH_RNW should be used as the readwrite control signal For asynchronous mode of operation PRH_RNW is driven high
P21 PRH_Rd_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Rd_n should be used as the read strobe For synchronous mode of operation PRH_Rd_n is driven high
P22 PRH_Wr_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Wr_n should be used as the write strobe For synchronous mode of operation PRH_Wr_n is driven high
P23 PRH_Burst-
G18 G19
If the device is synchronous with data width matching enabled ie C_PRHx_SYNC = 1 and C_PRHx_DWIDTH_MATCH = 1 then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
P24 PRH_Rdy-
G6The number of device ready inputs decoded by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P25 PRH_Data_I-
G9The peripheral input data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P26 PRH_Data_O - G9The peripheral output data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P27 PRH_Data_T - G9
The peripheral output data bus 3-state control width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
Discontinued IP
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OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
FIFO Transactions
When C_PRHx_FIFO_ACCESS = 1 the OPB EPC supports access to FIFOrsquos within the external peripheral devices When the FIFO within the external device is accessed then the peripheral address bus (PRH_Addr) must remain constant representing the FIFO address within the address range assigned to the peripheral device When data width matching is enabled and the access corresponds to the FIFO the OPB EPC does not increment the peripheral address (PRH_Addr) bus
Abnormal Terminations
If PRH_Rdy is de-asserted for more than the maximum period as specified by C_PRHx_RDY_WIDTH then the OPB EPC terminates the current access to the external device and signals an error to the OPB master by asserting Sln_errAck on the OPB Similarly when the OPB master terminates the current access (master abort on the OPB) OPB EPC terminates the access to the external device immediately In both cases the access to the external device is terminated abnormally Therefore the external device may be in an indeterminate state and the exceptions should be handled appropriately at the system level
Interrupt Handling
If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Peripheral Data Bus Mapping
The peripheral data bus (PRH_Data) uses big endian bit labelling (ie bit-0 is Most Significant Bit (MSB) and bit-31 is Least Significant Bit (LSB) for a 32-bit bus) and is sized according to the C_PRH_MAX_ADWIDTH parameter Peripherals that have smaller widths should connect to this bus starting at bit 0 (MSB) For example if three external devices are present in the system with data bus width of 8-bit 16-bit and 32-bit the 8-bit device should connect to PRH_Data[07] the 16-bit wide peripheral should connect to PRH_Data[015] and the 32-bit peripheral should connect to PRH_Data[031]
The bit and byte labeling for the big endian data types is shown in Figure 3
Discontinued IP
ust 10 2007 wwwxilinxcom 17ecification
F
OPB External Peripheral Controller (EPC) v100a
18
Figure 3 OPB EPC Big Endian Data Type
igure Top x-ref 3
2 3
n+2 n+3
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 15
Halfword
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 31
Word
Byte
MS Byte
LS BitMS Bit
0
nByte address
Byte label
Byte significance
Bit label
Bit significance
0 7
DS325_03_071406
Unsupported Features
Many peripheral devices have the device specific inputoutput ports such as status remote reset remote wakeup interrupts etc The OPB EPC does not have any provision to support these device specific inputoutput ports Therefore if the external device has any such device specific ports then these inputoutput ports may be connected directly to system general purpose input output controller or to the system interrupt controller If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Many peripheral devices support DMA capability However currently OPB EPC is an OPB slave only device and therefore does not support DMA operations from the external peripheral devices
Current version of the OPB EPC does not support burst transactions tofrom the OPB
OPB EPC Latency
The OPB EPC latency calculations are based on the OPB clock The OPB latency is defined as the number of OPB clock cycles elapsed from the time an access is initiated to the time the access is completed (Sln_xferAck is asserted) on the OPB Table 4 shows the latency calculations for asynchronous mode and Table 5 shows the latency calculations for synchronous mode of operation
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 4 Asynchronous Mode OPB EPC Latency
Transaction Type
ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation(1)
OPB Latency
50 MHz
OPB Latency 100 MHz
ReadWrite access to asynchronous device when addressdata bus is not multiplexed
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5)
9(7) 12(7)
1FIFO
Memory
5 + N(2) (T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5))
21(7) 33(7)
ReadWrite access to asynchronous device when addressdata bus is multiplexed (Register access)
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + (T_SETUP(3) + T_ADDR_HOLD(6) + 1 + CONTROL_WIDTH(4) + T_HOLD(5))
11(7) 14(7)
1 FIFO
5 + T_SETUP(3) + T_ADDR_HOLD(6) + 1 + N(2) (CONTROL_WIDTH(4) + T_HOLD(5))
20(7) 29(7)
1 Memory
4 + N(2) (T_SETUP(3) + T_ADDR_HOLD(6) + CONTROL_WIDTH(4) + T_HOLD(5) + 2)
32(7) 44(7)
Notes 1 Latency calculations assumes the device is always ready2 If C_PRHx_DWIDTH_MATCH = 1 then N = Access size on OPB (in bytes)width of peripheral data bus (in
bytes)3 T_SETUP is the setup time requirement on various control signals in terms of number of OPB clocks and is
device specific4 CONTROL_WIDTH represents the required width for readwrite signal in terms of number of OPB clocks and
is device specific 5 T_HOLD is the hold time requirement on various control signals in terms of number of OPB clocks and is
device specific6 T_ADDR_HOLD is the required hold time on the address bus (as specified by generic C_PRHx_ADDR_TH) in
terms of number of OPB clocks and is device specific 7 Calculation are made for typical values of various timing parameters with T_SETUP = 20ns T_HOLD = 10ns
T_ADDR_HOLD = 6ns and STROBE_WIDTH = 40ns
Discontinued IP
ust 10 2007 wwwxilinxcom 19ecification
OPB External Peripheral Controller (EPC) v100a
20
Table 5 Synchronous Mode OPB EPC Latency
Transaction Type ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory 9
1FIFO
Memory 8 + N(2)
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory 11
1 FIFO 10 + N(2)
1 Memory 6 + 5N(2)
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 7 peripheral clocks
1FIFO
Memory
7 OPB clocks + (6+N(2)) peripheral clocks
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 9 peripheral clocks
1 FIFO7 OPB clocks + (8+N(2)) peripheral clocks
1 Memory7 OPB clocks + (4+5N(2)) peripheral clocks
Notes 1 Latency calculations assumes the device is always ready2 N = Access size on the OPB (in bytes)width of peripheral data bus (in bytes) where access size on OPB
equals or less than C_OPB_DWIDTH expressed in terms of bytes3 Latency calculation assumes that the requirement on address setup (C_PRHx_ADDR_TSU) address hold
(C_PRHx_ADDR_TH) and ADS pulse width (C_PRHx_ADS_WIDTH) are all less than one OPB clock
OPB EPC External Peripheral ConnectionsThe OPB EPC interface to the external device is based upon the width of the OPB data bus address and data width of the peripheral subsystem number of peripherals in the system addressdata multiplex support mode of operation (synchronous or asynchronous) and if synchronous device the operating clock for the synchronous data path
Determining Address and Data Width
The address bus width of the peripheral subsystem is the maximum width of the address bus of all peripheral devices connected to the OPB EPC If all devices employ non-multiplexed address and data bus the data bus width of the peripheral subsystem is the maximum of the data bus width of all external devices If any of the devices are configured for multiplexed address and data bus then the data bus width of the peripheral subsystem should be set as the maximum of the data bus and the address bus of the device(s) employing a multiplexed address and data bus
Discontinued IP
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OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Endian Considerations
The peripheral address and data bus of the OPB EPC is labeled with big endian bit labeling (D0 is the MSB and D31 is the LSB for a 32-bit bus) while most peripheral devices are either endian agnostic ie they can be connected either way or little endian (D31 is the MSB and D0 is the LSB for a 32-bit bus) Caution must be exercised with the connection to the external peripheral devices to avoid incorrect data and address connections
Clock Generation
When connecting to a synchronous external device the OPB EPC may operate either on the OPB clock (OPB_Clk) or on a peripheral clock (PRH_Clk) The operating clock for the synchronous interface is based on the generic C_PRH_CLK_SUPPORT If C_PRH_CLK_SUPPORT = 1 the peripheral clock is used else the OPB clock is used The external devices connected to the OPB EPC will determine the operating frequency of the peripheral clock The minimum of the operating frequencies of various devices connected to OPB EPC should be used as the operating frequency of the peripheral clock (PRH_Clk)
Figure 4 illustrates a block diagram for generating a device specific clock source clock source using two DCMs The DCM modules are located within the FPGA but are external to the OPB EPC An external clock source is used to generate the OPB clock (OPB_Clk) to the OPB EPC The device clock source (PRH_Clk) is also generated from the same DCM (DCM0) using the CLKFX output and must be routed on the board to be fed back to the FPGA Another DCM (DCM1) is used to synchronize the device peripheral clock to the OPB EPC PRH_Clk
Figure 4 External Peripherals clocked by FPGA output with feedback
igure Top x-ref 4
DS325_04_071406
CLKFB CLK0
CLKFXCLKIN
DCM0
PRH_Clk_FB
PRH_Clk
OPB_Clk
CLKFB CLK0
CLKIN
DCM1
PRH_Clk
OPB_Clk
OPB EPCExternalDevice
CLK
FPGA
Example Peripheral Connections
Example SMSC LAN91C111 10100 non-PCI Ethernet Single Chip MAC + PHY
An example peripheral device supported by the OPB EPC is the SMSC 10100 non-PCI Ethernet Single Chip MAC + PHY LAN91C111 The OPB EPC allows OPB masters to access the device both in synchronous and asynchronous mode The device connections for synchronous and asynchronous mode of operations are outlined in the Asynchronous Mode and Synchronous Mode sections
Discontinued IP
ust 10 2007 wwwxilinxcom 21ecification
OPB External Peripheral Controller (EPC) v100a
22
F
Asynchronous Mode
Figure 5 illustrates the SMSC LAN91C111 connections to the OPB EPC in asynchronous mode with non-multiplexed address and data buses In asynchronous mode the input clock source (PRH_Clk) to the external device must be tied to VCC When the SMSC LAN91C111 is accessed through the asynchronous mode the rising edge of PRH_Rd_n and PRH_Wr_n signals are used to control the read and the write operations respectively As the device uses Asynchronous Ready (ARDY) signal to indicate its readiness in asynchronous mode This signal is connected to the PRH_Rdy input of the OPB EPC Since the address and the data buses are not multiplexed PRH_ADS will be driven low by the OPB EPC
The following parameter settings apply for the connections shown in Figure 5
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 5 SMSC LAN91C111 Connection to OPB EPC in Asynchronous Mode
igure Top x-ref 5
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]
PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
To System Interrupt Controller
VCC
LCLKResetAENnADSA[151]
nBE[30]
ARDYnRdnWR
D[310]
INTRO
WnRnVLBUSnCYCLE
nRDYRTNnDADACS
nLDEVnSARDY
SMSC LAN91C111
ExternalGlue Logic
PPC
OP
B B
us
FPGA
DS325_05_071406
ExternalReset VCC
External Glue Logic
Special attention must be given while interfacing the OPB EPC to the SMSC LAN91C111 in asynchronous mode The OPB EPC drives the PRH_BE active high while the SMSC LAN91C111 requires the input byte enable to be active low To match this requirement external glue logic is required to invert the PRH_BE signals before they are interfaced with the byte enable signals of the SMSC LAN91C111
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Synchronous Mode
Figure 6 illustrates the SMSC LAN91C111 connection to the OPB EPC in synchronous VL Bus mode with non-multiplexed address and data buses In synchronous mode the device requires an input clock source to the LCLK pin with a maximum operating frequency of 50MHz The local clock generated by the DCM for the peripheral interface must be routed to the LCLK input of SMSC LAN91C111 and PRH_Clk of OPB EPC When the device is accessed PRH_RNW is used as the control signal to indicate a readwrite access When PRH_RNW is high it indicates a read operation and when low it indicates a write operation The SMSC LAN91C111 uses nSRDY signal to indicate the device readiness This signal is connected to PRH_Rdy input of the OPB_EPC As the address and the data bus are not multiplexed PRH_ADS will be driven low
The following parameter settings apply for the connections shown in Figure 6
bull C_PRH_CLK_SUPPORT = 1
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 1
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 6 SMSC LAN91C111 Connection to OPB EPC in Synchronous Mode
igure Top x-ref 6
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
LCLKResetAENnADSA[151]nBE[30]WnRnSRDY
D[310]
nCYCLEnRDYRTN
INTRO
nRdnWR
nDADACSnLDEVARDY
nVLBUS
SMSC LAN91C111
ExternalGlue Logic
DigitalClock
Manager
PP
C
OP
B B
us
FPGA
DS325_06_071406
External Reset
VCC
GND
To System Interrupt Controller
External Glue Logic
The SMSC LAN91C111 device requires two inputs nCYCLE and nRDYRTN to control synchronous operation The definition of these signals is outside the scope of this document and can be found in the documents listed in the Reference Documents section The nCYCLE and nRDYRTN signals are generated in external glue logic nCYCLE may be generated from PRH_CS_n and is driven low for a
Discontinued IP
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OPB External Peripheral Controller (EPC) v100a
24
single clock cycle on a high to low transition on PRH_CS_n nRDYRTN is simply the registered value of the nSRDY signal
Design Considerations
When the OPB EPC is interfaced to the SMSC LAN91C111 with data width match enabled (C_PRHx_DWIDTH_MATCH = 1) and the internal SRAM of the peripheral is being accessed the device has to be configured in the address auto increment mode Address auto increment mode can be configured by setting AUTO INCR bit in the Bank 2 Pointer Register of SMSC LAN91C111 More information can be obtained by referring the registers of Bank 2 in SMSC LAN91C111 data sheet See the Reference Documents section
Example Cypress Semiconductorrsquos CY7C67300 EZ-Host Programmable Embedded USB HostPeripheral Controller
The Cypress Semiconductorrsquos CY7C67300 EZ-Hosttrade Programmable Embedded USB HostPeripheral Controller is another example of a peripheral device supported by the OPB EPC Since the Cypress USB controller operates in asynchronous mode the OPB EPC must be configured to support asynchronous mode operation
Asynchronous Mode
Figure 7 illustrates the CY7C67300 USB Controller connection to the OPB EPC in asynchronous mode with non-multiplexed address and data buses
The following parameter settings apply for the connection shown in Figure 7
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 4
bull C_PRH0_DWIDTH = 16
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Configuration of CY7C67300 USB Controller
The CY7C67300 USB Controller is configured as a Host Processor Interface (HPI) The boot-up sequence code for the CY7C67300 USB Controller in this particular example is present on the external Compact Flash memory device and is accessed through the OPB SYSACE interface This code is downloaded to the CY7C67300 USB Controller through the HPI interface Once this boot-up sequence is executed by the CY7C67300 USB Controller it becomes ready to operate in normal HPI mode with the external host controller (OPB EPC)
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
F
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 7 CY7C67300 USB Controller connection to OPB EPC in asynchronous mode
igure Top x-ref 7
SysACE_mpd_I[015]SysACE_mpd_O[015]SysACE_mpd_T[015]
SysACE_mpweSysACE_mpoe
SysACE_MPA[06]
SysACE_CEN
OPB SYS ACE Cntlr[150][150][150]
[60]
PRH_RstPRH_Rdy
PRH_CS_n
PRH_Data_I[015]PRH_Data_O[015]PRH_Data_T[015]
PRH_ADSPRH_RRNW
PRH_BurstPRH_Rd_nPRH_Wr_n
PRH_Addr[01]
OPB EPC
VCC
Ext
erna
l US
B P
orts
P
ort 1
A 1
B 2
AnCS
nRD
nWR
[D15D0]
[A1A0]
INT
CompactFLASH
TQFP144 SYSTEMACE
System ACE CompactFlash Controller
Ext
erna
l Glu
e Lo
gic
OPBINTC
US
B C
Y7C
6730
0
PP
C
OP
B B
us
FPGA
DS325_07_071406
Sysace_epc_data[150]
HPI interface
Sysace_epc_rd_n
Sysace_epc_wr_n
Sysace_epc_a[10]
DM1B
DP1B
DM2A
DP2A
DM1A
DP1A
External Glue Logic
In the interface diagram shown in Figure 7 the OPB EPC as well as the OPB SYSACE share the interface for data address and control lines on the board This requires external multiplex logic to be placed outside of IP cores in the FPGA The OPB EPC control signals PRH_RD_n and PRH_WR_n are muxed with the MEM_CEN and MEM_WEN signals of the OPB SYSACE When CY7C67300 USB Controller is accessed through the asynchronous mode the rising edge of sysace_epc_rd_n and sysace_epc_wr_n signals are used to control the read and the write operations respectively See the Reference Documents section for more information on OPB SYSACE
Design Constraints
Timing Constraints
Timing constraints must be placed on the system clock and the peripheral clock setting the frequency to meet the bus timing requirements An example is shown in Figure 8
Discontinued IP
ust 10 2007 wwwxilinxcom 25ecification
F
OPB External Peripheral Controller (EPC) v100a
26
Figure 8 EPC Timing Constraints
igure Top x-ref 8
Following constraint must be placed on the system clock
TIMESPEC TS_OPB_Clk = PERIOD OPB_Clk 10 ns HIGH 50
NET OPB_Clk TNM_NET = OPB_Clk
If C_PRH_CLK_SUPPORT=1 then the following constraint must be placed on the peripheral clock
TIMESPEC TS_PRH_Clk = PERIOD PRH_Clk 20 ns HIGH 50
NET PRH_Clk TNM_NET = PRH_Clk
DS325_08_071406
Design Implementation
Timing Diagrams
The timing diagrams in the figures below show various OPB transactions and the resulting access cycles on the peripheral interface Timing diagrams are not shown for all possible combinations of generics and the resulting access cycles However the timing diagrams shown are sufficient for the basic understanding of various access cycles supported by the OPB EPC
Figure 9 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 9
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
DS325_09_071206
8
4000000
004
04
Figure 10 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 10
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
04000000
20000004
8
00000000
004
04DS325_10_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 11 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 11
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000000
F
00010203
000 001 002 003
00 01 02 03DS325_11_071206
Figure 12 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 12
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
20000000
F
0000000000000000
000 001 002 003
00 01 02 03DS325_12_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 27ecification
OPB External Peripheral Controller (EPC) v100a
28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 29ecification
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
10
G19 Peripheral access mode C_PRHx_SYNC(1 3)
0 = External device is asynchronous 1 = External device is synchronous
1 integer
G20 Peripheral bus typeC_PRHx_BUS_MULTIPLEX(3)
0 = External device has separate address and data bus1 = External device has multiplexed address and data bus
0 integer
OPB EPC Timing Parameters
G21
Address bus (PRH_Addr) setup with respect to rising edge of address strobe (PRH_ADS) or falling edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_ADDR_TSU(3 10)
Integer number of picoseconds
User must set values(11)
integer
G22
Address bus (PRH_Addr) hold with respect to falling edge of address strobe (PRH_ADS) or rising edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_ADDR_TH(3 12 16 19)
Integer number of picoseconds
User must set values(11)
integer
G23Minimum pulse width of address strobe (PRH_ADS)
C_PRHx_ADS_WIDTH(3)
Integer number of picoseconds
User must set values(11)
integer
G24
Chip select (PRH_CS_n) setup with respect to falling edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_CSN_TSU(3 10)
Integer number of picoseconds
User must set values(13)
integer
G25
Chip select (PRH_CS_n) hold with respect to rising edge of readwrite (PRH_Rd_n PRH_Wr_n)
C_PRHx_CSN_TH(3 16 19)
Integer number of picoseconds
User must set values(13)
integer
G26Minimum pulse width of write signal (PRH_Wr_n)
C_PRHx_WRN_WIDTH(3 14 15 16)
Integer number of picoseconds
User must set values(13)
integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G27Cycle time of write signal (PRH_Wr_n)
C_PRHx_WR_CYCLE(3 15 16)
Integer number of picoseconds
User must set values(13)
integer
G28
Data bus (PRH_Data) setup with respect to falling edge of write signal (PRH_Wr_n)
C_PRHx_DATA_TSU(3 14)
Integer number of picoseconds
User must set values(13)
integer
G29
Data bus (PRH_Data) hold with respect to rising edge of write signal (PRH_Wr_n)
C_PRHx_DATA_TH(3 16)
Integer number of picoseconds
User must set values(13)
integer
G30Minimum pulse width of read signal (PRH_Rd_n)
C_PRHx_RDN_WIDTH(3 17 18 19)
Integer number of picoseconds
User must set values(13)
integer
G31Cycle time of read signal (PRH_Rd_n)
C_PRHx_RD_CYCLE(3 18 19)
Integer number of picoseconds
User must set values(13)
integer
G32
Data bus (PRH_Data) validity from falling edge of read signal (PRH_Rd_n)
C_PRHx_DATA_TOUT(3 17)
Integer number of picoseconds
User must set values(13)
integer
G33
Data bus (PRH_Data) high impedance from rising edge of read (PRH_Rd_n)
C_PRHx_DATA_TINV(3 19)
Integer number of picoseconds
User must set values(13)
integer
G34
Device ready (PRH_Rdy) validity from the falling edge of read or write (PRH_Rd_n PRH_Wr_n)
C_PRHx_RDY_TOUT(3 20 22)
Integer number of picoseconds
User must set values(13)
integer
G35
Maximum period of device ready signal (PRH_Rdy) to wait before device timeout
C_PRHx_RDY_WIDTH(3 21 22)
Integer number of picoseconds
User must set values(23)
integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
ust 10 2007 wwwxilinxcom 11ecification
OPB External Peripheral Controller (EPC) v100a
12
Notes 1 The generic C_PRH_CLK_SUPPORT is relevant only when the device is configured for synchronous access
ie C_PRHx_SYNC = 1 If more than one device is synchronous then the frequency for the peripheral clock (PRH_Clk) should be chosen as the minimum of the operating frequencies of those devices
2 The C_PRH_MAX_ADWIDTH determines the size of the data bus For all non multiplexed devices the C_PRH_MAX_ADWIDTH reflects the maximum of data bus width of all external devices ie C_PRH_MAX_ADWIDTH equals C_PRH_MAX_DWIDTH However if any of the devices is configured for multiplexed address and data bus then C_PRH_MAX_ADWIDTH should be set as the maximum of data bus of all external devices and the address bus of device(s) employing multiplexed address and data bus
3 rsquoxrsquo in the generic refers to the number of the peripheral device and takes a value in the range of 0 to C_NUM_PERIPHERALS - 1
4 OPB EPC design can accommodate up to four peripheral devices The address range for the devices are designated as C_PRH0_BASEADDR C_PRH0_HIGHADDR C_PRH1_BASEADDR C_PRH1_HIGHADDR etc
5 The range specified by C_PRHx_BASEADDR and C_PRHx_HIGHADDR must comprise a contiguous range and the size of the range must be a power of two ie size of range = 2m Further the rsquomrsquo least significant bits of C_PRHx_BASEADDR must be zero The base and high address range assigned to different peripherals must be mutually exclusive
6 No default value will be specified to ensure that the actual value is set ie if the value is not set a compiler error will be generated
7 C_PRHx_FIFO_ACCESS must be set to 1 if the support for access to FIFO within external peripheral device is to be included
8 C_PRHx_FIFO_OFFSET is the byte offset of the external peripheral FIFO from the base address (C_PRHx_BASEADDR) of the peripheral irrespective of the data width of the peripheral device If C_PRHx_FIFO_ACCESS = 1 then C_PRHx_FIFO_OFFSET must be set to a valid offset within the address range assigned to the peripheral
9 The generic C_PRHx_DWIDTH_MATCH is relevant only when the width of the peripheral data (PRH_Data) bus is less than the OPB data bus (OPB_DBus)
10Address setup time is with respect to falling edge of address strobe (PRH_ADS) if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 and must be set both in synchronous and asynchronous mode Address setup time is with respect to falling edge of readwrite signals (PRH_Wr_nPRH_Rd_n) if the device is non multiplexed and is relevant only if the access mode is asynchronous
11Value for the parameter must be assigned if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 This parameter assignment is appicalble for synchronous and asynchronous devices
12Address hold time is with respect to falling edge of address strobe (PRH_ADS) if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 and must be set both in synchronous and asynchronous mode Address hold time is with respect to rising edge of readwrite signals (PRH_Wr_nPRH_Rd_n) if the address and the data bus are separate and is relevant only if the access mode is asynchronous
13Value must be assigned if the access mode of the peripherals is asynchronous ie C_PRHx_SYNC = 0 If the access mode of the peripheral is synchronous ie C_PRHx_SYNC = 1 then the zero should be assigned to the parameter
14Write signal (PRH_Wr_n) low time is the maximum of C_PRHx_WRN_WIDTH and C_PRHx_DATA_TSU15The value of C_PRHx_WRN_WIDTH must be smaller than C_PRHx_WR_CYCLE16 In non-multiplexed address and data bus mode write recovery time will be maximum of C_PRHx_ADDR_TH
C_PRHx_CSN_TH C_PRHx_DATA_TH and PRH_Wr_n high time (ie C_PRHx_WR_CYCLE minus C_PRHx_WRN_WIDTH) If the peripheral uses multiplexed address and data bus then the write recovery time will be maximum of C_PRHx_CSN_TH C_PRHx_DATA_TH and PRH_Wr_n high time
17Read signal (PRH_Rd_n) low time is the maximum of C_PRHx_RDN_WIDTH and C_PRHx_DATA_TOUT18The value of C_PRHx_RDN_WIDTH must be smaller than C_PRHx_RD_CYCLE19 In non-multiplexed address and data bus mode read recovery time will be maximum of C_PRHx_ADDR_TH
C_PRHx_CSN_TH C_PRHx_DATA_TINV and PRH_Rd_n high time (ie C_PRHx_RD_CYCLE minus C_PRHx_RDN_WIDTH) If the peripheral uses multiplexed address and data bus then the read recovery time will be maximum of C_PRHx_CSN_TH C_PRHx_DATA_TINV and PRH_Rd_n high time
20Device ready validity period (C_PRHx_RDY_TOUT) must be set as the maximum of the values specified for read and write transactions
21Device ready pulse width (C_PRHx_RDY_WIDTH) must be set as the maximum of the values specified for read and write transactions
22Device ready validity (C_PRHx_RDY_TOUT) period must be less than the write strobe width (C_PRHx_WRN_WIDTH) read strobe width (C_PRHx_RDN_WIDTH) and device ready signal width (C_PRHx_RDY_WIDTH)
23Device ready signal width (C_PRHx_RDY_WIDTH) must be set for both synchronous and asynchronous
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
access mode in order to prevent the device from holding the OPB indefinitely24Current version of the OPB EPC do not support the burst transactions tofrom the OPB
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Allowable Parameter Combinations
When the peripheral devices are confugured in non multiplexed mode the C_PRH_MAX_AWIDTH should be the maximum of C_PRHx_AWIDTH of all peripherals in the system ie if C_NUM_PERIPHERALS is 2 then C_PRH_MAX_AWIDTH should be maximum of C_PRH0_AWIDTH and C_PRH1_AWIDTH
C_PRH_MAX_DWIDTH should be the maximum of C_PRHx_DWIDTH of all peripherals in the system ie if C_NUM_PERIPHERALS is 2 then C_PRH_MAX_DWIDTH should be maximum of C_PRH0_DWIDTH and C_PRH1_DWIDTH
If any of the peripheral devices are configured for a multiplexed address and data buses then the parameter C_PRH_MAX_ADWIDTH should be set as the maximum of the data bus and address bus of the device(s) employing a multiplexed address and data bus If all devices employ non-multiplexed address and data buses then C_PRH_MAX_ADWIDTH reflects the maximum of data bus width of all external devices Therefore for any configuration the parameter C_PRH_MAX_ADWIDTH should be greater than or equal to C_PRH_MAX_DWIDTH
The generic C_PRH_CLK_SUPPORT is relevant only when the devices are configured for the synchronous access ie C_PRHx_SYNC = 1 If more than one of the devices are synchronous then the frequency for the peripheral clock should be chosen as the minimum of the operating frequencies of those devices
The range specified by C_PRHx_BASEADDR and C_PRHx_HIGHADDR parameters must comprise a contiguous range and the size of the range must be a power of two ie size of range = 2m Furthermore the rsquomrsquo least significant bits of C_PRHx_BASEADDR must be zero The base and high address range assigned to different peripherals must be mutually exclusive No default value will be specified for C_PRHx_BASEADDR and C_PRHx_HIGHADDR in order to enforce that the user configures these parameters with the actual values If the values are not set for C_PRHx_BASEADDR and C_PRHx_HIGHADDR a compiler error will be generated
In order to access FIFO like structures within the external peripheral devices C_PRHx_FIFO_ACCESS must be set to rsquo1rsquo When FIFO access is enabled C_PRHx_FIFO_OFFSET specifies the offset of the FIFO in terms of number of byte locations from the base address (C_PRHx_BASEADDR) of the peripheral and should be set to an offset that lies within the address range assigned to the peripheral device ie C_PRHx_BASEADDR + C_PRHx_FIFO_OFFSET le C_PRHx_HIGHADDR Furthermore the FIFO offset should be within the range addressable by the address bus ie C_PRHx_FIFO_OFFSET lt 2n
where n = C_PRHx_AWIDTH
The width of the readwrite strobe must be less than the cycle time of the corresponding access ie C_PRHx_WRN_WIDTH lt C_PRHx_WR_CYCLE and C_PRHx_RDN_WIDTH lt C_PRHx_RD_CYCLE The value of device ready validity period must be less than the readwrite strobe width and the maximum pulse width of the device ready signal ie C_PRHx_RDY_TOUT lt minimum of C_PRHx_WRN_WIDTH C_PRHx_RDN_WIDTH and C_PRHx_RDY_WIDTH
Parameter - Port Dependencies
The dependencies between the OPB EPC design parameters and the IO ports are shown in Table 3 The width of the OPB EPC signals depend on some of the parameters In addition when certain features are parameterized away the related logic is removed
Discontinued IP
ust 10 2007 wwwxilinxcom 13ecification
OPB External Peripheral Controller (EPC) v100a
14
Table 3 Parameter - Port Dependencies
Generic or Port
Name Affects Depends Description
Design Parameters
G3 C_OPB_AWIDTH P1 -The OPB address width parameter sets the width of the OPB address bus
G4 C_OPB_DWIDTHP2 P3
P7-
The OPB data width parameter affects the number of byte enables configured for the OPB data bus width of the OPB data bus and the width of the OPB slave read data bus
G6C_NUM_PERIPHERALS
P16 P24-
The number of peripherals in the system determines the number of chip select signals driven and the number of device ready inputs decoded by the OPB external peripheral controller
G7C_PRH_MAX_AWIDTH
P17- The width of the peripheral address bus is set to
the maximum of address bus width of all peripheral devices
G8C_PRH_MAX_DWIDTH
P19- The number of byte enables for the peripheral data
bus is determined by the maximum of data bus width of the peripheral devices
G9C_PRH_MAX_ADWIDTH
P25 P26 P27
-
The width of the peripheral input data bus peripheral output data bus and the peripheral output data bus 3-state control are determined by the maximum of data bus width of all peripherals and the address bus width of peripherals employing address data bus multiplexing
G10C_PRH_CLK_SUPPORT
P14- If C_PRH_CLK_SUPPORT = 0 then all external
devices operate on OPB clock The input PRH_Clk must be driven high externally
G18C_PRHx_DWIDTH_MATCH
P23-
If the device is configured for synchronous mode with data width matching enabled then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G19 C_PRHx_SYNCP14 P20 P21 P22
P23
-
If the device is configured for asynchronous mode
bull With peripheral clock support the peripheral clock input (PRH_Clk) must be driven high externally
bull PRH_RNW is driven high as PRH_Rd_n and PRH_Wr_n should be used as read and write strobe
bull With data width matching enabled the OPB EPC drives PRH_Burst to its default low
If the device is configured for synchronous mode
bull The OPB EPC drives PRH_Rd_n and PRH_Wr_n outputs to their default state of high since PRH_RNW output is used as readwrite strobe
G20C_PRHx_BUS_MULTIPLEX
P18- PRH_ADS is driven low if the device does not use
multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
IO Signals
P1 OPB_ABus - G3The OPB address bus width is determined by the C_OPB_AWIDTH parameter
P2 OPB_BE - G4The number of byte enables for the OPB data bus is determined by the C_OPB_DWIDTH parameter
P3 OPB_DBus - G4The OPB data bus width is determined by the C_OPB_DWIDTH parameter
P7 Sln_DBus-
G4The width of the OPB slave read data bus is determined by the C_OPB_DWIDTH parameter
P14 PRH_Clk-
G10 G19
PRH_Clk is selected as operating clock only if the device is configured for synchronous mode with peripheral clock support ie C_PRHx_SYNC = 1 and C_PRH_CLK_SUPPORT = 1 Asynchronous interface always operates on OPB_Clk Therefore if no device is configured for synchronous mode with peripheral clock support enabled then the input PRH_Clk must be driven high
P16 PRH_CS_n-
G6The number of chip select signals driven by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P17 PRH_Addr-
G7The width of the peripheral address bus is determined by the C_PRH_MAX_AWIDTH parameter
P18 PRH_ADS-
G20PRH_ADS is driven low if the device does not use multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
Discontinued IP
ust 10 2007 wwwxilinxcom 15ecification
OPB External Peripheral Controller (EPC) v100a
16
OPB EPC Design Considerations
The OPB EPC is an OPB slave only device It receives read or write instructions from the processor and generates a corresponding access cycle on the peripheral interface Examples of read and write accesses are illustrated in the Timing Diagrams section The user must take the following considerations into account while designing with the OPB EPC
Device Ready Signal
The OPB EPC readwrite access cycles are executed only when the external device assert the device ready signal (PRH_Rdy) If the external peripheral device does not have a device ready signal then the PRH_Rdy input of the OPB EPC must be tied to logic high
P19 PRH_BE - G8The number of byte enables for the peripheral data bus is determined by the C_PRH_MAX_DWIDTH parameter
P20 PHR_RNW-
G19
If the device is synchronous ie C_PRHx_SYNC = 1 then PRH_RNW should be used as the readwrite control signal For asynchronous mode of operation PRH_RNW is driven high
P21 PRH_Rd_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Rd_n should be used as the read strobe For synchronous mode of operation PRH_Rd_n is driven high
P22 PRH_Wr_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Wr_n should be used as the write strobe For synchronous mode of operation PRH_Wr_n is driven high
P23 PRH_Burst-
G18 G19
If the device is synchronous with data width matching enabled ie C_PRHx_SYNC = 1 and C_PRHx_DWIDTH_MATCH = 1 then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
P24 PRH_Rdy-
G6The number of device ready inputs decoded by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P25 PRH_Data_I-
G9The peripheral input data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P26 PRH_Data_O - G9The peripheral output data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P27 PRH_Data_T - G9
The peripheral output data bus 3-state control width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
FIFO Transactions
When C_PRHx_FIFO_ACCESS = 1 the OPB EPC supports access to FIFOrsquos within the external peripheral devices When the FIFO within the external device is accessed then the peripheral address bus (PRH_Addr) must remain constant representing the FIFO address within the address range assigned to the peripheral device When data width matching is enabled and the access corresponds to the FIFO the OPB EPC does not increment the peripheral address (PRH_Addr) bus
Abnormal Terminations
If PRH_Rdy is de-asserted for more than the maximum period as specified by C_PRHx_RDY_WIDTH then the OPB EPC terminates the current access to the external device and signals an error to the OPB master by asserting Sln_errAck on the OPB Similarly when the OPB master terminates the current access (master abort on the OPB) OPB EPC terminates the access to the external device immediately In both cases the access to the external device is terminated abnormally Therefore the external device may be in an indeterminate state and the exceptions should be handled appropriately at the system level
Interrupt Handling
If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Peripheral Data Bus Mapping
The peripheral data bus (PRH_Data) uses big endian bit labelling (ie bit-0 is Most Significant Bit (MSB) and bit-31 is Least Significant Bit (LSB) for a 32-bit bus) and is sized according to the C_PRH_MAX_ADWIDTH parameter Peripherals that have smaller widths should connect to this bus starting at bit 0 (MSB) For example if three external devices are present in the system with data bus width of 8-bit 16-bit and 32-bit the 8-bit device should connect to PRH_Data[07] the 16-bit wide peripheral should connect to PRH_Data[015] and the 32-bit peripheral should connect to PRH_Data[031]
The bit and byte labeling for the big endian data types is shown in Figure 3
Discontinued IP
ust 10 2007 wwwxilinxcom 17ecification
F
OPB External Peripheral Controller (EPC) v100a
18
Figure 3 OPB EPC Big Endian Data Type
igure Top x-ref 3
2 3
n+2 n+3
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 15
Halfword
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 31
Word
Byte
MS Byte
LS BitMS Bit
0
nByte address
Byte label
Byte significance
Bit label
Bit significance
0 7
DS325_03_071406
Unsupported Features
Many peripheral devices have the device specific inputoutput ports such as status remote reset remote wakeup interrupts etc The OPB EPC does not have any provision to support these device specific inputoutput ports Therefore if the external device has any such device specific ports then these inputoutput ports may be connected directly to system general purpose input output controller or to the system interrupt controller If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Many peripheral devices support DMA capability However currently OPB EPC is an OPB slave only device and therefore does not support DMA operations from the external peripheral devices
Current version of the OPB EPC does not support burst transactions tofrom the OPB
OPB EPC Latency
The OPB EPC latency calculations are based on the OPB clock The OPB latency is defined as the number of OPB clock cycles elapsed from the time an access is initiated to the time the access is completed (Sln_xferAck is asserted) on the OPB Table 4 shows the latency calculations for asynchronous mode and Table 5 shows the latency calculations for synchronous mode of operation
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OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 4 Asynchronous Mode OPB EPC Latency
Transaction Type
ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation(1)
OPB Latency
50 MHz
OPB Latency 100 MHz
ReadWrite access to asynchronous device when addressdata bus is not multiplexed
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5)
9(7) 12(7)
1FIFO
Memory
5 + N(2) (T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5))
21(7) 33(7)
ReadWrite access to asynchronous device when addressdata bus is multiplexed (Register access)
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + (T_SETUP(3) + T_ADDR_HOLD(6) + 1 + CONTROL_WIDTH(4) + T_HOLD(5))
11(7) 14(7)
1 FIFO
5 + T_SETUP(3) + T_ADDR_HOLD(6) + 1 + N(2) (CONTROL_WIDTH(4) + T_HOLD(5))
20(7) 29(7)
1 Memory
4 + N(2) (T_SETUP(3) + T_ADDR_HOLD(6) + CONTROL_WIDTH(4) + T_HOLD(5) + 2)
32(7) 44(7)
Notes 1 Latency calculations assumes the device is always ready2 If C_PRHx_DWIDTH_MATCH = 1 then N = Access size on OPB (in bytes)width of peripheral data bus (in
bytes)3 T_SETUP is the setup time requirement on various control signals in terms of number of OPB clocks and is
device specific4 CONTROL_WIDTH represents the required width for readwrite signal in terms of number of OPB clocks and
is device specific 5 T_HOLD is the hold time requirement on various control signals in terms of number of OPB clocks and is
device specific6 T_ADDR_HOLD is the required hold time on the address bus (as specified by generic C_PRHx_ADDR_TH) in
terms of number of OPB clocks and is device specific 7 Calculation are made for typical values of various timing parameters with T_SETUP = 20ns T_HOLD = 10ns
T_ADDR_HOLD = 6ns and STROBE_WIDTH = 40ns
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ust 10 2007 wwwxilinxcom 19ecification
OPB External Peripheral Controller (EPC) v100a
20
Table 5 Synchronous Mode OPB EPC Latency
Transaction Type ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory 9
1FIFO
Memory 8 + N(2)
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory 11
1 FIFO 10 + N(2)
1 Memory 6 + 5N(2)
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 7 peripheral clocks
1FIFO
Memory
7 OPB clocks + (6+N(2)) peripheral clocks
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 9 peripheral clocks
1 FIFO7 OPB clocks + (8+N(2)) peripheral clocks
1 Memory7 OPB clocks + (4+5N(2)) peripheral clocks
Notes 1 Latency calculations assumes the device is always ready2 N = Access size on the OPB (in bytes)width of peripheral data bus (in bytes) where access size on OPB
equals or less than C_OPB_DWIDTH expressed in terms of bytes3 Latency calculation assumes that the requirement on address setup (C_PRHx_ADDR_TSU) address hold
(C_PRHx_ADDR_TH) and ADS pulse width (C_PRHx_ADS_WIDTH) are all less than one OPB clock
OPB EPC External Peripheral ConnectionsThe OPB EPC interface to the external device is based upon the width of the OPB data bus address and data width of the peripheral subsystem number of peripherals in the system addressdata multiplex support mode of operation (synchronous or asynchronous) and if synchronous device the operating clock for the synchronous data path
Determining Address and Data Width
The address bus width of the peripheral subsystem is the maximum width of the address bus of all peripheral devices connected to the OPB EPC If all devices employ non-multiplexed address and data bus the data bus width of the peripheral subsystem is the maximum of the data bus width of all external devices If any of the devices are configured for multiplexed address and data bus then the data bus width of the peripheral subsystem should be set as the maximum of the data bus and the address bus of the device(s) employing a multiplexed address and data bus
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DS325 AugProduct Sp
F
Endian Considerations
The peripheral address and data bus of the OPB EPC is labeled with big endian bit labeling (D0 is the MSB and D31 is the LSB for a 32-bit bus) while most peripheral devices are either endian agnostic ie they can be connected either way or little endian (D31 is the MSB and D0 is the LSB for a 32-bit bus) Caution must be exercised with the connection to the external peripheral devices to avoid incorrect data and address connections
Clock Generation
When connecting to a synchronous external device the OPB EPC may operate either on the OPB clock (OPB_Clk) or on a peripheral clock (PRH_Clk) The operating clock for the synchronous interface is based on the generic C_PRH_CLK_SUPPORT If C_PRH_CLK_SUPPORT = 1 the peripheral clock is used else the OPB clock is used The external devices connected to the OPB EPC will determine the operating frequency of the peripheral clock The minimum of the operating frequencies of various devices connected to OPB EPC should be used as the operating frequency of the peripheral clock (PRH_Clk)
Figure 4 illustrates a block diagram for generating a device specific clock source clock source using two DCMs The DCM modules are located within the FPGA but are external to the OPB EPC An external clock source is used to generate the OPB clock (OPB_Clk) to the OPB EPC The device clock source (PRH_Clk) is also generated from the same DCM (DCM0) using the CLKFX output and must be routed on the board to be fed back to the FPGA Another DCM (DCM1) is used to synchronize the device peripheral clock to the OPB EPC PRH_Clk
Figure 4 External Peripherals clocked by FPGA output with feedback
igure Top x-ref 4
DS325_04_071406
CLKFB CLK0
CLKFXCLKIN
DCM0
PRH_Clk_FB
PRH_Clk
OPB_Clk
CLKFB CLK0
CLKIN
DCM1
PRH_Clk
OPB_Clk
OPB EPCExternalDevice
CLK
FPGA
Example Peripheral Connections
Example SMSC LAN91C111 10100 non-PCI Ethernet Single Chip MAC + PHY
An example peripheral device supported by the OPB EPC is the SMSC 10100 non-PCI Ethernet Single Chip MAC + PHY LAN91C111 The OPB EPC allows OPB masters to access the device both in synchronous and asynchronous mode The device connections for synchronous and asynchronous mode of operations are outlined in the Asynchronous Mode and Synchronous Mode sections
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OPB External Peripheral Controller (EPC) v100a
22
F
Asynchronous Mode
Figure 5 illustrates the SMSC LAN91C111 connections to the OPB EPC in asynchronous mode with non-multiplexed address and data buses In asynchronous mode the input clock source (PRH_Clk) to the external device must be tied to VCC When the SMSC LAN91C111 is accessed through the asynchronous mode the rising edge of PRH_Rd_n and PRH_Wr_n signals are used to control the read and the write operations respectively As the device uses Asynchronous Ready (ARDY) signal to indicate its readiness in asynchronous mode This signal is connected to the PRH_Rdy input of the OPB EPC Since the address and the data buses are not multiplexed PRH_ADS will be driven low by the OPB EPC
The following parameter settings apply for the connections shown in Figure 5
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 5 SMSC LAN91C111 Connection to OPB EPC in Asynchronous Mode
igure Top x-ref 5
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]
PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
To System Interrupt Controller
VCC
LCLKResetAENnADSA[151]
nBE[30]
ARDYnRdnWR
D[310]
INTRO
WnRnVLBUSnCYCLE
nRDYRTNnDADACS
nLDEVnSARDY
SMSC LAN91C111
ExternalGlue Logic
PPC
OP
B B
us
FPGA
DS325_05_071406
ExternalReset VCC
External Glue Logic
Special attention must be given while interfacing the OPB EPC to the SMSC LAN91C111 in asynchronous mode The OPB EPC drives the PRH_BE active high while the SMSC LAN91C111 requires the input byte enable to be active low To match this requirement external glue logic is required to invert the PRH_BE signals before they are interfaced with the byte enable signals of the SMSC LAN91C111
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OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Synchronous Mode
Figure 6 illustrates the SMSC LAN91C111 connection to the OPB EPC in synchronous VL Bus mode with non-multiplexed address and data buses In synchronous mode the device requires an input clock source to the LCLK pin with a maximum operating frequency of 50MHz The local clock generated by the DCM for the peripheral interface must be routed to the LCLK input of SMSC LAN91C111 and PRH_Clk of OPB EPC When the device is accessed PRH_RNW is used as the control signal to indicate a readwrite access When PRH_RNW is high it indicates a read operation and when low it indicates a write operation The SMSC LAN91C111 uses nSRDY signal to indicate the device readiness This signal is connected to PRH_Rdy input of the OPB_EPC As the address and the data bus are not multiplexed PRH_ADS will be driven low
The following parameter settings apply for the connections shown in Figure 6
bull C_PRH_CLK_SUPPORT = 1
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 1
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 6 SMSC LAN91C111 Connection to OPB EPC in Synchronous Mode
igure Top x-ref 6
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
LCLKResetAENnADSA[151]nBE[30]WnRnSRDY
D[310]
nCYCLEnRDYRTN
INTRO
nRdnWR
nDADACSnLDEVARDY
nVLBUS
SMSC LAN91C111
ExternalGlue Logic
DigitalClock
Manager
PP
C
OP
B B
us
FPGA
DS325_06_071406
External Reset
VCC
GND
To System Interrupt Controller
External Glue Logic
The SMSC LAN91C111 device requires two inputs nCYCLE and nRDYRTN to control synchronous operation The definition of these signals is outside the scope of this document and can be found in the documents listed in the Reference Documents section The nCYCLE and nRDYRTN signals are generated in external glue logic nCYCLE may be generated from PRH_CS_n and is driven low for a
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24
single clock cycle on a high to low transition on PRH_CS_n nRDYRTN is simply the registered value of the nSRDY signal
Design Considerations
When the OPB EPC is interfaced to the SMSC LAN91C111 with data width match enabled (C_PRHx_DWIDTH_MATCH = 1) and the internal SRAM of the peripheral is being accessed the device has to be configured in the address auto increment mode Address auto increment mode can be configured by setting AUTO INCR bit in the Bank 2 Pointer Register of SMSC LAN91C111 More information can be obtained by referring the registers of Bank 2 in SMSC LAN91C111 data sheet See the Reference Documents section
Example Cypress Semiconductorrsquos CY7C67300 EZ-Host Programmable Embedded USB HostPeripheral Controller
The Cypress Semiconductorrsquos CY7C67300 EZ-Hosttrade Programmable Embedded USB HostPeripheral Controller is another example of a peripheral device supported by the OPB EPC Since the Cypress USB controller operates in asynchronous mode the OPB EPC must be configured to support asynchronous mode operation
Asynchronous Mode
Figure 7 illustrates the CY7C67300 USB Controller connection to the OPB EPC in asynchronous mode with non-multiplexed address and data buses
The following parameter settings apply for the connection shown in Figure 7
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 4
bull C_PRH0_DWIDTH = 16
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Configuration of CY7C67300 USB Controller
The CY7C67300 USB Controller is configured as a Host Processor Interface (HPI) The boot-up sequence code for the CY7C67300 USB Controller in this particular example is present on the external Compact Flash memory device and is accessed through the OPB SYSACE interface This code is downloaded to the CY7C67300 USB Controller through the HPI interface Once this boot-up sequence is executed by the CY7C67300 USB Controller it becomes ready to operate in normal HPI mode with the external host controller (OPB EPC)
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F
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 7 CY7C67300 USB Controller connection to OPB EPC in asynchronous mode
igure Top x-ref 7
SysACE_mpd_I[015]SysACE_mpd_O[015]SysACE_mpd_T[015]
SysACE_mpweSysACE_mpoe
SysACE_MPA[06]
SysACE_CEN
OPB SYS ACE Cntlr[150][150][150]
[60]
PRH_RstPRH_Rdy
PRH_CS_n
PRH_Data_I[015]PRH_Data_O[015]PRH_Data_T[015]
PRH_ADSPRH_RRNW
PRH_BurstPRH_Rd_nPRH_Wr_n
PRH_Addr[01]
OPB EPC
VCC
Ext
erna
l US
B P
orts
P
ort 1
A 1
B 2
AnCS
nRD
nWR
[D15D0]
[A1A0]
INT
CompactFLASH
TQFP144 SYSTEMACE
System ACE CompactFlash Controller
Ext
erna
l Glu
e Lo
gic
OPBINTC
US
B C
Y7C
6730
0
PP
C
OP
B B
us
FPGA
DS325_07_071406
Sysace_epc_data[150]
HPI interface
Sysace_epc_rd_n
Sysace_epc_wr_n
Sysace_epc_a[10]
DM1B
DP1B
DM2A
DP2A
DM1A
DP1A
External Glue Logic
In the interface diagram shown in Figure 7 the OPB EPC as well as the OPB SYSACE share the interface for data address and control lines on the board This requires external multiplex logic to be placed outside of IP cores in the FPGA The OPB EPC control signals PRH_RD_n and PRH_WR_n are muxed with the MEM_CEN and MEM_WEN signals of the OPB SYSACE When CY7C67300 USB Controller is accessed through the asynchronous mode the rising edge of sysace_epc_rd_n and sysace_epc_wr_n signals are used to control the read and the write operations respectively See the Reference Documents section for more information on OPB SYSACE
Design Constraints
Timing Constraints
Timing constraints must be placed on the system clock and the peripheral clock setting the frequency to meet the bus timing requirements An example is shown in Figure 8
Discontinued IP
ust 10 2007 wwwxilinxcom 25ecification
F
OPB External Peripheral Controller (EPC) v100a
26
Figure 8 EPC Timing Constraints
igure Top x-ref 8
Following constraint must be placed on the system clock
TIMESPEC TS_OPB_Clk = PERIOD OPB_Clk 10 ns HIGH 50
NET OPB_Clk TNM_NET = OPB_Clk
If C_PRH_CLK_SUPPORT=1 then the following constraint must be placed on the peripheral clock
TIMESPEC TS_PRH_Clk = PERIOD PRH_Clk 20 ns HIGH 50
NET PRH_Clk TNM_NET = PRH_Clk
DS325_08_071406
Design Implementation
Timing Diagrams
The timing diagrams in the figures below show various OPB transactions and the resulting access cycles on the peripheral interface Timing diagrams are not shown for all possible combinations of generics and the resulting access cycles However the timing diagrams shown are sufficient for the basic understanding of various access cycles supported by the OPB EPC
Figure 9 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 9
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
DS325_09_071206
8
4000000
004
04
Figure 10 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 10
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
04000000
20000004
8
00000000
004
04DS325_10_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 11 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 11
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000000
F
00010203
000 001 002 003
00 01 02 03DS325_11_071206
Figure 12 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 12
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
20000000
F
0000000000000000
000 001 002 003
00 01 02 03DS325_12_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 27ecification
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28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 29ecification
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN 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ESP 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FRA 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ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR 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50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G27Cycle time of write signal (PRH_Wr_n)
C_PRHx_WR_CYCLE(3 15 16)
Integer number of picoseconds
User must set values(13)
integer
G28
Data bus (PRH_Data) setup with respect to falling edge of write signal (PRH_Wr_n)
C_PRHx_DATA_TSU(3 14)
Integer number of picoseconds
User must set values(13)
integer
G29
Data bus (PRH_Data) hold with respect to rising edge of write signal (PRH_Wr_n)
C_PRHx_DATA_TH(3 16)
Integer number of picoseconds
User must set values(13)
integer
G30Minimum pulse width of read signal (PRH_Rd_n)
C_PRHx_RDN_WIDTH(3 17 18 19)
Integer number of picoseconds
User must set values(13)
integer
G31Cycle time of read signal (PRH_Rd_n)
C_PRHx_RD_CYCLE(3 18 19)
Integer number of picoseconds
User must set values(13)
integer
G32
Data bus (PRH_Data) validity from falling edge of read signal (PRH_Rd_n)
C_PRHx_DATA_TOUT(3 17)
Integer number of picoseconds
User must set values(13)
integer
G33
Data bus (PRH_Data) high impedance from rising edge of read (PRH_Rd_n)
C_PRHx_DATA_TINV(3 19)
Integer number of picoseconds
User must set values(13)
integer
G34
Device ready (PRH_Rdy) validity from the falling edge of read or write (PRH_Rd_n PRH_Wr_n)
C_PRHx_RDY_TOUT(3 20 22)
Integer number of picoseconds
User must set values(13)
integer
G35
Maximum period of device ready signal (PRH_Rdy) to wait before device timeout
C_PRHx_RDY_WIDTH(3 21 22)
Integer number of picoseconds
User must set values(23)
integer
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
ust 10 2007 wwwxilinxcom 11ecification
OPB External Peripheral Controller (EPC) v100a
12
Notes 1 The generic C_PRH_CLK_SUPPORT is relevant only when the device is configured for synchronous access
ie C_PRHx_SYNC = 1 If more than one device is synchronous then the frequency for the peripheral clock (PRH_Clk) should be chosen as the minimum of the operating frequencies of those devices
2 The C_PRH_MAX_ADWIDTH determines the size of the data bus For all non multiplexed devices the C_PRH_MAX_ADWIDTH reflects the maximum of data bus width of all external devices ie C_PRH_MAX_ADWIDTH equals C_PRH_MAX_DWIDTH However if any of the devices is configured for multiplexed address and data bus then C_PRH_MAX_ADWIDTH should be set as the maximum of data bus of all external devices and the address bus of device(s) employing multiplexed address and data bus
3 rsquoxrsquo in the generic refers to the number of the peripheral device and takes a value in the range of 0 to C_NUM_PERIPHERALS - 1
4 OPB EPC design can accommodate up to four peripheral devices The address range for the devices are designated as C_PRH0_BASEADDR C_PRH0_HIGHADDR C_PRH1_BASEADDR C_PRH1_HIGHADDR etc
5 The range specified by C_PRHx_BASEADDR and C_PRHx_HIGHADDR must comprise a contiguous range and the size of the range must be a power of two ie size of range = 2m Further the rsquomrsquo least significant bits of C_PRHx_BASEADDR must be zero The base and high address range assigned to different peripherals must be mutually exclusive
6 No default value will be specified to ensure that the actual value is set ie if the value is not set a compiler error will be generated
7 C_PRHx_FIFO_ACCESS must be set to 1 if the support for access to FIFO within external peripheral device is to be included
8 C_PRHx_FIFO_OFFSET is the byte offset of the external peripheral FIFO from the base address (C_PRHx_BASEADDR) of the peripheral irrespective of the data width of the peripheral device If C_PRHx_FIFO_ACCESS = 1 then C_PRHx_FIFO_OFFSET must be set to a valid offset within the address range assigned to the peripheral
9 The generic C_PRHx_DWIDTH_MATCH is relevant only when the width of the peripheral data (PRH_Data) bus is less than the OPB data bus (OPB_DBus)
10Address setup time is with respect to falling edge of address strobe (PRH_ADS) if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 and must be set both in synchronous and asynchronous mode Address setup time is with respect to falling edge of readwrite signals (PRH_Wr_nPRH_Rd_n) if the device is non multiplexed and is relevant only if the access mode is asynchronous
11Value for the parameter must be assigned if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 This parameter assignment is appicalble for synchronous and asynchronous devices
12Address hold time is with respect to falling edge of address strobe (PRH_ADS) if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 and must be set both in synchronous and asynchronous mode Address hold time is with respect to rising edge of readwrite signals (PRH_Wr_nPRH_Rd_n) if the address and the data bus are separate and is relevant only if the access mode is asynchronous
13Value must be assigned if the access mode of the peripherals is asynchronous ie C_PRHx_SYNC = 0 If the access mode of the peripheral is synchronous ie C_PRHx_SYNC = 1 then the zero should be assigned to the parameter
14Write signal (PRH_Wr_n) low time is the maximum of C_PRHx_WRN_WIDTH and C_PRHx_DATA_TSU15The value of C_PRHx_WRN_WIDTH must be smaller than C_PRHx_WR_CYCLE16 In non-multiplexed address and data bus mode write recovery time will be maximum of C_PRHx_ADDR_TH
C_PRHx_CSN_TH C_PRHx_DATA_TH and PRH_Wr_n high time (ie C_PRHx_WR_CYCLE minus C_PRHx_WRN_WIDTH) If the peripheral uses multiplexed address and data bus then the write recovery time will be maximum of C_PRHx_CSN_TH C_PRHx_DATA_TH and PRH_Wr_n high time
17Read signal (PRH_Rd_n) low time is the maximum of C_PRHx_RDN_WIDTH and C_PRHx_DATA_TOUT18The value of C_PRHx_RDN_WIDTH must be smaller than C_PRHx_RD_CYCLE19 In non-multiplexed address and data bus mode read recovery time will be maximum of C_PRHx_ADDR_TH
C_PRHx_CSN_TH C_PRHx_DATA_TINV and PRH_Rd_n high time (ie C_PRHx_RD_CYCLE minus C_PRHx_RDN_WIDTH) If the peripheral uses multiplexed address and data bus then the read recovery time will be maximum of C_PRHx_CSN_TH C_PRHx_DATA_TINV and PRH_Rd_n high time
20Device ready validity period (C_PRHx_RDY_TOUT) must be set as the maximum of the values specified for read and write transactions
21Device ready pulse width (C_PRHx_RDY_WIDTH) must be set as the maximum of the values specified for read and write transactions
22Device ready validity (C_PRHx_RDY_TOUT) period must be less than the write strobe width (C_PRHx_WRN_WIDTH) read strobe width (C_PRHx_RDN_WIDTH) and device ready signal width (C_PRHx_RDY_WIDTH)
23Device ready signal width (C_PRHx_RDY_WIDTH) must be set for both synchronous and asynchronous
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
access mode in order to prevent the device from holding the OPB indefinitely24Current version of the OPB EPC do not support the burst transactions tofrom the OPB
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Allowable Parameter Combinations
When the peripheral devices are confugured in non multiplexed mode the C_PRH_MAX_AWIDTH should be the maximum of C_PRHx_AWIDTH of all peripherals in the system ie if C_NUM_PERIPHERALS is 2 then C_PRH_MAX_AWIDTH should be maximum of C_PRH0_AWIDTH and C_PRH1_AWIDTH
C_PRH_MAX_DWIDTH should be the maximum of C_PRHx_DWIDTH of all peripherals in the system ie if C_NUM_PERIPHERALS is 2 then C_PRH_MAX_DWIDTH should be maximum of C_PRH0_DWIDTH and C_PRH1_DWIDTH
If any of the peripheral devices are configured for a multiplexed address and data buses then the parameter C_PRH_MAX_ADWIDTH should be set as the maximum of the data bus and address bus of the device(s) employing a multiplexed address and data bus If all devices employ non-multiplexed address and data buses then C_PRH_MAX_ADWIDTH reflects the maximum of data bus width of all external devices Therefore for any configuration the parameter C_PRH_MAX_ADWIDTH should be greater than or equal to C_PRH_MAX_DWIDTH
The generic C_PRH_CLK_SUPPORT is relevant only when the devices are configured for the synchronous access ie C_PRHx_SYNC = 1 If more than one of the devices are synchronous then the frequency for the peripheral clock should be chosen as the minimum of the operating frequencies of those devices
The range specified by C_PRHx_BASEADDR and C_PRHx_HIGHADDR parameters must comprise a contiguous range and the size of the range must be a power of two ie size of range = 2m Furthermore the rsquomrsquo least significant bits of C_PRHx_BASEADDR must be zero The base and high address range assigned to different peripherals must be mutually exclusive No default value will be specified for C_PRHx_BASEADDR and C_PRHx_HIGHADDR in order to enforce that the user configures these parameters with the actual values If the values are not set for C_PRHx_BASEADDR and C_PRHx_HIGHADDR a compiler error will be generated
In order to access FIFO like structures within the external peripheral devices C_PRHx_FIFO_ACCESS must be set to rsquo1rsquo When FIFO access is enabled C_PRHx_FIFO_OFFSET specifies the offset of the FIFO in terms of number of byte locations from the base address (C_PRHx_BASEADDR) of the peripheral and should be set to an offset that lies within the address range assigned to the peripheral device ie C_PRHx_BASEADDR + C_PRHx_FIFO_OFFSET le C_PRHx_HIGHADDR Furthermore the FIFO offset should be within the range addressable by the address bus ie C_PRHx_FIFO_OFFSET lt 2n
where n = C_PRHx_AWIDTH
The width of the readwrite strobe must be less than the cycle time of the corresponding access ie C_PRHx_WRN_WIDTH lt C_PRHx_WR_CYCLE and C_PRHx_RDN_WIDTH lt C_PRHx_RD_CYCLE The value of device ready validity period must be less than the readwrite strobe width and the maximum pulse width of the device ready signal ie C_PRHx_RDY_TOUT lt minimum of C_PRHx_WRN_WIDTH C_PRHx_RDN_WIDTH and C_PRHx_RDY_WIDTH
Parameter - Port Dependencies
The dependencies between the OPB EPC design parameters and the IO ports are shown in Table 3 The width of the OPB EPC signals depend on some of the parameters In addition when certain features are parameterized away the related logic is removed
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ust 10 2007 wwwxilinxcom 13ecification
OPB External Peripheral Controller (EPC) v100a
14
Table 3 Parameter - Port Dependencies
Generic or Port
Name Affects Depends Description
Design Parameters
G3 C_OPB_AWIDTH P1 -The OPB address width parameter sets the width of the OPB address bus
G4 C_OPB_DWIDTHP2 P3
P7-
The OPB data width parameter affects the number of byte enables configured for the OPB data bus width of the OPB data bus and the width of the OPB slave read data bus
G6C_NUM_PERIPHERALS
P16 P24-
The number of peripherals in the system determines the number of chip select signals driven and the number of device ready inputs decoded by the OPB external peripheral controller
G7C_PRH_MAX_AWIDTH
P17- The width of the peripheral address bus is set to
the maximum of address bus width of all peripheral devices
G8C_PRH_MAX_DWIDTH
P19- The number of byte enables for the peripheral data
bus is determined by the maximum of data bus width of the peripheral devices
G9C_PRH_MAX_ADWIDTH
P25 P26 P27
-
The width of the peripheral input data bus peripheral output data bus and the peripheral output data bus 3-state control are determined by the maximum of data bus width of all peripherals and the address bus width of peripherals employing address data bus multiplexing
G10C_PRH_CLK_SUPPORT
P14- If C_PRH_CLK_SUPPORT = 0 then all external
devices operate on OPB clock The input PRH_Clk must be driven high externally
G18C_PRHx_DWIDTH_MATCH
P23-
If the device is configured for synchronous mode with data width matching enabled then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
Discontinued IP
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OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G19 C_PRHx_SYNCP14 P20 P21 P22
P23
-
If the device is configured for asynchronous mode
bull With peripheral clock support the peripheral clock input (PRH_Clk) must be driven high externally
bull PRH_RNW is driven high as PRH_Rd_n and PRH_Wr_n should be used as read and write strobe
bull With data width matching enabled the OPB EPC drives PRH_Burst to its default low
If the device is configured for synchronous mode
bull The OPB EPC drives PRH_Rd_n and PRH_Wr_n outputs to their default state of high since PRH_RNW output is used as readwrite strobe
G20C_PRHx_BUS_MULTIPLEX
P18- PRH_ADS is driven low if the device does not use
multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
IO Signals
P1 OPB_ABus - G3The OPB address bus width is determined by the C_OPB_AWIDTH parameter
P2 OPB_BE - G4The number of byte enables for the OPB data bus is determined by the C_OPB_DWIDTH parameter
P3 OPB_DBus - G4The OPB data bus width is determined by the C_OPB_DWIDTH parameter
P7 Sln_DBus-
G4The width of the OPB slave read data bus is determined by the C_OPB_DWIDTH parameter
P14 PRH_Clk-
G10 G19
PRH_Clk is selected as operating clock only if the device is configured for synchronous mode with peripheral clock support ie C_PRHx_SYNC = 1 and C_PRH_CLK_SUPPORT = 1 Asynchronous interface always operates on OPB_Clk Therefore if no device is configured for synchronous mode with peripheral clock support enabled then the input PRH_Clk must be driven high
P16 PRH_CS_n-
G6The number of chip select signals driven by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P17 PRH_Addr-
G7The width of the peripheral address bus is determined by the C_PRH_MAX_AWIDTH parameter
P18 PRH_ADS-
G20PRH_ADS is driven low if the device does not use multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
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ust 10 2007 wwwxilinxcom 15ecification
OPB External Peripheral Controller (EPC) v100a
16
OPB EPC Design Considerations
The OPB EPC is an OPB slave only device It receives read or write instructions from the processor and generates a corresponding access cycle on the peripheral interface Examples of read and write accesses are illustrated in the Timing Diagrams section The user must take the following considerations into account while designing with the OPB EPC
Device Ready Signal
The OPB EPC readwrite access cycles are executed only when the external device assert the device ready signal (PRH_Rdy) If the external peripheral device does not have a device ready signal then the PRH_Rdy input of the OPB EPC must be tied to logic high
P19 PRH_BE - G8The number of byte enables for the peripheral data bus is determined by the C_PRH_MAX_DWIDTH parameter
P20 PHR_RNW-
G19
If the device is synchronous ie C_PRHx_SYNC = 1 then PRH_RNW should be used as the readwrite control signal For asynchronous mode of operation PRH_RNW is driven high
P21 PRH_Rd_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Rd_n should be used as the read strobe For synchronous mode of operation PRH_Rd_n is driven high
P22 PRH_Wr_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Wr_n should be used as the write strobe For synchronous mode of operation PRH_Wr_n is driven high
P23 PRH_Burst-
G18 G19
If the device is synchronous with data width matching enabled ie C_PRHx_SYNC = 1 and C_PRHx_DWIDTH_MATCH = 1 then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
P24 PRH_Rdy-
G6The number of device ready inputs decoded by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P25 PRH_Data_I-
G9The peripheral input data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P26 PRH_Data_O - G9The peripheral output data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P27 PRH_Data_T - G9
The peripheral output data bus 3-state control width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
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OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
FIFO Transactions
When C_PRHx_FIFO_ACCESS = 1 the OPB EPC supports access to FIFOrsquos within the external peripheral devices When the FIFO within the external device is accessed then the peripheral address bus (PRH_Addr) must remain constant representing the FIFO address within the address range assigned to the peripheral device When data width matching is enabled and the access corresponds to the FIFO the OPB EPC does not increment the peripheral address (PRH_Addr) bus
Abnormal Terminations
If PRH_Rdy is de-asserted for more than the maximum period as specified by C_PRHx_RDY_WIDTH then the OPB EPC terminates the current access to the external device and signals an error to the OPB master by asserting Sln_errAck on the OPB Similarly when the OPB master terminates the current access (master abort on the OPB) OPB EPC terminates the access to the external device immediately In both cases the access to the external device is terminated abnormally Therefore the external device may be in an indeterminate state and the exceptions should be handled appropriately at the system level
Interrupt Handling
If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Peripheral Data Bus Mapping
The peripheral data bus (PRH_Data) uses big endian bit labelling (ie bit-0 is Most Significant Bit (MSB) and bit-31 is Least Significant Bit (LSB) for a 32-bit bus) and is sized according to the C_PRH_MAX_ADWIDTH parameter Peripherals that have smaller widths should connect to this bus starting at bit 0 (MSB) For example if three external devices are present in the system with data bus width of 8-bit 16-bit and 32-bit the 8-bit device should connect to PRH_Data[07] the 16-bit wide peripheral should connect to PRH_Data[015] and the 32-bit peripheral should connect to PRH_Data[031]
The bit and byte labeling for the big endian data types is shown in Figure 3
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ust 10 2007 wwwxilinxcom 17ecification
F
OPB External Peripheral Controller (EPC) v100a
18
Figure 3 OPB EPC Big Endian Data Type
igure Top x-ref 3
2 3
n+2 n+3
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 15
Halfword
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 31
Word
Byte
MS Byte
LS BitMS Bit
0
nByte address
Byte label
Byte significance
Bit label
Bit significance
0 7
DS325_03_071406
Unsupported Features
Many peripheral devices have the device specific inputoutput ports such as status remote reset remote wakeup interrupts etc The OPB EPC does not have any provision to support these device specific inputoutput ports Therefore if the external device has any such device specific ports then these inputoutput ports may be connected directly to system general purpose input output controller or to the system interrupt controller If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Many peripheral devices support DMA capability However currently OPB EPC is an OPB slave only device and therefore does not support DMA operations from the external peripheral devices
Current version of the OPB EPC does not support burst transactions tofrom the OPB
OPB EPC Latency
The OPB EPC latency calculations are based on the OPB clock The OPB latency is defined as the number of OPB clock cycles elapsed from the time an access is initiated to the time the access is completed (Sln_xferAck is asserted) on the OPB Table 4 shows the latency calculations for asynchronous mode and Table 5 shows the latency calculations for synchronous mode of operation
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 4 Asynchronous Mode OPB EPC Latency
Transaction Type
ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation(1)
OPB Latency
50 MHz
OPB Latency 100 MHz
ReadWrite access to asynchronous device when addressdata bus is not multiplexed
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5)
9(7) 12(7)
1FIFO
Memory
5 + N(2) (T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5))
21(7) 33(7)
ReadWrite access to asynchronous device when addressdata bus is multiplexed (Register access)
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + (T_SETUP(3) + T_ADDR_HOLD(6) + 1 + CONTROL_WIDTH(4) + T_HOLD(5))
11(7) 14(7)
1 FIFO
5 + T_SETUP(3) + T_ADDR_HOLD(6) + 1 + N(2) (CONTROL_WIDTH(4) + T_HOLD(5))
20(7) 29(7)
1 Memory
4 + N(2) (T_SETUP(3) + T_ADDR_HOLD(6) + CONTROL_WIDTH(4) + T_HOLD(5) + 2)
32(7) 44(7)
Notes 1 Latency calculations assumes the device is always ready2 If C_PRHx_DWIDTH_MATCH = 1 then N = Access size on OPB (in bytes)width of peripheral data bus (in
bytes)3 T_SETUP is the setup time requirement on various control signals in terms of number of OPB clocks and is
device specific4 CONTROL_WIDTH represents the required width for readwrite signal in terms of number of OPB clocks and
is device specific 5 T_HOLD is the hold time requirement on various control signals in terms of number of OPB clocks and is
device specific6 T_ADDR_HOLD is the required hold time on the address bus (as specified by generic C_PRHx_ADDR_TH) in
terms of number of OPB clocks and is device specific 7 Calculation are made for typical values of various timing parameters with T_SETUP = 20ns T_HOLD = 10ns
T_ADDR_HOLD = 6ns and STROBE_WIDTH = 40ns
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ust 10 2007 wwwxilinxcom 19ecification
OPB External Peripheral Controller (EPC) v100a
20
Table 5 Synchronous Mode OPB EPC Latency
Transaction Type ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory 9
1FIFO
Memory 8 + N(2)
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory 11
1 FIFO 10 + N(2)
1 Memory 6 + 5N(2)
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 7 peripheral clocks
1FIFO
Memory
7 OPB clocks + (6+N(2)) peripheral clocks
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 9 peripheral clocks
1 FIFO7 OPB clocks + (8+N(2)) peripheral clocks
1 Memory7 OPB clocks + (4+5N(2)) peripheral clocks
Notes 1 Latency calculations assumes the device is always ready2 N = Access size on the OPB (in bytes)width of peripheral data bus (in bytes) where access size on OPB
equals or less than C_OPB_DWIDTH expressed in terms of bytes3 Latency calculation assumes that the requirement on address setup (C_PRHx_ADDR_TSU) address hold
(C_PRHx_ADDR_TH) and ADS pulse width (C_PRHx_ADS_WIDTH) are all less than one OPB clock
OPB EPC External Peripheral ConnectionsThe OPB EPC interface to the external device is based upon the width of the OPB data bus address and data width of the peripheral subsystem number of peripherals in the system addressdata multiplex support mode of operation (synchronous or asynchronous) and if synchronous device the operating clock for the synchronous data path
Determining Address and Data Width
The address bus width of the peripheral subsystem is the maximum width of the address bus of all peripheral devices connected to the OPB EPC If all devices employ non-multiplexed address and data bus the data bus width of the peripheral subsystem is the maximum of the data bus width of all external devices If any of the devices are configured for multiplexed address and data bus then the data bus width of the peripheral subsystem should be set as the maximum of the data bus and the address bus of the device(s) employing a multiplexed address and data bus
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Endian Considerations
The peripheral address and data bus of the OPB EPC is labeled with big endian bit labeling (D0 is the MSB and D31 is the LSB for a 32-bit bus) while most peripheral devices are either endian agnostic ie they can be connected either way or little endian (D31 is the MSB and D0 is the LSB for a 32-bit bus) Caution must be exercised with the connection to the external peripheral devices to avoid incorrect data and address connections
Clock Generation
When connecting to a synchronous external device the OPB EPC may operate either on the OPB clock (OPB_Clk) or on a peripheral clock (PRH_Clk) The operating clock for the synchronous interface is based on the generic C_PRH_CLK_SUPPORT If C_PRH_CLK_SUPPORT = 1 the peripheral clock is used else the OPB clock is used The external devices connected to the OPB EPC will determine the operating frequency of the peripheral clock The minimum of the operating frequencies of various devices connected to OPB EPC should be used as the operating frequency of the peripheral clock (PRH_Clk)
Figure 4 illustrates a block diagram for generating a device specific clock source clock source using two DCMs The DCM modules are located within the FPGA but are external to the OPB EPC An external clock source is used to generate the OPB clock (OPB_Clk) to the OPB EPC The device clock source (PRH_Clk) is also generated from the same DCM (DCM0) using the CLKFX output and must be routed on the board to be fed back to the FPGA Another DCM (DCM1) is used to synchronize the device peripheral clock to the OPB EPC PRH_Clk
Figure 4 External Peripherals clocked by FPGA output with feedback
igure Top x-ref 4
DS325_04_071406
CLKFB CLK0
CLKFXCLKIN
DCM0
PRH_Clk_FB
PRH_Clk
OPB_Clk
CLKFB CLK0
CLKIN
DCM1
PRH_Clk
OPB_Clk
OPB EPCExternalDevice
CLK
FPGA
Example Peripheral Connections
Example SMSC LAN91C111 10100 non-PCI Ethernet Single Chip MAC + PHY
An example peripheral device supported by the OPB EPC is the SMSC 10100 non-PCI Ethernet Single Chip MAC + PHY LAN91C111 The OPB EPC allows OPB masters to access the device both in synchronous and asynchronous mode The device connections for synchronous and asynchronous mode of operations are outlined in the Asynchronous Mode and Synchronous Mode sections
Discontinued IP
ust 10 2007 wwwxilinxcom 21ecification
OPB External Peripheral Controller (EPC) v100a
22
F
Asynchronous Mode
Figure 5 illustrates the SMSC LAN91C111 connections to the OPB EPC in asynchronous mode with non-multiplexed address and data buses In asynchronous mode the input clock source (PRH_Clk) to the external device must be tied to VCC When the SMSC LAN91C111 is accessed through the asynchronous mode the rising edge of PRH_Rd_n and PRH_Wr_n signals are used to control the read and the write operations respectively As the device uses Asynchronous Ready (ARDY) signal to indicate its readiness in asynchronous mode This signal is connected to the PRH_Rdy input of the OPB EPC Since the address and the data buses are not multiplexed PRH_ADS will be driven low by the OPB EPC
The following parameter settings apply for the connections shown in Figure 5
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 5 SMSC LAN91C111 Connection to OPB EPC in Asynchronous Mode
igure Top x-ref 5
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]
PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
To System Interrupt Controller
VCC
LCLKResetAENnADSA[151]
nBE[30]
ARDYnRdnWR
D[310]
INTRO
WnRnVLBUSnCYCLE
nRDYRTNnDADACS
nLDEVnSARDY
SMSC LAN91C111
ExternalGlue Logic
PPC
OP
B B
us
FPGA
DS325_05_071406
ExternalReset VCC
External Glue Logic
Special attention must be given while interfacing the OPB EPC to the SMSC LAN91C111 in asynchronous mode The OPB EPC drives the PRH_BE active high while the SMSC LAN91C111 requires the input byte enable to be active low To match this requirement external glue logic is required to invert the PRH_BE signals before they are interfaced with the byte enable signals of the SMSC LAN91C111
Discontinued IP
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OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Synchronous Mode
Figure 6 illustrates the SMSC LAN91C111 connection to the OPB EPC in synchronous VL Bus mode with non-multiplexed address and data buses In synchronous mode the device requires an input clock source to the LCLK pin with a maximum operating frequency of 50MHz The local clock generated by the DCM for the peripheral interface must be routed to the LCLK input of SMSC LAN91C111 and PRH_Clk of OPB EPC When the device is accessed PRH_RNW is used as the control signal to indicate a readwrite access When PRH_RNW is high it indicates a read operation and when low it indicates a write operation The SMSC LAN91C111 uses nSRDY signal to indicate the device readiness This signal is connected to PRH_Rdy input of the OPB_EPC As the address and the data bus are not multiplexed PRH_ADS will be driven low
The following parameter settings apply for the connections shown in Figure 6
bull C_PRH_CLK_SUPPORT = 1
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 1
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 6 SMSC LAN91C111 Connection to OPB EPC in Synchronous Mode
igure Top x-ref 6
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
LCLKResetAENnADSA[151]nBE[30]WnRnSRDY
D[310]
nCYCLEnRDYRTN
INTRO
nRdnWR
nDADACSnLDEVARDY
nVLBUS
SMSC LAN91C111
ExternalGlue Logic
DigitalClock
Manager
PP
C
OP
B B
us
FPGA
DS325_06_071406
External Reset
VCC
GND
To System Interrupt Controller
External Glue Logic
The SMSC LAN91C111 device requires two inputs nCYCLE and nRDYRTN to control synchronous operation The definition of these signals is outside the scope of this document and can be found in the documents listed in the Reference Documents section The nCYCLE and nRDYRTN signals are generated in external glue logic nCYCLE may be generated from PRH_CS_n and is driven low for a
Discontinued IP
ust 10 2007 wwwxilinxcom 23ecification
OPB External Peripheral Controller (EPC) v100a
24
single clock cycle on a high to low transition on PRH_CS_n nRDYRTN is simply the registered value of the nSRDY signal
Design Considerations
When the OPB EPC is interfaced to the SMSC LAN91C111 with data width match enabled (C_PRHx_DWIDTH_MATCH = 1) and the internal SRAM of the peripheral is being accessed the device has to be configured in the address auto increment mode Address auto increment mode can be configured by setting AUTO INCR bit in the Bank 2 Pointer Register of SMSC LAN91C111 More information can be obtained by referring the registers of Bank 2 in SMSC LAN91C111 data sheet See the Reference Documents section
Example Cypress Semiconductorrsquos CY7C67300 EZ-Host Programmable Embedded USB HostPeripheral Controller
The Cypress Semiconductorrsquos CY7C67300 EZ-Hosttrade Programmable Embedded USB HostPeripheral Controller is another example of a peripheral device supported by the OPB EPC Since the Cypress USB controller operates in asynchronous mode the OPB EPC must be configured to support asynchronous mode operation
Asynchronous Mode
Figure 7 illustrates the CY7C67300 USB Controller connection to the OPB EPC in asynchronous mode with non-multiplexed address and data buses
The following parameter settings apply for the connection shown in Figure 7
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 4
bull C_PRH0_DWIDTH = 16
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Configuration of CY7C67300 USB Controller
The CY7C67300 USB Controller is configured as a Host Processor Interface (HPI) The boot-up sequence code for the CY7C67300 USB Controller in this particular example is present on the external Compact Flash memory device and is accessed through the OPB SYSACE interface This code is downloaded to the CY7C67300 USB Controller through the HPI interface Once this boot-up sequence is executed by the CY7C67300 USB Controller it becomes ready to operate in normal HPI mode with the external host controller (OPB EPC)
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
F
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 7 CY7C67300 USB Controller connection to OPB EPC in asynchronous mode
igure Top x-ref 7
SysACE_mpd_I[015]SysACE_mpd_O[015]SysACE_mpd_T[015]
SysACE_mpweSysACE_mpoe
SysACE_MPA[06]
SysACE_CEN
OPB SYS ACE Cntlr[150][150][150]
[60]
PRH_RstPRH_Rdy
PRH_CS_n
PRH_Data_I[015]PRH_Data_O[015]PRH_Data_T[015]
PRH_ADSPRH_RRNW
PRH_BurstPRH_Rd_nPRH_Wr_n
PRH_Addr[01]
OPB EPC
VCC
Ext
erna
l US
B P
orts
P
ort 1
A 1
B 2
AnCS
nRD
nWR
[D15D0]
[A1A0]
INT
CompactFLASH
TQFP144 SYSTEMACE
System ACE CompactFlash Controller
Ext
erna
l Glu
e Lo
gic
OPBINTC
US
B C
Y7C
6730
0
PP
C
OP
B B
us
FPGA
DS325_07_071406
Sysace_epc_data[150]
HPI interface
Sysace_epc_rd_n
Sysace_epc_wr_n
Sysace_epc_a[10]
DM1B
DP1B
DM2A
DP2A
DM1A
DP1A
External Glue Logic
In the interface diagram shown in Figure 7 the OPB EPC as well as the OPB SYSACE share the interface for data address and control lines on the board This requires external multiplex logic to be placed outside of IP cores in the FPGA The OPB EPC control signals PRH_RD_n and PRH_WR_n are muxed with the MEM_CEN and MEM_WEN signals of the OPB SYSACE When CY7C67300 USB Controller is accessed through the asynchronous mode the rising edge of sysace_epc_rd_n and sysace_epc_wr_n signals are used to control the read and the write operations respectively See the Reference Documents section for more information on OPB SYSACE
Design Constraints
Timing Constraints
Timing constraints must be placed on the system clock and the peripheral clock setting the frequency to meet the bus timing requirements An example is shown in Figure 8
Discontinued IP
ust 10 2007 wwwxilinxcom 25ecification
F
OPB External Peripheral Controller (EPC) v100a
26
Figure 8 EPC Timing Constraints
igure Top x-ref 8
Following constraint must be placed on the system clock
TIMESPEC TS_OPB_Clk = PERIOD OPB_Clk 10 ns HIGH 50
NET OPB_Clk TNM_NET = OPB_Clk
If C_PRH_CLK_SUPPORT=1 then the following constraint must be placed on the peripheral clock
TIMESPEC TS_PRH_Clk = PERIOD PRH_Clk 20 ns HIGH 50
NET PRH_Clk TNM_NET = PRH_Clk
DS325_08_071406
Design Implementation
Timing Diagrams
The timing diagrams in the figures below show various OPB transactions and the resulting access cycles on the peripheral interface Timing diagrams are not shown for all possible combinations of generics and the resulting access cycles However the timing diagrams shown are sufficient for the basic understanding of various access cycles supported by the OPB EPC
Figure 9 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 9
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
DS325_09_071206
8
4000000
004
04
Figure 10 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 10
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
04000000
20000004
8
00000000
004
04DS325_10_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 11 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 11
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000000
F
00010203
000 001 002 003
00 01 02 03DS325_11_071206
Figure 12 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 12
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
20000000
F
0000000000000000
000 001 002 003
00 01 02 03DS325_12_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 27ecification
OPB External Peripheral Controller (EPC) v100a
28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 29ecification
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
12
Notes 1 The generic C_PRH_CLK_SUPPORT is relevant only when the device is configured for synchronous access
ie C_PRHx_SYNC = 1 If more than one device is synchronous then the frequency for the peripheral clock (PRH_Clk) should be chosen as the minimum of the operating frequencies of those devices
2 The C_PRH_MAX_ADWIDTH determines the size of the data bus For all non multiplexed devices the C_PRH_MAX_ADWIDTH reflects the maximum of data bus width of all external devices ie C_PRH_MAX_ADWIDTH equals C_PRH_MAX_DWIDTH However if any of the devices is configured for multiplexed address and data bus then C_PRH_MAX_ADWIDTH should be set as the maximum of data bus of all external devices and the address bus of device(s) employing multiplexed address and data bus
3 rsquoxrsquo in the generic refers to the number of the peripheral device and takes a value in the range of 0 to C_NUM_PERIPHERALS - 1
4 OPB EPC design can accommodate up to four peripheral devices The address range for the devices are designated as C_PRH0_BASEADDR C_PRH0_HIGHADDR C_PRH1_BASEADDR C_PRH1_HIGHADDR etc
5 The range specified by C_PRHx_BASEADDR and C_PRHx_HIGHADDR must comprise a contiguous range and the size of the range must be a power of two ie size of range = 2m Further the rsquomrsquo least significant bits of C_PRHx_BASEADDR must be zero The base and high address range assigned to different peripherals must be mutually exclusive
6 No default value will be specified to ensure that the actual value is set ie if the value is not set a compiler error will be generated
7 C_PRHx_FIFO_ACCESS must be set to 1 if the support for access to FIFO within external peripheral device is to be included
8 C_PRHx_FIFO_OFFSET is the byte offset of the external peripheral FIFO from the base address (C_PRHx_BASEADDR) of the peripheral irrespective of the data width of the peripheral device If C_PRHx_FIFO_ACCESS = 1 then C_PRHx_FIFO_OFFSET must be set to a valid offset within the address range assigned to the peripheral
9 The generic C_PRHx_DWIDTH_MATCH is relevant only when the width of the peripheral data (PRH_Data) bus is less than the OPB data bus (OPB_DBus)
10Address setup time is with respect to falling edge of address strobe (PRH_ADS) if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 and must be set both in synchronous and asynchronous mode Address setup time is with respect to falling edge of readwrite signals (PRH_Wr_nPRH_Rd_n) if the device is non multiplexed and is relevant only if the access mode is asynchronous
11Value for the parameter must be assigned if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 This parameter assignment is appicalble for synchronous and asynchronous devices
12Address hold time is with respect to falling edge of address strobe (PRH_ADS) if the address and the data bus are multiplexed ie C_PRHx_BUS_MULTIPLEX = 1 and must be set both in synchronous and asynchronous mode Address hold time is with respect to rising edge of readwrite signals (PRH_Wr_nPRH_Rd_n) if the address and the data bus are separate and is relevant only if the access mode is asynchronous
13Value must be assigned if the access mode of the peripherals is asynchronous ie C_PRHx_SYNC = 0 If the access mode of the peripheral is synchronous ie C_PRHx_SYNC = 1 then the zero should be assigned to the parameter
14Write signal (PRH_Wr_n) low time is the maximum of C_PRHx_WRN_WIDTH and C_PRHx_DATA_TSU15The value of C_PRHx_WRN_WIDTH must be smaller than C_PRHx_WR_CYCLE16 In non-multiplexed address and data bus mode write recovery time will be maximum of C_PRHx_ADDR_TH
C_PRHx_CSN_TH C_PRHx_DATA_TH and PRH_Wr_n high time (ie C_PRHx_WR_CYCLE minus C_PRHx_WRN_WIDTH) If the peripheral uses multiplexed address and data bus then the write recovery time will be maximum of C_PRHx_CSN_TH C_PRHx_DATA_TH and PRH_Wr_n high time
17Read signal (PRH_Rd_n) low time is the maximum of C_PRHx_RDN_WIDTH and C_PRHx_DATA_TOUT18The value of C_PRHx_RDN_WIDTH must be smaller than C_PRHx_RD_CYCLE19 In non-multiplexed address and data bus mode read recovery time will be maximum of C_PRHx_ADDR_TH
C_PRHx_CSN_TH C_PRHx_DATA_TINV and PRH_Rd_n high time (ie C_PRHx_RD_CYCLE minus C_PRHx_RDN_WIDTH) If the peripheral uses multiplexed address and data bus then the read recovery time will be maximum of C_PRHx_CSN_TH C_PRHx_DATA_TINV and PRH_Rd_n high time
20Device ready validity period (C_PRHx_RDY_TOUT) must be set as the maximum of the values specified for read and write transactions
21Device ready pulse width (C_PRHx_RDY_WIDTH) must be set as the maximum of the values specified for read and write transactions
22Device ready validity (C_PRHx_RDY_TOUT) period must be less than the write strobe width (C_PRHx_WRN_WIDTH) read strobe width (C_PRHx_RDN_WIDTH) and device ready signal width (C_PRHx_RDY_WIDTH)
23Device ready signal width (C_PRHx_RDY_WIDTH) must be set for both synchronous and asynchronous
Table 2 OPB EPC Design Parameters (Contd)
GenericFeature
DescriptionParameter Name
Allowable Values
Default Value
VHDL Type
Discontinued IP
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access mode in order to prevent the device from holding the OPB indefinitely24Current version of the OPB EPC do not support the burst transactions tofrom the OPB
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Allowable Parameter Combinations
When the peripheral devices are confugured in non multiplexed mode the C_PRH_MAX_AWIDTH should be the maximum of C_PRHx_AWIDTH of all peripherals in the system ie if C_NUM_PERIPHERALS is 2 then C_PRH_MAX_AWIDTH should be maximum of C_PRH0_AWIDTH and C_PRH1_AWIDTH
C_PRH_MAX_DWIDTH should be the maximum of C_PRHx_DWIDTH of all peripherals in the system ie if C_NUM_PERIPHERALS is 2 then C_PRH_MAX_DWIDTH should be maximum of C_PRH0_DWIDTH and C_PRH1_DWIDTH
If any of the peripheral devices are configured for a multiplexed address and data buses then the parameter C_PRH_MAX_ADWIDTH should be set as the maximum of the data bus and address bus of the device(s) employing a multiplexed address and data bus If all devices employ non-multiplexed address and data buses then C_PRH_MAX_ADWIDTH reflects the maximum of data bus width of all external devices Therefore for any configuration the parameter C_PRH_MAX_ADWIDTH should be greater than or equal to C_PRH_MAX_DWIDTH
The generic C_PRH_CLK_SUPPORT is relevant only when the devices are configured for the synchronous access ie C_PRHx_SYNC = 1 If more than one of the devices are synchronous then the frequency for the peripheral clock should be chosen as the minimum of the operating frequencies of those devices
The range specified by C_PRHx_BASEADDR and C_PRHx_HIGHADDR parameters must comprise a contiguous range and the size of the range must be a power of two ie size of range = 2m Furthermore the rsquomrsquo least significant bits of C_PRHx_BASEADDR must be zero The base and high address range assigned to different peripherals must be mutually exclusive No default value will be specified for C_PRHx_BASEADDR and C_PRHx_HIGHADDR in order to enforce that the user configures these parameters with the actual values If the values are not set for C_PRHx_BASEADDR and C_PRHx_HIGHADDR a compiler error will be generated
In order to access FIFO like structures within the external peripheral devices C_PRHx_FIFO_ACCESS must be set to rsquo1rsquo When FIFO access is enabled C_PRHx_FIFO_OFFSET specifies the offset of the FIFO in terms of number of byte locations from the base address (C_PRHx_BASEADDR) of the peripheral and should be set to an offset that lies within the address range assigned to the peripheral device ie C_PRHx_BASEADDR + C_PRHx_FIFO_OFFSET le C_PRHx_HIGHADDR Furthermore the FIFO offset should be within the range addressable by the address bus ie C_PRHx_FIFO_OFFSET lt 2n
where n = C_PRHx_AWIDTH
The width of the readwrite strobe must be less than the cycle time of the corresponding access ie C_PRHx_WRN_WIDTH lt C_PRHx_WR_CYCLE and C_PRHx_RDN_WIDTH lt C_PRHx_RD_CYCLE The value of device ready validity period must be less than the readwrite strobe width and the maximum pulse width of the device ready signal ie C_PRHx_RDY_TOUT lt minimum of C_PRHx_WRN_WIDTH C_PRHx_RDN_WIDTH and C_PRHx_RDY_WIDTH
Parameter - Port Dependencies
The dependencies between the OPB EPC design parameters and the IO ports are shown in Table 3 The width of the OPB EPC signals depend on some of the parameters In addition when certain features are parameterized away the related logic is removed
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ust 10 2007 wwwxilinxcom 13ecification
OPB External Peripheral Controller (EPC) v100a
14
Table 3 Parameter - Port Dependencies
Generic or Port
Name Affects Depends Description
Design Parameters
G3 C_OPB_AWIDTH P1 -The OPB address width parameter sets the width of the OPB address bus
G4 C_OPB_DWIDTHP2 P3
P7-
The OPB data width parameter affects the number of byte enables configured for the OPB data bus width of the OPB data bus and the width of the OPB slave read data bus
G6C_NUM_PERIPHERALS
P16 P24-
The number of peripherals in the system determines the number of chip select signals driven and the number of device ready inputs decoded by the OPB external peripheral controller
G7C_PRH_MAX_AWIDTH
P17- The width of the peripheral address bus is set to
the maximum of address bus width of all peripheral devices
G8C_PRH_MAX_DWIDTH
P19- The number of byte enables for the peripheral data
bus is determined by the maximum of data bus width of the peripheral devices
G9C_PRH_MAX_ADWIDTH
P25 P26 P27
-
The width of the peripheral input data bus peripheral output data bus and the peripheral output data bus 3-state control are determined by the maximum of data bus width of all peripherals and the address bus width of peripherals employing address data bus multiplexing
G10C_PRH_CLK_SUPPORT
P14- If C_PRH_CLK_SUPPORT = 0 then all external
devices operate on OPB clock The input PRH_Clk must be driven high externally
G18C_PRHx_DWIDTH_MATCH
P23-
If the device is configured for synchronous mode with data width matching enabled then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
Discontinued IP
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DS325 AugProduct Sp
G19 C_PRHx_SYNCP14 P20 P21 P22
P23
-
If the device is configured for asynchronous mode
bull With peripheral clock support the peripheral clock input (PRH_Clk) must be driven high externally
bull PRH_RNW is driven high as PRH_Rd_n and PRH_Wr_n should be used as read and write strobe
bull With data width matching enabled the OPB EPC drives PRH_Burst to its default low
If the device is configured for synchronous mode
bull The OPB EPC drives PRH_Rd_n and PRH_Wr_n outputs to their default state of high since PRH_RNW output is used as readwrite strobe
G20C_PRHx_BUS_MULTIPLEX
P18- PRH_ADS is driven low if the device does not use
multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
IO Signals
P1 OPB_ABus - G3The OPB address bus width is determined by the C_OPB_AWIDTH parameter
P2 OPB_BE - G4The number of byte enables for the OPB data bus is determined by the C_OPB_DWIDTH parameter
P3 OPB_DBus - G4The OPB data bus width is determined by the C_OPB_DWIDTH parameter
P7 Sln_DBus-
G4The width of the OPB slave read data bus is determined by the C_OPB_DWIDTH parameter
P14 PRH_Clk-
G10 G19
PRH_Clk is selected as operating clock only if the device is configured for synchronous mode with peripheral clock support ie C_PRHx_SYNC = 1 and C_PRH_CLK_SUPPORT = 1 Asynchronous interface always operates on OPB_Clk Therefore if no device is configured for synchronous mode with peripheral clock support enabled then the input PRH_Clk must be driven high
P16 PRH_CS_n-
G6The number of chip select signals driven by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P17 PRH_Addr-
G7The width of the peripheral address bus is determined by the C_PRH_MAX_AWIDTH parameter
P18 PRH_ADS-
G20PRH_ADS is driven low if the device does not use multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
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ust 10 2007 wwwxilinxcom 15ecification
OPB External Peripheral Controller (EPC) v100a
16
OPB EPC Design Considerations
The OPB EPC is an OPB slave only device It receives read or write instructions from the processor and generates a corresponding access cycle on the peripheral interface Examples of read and write accesses are illustrated in the Timing Diagrams section The user must take the following considerations into account while designing with the OPB EPC
Device Ready Signal
The OPB EPC readwrite access cycles are executed only when the external device assert the device ready signal (PRH_Rdy) If the external peripheral device does not have a device ready signal then the PRH_Rdy input of the OPB EPC must be tied to logic high
P19 PRH_BE - G8The number of byte enables for the peripheral data bus is determined by the C_PRH_MAX_DWIDTH parameter
P20 PHR_RNW-
G19
If the device is synchronous ie C_PRHx_SYNC = 1 then PRH_RNW should be used as the readwrite control signal For asynchronous mode of operation PRH_RNW is driven high
P21 PRH_Rd_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Rd_n should be used as the read strobe For synchronous mode of operation PRH_Rd_n is driven high
P22 PRH_Wr_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Wr_n should be used as the write strobe For synchronous mode of operation PRH_Wr_n is driven high
P23 PRH_Burst-
G18 G19
If the device is synchronous with data width matching enabled ie C_PRHx_SYNC = 1 and C_PRHx_DWIDTH_MATCH = 1 then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
P24 PRH_Rdy-
G6The number of device ready inputs decoded by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P25 PRH_Data_I-
G9The peripheral input data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P26 PRH_Data_O - G9The peripheral output data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P27 PRH_Data_T - G9
The peripheral output data bus 3-state control width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
Discontinued IP
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OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
FIFO Transactions
When C_PRHx_FIFO_ACCESS = 1 the OPB EPC supports access to FIFOrsquos within the external peripheral devices When the FIFO within the external device is accessed then the peripheral address bus (PRH_Addr) must remain constant representing the FIFO address within the address range assigned to the peripheral device When data width matching is enabled and the access corresponds to the FIFO the OPB EPC does not increment the peripheral address (PRH_Addr) bus
Abnormal Terminations
If PRH_Rdy is de-asserted for more than the maximum period as specified by C_PRHx_RDY_WIDTH then the OPB EPC terminates the current access to the external device and signals an error to the OPB master by asserting Sln_errAck on the OPB Similarly when the OPB master terminates the current access (master abort on the OPB) OPB EPC terminates the access to the external device immediately In both cases the access to the external device is terminated abnormally Therefore the external device may be in an indeterminate state and the exceptions should be handled appropriately at the system level
Interrupt Handling
If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Peripheral Data Bus Mapping
The peripheral data bus (PRH_Data) uses big endian bit labelling (ie bit-0 is Most Significant Bit (MSB) and bit-31 is Least Significant Bit (LSB) for a 32-bit bus) and is sized according to the C_PRH_MAX_ADWIDTH parameter Peripherals that have smaller widths should connect to this bus starting at bit 0 (MSB) For example if three external devices are present in the system with data bus width of 8-bit 16-bit and 32-bit the 8-bit device should connect to PRH_Data[07] the 16-bit wide peripheral should connect to PRH_Data[015] and the 32-bit peripheral should connect to PRH_Data[031]
The bit and byte labeling for the big endian data types is shown in Figure 3
Discontinued IP
ust 10 2007 wwwxilinxcom 17ecification
F
OPB External Peripheral Controller (EPC) v100a
18
Figure 3 OPB EPC Big Endian Data Type
igure Top x-ref 3
2 3
n+2 n+3
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 15
Halfword
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 31
Word
Byte
MS Byte
LS BitMS Bit
0
nByte address
Byte label
Byte significance
Bit label
Bit significance
0 7
DS325_03_071406
Unsupported Features
Many peripheral devices have the device specific inputoutput ports such as status remote reset remote wakeup interrupts etc The OPB EPC does not have any provision to support these device specific inputoutput ports Therefore if the external device has any such device specific ports then these inputoutput ports may be connected directly to system general purpose input output controller or to the system interrupt controller If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Many peripheral devices support DMA capability However currently OPB EPC is an OPB slave only device and therefore does not support DMA operations from the external peripheral devices
Current version of the OPB EPC does not support burst transactions tofrom the OPB
OPB EPC Latency
The OPB EPC latency calculations are based on the OPB clock The OPB latency is defined as the number of OPB clock cycles elapsed from the time an access is initiated to the time the access is completed (Sln_xferAck is asserted) on the OPB Table 4 shows the latency calculations for asynchronous mode and Table 5 shows the latency calculations for synchronous mode of operation
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 4 Asynchronous Mode OPB EPC Latency
Transaction Type
ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation(1)
OPB Latency
50 MHz
OPB Latency 100 MHz
ReadWrite access to asynchronous device when addressdata bus is not multiplexed
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5)
9(7) 12(7)
1FIFO
Memory
5 + N(2) (T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5))
21(7) 33(7)
ReadWrite access to asynchronous device when addressdata bus is multiplexed (Register access)
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + (T_SETUP(3) + T_ADDR_HOLD(6) + 1 + CONTROL_WIDTH(4) + T_HOLD(5))
11(7) 14(7)
1 FIFO
5 + T_SETUP(3) + T_ADDR_HOLD(6) + 1 + N(2) (CONTROL_WIDTH(4) + T_HOLD(5))
20(7) 29(7)
1 Memory
4 + N(2) (T_SETUP(3) + T_ADDR_HOLD(6) + CONTROL_WIDTH(4) + T_HOLD(5) + 2)
32(7) 44(7)
Notes 1 Latency calculations assumes the device is always ready2 If C_PRHx_DWIDTH_MATCH = 1 then N = Access size on OPB (in bytes)width of peripheral data bus (in
bytes)3 T_SETUP is the setup time requirement on various control signals in terms of number of OPB clocks and is
device specific4 CONTROL_WIDTH represents the required width for readwrite signal in terms of number of OPB clocks and
is device specific 5 T_HOLD is the hold time requirement on various control signals in terms of number of OPB clocks and is
device specific6 T_ADDR_HOLD is the required hold time on the address bus (as specified by generic C_PRHx_ADDR_TH) in
terms of number of OPB clocks and is device specific 7 Calculation are made for typical values of various timing parameters with T_SETUP = 20ns T_HOLD = 10ns
T_ADDR_HOLD = 6ns and STROBE_WIDTH = 40ns
Discontinued IP
ust 10 2007 wwwxilinxcom 19ecification
OPB External Peripheral Controller (EPC) v100a
20
Table 5 Synchronous Mode OPB EPC Latency
Transaction Type ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory 9
1FIFO
Memory 8 + N(2)
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory 11
1 FIFO 10 + N(2)
1 Memory 6 + 5N(2)
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 7 peripheral clocks
1FIFO
Memory
7 OPB clocks + (6+N(2)) peripheral clocks
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 9 peripheral clocks
1 FIFO7 OPB clocks + (8+N(2)) peripheral clocks
1 Memory7 OPB clocks + (4+5N(2)) peripheral clocks
Notes 1 Latency calculations assumes the device is always ready2 N = Access size on the OPB (in bytes)width of peripheral data bus (in bytes) where access size on OPB
equals or less than C_OPB_DWIDTH expressed in terms of bytes3 Latency calculation assumes that the requirement on address setup (C_PRHx_ADDR_TSU) address hold
(C_PRHx_ADDR_TH) and ADS pulse width (C_PRHx_ADS_WIDTH) are all less than one OPB clock
OPB EPC External Peripheral ConnectionsThe OPB EPC interface to the external device is based upon the width of the OPB data bus address and data width of the peripheral subsystem number of peripherals in the system addressdata multiplex support mode of operation (synchronous or asynchronous) and if synchronous device the operating clock for the synchronous data path
Determining Address and Data Width
The address bus width of the peripheral subsystem is the maximum width of the address bus of all peripheral devices connected to the OPB EPC If all devices employ non-multiplexed address and data bus the data bus width of the peripheral subsystem is the maximum of the data bus width of all external devices If any of the devices are configured for multiplexed address and data bus then the data bus width of the peripheral subsystem should be set as the maximum of the data bus and the address bus of the device(s) employing a multiplexed address and data bus
Discontinued IP
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OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Endian Considerations
The peripheral address and data bus of the OPB EPC is labeled with big endian bit labeling (D0 is the MSB and D31 is the LSB for a 32-bit bus) while most peripheral devices are either endian agnostic ie they can be connected either way or little endian (D31 is the MSB and D0 is the LSB for a 32-bit bus) Caution must be exercised with the connection to the external peripheral devices to avoid incorrect data and address connections
Clock Generation
When connecting to a synchronous external device the OPB EPC may operate either on the OPB clock (OPB_Clk) or on a peripheral clock (PRH_Clk) The operating clock for the synchronous interface is based on the generic C_PRH_CLK_SUPPORT If C_PRH_CLK_SUPPORT = 1 the peripheral clock is used else the OPB clock is used The external devices connected to the OPB EPC will determine the operating frequency of the peripheral clock The minimum of the operating frequencies of various devices connected to OPB EPC should be used as the operating frequency of the peripheral clock (PRH_Clk)
Figure 4 illustrates a block diagram for generating a device specific clock source clock source using two DCMs The DCM modules are located within the FPGA but are external to the OPB EPC An external clock source is used to generate the OPB clock (OPB_Clk) to the OPB EPC The device clock source (PRH_Clk) is also generated from the same DCM (DCM0) using the CLKFX output and must be routed on the board to be fed back to the FPGA Another DCM (DCM1) is used to synchronize the device peripheral clock to the OPB EPC PRH_Clk
Figure 4 External Peripherals clocked by FPGA output with feedback
igure Top x-ref 4
DS325_04_071406
CLKFB CLK0
CLKFXCLKIN
DCM0
PRH_Clk_FB
PRH_Clk
OPB_Clk
CLKFB CLK0
CLKIN
DCM1
PRH_Clk
OPB_Clk
OPB EPCExternalDevice
CLK
FPGA
Example Peripheral Connections
Example SMSC LAN91C111 10100 non-PCI Ethernet Single Chip MAC + PHY
An example peripheral device supported by the OPB EPC is the SMSC 10100 non-PCI Ethernet Single Chip MAC + PHY LAN91C111 The OPB EPC allows OPB masters to access the device both in synchronous and asynchronous mode The device connections for synchronous and asynchronous mode of operations are outlined in the Asynchronous Mode and Synchronous Mode sections
Discontinued IP
ust 10 2007 wwwxilinxcom 21ecification
OPB External Peripheral Controller (EPC) v100a
22
F
Asynchronous Mode
Figure 5 illustrates the SMSC LAN91C111 connections to the OPB EPC in asynchronous mode with non-multiplexed address and data buses In asynchronous mode the input clock source (PRH_Clk) to the external device must be tied to VCC When the SMSC LAN91C111 is accessed through the asynchronous mode the rising edge of PRH_Rd_n and PRH_Wr_n signals are used to control the read and the write operations respectively As the device uses Asynchronous Ready (ARDY) signal to indicate its readiness in asynchronous mode This signal is connected to the PRH_Rdy input of the OPB EPC Since the address and the data buses are not multiplexed PRH_ADS will be driven low by the OPB EPC
The following parameter settings apply for the connections shown in Figure 5
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 5 SMSC LAN91C111 Connection to OPB EPC in Asynchronous Mode
igure Top x-ref 5
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]
PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
To System Interrupt Controller
VCC
LCLKResetAENnADSA[151]
nBE[30]
ARDYnRdnWR
D[310]
INTRO
WnRnVLBUSnCYCLE
nRDYRTNnDADACS
nLDEVnSARDY
SMSC LAN91C111
ExternalGlue Logic
PPC
OP
B B
us
FPGA
DS325_05_071406
ExternalReset VCC
External Glue Logic
Special attention must be given while interfacing the OPB EPC to the SMSC LAN91C111 in asynchronous mode The OPB EPC drives the PRH_BE active high while the SMSC LAN91C111 requires the input byte enable to be active low To match this requirement external glue logic is required to invert the PRH_BE signals before they are interfaced with the byte enable signals of the SMSC LAN91C111
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Synchronous Mode
Figure 6 illustrates the SMSC LAN91C111 connection to the OPB EPC in synchronous VL Bus mode with non-multiplexed address and data buses In synchronous mode the device requires an input clock source to the LCLK pin with a maximum operating frequency of 50MHz The local clock generated by the DCM for the peripheral interface must be routed to the LCLK input of SMSC LAN91C111 and PRH_Clk of OPB EPC When the device is accessed PRH_RNW is used as the control signal to indicate a readwrite access When PRH_RNW is high it indicates a read operation and when low it indicates a write operation The SMSC LAN91C111 uses nSRDY signal to indicate the device readiness This signal is connected to PRH_Rdy input of the OPB_EPC As the address and the data bus are not multiplexed PRH_ADS will be driven low
The following parameter settings apply for the connections shown in Figure 6
bull C_PRH_CLK_SUPPORT = 1
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 1
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 6 SMSC LAN91C111 Connection to OPB EPC in Synchronous Mode
igure Top x-ref 6
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
LCLKResetAENnADSA[151]nBE[30]WnRnSRDY
D[310]
nCYCLEnRDYRTN
INTRO
nRdnWR
nDADACSnLDEVARDY
nVLBUS
SMSC LAN91C111
ExternalGlue Logic
DigitalClock
Manager
PP
C
OP
B B
us
FPGA
DS325_06_071406
External Reset
VCC
GND
To System Interrupt Controller
External Glue Logic
The SMSC LAN91C111 device requires two inputs nCYCLE and nRDYRTN to control synchronous operation The definition of these signals is outside the scope of this document and can be found in the documents listed in the Reference Documents section The nCYCLE and nRDYRTN signals are generated in external glue logic nCYCLE may be generated from PRH_CS_n and is driven low for a
Discontinued IP
ust 10 2007 wwwxilinxcom 23ecification
OPB External Peripheral Controller (EPC) v100a
24
single clock cycle on a high to low transition on PRH_CS_n nRDYRTN is simply the registered value of the nSRDY signal
Design Considerations
When the OPB EPC is interfaced to the SMSC LAN91C111 with data width match enabled (C_PRHx_DWIDTH_MATCH = 1) and the internal SRAM of the peripheral is being accessed the device has to be configured in the address auto increment mode Address auto increment mode can be configured by setting AUTO INCR bit in the Bank 2 Pointer Register of SMSC LAN91C111 More information can be obtained by referring the registers of Bank 2 in SMSC LAN91C111 data sheet See the Reference Documents section
Example Cypress Semiconductorrsquos CY7C67300 EZ-Host Programmable Embedded USB HostPeripheral Controller
The Cypress Semiconductorrsquos CY7C67300 EZ-Hosttrade Programmable Embedded USB HostPeripheral Controller is another example of a peripheral device supported by the OPB EPC Since the Cypress USB controller operates in asynchronous mode the OPB EPC must be configured to support asynchronous mode operation
Asynchronous Mode
Figure 7 illustrates the CY7C67300 USB Controller connection to the OPB EPC in asynchronous mode with non-multiplexed address and data buses
The following parameter settings apply for the connection shown in Figure 7
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 4
bull C_PRH0_DWIDTH = 16
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Configuration of CY7C67300 USB Controller
The CY7C67300 USB Controller is configured as a Host Processor Interface (HPI) The boot-up sequence code for the CY7C67300 USB Controller in this particular example is present on the external Compact Flash memory device and is accessed through the OPB SYSACE interface This code is downloaded to the CY7C67300 USB Controller through the HPI interface Once this boot-up sequence is executed by the CY7C67300 USB Controller it becomes ready to operate in normal HPI mode with the external host controller (OPB EPC)
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
F
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 7 CY7C67300 USB Controller connection to OPB EPC in asynchronous mode
igure Top x-ref 7
SysACE_mpd_I[015]SysACE_mpd_O[015]SysACE_mpd_T[015]
SysACE_mpweSysACE_mpoe
SysACE_MPA[06]
SysACE_CEN
OPB SYS ACE Cntlr[150][150][150]
[60]
PRH_RstPRH_Rdy
PRH_CS_n
PRH_Data_I[015]PRH_Data_O[015]PRH_Data_T[015]
PRH_ADSPRH_RRNW
PRH_BurstPRH_Rd_nPRH_Wr_n
PRH_Addr[01]
OPB EPC
VCC
Ext
erna
l US
B P
orts
P
ort 1
A 1
B 2
AnCS
nRD
nWR
[D15D0]
[A1A0]
INT
CompactFLASH
TQFP144 SYSTEMACE
System ACE CompactFlash Controller
Ext
erna
l Glu
e Lo
gic
OPBINTC
US
B C
Y7C
6730
0
PP
C
OP
B B
us
FPGA
DS325_07_071406
Sysace_epc_data[150]
HPI interface
Sysace_epc_rd_n
Sysace_epc_wr_n
Sysace_epc_a[10]
DM1B
DP1B
DM2A
DP2A
DM1A
DP1A
External Glue Logic
In the interface diagram shown in Figure 7 the OPB EPC as well as the OPB SYSACE share the interface for data address and control lines on the board This requires external multiplex logic to be placed outside of IP cores in the FPGA The OPB EPC control signals PRH_RD_n and PRH_WR_n are muxed with the MEM_CEN and MEM_WEN signals of the OPB SYSACE When CY7C67300 USB Controller is accessed through the asynchronous mode the rising edge of sysace_epc_rd_n and sysace_epc_wr_n signals are used to control the read and the write operations respectively See the Reference Documents section for more information on OPB SYSACE
Design Constraints
Timing Constraints
Timing constraints must be placed on the system clock and the peripheral clock setting the frequency to meet the bus timing requirements An example is shown in Figure 8
Discontinued IP
ust 10 2007 wwwxilinxcom 25ecification
F
OPB External Peripheral Controller (EPC) v100a
26
Figure 8 EPC Timing Constraints
igure Top x-ref 8
Following constraint must be placed on the system clock
TIMESPEC TS_OPB_Clk = PERIOD OPB_Clk 10 ns HIGH 50
NET OPB_Clk TNM_NET = OPB_Clk
If C_PRH_CLK_SUPPORT=1 then the following constraint must be placed on the peripheral clock
TIMESPEC TS_PRH_Clk = PERIOD PRH_Clk 20 ns HIGH 50
NET PRH_Clk TNM_NET = PRH_Clk
DS325_08_071406
Design Implementation
Timing Diagrams
The timing diagrams in the figures below show various OPB transactions and the resulting access cycles on the peripheral interface Timing diagrams are not shown for all possible combinations of generics and the resulting access cycles However the timing diagrams shown are sufficient for the basic understanding of various access cycles supported by the OPB EPC
Figure 9 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 9
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
DS325_09_071206
8
4000000
004
04
Figure 10 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 10
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
04000000
20000004
8
00000000
004
04DS325_10_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 11 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 11
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000000
F
00010203
000 001 002 003
00 01 02 03DS325_11_071206
Figure 12 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 12
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
20000000
F
0000000000000000
000 001 002 003
00 01 02 03DS325_12_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 27ecification
OPB External Peripheral Controller (EPC) v100a
28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 29ecification
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO 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50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Allowable Parameter Combinations
When the peripheral devices are confugured in non multiplexed mode the C_PRH_MAX_AWIDTH should be the maximum of C_PRHx_AWIDTH of all peripherals in the system ie if C_NUM_PERIPHERALS is 2 then C_PRH_MAX_AWIDTH should be maximum of C_PRH0_AWIDTH and C_PRH1_AWIDTH
C_PRH_MAX_DWIDTH should be the maximum of C_PRHx_DWIDTH of all peripherals in the system ie if C_NUM_PERIPHERALS is 2 then C_PRH_MAX_DWIDTH should be maximum of C_PRH0_DWIDTH and C_PRH1_DWIDTH
If any of the peripheral devices are configured for a multiplexed address and data buses then the parameter C_PRH_MAX_ADWIDTH should be set as the maximum of the data bus and address bus of the device(s) employing a multiplexed address and data bus If all devices employ non-multiplexed address and data buses then C_PRH_MAX_ADWIDTH reflects the maximum of data bus width of all external devices Therefore for any configuration the parameter C_PRH_MAX_ADWIDTH should be greater than or equal to C_PRH_MAX_DWIDTH
The generic C_PRH_CLK_SUPPORT is relevant only when the devices are configured for the synchronous access ie C_PRHx_SYNC = 1 If more than one of the devices are synchronous then the frequency for the peripheral clock should be chosen as the minimum of the operating frequencies of those devices
The range specified by C_PRHx_BASEADDR and C_PRHx_HIGHADDR parameters must comprise a contiguous range and the size of the range must be a power of two ie size of range = 2m Furthermore the rsquomrsquo least significant bits of C_PRHx_BASEADDR must be zero The base and high address range assigned to different peripherals must be mutually exclusive No default value will be specified for C_PRHx_BASEADDR and C_PRHx_HIGHADDR in order to enforce that the user configures these parameters with the actual values If the values are not set for C_PRHx_BASEADDR and C_PRHx_HIGHADDR a compiler error will be generated
In order to access FIFO like structures within the external peripheral devices C_PRHx_FIFO_ACCESS must be set to rsquo1rsquo When FIFO access is enabled C_PRHx_FIFO_OFFSET specifies the offset of the FIFO in terms of number of byte locations from the base address (C_PRHx_BASEADDR) of the peripheral and should be set to an offset that lies within the address range assigned to the peripheral device ie C_PRHx_BASEADDR + C_PRHx_FIFO_OFFSET le C_PRHx_HIGHADDR Furthermore the FIFO offset should be within the range addressable by the address bus ie C_PRHx_FIFO_OFFSET lt 2n
where n = C_PRHx_AWIDTH
The width of the readwrite strobe must be less than the cycle time of the corresponding access ie C_PRHx_WRN_WIDTH lt C_PRHx_WR_CYCLE and C_PRHx_RDN_WIDTH lt C_PRHx_RD_CYCLE The value of device ready validity period must be less than the readwrite strobe width and the maximum pulse width of the device ready signal ie C_PRHx_RDY_TOUT lt minimum of C_PRHx_WRN_WIDTH C_PRHx_RDN_WIDTH and C_PRHx_RDY_WIDTH
Parameter - Port Dependencies
The dependencies between the OPB EPC design parameters and the IO ports are shown in Table 3 The width of the OPB EPC signals depend on some of the parameters In addition when certain features are parameterized away the related logic is removed
Discontinued IP
ust 10 2007 wwwxilinxcom 13ecification
OPB External Peripheral Controller (EPC) v100a
14
Table 3 Parameter - Port Dependencies
Generic or Port
Name Affects Depends Description
Design Parameters
G3 C_OPB_AWIDTH P1 -The OPB address width parameter sets the width of the OPB address bus
G4 C_OPB_DWIDTHP2 P3
P7-
The OPB data width parameter affects the number of byte enables configured for the OPB data bus width of the OPB data bus and the width of the OPB slave read data bus
G6C_NUM_PERIPHERALS
P16 P24-
The number of peripherals in the system determines the number of chip select signals driven and the number of device ready inputs decoded by the OPB external peripheral controller
G7C_PRH_MAX_AWIDTH
P17- The width of the peripheral address bus is set to
the maximum of address bus width of all peripheral devices
G8C_PRH_MAX_DWIDTH
P19- The number of byte enables for the peripheral data
bus is determined by the maximum of data bus width of the peripheral devices
G9C_PRH_MAX_ADWIDTH
P25 P26 P27
-
The width of the peripheral input data bus peripheral output data bus and the peripheral output data bus 3-state control are determined by the maximum of data bus width of all peripherals and the address bus width of peripherals employing address data bus multiplexing
G10C_PRH_CLK_SUPPORT
P14- If C_PRH_CLK_SUPPORT = 0 then all external
devices operate on OPB clock The input PRH_Clk must be driven high externally
G18C_PRHx_DWIDTH_MATCH
P23-
If the device is configured for synchronous mode with data width matching enabled then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G19 C_PRHx_SYNCP14 P20 P21 P22
P23
-
If the device is configured for asynchronous mode
bull With peripheral clock support the peripheral clock input (PRH_Clk) must be driven high externally
bull PRH_RNW is driven high as PRH_Rd_n and PRH_Wr_n should be used as read and write strobe
bull With data width matching enabled the OPB EPC drives PRH_Burst to its default low
If the device is configured for synchronous mode
bull The OPB EPC drives PRH_Rd_n and PRH_Wr_n outputs to their default state of high since PRH_RNW output is used as readwrite strobe
G20C_PRHx_BUS_MULTIPLEX
P18- PRH_ADS is driven low if the device does not use
multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
IO Signals
P1 OPB_ABus - G3The OPB address bus width is determined by the C_OPB_AWIDTH parameter
P2 OPB_BE - G4The number of byte enables for the OPB data bus is determined by the C_OPB_DWIDTH parameter
P3 OPB_DBus - G4The OPB data bus width is determined by the C_OPB_DWIDTH parameter
P7 Sln_DBus-
G4The width of the OPB slave read data bus is determined by the C_OPB_DWIDTH parameter
P14 PRH_Clk-
G10 G19
PRH_Clk is selected as operating clock only if the device is configured for synchronous mode with peripheral clock support ie C_PRHx_SYNC = 1 and C_PRH_CLK_SUPPORT = 1 Asynchronous interface always operates on OPB_Clk Therefore if no device is configured for synchronous mode with peripheral clock support enabled then the input PRH_Clk must be driven high
P16 PRH_CS_n-
G6The number of chip select signals driven by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P17 PRH_Addr-
G7The width of the peripheral address bus is determined by the C_PRH_MAX_AWIDTH parameter
P18 PRH_ADS-
G20PRH_ADS is driven low if the device does not use multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
Discontinued IP
ust 10 2007 wwwxilinxcom 15ecification
OPB External Peripheral Controller (EPC) v100a
16
OPB EPC Design Considerations
The OPB EPC is an OPB slave only device It receives read or write instructions from the processor and generates a corresponding access cycle on the peripheral interface Examples of read and write accesses are illustrated in the Timing Diagrams section The user must take the following considerations into account while designing with the OPB EPC
Device Ready Signal
The OPB EPC readwrite access cycles are executed only when the external device assert the device ready signal (PRH_Rdy) If the external peripheral device does not have a device ready signal then the PRH_Rdy input of the OPB EPC must be tied to logic high
P19 PRH_BE - G8The number of byte enables for the peripheral data bus is determined by the C_PRH_MAX_DWIDTH parameter
P20 PHR_RNW-
G19
If the device is synchronous ie C_PRHx_SYNC = 1 then PRH_RNW should be used as the readwrite control signal For asynchronous mode of operation PRH_RNW is driven high
P21 PRH_Rd_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Rd_n should be used as the read strobe For synchronous mode of operation PRH_Rd_n is driven high
P22 PRH_Wr_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Wr_n should be used as the write strobe For synchronous mode of operation PRH_Wr_n is driven high
P23 PRH_Burst-
G18 G19
If the device is synchronous with data width matching enabled ie C_PRHx_SYNC = 1 and C_PRHx_DWIDTH_MATCH = 1 then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
P24 PRH_Rdy-
G6The number of device ready inputs decoded by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P25 PRH_Data_I-
G9The peripheral input data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P26 PRH_Data_O - G9The peripheral output data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P27 PRH_Data_T - G9
The peripheral output data bus 3-state control width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
FIFO Transactions
When C_PRHx_FIFO_ACCESS = 1 the OPB EPC supports access to FIFOrsquos within the external peripheral devices When the FIFO within the external device is accessed then the peripheral address bus (PRH_Addr) must remain constant representing the FIFO address within the address range assigned to the peripheral device When data width matching is enabled and the access corresponds to the FIFO the OPB EPC does not increment the peripheral address (PRH_Addr) bus
Abnormal Terminations
If PRH_Rdy is de-asserted for more than the maximum period as specified by C_PRHx_RDY_WIDTH then the OPB EPC terminates the current access to the external device and signals an error to the OPB master by asserting Sln_errAck on the OPB Similarly when the OPB master terminates the current access (master abort on the OPB) OPB EPC terminates the access to the external device immediately In both cases the access to the external device is terminated abnormally Therefore the external device may be in an indeterminate state and the exceptions should be handled appropriately at the system level
Interrupt Handling
If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Peripheral Data Bus Mapping
The peripheral data bus (PRH_Data) uses big endian bit labelling (ie bit-0 is Most Significant Bit (MSB) and bit-31 is Least Significant Bit (LSB) for a 32-bit bus) and is sized according to the C_PRH_MAX_ADWIDTH parameter Peripherals that have smaller widths should connect to this bus starting at bit 0 (MSB) For example if three external devices are present in the system with data bus width of 8-bit 16-bit and 32-bit the 8-bit device should connect to PRH_Data[07] the 16-bit wide peripheral should connect to PRH_Data[015] and the 32-bit peripheral should connect to PRH_Data[031]
The bit and byte labeling for the big endian data types is shown in Figure 3
Discontinued IP
ust 10 2007 wwwxilinxcom 17ecification
F
OPB External Peripheral Controller (EPC) v100a
18
Figure 3 OPB EPC Big Endian Data Type
igure Top x-ref 3
2 3
n+2 n+3
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 15
Halfword
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 31
Word
Byte
MS Byte
LS BitMS Bit
0
nByte address
Byte label
Byte significance
Bit label
Bit significance
0 7
DS325_03_071406
Unsupported Features
Many peripheral devices have the device specific inputoutput ports such as status remote reset remote wakeup interrupts etc The OPB EPC does not have any provision to support these device specific inputoutput ports Therefore if the external device has any such device specific ports then these inputoutput ports may be connected directly to system general purpose input output controller or to the system interrupt controller If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Many peripheral devices support DMA capability However currently OPB EPC is an OPB slave only device and therefore does not support DMA operations from the external peripheral devices
Current version of the OPB EPC does not support burst transactions tofrom the OPB
OPB EPC Latency
The OPB EPC latency calculations are based on the OPB clock The OPB latency is defined as the number of OPB clock cycles elapsed from the time an access is initiated to the time the access is completed (Sln_xferAck is asserted) on the OPB Table 4 shows the latency calculations for asynchronous mode and Table 5 shows the latency calculations for synchronous mode of operation
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 4 Asynchronous Mode OPB EPC Latency
Transaction Type
ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation(1)
OPB Latency
50 MHz
OPB Latency 100 MHz
ReadWrite access to asynchronous device when addressdata bus is not multiplexed
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5)
9(7) 12(7)
1FIFO
Memory
5 + N(2) (T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5))
21(7) 33(7)
ReadWrite access to asynchronous device when addressdata bus is multiplexed (Register access)
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + (T_SETUP(3) + T_ADDR_HOLD(6) + 1 + CONTROL_WIDTH(4) + T_HOLD(5))
11(7) 14(7)
1 FIFO
5 + T_SETUP(3) + T_ADDR_HOLD(6) + 1 + N(2) (CONTROL_WIDTH(4) + T_HOLD(5))
20(7) 29(7)
1 Memory
4 + N(2) (T_SETUP(3) + T_ADDR_HOLD(6) + CONTROL_WIDTH(4) + T_HOLD(5) + 2)
32(7) 44(7)
Notes 1 Latency calculations assumes the device is always ready2 If C_PRHx_DWIDTH_MATCH = 1 then N = Access size on OPB (in bytes)width of peripheral data bus (in
bytes)3 T_SETUP is the setup time requirement on various control signals in terms of number of OPB clocks and is
device specific4 CONTROL_WIDTH represents the required width for readwrite signal in terms of number of OPB clocks and
is device specific 5 T_HOLD is the hold time requirement on various control signals in terms of number of OPB clocks and is
device specific6 T_ADDR_HOLD is the required hold time on the address bus (as specified by generic C_PRHx_ADDR_TH) in
terms of number of OPB clocks and is device specific 7 Calculation are made for typical values of various timing parameters with T_SETUP = 20ns T_HOLD = 10ns
T_ADDR_HOLD = 6ns and STROBE_WIDTH = 40ns
Discontinued IP
ust 10 2007 wwwxilinxcom 19ecification
OPB External Peripheral Controller (EPC) v100a
20
Table 5 Synchronous Mode OPB EPC Latency
Transaction Type ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory 9
1FIFO
Memory 8 + N(2)
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory 11
1 FIFO 10 + N(2)
1 Memory 6 + 5N(2)
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 7 peripheral clocks
1FIFO
Memory
7 OPB clocks + (6+N(2)) peripheral clocks
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 9 peripheral clocks
1 FIFO7 OPB clocks + (8+N(2)) peripheral clocks
1 Memory7 OPB clocks + (4+5N(2)) peripheral clocks
Notes 1 Latency calculations assumes the device is always ready2 N = Access size on the OPB (in bytes)width of peripheral data bus (in bytes) where access size on OPB
equals or less than C_OPB_DWIDTH expressed in terms of bytes3 Latency calculation assumes that the requirement on address setup (C_PRHx_ADDR_TSU) address hold
(C_PRHx_ADDR_TH) and ADS pulse width (C_PRHx_ADS_WIDTH) are all less than one OPB clock
OPB EPC External Peripheral ConnectionsThe OPB EPC interface to the external device is based upon the width of the OPB data bus address and data width of the peripheral subsystem number of peripherals in the system addressdata multiplex support mode of operation (synchronous or asynchronous) and if synchronous device the operating clock for the synchronous data path
Determining Address and Data Width
The address bus width of the peripheral subsystem is the maximum width of the address bus of all peripheral devices connected to the OPB EPC If all devices employ non-multiplexed address and data bus the data bus width of the peripheral subsystem is the maximum of the data bus width of all external devices If any of the devices are configured for multiplexed address and data bus then the data bus width of the peripheral subsystem should be set as the maximum of the data bus and the address bus of the device(s) employing a multiplexed address and data bus
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Endian Considerations
The peripheral address and data bus of the OPB EPC is labeled with big endian bit labeling (D0 is the MSB and D31 is the LSB for a 32-bit bus) while most peripheral devices are either endian agnostic ie they can be connected either way or little endian (D31 is the MSB and D0 is the LSB for a 32-bit bus) Caution must be exercised with the connection to the external peripheral devices to avoid incorrect data and address connections
Clock Generation
When connecting to a synchronous external device the OPB EPC may operate either on the OPB clock (OPB_Clk) or on a peripheral clock (PRH_Clk) The operating clock for the synchronous interface is based on the generic C_PRH_CLK_SUPPORT If C_PRH_CLK_SUPPORT = 1 the peripheral clock is used else the OPB clock is used The external devices connected to the OPB EPC will determine the operating frequency of the peripheral clock The minimum of the operating frequencies of various devices connected to OPB EPC should be used as the operating frequency of the peripheral clock (PRH_Clk)
Figure 4 illustrates a block diagram for generating a device specific clock source clock source using two DCMs The DCM modules are located within the FPGA but are external to the OPB EPC An external clock source is used to generate the OPB clock (OPB_Clk) to the OPB EPC The device clock source (PRH_Clk) is also generated from the same DCM (DCM0) using the CLKFX output and must be routed on the board to be fed back to the FPGA Another DCM (DCM1) is used to synchronize the device peripheral clock to the OPB EPC PRH_Clk
Figure 4 External Peripherals clocked by FPGA output with feedback
igure Top x-ref 4
DS325_04_071406
CLKFB CLK0
CLKFXCLKIN
DCM0
PRH_Clk_FB
PRH_Clk
OPB_Clk
CLKFB CLK0
CLKIN
DCM1
PRH_Clk
OPB_Clk
OPB EPCExternalDevice
CLK
FPGA
Example Peripheral Connections
Example SMSC LAN91C111 10100 non-PCI Ethernet Single Chip MAC + PHY
An example peripheral device supported by the OPB EPC is the SMSC 10100 non-PCI Ethernet Single Chip MAC + PHY LAN91C111 The OPB EPC allows OPB masters to access the device both in synchronous and asynchronous mode The device connections for synchronous and asynchronous mode of operations are outlined in the Asynchronous Mode and Synchronous Mode sections
Discontinued IP
ust 10 2007 wwwxilinxcom 21ecification
OPB External Peripheral Controller (EPC) v100a
22
F
Asynchronous Mode
Figure 5 illustrates the SMSC LAN91C111 connections to the OPB EPC in asynchronous mode with non-multiplexed address and data buses In asynchronous mode the input clock source (PRH_Clk) to the external device must be tied to VCC When the SMSC LAN91C111 is accessed through the asynchronous mode the rising edge of PRH_Rd_n and PRH_Wr_n signals are used to control the read and the write operations respectively As the device uses Asynchronous Ready (ARDY) signal to indicate its readiness in asynchronous mode This signal is connected to the PRH_Rdy input of the OPB EPC Since the address and the data buses are not multiplexed PRH_ADS will be driven low by the OPB EPC
The following parameter settings apply for the connections shown in Figure 5
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 5 SMSC LAN91C111 Connection to OPB EPC in Asynchronous Mode
igure Top x-ref 5
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]
PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
To System Interrupt Controller
VCC
LCLKResetAENnADSA[151]
nBE[30]
ARDYnRdnWR
D[310]
INTRO
WnRnVLBUSnCYCLE
nRDYRTNnDADACS
nLDEVnSARDY
SMSC LAN91C111
ExternalGlue Logic
PPC
OP
B B
us
FPGA
DS325_05_071406
ExternalReset VCC
External Glue Logic
Special attention must be given while interfacing the OPB EPC to the SMSC LAN91C111 in asynchronous mode The OPB EPC drives the PRH_BE active high while the SMSC LAN91C111 requires the input byte enable to be active low To match this requirement external glue logic is required to invert the PRH_BE signals before they are interfaced with the byte enable signals of the SMSC LAN91C111
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Synchronous Mode
Figure 6 illustrates the SMSC LAN91C111 connection to the OPB EPC in synchronous VL Bus mode with non-multiplexed address and data buses In synchronous mode the device requires an input clock source to the LCLK pin with a maximum operating frequency of 50MHz The local clock generated by the DCM for the peripheral interface must be routed to the LCLK input of SMSC LAN91C111 and PRH_Clk of OPB EPC When the device is accessed PRH_RNW is used as the control signal to indicate a readwrite access When PRH_RNW is high it indicates a read operation and when low it indicates a write operation The SMSC LAN91C111 uses nSRDY signal to indicate the device readiness This signal is connected to PRH_Rdy input of the OPB_EPC As the address and the data bus are not multiplexed PRH_ADS will be driven low
The following parameter settings apply for the connections shown in Figure 6
bull C_PRH_CLK_SUPPORT = 1
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 1
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 6 SMSC LAN91C111 Connection to OPB EPC in Synchronous Mode
igure Top x-ref 6
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
LCLKResetAENnADSA[151]nBE[30]WnRnSRDY
D[310]
nCYCLEnRDYRTN
INTRO
nRdnWR
nDADACSnLDEVARDY
nVLBUS
SMSC LAN91C111
ExternalGlue Logic
DigitalClock
Manager
PP
C
OP
B B
us
FPGA
DS325_06_071406
External Reset
VCC
GND
To System Interrupt Controller
External Glue Logic
The SMSC LAN91C111 device requires two inputs nCYCLE and nRDYRTN to control synchronous operation The definition of these signals is outside the scope of this document and can be found in the documents listed in the Reference Documents section The nCYCLE and nRDYRTN signals are generated in external glue logic nCYCLE may be generated from PRH_CS_n and is driven low for a
Discontinued IP
ust 10 2007 wwwxilinxcom 23ecification
OPB External Peripheral Controller (EPC) v100a
24
single clock cycle on a high to low transition on PRH_CS_n nRDYRTN is simply the registered value of the nSRDY signal
Design Considerations
When the OPB EPC is interfaced to the SMSC LAN91C111 with data width match enabled (C_PRHx_DWIDTH_MATCH = 1) and the internal SRAM of the peripheral is being accessed the device has to be configured in the address auto increment mode Address auto increment mode can be configured by setting AUTO INCR bit in the Bank 2 Pointer Register of SMSC LAN91C111 More information can be obtained by referring the registers of Bank 2 in SMSC LAN91C111 data sheet See the Reference Documents section
Example Cypress Semiconductorrsquos CY7C67300 EZ-Host Programmable Embedded USB HostPeripheral Controller
The Cypress Semiconductorrsquos CY7C67300 EZ-Hosttrade Programmable Embedded USB HostPeripheral Controller is another example of a peripheral device supported by the OPB EPC Since the Cypress USB controller operates in asynchronous mode the OPB EPC must be configured to support asynchronous mode operation
Asynchronous Mode
Figure 7 illustrates the CY7C67300 USB Controller connection to the OPB EPC in asynchronous mode with non-multiplexed address and data buses
The following parameter settings apply for the connection shown in Figure 7
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 4
bull C_PRH0_DWIDTH = 16
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Configuration of CY7C67300 USB Controller
The CY7C67300 USB Controller is configured as a Host Processor Interface (HPI) The boot-up sequence code for the CY7C67300 USB Controller in this particular example is present on the external Compact Flash memory device and is accessed through the OPB SYSACE interface This code is downloaded to the CY7C67300 USB Controller through the HPI interface Once this boot-up sequence is executed by the CY7C67300 USB Controller it becomes ready to operate in normal HPI mode with the external host controller (OPB EPC)
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
F
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 7 CY7C67300 USB Controller connection to OPB EPC in asynchronous mode
igure Top x-ref 7
SysACE_mpd_I[015]SysACE_mpd_O[015]SysACE_mpd_T[015]
SysACE_mpweSysACE_mpoe
SysACE_MPA[06]
SysACE_CEN
OPB SYS ACE Cntlr[150][150][150]
[60]
PRH_RstPRH_Rdy
PRH_CS_n
PRH_Data_I[015]PRH_Data_O[015]PRH_Data_T[015]
PRH_ADSPRH_RRNW
PRH_BurstPRH_Rd_nPRH_Wr_n
PRH_Addr[01]
OPB EPC
VCC
Ext
erna
l US
B P
orts
P
ort 1
A 1
B 2
AnCS
nRD
nWR
[D15D0]
[A1A0]
INT
CompactFLASH
TQFP144 SYSTEMACE
System ACE CompactFlash Controller
Ext
erna
l Glu
e Lo
gic
OPBINTC
US
B C
Y7C
6730
0
PP
C
OP
B B
us
FPGA
DS325_07_071406
Sysace_epc_data[150]
HPI interface
Sysace_epc_rd_n
Sysace_epc_wr_n
Sysace_epc_a[10]
DM1B
DP1B
DM2A
DP2A
DM1A
DP1A
External Glue Logic
In the interface diagram shown in Figure 7 the OPB EPC as well as the OPB SYSACE share the interface for data address and control lines on the board This requires external multiplex logic to be placed outside of IP cores in the FPGA The OPB EPC control signals PRH_RD_n and PRH_WR_n are muxed with the MEM_CEN and MEM_WEN signals of the OPB SYSACE When CY7C67300 USB Controller is accessed through the asynchronous mode the rising edge of sysace_epc_rd_n and sysace_epc_wr_n signals are used to control the read and the write operations respectively See the Reference Documents section for more information on OPB SYSACE
Design Constraints
Timing Constraints
Timing constraints must be placed on the system clock and the peripheral clock setting the frequency to meet the bus timing requirements An example is shown in Figure 8
Discontinued IP
ust 10 2007 wwwxilinxcom 25ecification
F
OPB External Peripheral Controller (EPC) v100a
26
Figure 8 EPC Timing Constraints
igure Top x-ref 8
Following constraint must be placed on the system clock
TIMESPEC TS_OPB_Clk = PERIOD OPB_Clk 10 ns HIGH 50
NET OPB_Clk TNM_NET = OPB_Clk
If C_PRH_CLK_SUPPORT=1 then the following constraint must be placed on the peripheral clock
TIMESPEC TS_PRH_Clk = PERIOD PRH_Clk 20 ns HIGH 50
NET PRH_Clk TNM_NET = PRH_Clk
DS325_08_071406
Design Implementation
Timing Diagrams
The timing diagrams in the figures below show various OPB transactions and the resulting access cycles on the peripheral interface Timing diagrams are not shown for all possible combinations of generics and the resulting access cycles However the timing diagrams shown are sufficient for the basic understanding of various access cycles supported by the OPB EPC
Figure 9 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 9
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
DS325_09_071206
8
4000000
004
04
Figure 10 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 10
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
04000000
20000004
8
00000000
004
04DS325_10_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 11 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 11
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000000
F
00010203
000 001 002 003
00 01 02 03DS325_11_071206
Figure 12 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 12
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
20000000
F
0000000000000000
000 001 002 003
00 01 02 03DS325_12_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 27ecification
OPB External Peripheral Controller (EPC) v100a
28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 29ecification
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
14
Table 3 Parameter - Port Dependencies
Generic or Port
Name Affects Depends Description
Design Parameters
G3 C_OPB_AWIDTH P1 -The OPB address width parameter sets the width of the OPB address bus
G4 C_OPB_DWIDTHP2 P3
P7-
The OPB data width parameter affects the number of byte enables configured for the OPB data bus width of the OPB data bus and the width of the OPB slave read data bus
G6C_NUM_PERIPHERALS
P16 P24-
The number of peripherals in the system determines the number of chip select signals driven and the number of device ready inputs decoded by the OPB external peripheral controller
G7C_PRH_MAX_AWIDTH
P17- The width of the peripheral address bus is set to
the maximum of address bus width of all peripheral devices
G8C_PRH_MAX_DWIDTH
P19- The number of byte enables for the peripheral data
bus is determined by the maximum of data bus width of the peripheral devices
G9C_PRH_MAX_ADWIDTH
P25 P26 P27
-
The width of the peripheral input data bus peripheral output data bus and the peripheral output data bus 3-state control are determined by the maximum of data bus width of all peripherals and the address bus width of peripherals employing address data bus multiplexing
G10C_PRH_CLK_SUPPORT
P14- If C_PRH_CLK_SUPPORT = 0 then all external
devices operate on OPB clock The input PRH_Clk must be driven high externally
G18C_PRHx_DWIDTH_MATCH
P23-
If the device is configured for synchronous mode with data width matching enabled then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G19 C_PRHx_SYNCP14 P20 P21 P22
P23
-
If the device is configured for asynchronous mode
bull With peripheral clock support the peripheral clock input (PRH_Clk) must be driven high externally
bull PRH_RNW is driven high as PRH_Rd_n and PRH_Wr_n should be used as read and write strobe
bull With data width matching enabled the OPB EPC drives PRH_Burst to its default low
If the device is configured for synchronous mode
bull The OPB EPC drives PRH_Rd_n and PRH_Wr_n outputs to their default state of high since PRH_RNW output is used as readwrite strobe
G20C_PRHx_BUS_MULTIPLEX
P18- PRH_ADS is driven low if the device does not use
multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
IO Signals
P1 OPB_ABus - G3The OPB address bus width is determined by the C_OPB_AWIDTH parameter
P2 OPB_BE - G4The number of byte enables for the OPB data bus is determined by the C_OPB_DWIDTH parameter
P3 OPB_DBus - G4The OPB data bus width is determined by the C_OPB_DWIDTH parameter
P7 Sln_DBus-
G4The width of the OPB slave read data bus is determined by the C_OPB_DWIDTH parameter
P14 PRH_Clk-
G10 G19
PRH_Clk is selected as operating clock only if the device is configured for synchronous mode with peripheral clock support ie C_PRHx_SYNC = 1 and C_PRH_CLK_SUPPORT = 1 Asynchronous interface always operates on OPB_Clk Therefore if no device is configured for synchronous mode with peripheral clock support enabled then the input PRH_Clk must be driven high
P16 PRH_CS_n-
G6The number of chip select signals driven by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P17 PRH_Addr-
G7The width of the peripheral address bus is determined by the C_PRH_MAX_AWIDTH parameter
P18 PRH_ADS-
G20PRH_ADS is driven low if the device does not use multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
Discontinued IP
ust 10 2007 wwwxilinxcom 15ecification
OPB External Peripheral Controller (EPC) v100a
16
OPB EPC Design Considerations
The OPB EPC is an OPB slave only device It receives read or write instructions from the processor and generates a corresponding access cycle on the peripheral interface Examples of read and write accesses are illustrated in the Timing Diagrams section The user must take the following considerations into account while designing with the OPB EPC
Device Ready Signal
The OPB EPC readwrite access cycles are executed only when the external device assert the device ready signal (PRH_Rdy) If the external peripheral device does not have a device ready signal then the PRH_Rdy input of the OPB EPC must be tied to logic high
P19 PRH_BE - G8The number of byte enables for the peripheral data bus is determined by the C_PRH_MAX_DWIDTH parameter
P20 PHR_RNW-
G19
If the device is synchronous ie C_PRHx_SYNC = 1 then PRH_RNW should be used as the readwrite control signal For asynchronous mode of operation PRH_RNW is driven high
P21 PRH_Rd_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Rd_n should be used as the read strobe For synchronous mode of operation PRH_Rd_n is driven high
P22 PRH_Wr_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Wr_n should be used as the write strobe For synchronous mode of operation PRH_Wr_n is driven high
P23 PRH_Burst-
G18 G19
If the device is synchronous with data width matching enabled ie C_PRHx_SYNC = 1 and C_PRHx_DWIDTH_MATCH = 1 then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
P24 PRH_Rdy-
G6The number of device ready inputs decoded by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P25 PRH_Data_I-
G9The peripheral input data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P26 PRH_Data_O - G9The peripheral output data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P27 PRH_Data_T - G9
The peripheral output data bus 3-state control width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
Discontinued IP
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OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
FIFO Transactions
When C_PRHx_FIFO_ACCESS = 1 the OPB EPC supports access to FIFOrsquos within the external peripheral devices When the FIFO within the external device is accessed then the peripheral address bus (PRH_Addr) must remain constant representing the FIFO address within the address range assigned to the peripheral device When data width matching is enabled and the access corresponds to the FIFO the OPB EPC does not increment the peripheral address (PRH_Addr) bus
Abnormal Terminations
If PRH_Rdy is de-asserted for more than the maximum period as specified by C_PRHx_RDY_WIDTH then the OPB EPC terminates the current access to the external device and signals an error to the OPB master by asserting Sln_errAck on the OPB Similarly when the OPB master terminates the current access (master abort on the OPB) OPB EPC terminates the access to the external device immediately In both cases the access to the external device is terminated abnormally Therefore the external device may be in an indeterminate state and the exceptions should be handled appropriately at the system level
Interrupt Handling
If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Peripheral Data Bus Mapping
The peripheral data bus (PRH_Data) uses big endian bit labelling (ie bit-0 is Most Significant Bit (MSB) and bit-31 is Least Significant Bit (LSB) for a 32-bit bus) and is sized according to the C_PRH_MAX_ADWIDTH parameter Peripherals that have smaller widths should connect to this bus starting at bit 0 (MSB) For example if three external devices are present in the system with data bus width of 8-bit 16-bit and 32-bit the 8-bit device should connect to PRH_Data[07] the 16-bit wide peripheral should connect to PRH_Data[015] and the 32-bit peripheral should connect to PRH_Data[031]
The bit and byte labeling for the big endian data types is shown in Figure 3
Discontinued IP
ust 10 2007 wwwxilinxcom 17ecification
F
OPB External Peripheral Controller (EPC) v100a
18
Figure 3 OPB EPC Big Endian Data Type
igure Top x-ref 3
2 3
n+2 n+3
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 15
Halfword
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 31
Word
Byte
MS Byte
LS BitMS Bit
0
nByte address
Byte label
Byte significance
Bit label
Bit significance
0 7
DS325_03_071406
Unsupported Features
Many peripheral devices have the device specific inputoutput ports such as status remote reset remote wakeup interrupts etc The OPB EPC does not have any provision to support these device specific inputoutput ports Therefore if the external device has any such device specific ports then these inputoutput ports may be connected directly to system general purpose input output controller or to the system interrupt controller If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Many peripheral devices support DMA capability However currently OPB EPC is an OPB slave only device and therefore does not support DMA operations from the external peripheral devices
Current version of the OPB EPC does not support burst transactions tofrom the OPB
OPB EPC Latency
The OPB EPC latency calculations are based on the OPB clock The OPB latency is defined as the number of OPB clock cycles elapsed from the time an access is initiated to the time the access is completed (Sln_xferAck is asserted) on the OPB Table 4 shows the latency calculations for asynchronous mode and Table 5 shows the latency calculations for synchronous mode of operation
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 4 Asynchronous Mode OPB EPC Latency
Transaction Type
ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation(1)
OPB Latency
50 MHz
OPB Latency 100 MHz
ReadWrite access to asynchronous device when addressdata bus is not multiplexed
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5)
9(7) 12(7)
1FIFO
Memory
5 + N(2) (T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5))
21(7) 33(7)
ReadWrite access to asynchronous device when addressdata bus is multiplexed (Register access)
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + (T_SETUP(3) + T_ADDR_HOLD(6) + 1 + CONTROL_WIDTH(4) + T_HOLD(5))
11(7) 14(7)
1 FIFO
5 + T_SETUP(3) + T_ADDR_HOLD(6) + 1 + N(2) (CONTROL_WIDTH(4) + T_HOLD(5))
20(7) 29(7)
1 Memory
4 + N(2) (T_SETUP(3) + T_ADDR_HOLD(6) + CONTROL_WIDTH(4) + T_HOLD(5) + 2)
32(7) 44(7)
Notes 1 Latency calculations assumes the device is always ready2 If C_PRHx_DWIDTH_MATCH = 1 then N = Access size on OPB (in bytes)width of peripheral data bus (in
bytes)3 T_SETUP is the setup time requirement on various control signals in terms of number of OPB clocks and is
device specific4 CONTROL_WIDTH represents the required width for readwrite signal in terms of number of OPB clocks and
is device specific 5 T_HOLD is the hold time requirement on various control signals in terms of number of OPB clocks and is
device specific6 T_ADDR_HOLD is the required hold time on the address bus (as specified by generic C_PRHx_ADDR_TH) in
terms of number of OPB clocks and is device specific 7 Calculation are made for typical values of various timing parameters with T_SETUP = 20ns T_HOLD = 10ns
T_ADDR_HOLD = 6ns and STROBE_WIDTH = 40ns
Discontinued IP
ust 10 2007 wwwxilinxcom 19ecification
OPB External Peripheral Controller (EPC) v100a
20
Table 5 Synchronous Mode OPB EPC Latency
Transaction Type ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory 9
1FIFO
Memory 8 + N(2)
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory 11
1 FIFO 10 + N(2)
1 Memory 6 + 5N(2)
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 7 peripheral clocks
1FIFO
Memory
7 OPB clocks + (6+N(2)) peripheral clocks
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 9 peripheral clocks
1 FIFO7 OPB clocks + (8+N(2)) peripheral clocks
1 Memory7 OPB clocks + (4+5N(2)) peripheral clocks
Notes 1 Latency calculations assumes the device is always ready2 N = Access size on the OPB (in bytes)width of peripheral data bus (in bytes) where access size on OPB
equals or less than C_OPB_DWIDTH expressed in terms of bytes3 Latency calculation assumes that the requirement on address setup (C_PRHx_ADDR_TSU) address hold
(C_PRHx_ADDR_TH) and ADS pulse width (C_PRHx_ADS_WIDTH) are all less than one OPB clock
OPB EPC External Peripheral ConnectionsThe OPB EPC interface to the external device is based upon the width of the OPB data bus address and data width of the peripheral subsystem number of peripherals in the system addressdata multiplex support mode of operation (synchronous or asynchronous) and if synchronous device the operating clock for the synchronous data path
Determining Address and Data Width
The address bus width of the peripheral subsystem is the maximum width of the address bus of all peripheral devices connected to the OPB EPC If all devices employ non-multiplexed address and data bus the data bus width of the peripheral subsystem is the maximum of the data bus width of all external devices If any of the devices are configured for multiplexed address and data bus then the data bus width of the peripheral subsystem should be set as the maximum of the data bus and the address bus of the device(s) employing a multiplexed address and data bus
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Endian Considerations
The peripheral address and data bus of the OPB EPC is labeled with big endian bit labeling (D0 is the MSB and D31 is the LSB for a 32-bit bus) while most peripheral devices are either endian agnostic ie they can be connected either way or little endian (D31 is the MSB and D0 is the LSB for a 32-bit bus) Caution must be exercised with the connection to the external peripheral devices to avoid incorrect data and address connections
Clock Generation
When connecting to a synchronous external device the OPB EPC may operate either on the OPB clock (OPB_Clk) or on a peripheral clock (PRH_Clk) The operating clock for the synchronous interface is based on the generic C_PRH_CLK_SUPPORT If C_PRH_CLK_SUPPORT = 1 the peripheral clock is used else the OPB clock is used The external devices connected to the OPB EPC will determine the operating frequency of the peripheral clock The minimum of the operating frequencies of various devices connected to OPB EPC should be used as the operating frequency of the peripheral clock (PRH_Clk)
Figure 4 illustrates a block diagram for generating a device specific clock source clock source using two DCMs The DCM modules are located within the FPGA but are external to the OPB EPC An external clock source is used to generate the OPB clock (OPB_Clk) to the OPB EPC The device clock source (PRH_Clk) is also generated from the same DCM (DCM0) using the CLKFX output and must be routed on the board to be fed back to the FPGA Another DCM (DCM1) is used to synchronize the device peripheral clock to the OPB EPC PRH_Clk
Figure 4 External Peripherals clocked by FPGA output with feedback
igure Top x-ref 4
DS325_04_071406
CLKFB CLK0
CLKFXCLKIN
DCM0
PRH_Clk_FB
PRH_Clk
OPB_Clk
CLKFB CLK0
CLKIN
DCM1
PRH_Clk
OPB_Clk
OPB EPCExternalDevice
CLK
FPGA
Example Peripheral Connections
Example SMSC LAN91C111 10100 non-PCI Ethernet Single Chip MAC + PHY
An example peripheral device supported by the OPB EPC is the SMSC 10100 non-PCI Ethernet Single Chip MAC + PHY LAN91C111 The OPB EPC allows OPB masters to access the device both in synchronous and asynchronous mode The device connections for synchronous and asynchronous mode of operations are outlined in the Asynchronous Mode and Synchronous Mode sections
Discontinued IP
ust 10 2007 wwwxilinxcom 21ecification
OPB External Peripheral Controller (EPC) v100a
22
F
Asynchronous Mode
Figure 5 illustrates the SMSC LAN91C111 connections to the OPB EPC in asynchronous mode with non-multiplexed address and data buses In asynchronous mode the input clock source (PRH_Clk) to the external device must be tied to VCC When the SMSC LAN91C111 is accessed through the asynchronous mode the rising edge of PRH_Rd_n and PRH_Wr_n signals are used to control the read and the write operations respectively As the device uses Asynchronous Ready (ARDY) signal to indicate its readiness in asynchronous mode This signal is connected to the PRH_Rdy input of the OPB EPC Since the address and the data buses are not multiplexed PRH_ADS will be driven low by the OPB EPC
The following parameter settings apply for the connections shown in Figure 5
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 5 SMSC LAN91C111 Connection to OPB EPC in Asynchronous Mode
igure Top x-ref 5
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]
PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
To System Interrupt Controller
VCC
LCLKResetAENnADSA[151]
nBE[30]
ARDYnRdnWR
D[310]
INTRO
WnRnVLBUSnCYCLE
nRDYRTNnDADACS
nLDEVnSARDY
SMSC LAN91C111
ExternalGlue Logic
PPC
OP
B B
us
FPGA
DS325_05_071406
ExternalReset VCC
External Glue Logic
Special attention must be given while interfacing the OPB EPC to the SMSC LAN91C111 in asynchronous mode The OPB EPC drives the PRH_BE active high while the SMSC LAN91C111 requires the input byte enable to be active low To match this requirement external glue logic is required to invert the PRH_BE signals before they are interfaced with the byte enable signals of the SMSC LAN91C111
Discontinued IP
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OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Synchronous Mode
Figure 6 illustrates the SMSC LAN91C111 connection to the OPB EPC in synchronous VL Bus mode with non-multiplexed address and data buses In synchronous mode the device requires an input clock source to the LCLK pin with a maximum operating frequency of 50MHz The local clock generated by the DCM for the peripheral interface must be routed to the LCLK input of SMSC LAN91C111 and PRH_Clk of OPB EPC When the device is accessed PRH_RNW is used as the control signal to indicate a readwrite access When PRH_RNW is high it indicates a read operation and when low it indicates a write operation The SMSC LAN91C111 uses nSRDY signal to indicate the device readiness This signal is connected to PRH_Rdy input of the OPB_EPC As the address and the data bus are not multiplexed PRH_ADS will be driven low
The following parameter settings apply for the connections shown in Figure 6
bull C_PRH_CLK_SUPPORT = 1
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 1
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 6 SMSC LAN91C111 Connection to OPB EPC in Synchronous Mode
igure Top x-ref 6
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
LCLKResetAENnADSA[151]nBE[30]WnRnSRDY
D[310]
nCYCLEnRDYRTN
INTRO
nRdnWR
nDADACSnLDEVARDY
nVLBUS
SMSC LAN91C111
ExternalGlue Logic
DigitalClock
Manager
PP
C
OP
B B
us
FPGA
DS325_06_071406
External Reset
VCC
GND
To System Interrupt Controller
External Glue Logic
The SMSC LAN91C111 device requires two inputs nCYCLE and nRDYRTN to control synchronous operation The definition of these signals is outside the scope of this document and can be found in the documents listed in the Reference Documents section The nCYCLE and nRDYRTN signals are generated in external glue logic nCYCLE may be generated from PRH_CS_n and is driven low for a
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ust 10 2007 wwwxilinxcom 23ecification
OPB External Peripheral Controller (EPC) v100a
24
single clock cycle on a high to low transition on PRH_CS_n nRDYRTN is simply the registered value of the nSRDY signal
Design Considerations
When the OPB EPC is interfaced to the SMSC LAN91C111 with data width match enabled (C_PRHx_DWIDTH_MATCH = 1) and the internal SRAM of the peripheral is being accessed the device has to be configured in the address auto increment mode Address auto increment mode can be configured by setting AUTO INCR bit in the Bank 2 Pointer Register of SMSC LAN91C111 More information can be obtained by referring the registers of Bank 2 in SMSC LAN91C111 data sheet See the Reference Documents section
Example Cypress Semiconductorrsquos CY7C67300 EZ-Host Programmable Embedded USB HostPeripheral Controller
The Cypress Semiconductorrsquos CY7C67300 EZ-Hosttrade Programmable Embedded USB HostPeripheral Controller is another example of a peripheral device supported by the OPB EPC Since the Cypress USB controller operates in asynchronous mode the OPB EPC must be configured to support asynchronous mode operation
Asynchronous Mode
Figure 7 illustrates the CY7C67300 USB Controller connection to the OPB EPC in asynchronous mode with non-multiplexed address and data buses
The following parameter settings apply for the connection shown in Figure 7
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 4
bull C_PRH0_DWIDTH = 16
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Configuration of CY7C67300 USB Controller
The CY7C67300 USB Controller is configured as a Host Processor Interface (HPI) The boot-up sequence code for the CY7C67300 USB Controller in this particular example is present on the external Compact Flash memory device and is accessed through the OPB SYSACE interface This code is downloaded to the CY7C67300 USB Controller through the HPI interface Once this boot-up sequence is executed by the CY7C67300 USB Controller it becomes ready to operate in normal HPI mode with the external host controller (OPB EPC)
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
F
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 7 CY7C67300 USB Controller connection to OPB EPC in asynchronous mode
igure Top x-ref 7
SysACE_mpd_I[015]SysACE_mpd_O[015]SysACE_mpd_T[015]
SysACE_mpweSysACE_mpoe
SysACE_MPA[06]
SysACE_CEN
OPB SYS ACE Cntlr[150][150][150]
[60]
PRH_RstPRH_Rdy
PRH_CS_n
PRH_Data_I[015]PRH_Data_O[015]PRH_Data_T[015]
PRH_ADSPRH_RRNW
PRH_BurstPRH_Rd_nPRH_Wr_n
PRH_Addr[01]
OPB EPC
VCC
Ext
erna
l US
B P
orts
P
ort 1
A 1
B 2
AnCS
nRD
nWR
[D15D0]
[A1A0]
INT
CompactFLASH
TQFP144 SYSTEMACE
System ACE CompactFlash Controller
Ext
erna
l Glu
e Lo
gic
OPBINTC
US
B C
Y7C
6730
0
PP
C
OP
B B
us
FPGA
DS325_07_071406
Sysace_epc_data[150]
HPI interface
Sysace_epc_rd_n
Sysace_epc_wr_n
Sysace_epc_a[10]
DM1B
DP1B
DM2A
DP2A
DM1A
DP1A
External Glue Logic
In the interface diagram shown in Figure 7 the OPB EPC as well as the OPB SYSACE share the interface for data address and control lines on the board This requires external multiplex logic to be placed outside of IP cores in the FPGA The OPB EPC control signals PRH_RD_n and PRH_WR_n are muxed with the MEM_CEN and MEM_WEN signals of the OPB SYSACE When CY7C67300 USB Controller is accessed through the asynchronous mode the rising edge of sysace_epc_rd_n and sysace_epc_wr_n signals are used to control the read and the write operations respectively See the Reference Documents section for more information on OPB SYSACE
Design Constraints
Timing Constraints
Timing constraints must be placed on the system clock and the peripheral clock setting the frequency to meet the bus timing requirements An example is shown in Figure 8
Discontinued IP
ust 10 2007 wwwxilinxcom 25ecification
F
OPB External Peripheral Controller (EPC) v100a
26
Figure 8 EPC Timing Constraints
igure Top x-ref 8
Following constraint must be placed on the system clock
TIMESPEC TS_OPB_Clk = PERIOD OPB_Clk 10 ns HIGH 50
NET OPB_Clk TNM_NET = OPB_Clk
If C_PRH_CLK_SUPPORT=1 then the following constraint must be placed on the peripheral clock
TIMESPEC TS_PRH_Clk = PERIOD PRH_Clk 20 ns HIGH 50
NET PRH_Clk TNM_NET = PRH_Clk
DS325_08_071406
Design Implementation
Timing Diagrams
The timing diagrams in the figures below show various OPB transactions and the resulting access cycles on the peripheral interface Timing diagrams are not shown for all possible combinations of generics and the resulting access cycles However the timing diagrams shown are sufficient for the basic understanding of various access cycles supported by the OPB EPC
Figure 9 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 9
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
DS325_09_071206
8
4000000
004
04
Figure 10 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 10
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
04000000
20000004
8
00000000
004
04DS325_10_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 11 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 11
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000000
F
00010203
000 001 002 003
00 01 02 03DS325_11_071206
Figure 12 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 12
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
20000000
F
0000000000000000
000 001 002 003
00 01 02 03DS325_12_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 27ecification
OPB External Peripheral Controller (EPC) v100a
28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 29ecification
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
G19 C_PRHx_SYNCP14 P20 P21 P22
P23
-
If the device is configured for asynchronous mode
bull With peripheral clock support the peripheral clock input (PRH_Clk) must be driven high externally
bull PRH_RNW is driven high as PRH_Rd_n and PRH_Wr_n should be used as read and write strobe
bull With data width matching enabled the OPB EPC drives PRH_Burst to its default low
If the device is configured for synchronous mode
bull The OPB EPC drives PRH_Rd_n and PRH_Wr_n outputs to their default state of high since PRH_RNW output is used as readwrite strobe
G20C_PRHx_BUS_MULTIPLEX
P18- PRH_ADS is driven low if the device does not use
multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
IO Signals
P1 OPB_ABus - G3The OPB address bus width is determined by the C_OPB_AWIDTH parameter
P2 OPB_BE - G4The number of byte enables for the OPB data bus is determined by the C_OPB_DWIDTH parameter
P3 OPB_DBus - G4The OPB data bus width is determined by the C_OPB_DWIDTH parameter
P7 Sln_DBus-
G4The width of the OPB slave read data bus is determined by the C_OPB_DWIDTH parameter
P14 PRH_Clk-
G10 G19
PRH_Clk is selected as operating clock only if the device is configured for synchronous mode with peripheral clock support ie C_PRHx_SYNC = 1 and C_PRH_CLK_SUPPORT = 1 Asynchronous interface always operates on OPB_Clk Therefore if no device is configured for synchronous mode with peripheral clock support enabled then the input PRH_Clk must be driven high
P16 PRH_CS_n-
G6The number of chip select signals driven by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P17 PRH_Addr-
G7The width of the peripheral address bus is determined by the C_PRH_MAX_AWIDTH parameter
P18 PRH_ADS-
G20PRH_ADS is driven low if the device does not use multiplexed address and data bus ie C_PRHx_BUS_MULTIPLEX = 0
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
Discontinued IP
ust 10 2007 wwwxilinxcom 15ecification
OPB External Peripheral Controller (EPC) v100a
16
OPB EPC Design Considerations
The OPB EPC is an OPB slave only device It receives read or write instructions from the processor and generates a corresponding access cycle on the peripheral interface Examples of read and write accesses are illustrated in the Timing Diagrams section The user must take the following considerations into account while designing with the OPB EPC
Device Ready Signal
The OPB EPC readwrite access cycles are executed only when the external device assert the device ready signal (PRH_Rdy) If the external peripheral device does not have a device ready signal then the PRH_Rdy input of the OPB EPC must be tied to logic high
P19 PRH_BE - G8The number of byte enables for the peripheral data bus is determined by the C_PRH_MAX_DWIDTH parameter
P20 PHR_RNW-
G19
If the device is synchronous ie C_PRHx_SYNC = 1 then PRH_RNW should be used as the readwrite control signal For asynchronous mode of operation PRH_RNW is driven high
P21 PRH_Rd_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Rd_n should be used as the read strobe For synchronous mode of operation PRH_Rd_n is driven high
P22 PRH_Wr_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Wr_n should be used as the write strobe For synchronous mode of operation PRH_Wr_n is driven high
P23 PRH_Burst-
G18 G19
If the device is synchronous with data width matching enabled ie C_PRHx_SYNC = 1 and C_PRHx_DWIDTH_MATCH = 1 then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
P24 PRH_Rdy-
G6The number of device ready inputs decoded by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P25 PRH_Data_I-
G9The peripheral input data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P26 PRH_Data_O - G9The peripheral output data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P27 PRH_Data_T - G9
The peripheral output data bus 3-state control width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
FIFO Transactions
When C_PRHx_FIFO_ACCESS = 1 the OPB EPC supports access to FIFOrsquos within the external peripheral devices When the FIFO within the external device is accessed then the peripheral address bus (PRH_Addr) must remain constant representing the FIFO address within the address range assigned to the peripheral device When data width matching is enabled and the access corresponds to the FIFO the OPB EPC does not increment the peripheral address (PRH_Addr) bus
Abnormal Terminations
If PRH_Rdy is de-asserted for more than the maximum period as specified by C_PRHx_RDY_WIDTH then the OPB EPC terminates the current access to the external device and signals an error to the OPB master by asserting Sln_errAck on the OPB Similarly when the OPB master terminates the current access (master abort on the OPB) OPB EPC terminates the access to the external device immediately In both cases the access to the external device is terminated abnormally Therefore the external device may be in an indeterminate state and the exceptions should be handled appropriately at the system level
Interrupt Handling
If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Peripheral Data Bus Mapping
The peripheral data bus (PRH_Data) uses big endian bit labelling (ie bit-0 is Most Significant Bit (MSB) and bit-31 is Least Significant Bit (LSB) for a 32-bit bus) and is sized according to the C_PRH_MAX_ADWIDTH parameter Peripherals that have smaller widths should connect to this bus starting at bit 0 (MSB) For example if three external devices are present in the system with data bus width of 8-bit 16-bit and 32-bit the 8-bit device should connect to PRH_Data[07] the 16-bit wide peripheral should connect to PRH_Data[015] and the 32-bit peripheral should connect to PRH_Data[031]
The bit and byte labeling for the big endian data types is shown in Figure 3
Discontinued IP
ust 10 2007 wwwxilinxcom 17ecification
F
OPB External Peripheral Controller (EPC) v100a
18
Figure 3 OPB EPC Big Endian Data Type
igure Top x-ref 3
2 3
n+2 n+3
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 15
Halfword
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 31
Word
Byte
MS Byte
LS BitMS Bit
0
nByte address
Byte label
Byte significance
Bit label
Bit significance
0 7
DS325_03_071406
Unsupported Features
Many peripheral devices have the device specific inputoutput ports such as status remote reset remote wakeup interrupts etc The OPB EPC does not have any provision to support these device specific inputoutput ports Therefore if the external device has any such device specific ports then these inputoutput ports may be connected directly to system general purpose input output controller or to the system interrupt controller If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Many peripheral devices support DMA capability However currently OPB EPC is an OPB slave only device and therefore does not support DMA operations from the external peripheral devices
Current version of the OPB EPC does not support burst transactions tofrom the OPB
OPB EPC Latency
The OPB EPC latency calculations are based on the OPB clock The OPB latency is defined as the number of OPB clock cycles elapsed from the time an access is initiated to the time the access is completed (Sln_xferAck is asserted) on the OPB Table 4 shows the latency calculations for asynchronous mode and Table 5 shows the latency calculations for synchronous mode of operation
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 4 Asynchronous Mode OPB EPC Latency
Transaction Type
ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation(1)
OPB Latency
50 MHz
OPB Latency 100 MHz
ReadWrite access to asynchronous device when addressdata bus is not multiplexed
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5)
9(7) 12(7)
1FIFO
Memory
5 + N(2) (T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5))
21(7) 33(7)
ReadWrite access to asynchronous device when addressdata bus is multiplexed (Register access)
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + (T_SETUP(3) + T_ADDR_HOLD(6) + 1 + CONTROL_WIDTH(4) + T_HOLD(5))
11(7) 14(7)
1 FIFO
5 + T_SETUP(3) + T_ADDR_HOLD(6) + 1 + N(2) (CONTROL_WIDTH(4) + T_HOLD(5))
20(7) 29(7)
1 Memory
4 + N(2) (T_SETUP(3) + T_ADDR_HOLD(6) + CONTROL_WIDTH(4) + T_HOLD(5) + 2)
32(7) 44(7)
Notes 1 Latency calculations assumes the device is always ready2 If C_PRHx_DWIDTH_MATCH = 1 then N = Access size on OPB (in bytes)width of peripheral data bus (in
bytes)3 T_SETUP is the setup time requirement on various control signals in terms of number of OPB clocks and is
device specific4 CONTROL_WIDTH represents the required width for readwrite signal in terms of number of OPB clocks and
is device specific 5 T_HOLD is the hold time requirement on various control signals in terms of number of OPB clocks and is
device specific6 T_ADDR_HOLD is the required hold time on the address bus (as specified by generic C_PRHx_ADDR_TH) in
terms of number of OPB clocks and is device specific 7 Calculation are made for typical values of various timing parameters with T_SETUP = 20ns T_HOLD = 10ns
T_ADDR_HOLD = 6ns and STROBE_WIDTH = 40ns
Discontinued IP
ust 10 2007 wwwxilinxcom 19ecification
OPB External Peripheral Controller (EPC) v100a
20
Table 5 Synchronous Mode OPB EPC Latency
Transaction Type ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory 9
1FIFO
Memory 8 + N(2)
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory 11
1 FIFO 10 + N(2)
1 Memory 6 + 5N(2)
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 7 peripheral clocks
1FIFO
Memory
7 OPB clocks + (6+N(2)) peripheral clocks
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 9 peripheral clocks
1 FIFO7 OPB clocks + (8+N(2)) peripheral clocks
1 Memory7 OPB clocks + (4+5N(2)) peripheral clocks
Notes 1 Latency calculations assumes the device is always ready2 N = Access size on the OPB (in bytes)width of peripheral data bus (in bytes) where access size on OPB
equals or less than C_OPB_DWIDTH expressed in terms of bytes3 Latency calculation assumes that the requirement on address setup (C_PRHx_ADDR_TSU) address hold
(C_PRHx_ADDR_TH) and ADS pulse width (C_PRHx_ADS_WIDTH) are all less than one OPB clock
OPB EPC External Peripheral ConnectionsThe OPB EPC interface to the external device is based upon the width of the OPB data bus address and data width of the peripheral subsystem number of peripherals in the system addressdata multiplex support mode of operation (synchronous or asynchronous) and if synchronous device the operating clock for the synchronous data path
Determining Address and Data Width
The address bus width of the peripheral subsystem is the maximum width of the address bus of all peripheral devices connected to the OPB EPC If all devices employ non-multiplexed address and data bus the data bus width of the peripheral subsystem is the maximum of the data bus width of all external devices If any of the devices are configured for multiplexed address and data bus then the data bus width of the peripheral subsystem should be set as the maximum of the data bus and the address bus of the device(s) employing a multiplexed address and data bus
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Endian Considerations
The peripheral address and data bus of the OPB EPC is labeled with big endian bit labeling (D0 is the MSB and D31 is the LSB for a 32-bit bus) while most peripheral devices are either endian agnostic ie they can be connected either way or little endian (D31 is the MSB and D0 is the LSB for a 32-bit bus) Caution must be exercised with the connection to the external peripheral devices to avoid incorrect data and address connections
Clock Generation
When connecting to a synchronous external device the OPB EPC may operate either on the OPB clock (OPB_Clk) or on a peripheral clock (PRH_Clk) The operating clock for the synchronous interface is based on the generic C_PRH_CLK_SUPPORT If C_PRH_CLK_SUPPORT = 1 the peripheral clock is used else the OPB clock is used The external devices connected to the OPB EPC will determine the operating frequency of the peripheral clock The minimum of the operating frequencies of various devices connected to OPB EPC should be used as the operating frequency of the peripheral clock (PRH_Clk)
Figure 4 illustrates a block diagram for generating a device specific clock source clock source using two DCMs The DCM modules are located within the FPGA but are external to the OPB EPC An external clock source is used to generate the OPB clock (OPB_Clk) to the OPB EPC The device clock source (PRH_Clk) is also generated from the same DCM (DCM0) using the CLKFX output and must be routed on the board to be fed back to the FPGA Another DCM (DCM1) is used to synchronize the device peripheral clock to the OPB EPC PRH_Clk
Figure 4 External Peripherals clocked by FPGA output with feedback
igure Top x-ref 4
DS325_04_071406
CLKFB CLK0
CLKFXCLKIN
DCM0
PRH_Clk_FB
PRH_Clk
OPB_Clk
CLKFB CLK0
CLKIN
DCM1
PRH_Clk
OPB_Clk
OPB EPCExternalDevice
CLK
FPGA
Example Peripheral Connections
Example SMSC LAN91C111 10100 non-PCI Ethernet Single Chip MAC + PHY
An example peripheral device supported by the OPB EPC is the SMSC 10100 non-PCI Ethernet Single Chip MAC + PHY LAN91C111 The OPB EPC allows OPB masters to access the device both in synchronous and asynchronous mode The device connections for synchronous and asynchronous mode of operations are outlined in the Asynchronous Mode and Synchronous Mode sections
Discontinued IP
ust 10 2007 wwwxilinxcom 21ecification
OPB External Peripheral Controller (EPC) v100a
22
F
Asynchronous Mode
Figure 5 illustrates the SMSC LAN91C111 connections to the OPB EPC in asynchronous mode with non-multiplexed address and data buses In asynchronous mode the input clock source (PRH_Clk) to the external device must be tied to VCC When the SMSC LAN91C111 is accessed through the asynchronous mode the rising edge of PRH_Rd_n and PRH_Wr_n signals are used to control the read and the write operations respectively As the device uses Asynchronous Ready (ARDY) signal to indicate its readiness in asynchronous mode This signal is connected to the PRH_Rdy input of the OPB EPC Since the address and the data buses are not multiplexed PRH_ADS will be driven low by the OPB EPC
The following parameter settings apply for the connections shown in Figure 5
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 5 SMSC LAN91C111 Connection to OPB EPC in Asynchronous Mode
igure Top x-ref 5
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]
PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
To System Interrupt Controller
VCC
LCLKResetAENnADSA[151]
nBE[30]
ARDYnRdnWR
D[310]
INTRO
WnRnVLBUSnCYCLE
nRDYRTNnDADACS
nLDEVnSARDY
SMSC LAN91C111
ExternalGlue Logic
PPC
OP
B B
us
FPGA
DS325_05_071406
ExternalReset VCC
External Glue Logic
Special attention must be given while interfacing the OPB EPC to the SMSC LAN91C111 in asynchronous mode The OPB EPC drives the PRH_BE active high while the SMSC LAN91C111 requires the input byte enable to be active low To match this requirement external glue logic is required to invert the PRH_BE signals before they are interfaced with the byte enable signals of the SMSC LAN91C111
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Synchronous Mode
Figure 6 illustrates the SMSC LAN91C111 connection to the OPB EPC in synchronous VL Bus mode with non-multiplexed address and data buses In synchronous mode the device requires an input clock source to the LCLK pin with a maximum operating frequency of 50MHz The local clock generated by the DCM for the peripheral interface must be routed to the LCLK input of SMSC LAN91C111 and PRH_Clk of OPB EPC When the device is accessed PRH_RNW is used as the control signal to indicate a readwrite access When PRH_RNW is high it indicates a read operation and when low it indicates a write operation The SMSC LAN91C111 uses nSRDY signal to indicate the device readiness This signal is connected to PRH_Rdy input of the OPB_EPC As the address and the data bus are not multiplexed PRH_ADS will be driven low
The following parameter settings apply for the connections shown in Figure 6
bull C_PRH_CLK_SUPPORT = 1
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 1
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 6 SMSC LAN91C111 Connection to OPB EPC in Synchronous Mode
igure Top x-ref 6
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
LCLKResetAENnADSA[151]nBE[30]WnRnSRDY
D[310]
nCYCLEnRDYRTN
INTRO
nRdnWR
nDADACSnLDEVARDY
nVLBUS
SMSC LAN91C111
ExternalGlue Logic
DigitalClock
Manager
PP
C
OP
B B
us
FPGA
DS325_06_071406
External Reset
VCC
GND
To System Interrupt Controller
External Glue Logic
The SMSC LAN91C111 device requires two inputs nCYCLE and nRDYRTN to control synchronous operation The definition of these signals is outside the scope of this document and can be found in the documents listed in the Reference Documents section The nCYCLE and nRDYRTN signals are generated in external glue logic nCYCLE may be generated from PRH_CS_n and is driven low for a
Discontinued IP
ust 10 2007 wwwxilinxcom 23ecification
OPB External Peripheral Controller (EPC) v100a
24
single clock cycle on a high to low transition on PRH_CS_n nRDYRTN is simply the registered value of the nSRDY signal
Design Considerations
When the OPB EPC is interfaced to the SMSC LAN91C111 with data width match enabled (C_PRHx_DWIDTH_MATCH = 1) and the internal SRAM of the peripheral is being accessed the device has to be configured in the address auto increment mode Address auto increment mode can be configured by setting AUTO INCR bit in the Bank 2 Pointer Register of SMSC LAN91C111 More information can be obtained by referring the registers of Bank 2 in SMSC LAN91C111 data sheet See the Reference Documents section
Example Cypress Semiconductorrsquos CY7C67300 EZ-Host Programmable Embedded USB HostPeripheral Controller
The Cypress Semiconductorrsquos CY7C67300 EZ-Hosttrade Programmable Embedded USB HostPeripheral Controller is another example of a peripheral device supported by the OPB EPC Since the Cypress USB controller operates in asynchronous mode the OPB EPC must be configured to support asynchronous mode operation
Asynchronous Mode
Figure 7 illustrates the CY7C67300 USB Controller connection to the OPB EPC in asynchronous mode with non-multiplexed address and data buses
The following parameter settings apply for the connection shown in Figure 7
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 4
bull C_PRH0_DWIDTH = 16
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Configuration of CY7C67300 USB Controller
The CY7C67300 USB Controller is configured as a Host Processor Interface (HPI) The boot-up sequence code for the CY7C67300 USB Controller in this particular example is present on the external Compact Flash memory device and is accessed through the OPB SYSACE interface This code is downloaded to the CY7C67300 USB Controller through the HPI interface Once this boot-up sequence is executed by the CY7C67300 USB Controller it becomes ready to operate in normal HPI mode with the external host controller (OPB EPC)
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
F
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 7 CY7C67300 USB Controller connection to OPB EPC in asynchronous mode
igure Top x-ref 7
SysACE_mpd_I[015]SysACE_mpd_O[015]SysACE_mpd_T[015]
SysACE_mpweSysACE_mpoe
SysACE_MPA[06]
SysACE_CEN
OPB SYS ACE Cntlr[150][150][150]
[60]
PRH_RstPRH_Rdy
PRH_CS_n
PRH_Data_I[015]PRH_Data_O[015]PRH_Data_T[015]
PRH_ADSPRH_RRNW
PRH_BurstPRH_Rd_nPRH_Wr_n
PRH_Addr[01]
OPB EPC
VCC
Ext
erna
l US
B P
orts
P
ort 1
A 1
B 2
AnCS
nRD
nWR
[D15D0]
[A1A0]
INT
CompactFLASH
TQFP144 SYSTEMACE
System ACE CompactFlash Controller
Ext
erna
l Glu
e Lo
gic
OPBINTC
US
B C
Y7C
6730
0
PP
C
OP
B B
us
FPGA
DS325_07_071406
Sysace_epc_data[150]
HPI interface
Sysace_epc_rd_n
Sysace_epc_wr_n
Sysace_epc_a[10]
DM1B
DP1B
DM2A
DP2A
DM1A
DP1A
External Glue Logic
In the interface diagram shown in Figure 7 the OPB EPC as well as the OPB SYSACE share the interface for data address and control lines on the board This requires external multiplex logic to be placed outside of IP cores in the FPGA The OPB EPC control signals PRH_RD_n and PRH_WR_n are muxed with the MEM_CEN and MEM_WEN signals of the OPB SYSACE When CY7C67300 USB Controller is accessed through the asynchronous mode the rising edge of sysace_epc_rd_n and sysace_epc_wr_n signals are used to control the read and the write operations respectively See the Reference Documents section for more information on OPB SYSACE
Design Constraints
Timing Constraints
Timing constraints must be placed on the system clock and the peripheral clock setting the frequency to meet the bus timing requirements An example is shown in Figure 8
Discontinued IP
ust 10 2007 wwwxilinxcom 25ecification
F
OPB External Peripheral Controller (EPC) v100a
26
Figure 8 EPC Timing Constraints
igure Top x-ref 8
Following constraint must be placed on the system clock
TIMESPEC TS_OPB_Clk = PERIOD OPB_Clk 10 ns HIGH 50
NET OPB_Clk TNM_NET = OPB_Clk
If C_PRH_CLK_SUPPORT=1 then the following constraint must be placed on the peripheral clock
TIMESPEC TS_PRH_Clk = PERIOD PRH_Clk 20 ns HIGH 50
NET PRH_Clk TNM_NET = PRH_Clk
DS325_08_071406
Design Implementation
Timing Diagrams
The timing diagrams in the figures below show various OPB transactions and the resulting access cycles on the peripheral interface Timing diagrams are not shown for all possible combinations of generics and the resulting access cycles However the timing diagrams shown are sufficient for the basic understanding of various access cycles supported by the OPB EPC
Figure 9 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 9
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
DS325_09_071206
8
4000000
004
04
Figure 10 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 10
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
04000000
20000004
8
00000000
004
04DS325_10_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 11 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 11
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000000
F
00010203
000 001 002 003
00 01 02 03DS325_11_071206
Figure 12 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 12
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
20000000
F
0000000000000000
000 001 002 003
00 01 02 03DS325_12_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 27ecification
OPB External Peripheral Controller (EPC) v100a
28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 29ecification
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
16
OPB EPC Design Considerations
The OPB EPC is an OPB slave only device It receives read or write instructions from the processor and generates a corresponding access cycle on the peripheral interface Examples of read and write accesses are illustrated in the Timing Diagrams section The user must take the following considerations into account while designing with the OPB EPC
Device Ready Signal
The OPB EPC readwrite access cycles are executed only when the external device assert the device ready signal (PRH_Rdy) If the external peripheral device does not have a device ready signal then the PRH_Rdy input of the OPB EPC must be tied to logic high
P19 PRH_BE - G8The number of byte enables for the peripheral data bus is determined by the C_PRH_MAX_DWIDTH parameter
P20 PHR_RNW-
G19
If the device is synchronous ie C_PRHx_SYNC = 1 then PRH_RNW should be used as the readwrite control signal For asynchronous mode of operation PRH_RNW is driven high
P21 PRH_Rd_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Rd_n should be used as the read strobe For synchronous mode of operation PRH_Rd_n is driven high
P22 PRH_Wr_n-
G19
If the device is asynchronous ie C_PRHx_SYNC = 0 then PRH_Wr_n should be used as the write strobe For synchronous mode of operation PRH_Wr_n is driven high
P23 PRH_Burst-
G18 G19
If the device is synchronous with data width matching enabled ie C_PRHx_SYNC = 1 and C_PRHx_DWIDTH_MATCH = 1 then PRH_Burst will be driven high until all but the last byte of data is flushed to the device For asynchronous mode and synchronous mode with data width match disabled PRH_Burst is driven low
P24 PRH_Rdy-
G6The number of device ready inputs decoded by the OPB external peripheral controller is determined by the C_NUM_PERIPHERALS parameter
P25 PRH_Data_I-
G9The peripheral input data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P26 PRH_Data_O - G9The peripheral output data bus width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
P27 PRH_Data_T - G9
The peripheral output data bus 3-state control width of OPB external peripheral controller is determined by the C_PRH_MAX_ADWIDTH parameter
Table 3 Parameter - Port Dependencies (Contd)
Generic or Port
Name Affects Depends Description
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
FIFO Transactions
When C_PRHx_FIFO_ACCESS = 1 the OPB EPC supports access to FIFOrsquos within the external peripheral devices When the FIFO within the external device is accessed then the peripheral address bus (PRH_Addr) must remain constant representing the FIFO address within the address range assigned to the peripheral device When data width matching is enabled and the access corresponds to the FIFO the OPB EPC does not increment the peripheral address (PRH_Addr) bus
Abnormal Terminations
If PRH_Rdy is de-asserted for more than the maximum period as specified by C_PRHx_RDY_WIDTH then the OPB EPC terminates the current access to the external device and signals an error to the OPB master by asserting Sln_errAck on the OPB Similarly when the OPB master terminates the current access (master abort on the OPB) OPB EPC terminates the access to the external device immediately In both cases the access to the external device is terminated abnormally Therefore the external device may be in an indeterminate state and the exceptions should be handled appropriately at the system level
Interrupt Handling
If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Peripheral Data Bus Mapping
The peripheral data bus (PRH_Data) uses big endian bit labelling (ie bit-0 is Most Significant Bit (MSB) and bit-31 is Least Significant Bit (LSB) for a 32-bit bus) and is sized according to the C_PRH_MAX_ADWIDTH parameter Peripherals that have smaller widths should connect to this bus starting at bit 0 (MSB) For example if three external devices are present in the system with data bus width of 8-bit 16-bit and 32-bit the 8-bit device should connect to PRH_Data[07] the 16-bit wide peripheral should connect to PRH_Data[015] and the 32-bit peripheral should connect to PRH_Data[031]
The bit and byte labeling for the big endian data types is shown in Figure 3
Discontinued IP
ust 10 2007 wwwxilinxcom 17ecification
F
OPB External Peripheral Controller (EPC) v100a
18
Figure 3 OPB EPC Big Endian Data Type
igure Top x-ref 3
2 3
n+2 n+3
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 15
Halfword
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 31
Word
Byte
MS Byte
LS BitMS Bit
0
nByte address
Byte label
Byte significance
Bit label
Bit significance
0 7
DS325_03_071406
Unsupported Features
Many peripheral devices have the device specific inputoutput ports such as status remote reset remote wakeup interrupts etc The OPB EPC does not have any provision to support these device specific inputoutput ports Therefore if the external device has any such device specific ports then these inputoutput ports may be connected directly to system general purpose input output controller or to the system interrupt controller If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Many peripheral devices support DMA capability However currently OPB EPC is an OPB slave only device and therefore does not support DMA operations from the external peripheral devices
Current version of the OPB EPC does not support burst transactions tofrom the OPB
OPB EPC Latency
The OPB EPC latency calculations are based on the OPB clock The OPB latency is defined as the number of OPB clock cycles elapsed from the time an access is initiated to the time the access is completed (Sln_xferAck is asserted) on the OPB Table 4 shows the latency calculations for asynchronous mode and Table 5 shows the latency calculations for synchronous mode of operation
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 4 Asynchronous Mode OPB EPC Latency
Transaction Type
ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation(1)
OPB Latency
50 MHz
OPB Latency 100 MHz
ReadWrite access to asynchronous device when addressdata bus is not multiplexed
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5)
9(7) 12(7)
1FIFO
Memory
5 + N(2) (T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5))
21(7) 33(7)
ReadWrite access to asynchronous device when addressdata bus is multiplexed (Register access)
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + (T_SETUP(3) + T_ADDR_HOLD(6) + 1 + CONTROL_WIDTH(4) + T_HOLD(5))
11(7) 14(7)
1 FIFO
5 + T_SETUP(3) + T_ADDR_HOLD(6) + 1 + N(2) (CONTROL_WIDTH(4) + T_HOLD(5))
20(7) 29(7)
1 Memory
4 + N(2) (T_SETUP(3) + T_ADDR_HOLD(6) + CONTROL_WIDTH(4) + T_HOLD(5) + 2)
32(7) 44(7)
Notes 1 Latency calculations assumes the device is always ready2 If C_PRHx_DWIDTH_MATCH = 1 then N = Access size on OPB (in bytes)width of peripheral data bus (in
bytes)3 T_SETUP is the setup time requirement on various control signals in terms of number of OPB clocks and is
device specific4 CONTROL_WIDTH represents the required width for readwrite signal in terms of number of OPB clocks and
is device specific 5 T_HOLD is the hold time requirement on various control signals in terms of number of OPB clocks and is
device specific6 T_ADDR_HOLD is the required hold time on the address bus (as specified by generic C_PRHx_ADDR_TH) in
terms of number of OPB clocks and is device specific 7 Calculation are made for typical values of various timing parameters with T_SETUP = 20ns T_HOLD = 10ns
T_ADDR_HOLD = 6ns and STROBE_WIDTH = 40ns
Discontinued IP
ust 10 2007 wwwxilinxcom 19ecification
OPB External Peripheral Controller (EPC) v100a
20
Table 5 Synchronous Mode OPB EPC Latency
Transaction Type ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory 9
1FIFO
Memory 8 + N(2)
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory 11
1 FIFO 10 + N(2)
1 Memory 6 + 5N(2)
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 7 peripheral clocks
1FIFO
Memory
7 OPB clocks + (6+N(2)) peripheral clocks
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 9 peripheral clocks
1 FIFO7 OPB clocks + (8+N(2)) peripheral clocks
1 Memory7 OPB clocks + (4+5N(2)) peripheral clocks
Notes 1 Latency calculations assumes the device is always ready2 N = Access size on the OPB (in bytes)width of peripheral data bus (in bytes) where access size on OPB
equals or less than C_OPB_DWIDTH expressed in terms of bytes3 Latency calculation assumes that the requirement on address setup (C_PRHx_ADDR_TSU) address hold
(C_PRHx_ADDR_TH) and ADS pulse width (C_PRHx_ADS_WIDTH) are all less than one OPB clock
OPB EPC External Peripheral ConnectionsThe OPB EPC interface to the external device is based upon the width of the OPB data bus address and data width of the peripheral subsystem number of peripherals in the system addressdata multiplex support mode of operation (synchronous or asynchronous) and if synchronous device the operating clock for the synchronous data path
Determining Address and Data Width
The address bus width of the peripheral subsystem is the maximum width of the address bus of all peripheral devices connected to the OPB EPC If all devices employ non-multiplexed address and data bus the data bus width of the peripheral subsystem is the maximum of the data bus width of all external devices If any of the devices are configured for multiplexed address and data bus then the data bus width of the peripheral subsystem should be set as the maximum of the data bus and the address bus of the device(s) employing a multiplexed address and data bus
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Endian Considerations
The peripheral address and data bus of the OPB EPC is labeled with big endian bit labeling (D0 is the MSB and D31 is the LSB for a 32-bit bus) while most peripheral devices are either endian agnostic ie they can be connected either way or little endian (D31 is the MSB and D0 is the LSB for a 32-bit bus) Caution must be exercised with the connection to the external peripheral devices to avoid incorrect data and address connections
Clock Generation
When connecting to a synchronous external device the OPB EPC may operate either on the OPB clock (OPB_Clk) or on a peripheral clock (PRH_Clk) The operating clock for the synchronous interface is based on the generic C_PRH_CLK_SUPPORT If C_PRH_CLK_SUPPORT = 1 the peripheral clock is used else the OPB clock is used The external devices connected to the OPB EPC will determine the operating frequency of the peripheral clock The minimum of the operating frequencies of various devices connected to OPB EPC should be used as the operating frequency of the peripheral clock (PRH_Clk)
Figure 4 illustrates a block diagram for generating a device specific clock source clock source using two DCMs The DCM modules are located within the FPGA but are external to the OPB EPC An external clock source is used to generate the OPB clock (OPB_Clk) to the OPB EPC The device clock source (PRH_Clk) is also generated from the same DCM (DCM0) using the CLKFX output and must be routed on the board to be fed back to the FPGA Another DCM (DCM1) is used to synchronize the device peripheral clock to the OPB EPC PRH_Clk
Figure 4 External Peripherals clocked by FPGA output with feedback
igure Top x-ref 4
DS325_04_071406
CLKFB CLK0
CLKFXCLKIN
DCM0
PRH_Clk_FB
PRH_Clk
OPB_Clk
CLKFB CLK0
CLKIN
DCM1
PRH_Clk
OPB_Clk
OPB EPCExternalDevice
CLK
FPGA
Example Peripheral Connections
Example SMSC LAN91C111 10100 non-PCI Ethernet Single Chip MAC + PHY
An example peripheral device supported by the OPB EPC is the SMSC 10100 non-PCI Ethernet Single Chip MAC + PHY LAN91C111 The OPB EPC allows OPB masters to access the device both in synchronous and asynchronous mode The device connections for synchronous and asynchronous mode of operations are outlined in the Asynchronous Mode and Synchronous Mode sections
Discontinued IP
ust 10 2007 wwwxilinxcom 21ecification
OPB External Peripheral Controller (EPC) v100a
22
F
Asynchronous Mode
Figure 5 illustrates the SMSC LAN91C111 connections to the OPB EPC in asynchronous mode with non-multiplexed address and data buses In asynchronous mode the input clock source (PRH_Clk) to the external device must be tied to VCC When the SMSC LAN91C111 is accessed through the asynchronous mode the rising edge of PRH_Rd_n and PRH_Wr_n signals are used to control the read and the write operations respectively As the device uses Asynchronous Ready (ARDY) signal to indicate its readiness in asynchronous mode This signal is connected to the PRH_Rdy input of the OPB EPC Since the address and the data buses are not multiplexed PRH_ADS will be driven low by the OPB EPC
The following parameter settings apply for the connections shown in Figure 5
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 5 SMSC LAN91C111 Connection to OPB EPC in Asynchronous Mode
igure Top x-ref 5
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]
PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
To System Interrupt Controller
VCC
LCLKResetAENnADSA[151]
nBE[30]
ARDYnRdnWR
D[310]
INTRO
WnRnVLBUSnCYCLE
nRDYRTNnDADACS
nLDEVnSARDY
SMSC LAN91C111
ExternalGlue Logic
PPC
OP
B B
us
FPGA
DS325_05_071406
ExternalReset VCC
External Glue Logic
Special attention must be given while interfacing the OPB EPC to the SMSC LAN91C111 in asynchronous mode The OPB EPC drives the PRH_BE active high while the SMSC LAN91C111 requires the input byte enable to be active low To match this requirement external glue logic is required to invert the PRH_BE signals before they are interfaced with the byte enable signals of the SMSC LAN91C111
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Synchronous Mode
Figure 6 illustrates the SMSC LAN91C111 connection to the OPB EPC in synchronous VL Bus mode with non-multiplexed address and data buses In synchronous mode the device requires an input clock source to the LCLK pin with a maximum operating frequency of 50MHz The local clock generated by the DCM for the peripheral interface must be routed to the LCLK input of SMSC LAN91C111 and PRH_Clk of OPB EPC When the device is accessed PRH_RNW is used as the control signal to indicate a readwrite access When PRH_RNW is high it indicates a read operation and when low it indicates a write operation The SMSC LAN91C111 uses nSRDY signal to indicate the device readiness This signal is connected to PRH_Rdy input of the OPB_EPC As the address and the data bus are not multiplexed PRH_ADS will be driven low
The following parameter settings apply for the connections shown in Figure 6
bull C_PRH_CLK_SUPPORT = 1
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 1
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 6 SMSC LAN91C111 Connection to OPB EPC in Synchronous Mode
igure Top x-ref 6
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
LCLKResetAENnADSA[151]nBE[30]WnRnSRDY
D[310]
nCYCLEnRDYRTN
INTRO
nRdnWR
nDADACSnLDEVARDY
nVLBUS
SMSC LAN91C111
ExternalGlue Logic
DigitalClock
Manager
PP
C
OP
B B
us
FPGA
DS325_06_071406
External Reset
VCC
GND
To System Interrupt Controller
External Glue Logic
The SMSC LAN91C111 device requires two inputs nCYCLE and nRDYRTN to control synchronous operation The definition of these signals is outside the scope of this document and can be found in the documents listed in the Reference Documents section The nCYCLE and nRDYRTN signals are generated in external glue logic nCYCLE may be generated from PRH_CS_n and is driven low for a
Discontinued IP
ust 10 2007 wwwxilinxcom 23ecification
OPB External Peripheral Controller (EPC) v100a
24
single clock cycle on a high to low transition on PRH_CS_n nRDYRTN is simply the registered value of the nSRDY signal
Design Considerations
When the OPB EPC is interfaced to the SMSC LAN91C111 with data width match enabled (C_PRHx_DWIDTH_MATCH = 1) and the internal SRAM of the peripheral is being accessed the device has to be configured in the address auto increment mode Address auto increment mode can be configured by setting AUTO INCR bit in the Bank 2 Pointer Register of SMSC LAN91C111 More information can be obtained by referring the registers of Bank 2 in SMSC LAN91C111 data sheet See the Reference Documents section
Example Cypress Semiconductorrsquos CY7C67300 EZ-Host Programmable Embedded USB HostPeripheral Controller
The Cypress Semiconductorrsquos CY7C67300 EZ-Hosttrade Programmable Embedded USB HostPeripheral Controller is another example of a peripheral device supported by the OPB EPC Since the Cypress USB controller operates in asynchronous mode the OPB EPC must be configured to support asynchronous mode operation
Asynchronous Mode
Figure 7 illustrates the CY7C67300 USB Controller connection to the OPB EPC in asynchronous mode with non-multiplexed address and data buses
The following parameter settings apply for the connection shown in Figure 7
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 4
bull C_PRH0_DWIDTH = 16
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Configuration of CY7C67300 USB Controller
The CY7C67300 USB Controller is configured as a Host Processor Interface (HPI) The boot-up sequence code for the CY7C67300 USB Controller in this particular example is present on the external Compact Flash memory device and is accessed through the OPB SYSACE interface This code is downloaded to the CY7C67300 USB Controller through the HPI interface Once this boot-up sequence is executed by the CY7C67300 USB Controller it becomes ready to operate in normal HPI mode with the external host controller (OPB EPC)
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
F
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 7 CY7C67300 USB Controller connection to OPB EPC in asynchronous mode
igure Top x-ref 7
SysACE_mpd_I[015]SysACE_mpd_O[015]SysACE_mpd_T[015]
SysACE_mpweSysACE_mpoe
SysACE_MPA[06]
SysACE_CEN
OPB SYS ACE Cntlr[150][150][150]
[60]
PRH_RstPRH_Rdy
PRH_CS_n
PRH_Data_I[015]PRH_Data_O[015]PRH_Data_T[015]
PRH_ADSPRH_RRNW
PRH_BurstPRH_Rd_nPRH_Wr_n
PRH_Addr[01]
OPB EPC
VCC
Ext
erna
l US
B P
orts
P
ort 1
A 1
B 2
AnCS
nRD
nWR
[D15D0]
[A1A0]
INT
CompactFLASH
TQFP144 SYSTEMACE
System ACE CompactFlash Controller
Ext
erna
l Glu
e Lo
gic
OPBINTC
US
B C
Y7C
6730
0
PP
C
OP
B B
us
FPGA
DS325_07_071406
Sysace_epc_data[150]
HPI interface
Sysace_epc_rd_n
Sysace_epc_wr_n
Sysace_epc_a[10]
DM1B
DP1B
DM2A
DP2A
DM1A
DP1A
External Glue Logic
In the interface diagram shown in Figure 7 the OPB EPC as well as the OPB SYSACE share the interface for data address and control lines on the board This requires external multiplex logic to be placed outside of IP cores in the FPGA The OPB EPC control signals PRH_RD_n and PRH_WR_n are muxed with the MEM_CEN and MEM_WEN signals of the OPB SYSACE When CY7C67300 USB Controller is accessed through the asynchronous mode the rising edge of sysace_epc_rd_n and sysace_epc_wr_n signals are used to control the read and the write operations respectively See the Reference Documents section for more information on OPB SYSACE
Design Constraints
Timing Constraints
Timing constraints must be placed on the system clock and the peripheral clock setting the frequency to meet the bus timing requirements An example is shown in Figure 8
Discontinued IP
ust 10 2007 wwwxilinxcom 25ecification
F
OPB External Peripheral Controller (EPC) v100a
26
Figure 8 EPC Timing Constraints
igure Top x-ref 8
Following constraint must be placed on the system clock
TIMESPEC TS_OPB_Clk = PERIOD OPB_Clk 10 ns HIGH 50
NET OPB_Clk TNM_NET = OPB_Clk
If C_PRH_CLK_SUPPORT=1 then the following constraint must be placed on the peripheral clock
TIMESPEC TS_PRH_Clk = PERIOD PRH_Clk 20 ns HIGH 50
NET PRH_Clk TNM_NET = PRH_Clk
DS325_08_071406
Design Implementation
Timing Diagrams
The timing diagrams in the figures below show various OPB transactions and the resulting access cycles on the peripheral interface Timing diagrams are not shown for all possible combinations of generics and the resulting access cycles However the timing diagrams shown are sufficient for the basic understanding of various access cycles supported by the OPB EPC
Figure 9 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 9
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
DS325_09_071206
8
4000000
004
04
Figure 10 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 10
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
04000000
20000004
8
00000000
004
04DS325_10_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 11 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 11
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000000
F
00010203
000 001 002 003
00 01 02 03DS325_11_071206
Figure 12 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 12
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
20000000
F
0000000000000000
000 001 002 003
00 01 02 03DS325_12_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 27ecification
OPB External Peripheral Controller (EPC) v100a
28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 29ecification
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
FIFO Transactions
When C_PRHx_FIFO_ACCESS = 1 the OPB EPC supports access to FIFOrsquos within the external peripheral devices When the FIFO within the external device is accessed then the peripheral address bus (PRH_Addr) must remain constant representing the FIFO address within the address range assigned to the peripheral device When data width matching is enabled and the access corresponds to the FIFO the OPB EPC does not increment the peripheral address (PRH_Addr) bus
Abnormal Terminations
If PRH_Rdy is de-asserted for more than the maximum period as specified by C_PRHx_RDY_WIDTH then the OPB EPC terminates the current access to the external device and signals an error to the OPB master by asserting Sln_errAck on the OPB Similarly when the OPB master terminates the current access (master abort on the OPB) OPB EPC terminates the access to the external device immediately In both cases the access to the external device is terminated abnormally Therefore the external device may be in an indeterminate state and the exceptions should be handled appropriately at the system level
Interrupt Handling
If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Peripheral Data Bus Mapping
The peripheral data bus (PRH_Data) uses big endian bit labelling (ie bit-0 is Most Significant Bit (MSB) and bit-31 is Least Significant Bit (LSB) for a 32-bit bus) and is sized according to the C_PRH_MAX_ADWIDTH parameter Peripherals that have smaller widths should connect to this bus starting at bit 0 (MSB) For example if three external devices are present in the system with data bus width of 8-bit 16-bit and 32-bit the 8-bit device should connect to PRH_Data[07] the 16-bit wide peripheral should connect to PRH_Data[015] and the 32-bit peripheral should connect to PRH_Data[031]
The bit and byte labeling for the big endian data types is shown in Figure 3
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F
OPB External Peripheral Controller (EPC) v100a
18
Figure 3 OPB EPC Big Endian Data Type
igure Top x-ref 3
2 3
n+2 n+3
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 15
Halfword
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 31
Word
Byte
MS Byte
LS BitMS Bit
0
nByte address
Byte label
Byte significance
Bit label
Bit significance
0 7
DS325_03_071406
Unsupported Features
Many peripheral devices have the device specific inputoutput ports such as status remote reset remote wakeup interrupts etc The OPB EPC does not have any provision to support these device specific inputoutput ports Therefore if the external device has any such device specific ports then these inputoutput ports may be connected directly to system general purpose input output controller or to the system interrupt controller If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Many peripheral devices support DMA capability However currently OPB EPC is an OPB slave only device and therefore does not support DMA operations from the external peripheral devices
Current version of the OPB EPC does not support burst transactions tofrom the OPB
OPB EPC Latency
The OPB EPC latency calculations are based on the OPB clock The OPB latency is defined as the number of OPB clock cycles elapsed from the time an access is initiated to the time the access is completed (Sln_xferAck is asserted) on the OPB Table 4 shows the latency calculations for asynchronous mode and Table 5 shows the latency calculations for synchronous mode of operation
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OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 4 Asynchronous Mode OPB EPC Latency
Transaction Type
ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation(1)
OPB Latency
50 MHz
OPB Latency 100 MHz
ReadWrite access to asynchronous device when addressdata bus is not multiplexed
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5)
9(7) 12(7)
1FIFO
Memory
5 + N(2) (T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5))
21(7) 33(7)
ReadWrite access to asynchronous device when addressdata bus is multiplexed (Register access)
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + (T_SETUP(3) + T_ADDR_HOLD(6) + 1 + CONTROL_WIDTH(4) + T_HOLD(5))
11(7) 14(7)
1 FIFO
5 + T_SETUP(3) + T_ADDR_HOLD(6) + 1 + N(2) (CONTROL_WIDTH(4) + T_HOLD(5))
20(7) 29(7)
1 Memory
4 + N(2) (T_SETUP(3) + T_ADDR_HOLD(6) + CONTROL_WIDTH(4) + T_HOLD(5) + 2)
32(7) 44(7)
Notes 1 Latency calculations assumes the device is always ready2 If C_PRHx_DWIDTH_MATCH = 1 then N = Access size on OPB (in bytes)width of peripheral data bus (in
bytes)3 T_SETUP is the setup time requirement on various control signals in terms of number of OPB clocks and is
device specific4 CONTROL_WIDTH represents the required width for readwrite signal in terms of number of OPB clocks and
is device specific 5 T_HOLD is the hold time requirement on various control signals in terms of number of OPB clocks and is
device specific6 T_ADDR_HOLD is the required hold time on the address bus (as specified by generic C_PRHx_ADDR_TH) in
terms of number of OPB clocks and is device specific 7 Calculation are made for typical values of various timing parameters with T_SETUP = 20ns T_HOLD = 10ns
T_ADDR_HOLD = 6ns and STROBE_WIDTH = 40ns
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OPB External Peripheral Controller (EPC) v100a
20
Table 5 Synchronous Mode OPB EPC Latency
Transaction Type ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory 9
1FIFO
Memory 8 + N(2)
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory 11
1 FIFO 10 + N(2)
1 Memory 6 + 5N(2)
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 7 peripheral clocks
1FIFO
Memory
7 OPB clocks + (6+N(2)) peripheral clocks
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 9 peripheral clocks
1 FIFO7 OPB clocks + (8+N(2)) peripheral clocks
1 Memory7 OPB clocks + (4+5N(2)) peripheral clocks
Notes 1 Latency calculations assumes the device is always ready2 N = Access size on the OPB (in bytes)width of peripheral data bus (in bytes) where access size on OPB
equals or less than C_OPB_DWIDTH expressed in terms of bytes3 Latency calculation assumes that the requirement on address setup (C_PRHx_ADDR_TSU) address hold
(C_PRHx_ADDR_TH) and ADS pulse width (C_PRHx_ADS_WIDTH) are all less than one OPB clock
OPB EPC External Peripheral ConnectionsThe OPB EPC interface to the external device is based upon the width of the OPB data bus address and data width of the peripheral subsystem number of peripherals in the system addressdata multiplex support mode of operation (synchronous or asynchronous) and if synchronous device the operating clock for the synchronous data path
Determining Address and Data Width
The address bus width of the peripheral subsystem is the maximum width of the address bus of all peripheral devices connected to the OPB EPC If all devices employ non-multiplexed address and data bus the data bus width of the peripheral subsystem is the maximum of the data bus width of all external devices If any of the devices are configured for multiplexed address and data bus then the data bus width of the peripheral subsystem should be set as the maximum of the data bus and the address bus of the device(s) employing a multiplexed address and data bus
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DS325 AugProduct Sp
F
Endian Considerations
The peripheral address and data bus of the OPB EPC is labeled with big endian bit labeling (D0 is the MSB and D31 is the LSB for a 32-bit bus) while most peripheral devices are either endian agnostic ie they can be connected either way or little endian (D31 is the MSB and D0 is the LSB for a 32-bit bus) Caution must be exercised with the connection to the external peripheral devices to avoid incorrect data and address connections
Clock Generation
When connecting to a synchronous external device the OPB EPC may operate either on the OPB clock (OPB_Clk) or on a peripheral clock (PRH_Clk) The operating clock for the synchronous interface is based on the generic C_PRH_CLK_SUPPORT If C_PRH_CLK_SUPPORT = 1 the peripheral clock is used else the OPB clock is used The external devices connected to the OPB EPC will determine the operating frequency of the peripheral clock The minimum of the operating frequencies of various devices connected to OPB EPC should be used as the operating frequency of the peripheral clock (PRH_Clk)
Figure 4 illustrates a block diagram for generating a device specific clock source clock source using two DCMs The DCM modules are located within the FPGA but are external to the OPB EPC An external clock source is used to generate the OPB clock (OPB_Clk) to the OPB EPC The device clock source (PRH_Clk) is also generated from the same DCM (DCM0) using the CLKFX output and must be routed on the board to be fed back to the FPGA Another DCM (DCM1) is used to synchronize the device peripheral clock to the OPB EPC PRH_Clk
Figure 4 External Peripherals clocked by FPGA output with feedback
igure Top x-ref 4
DS325_04_071406
CLKFB CLK0
CLKFXCLKIN
DCM0
PRH_Clk_FB
PRH_Clk
OPB_Clk
CLKFB CLK0
CLKIN
DCM1
PRH_Clk
OPB_Clk
OPB EPCExternalDevice
CLK
FPGA
Example Peripheral Connections
Example SMSC LAN91C111 10100 non-PCI Ethernet Single Chip MAC + PHY
An example peripheral device supported by the OPB EPC is the SMSC 10100 non-PCI Ethernet Single Chip MAC + PHY LAN91C111 The OPB EPC allows OPB masters to access the device both in synchronous and asynchronous mode The device connections for synchronous and asynchronous mode of operations are outlined in the Asynchronous Mode and Synchronous Mode sections
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22
F
Asynchronous Mode
Figure 5 illustrates the SMSC LAN91C111 connections to the OPB EPC in asynchronous mode with non-multiplexed address and data buses In asynchronous mode the input clock source (PRH_Clk) to the external device must be tied to VCC When the SMSC LAN91C111 is accessed through the asynchronous mode the rising edge of PRH_Rd_n and PRH_Wr_n signals are used to control the read and the write operations respectively As the device uses Asynchronous Ready (ARDY) signal to indicate its readiness in asynchronous mode This signal is connected to the PRH_Rdy input of the OPB EPC Since the address and the data buses are not multiplexed PRH_ADS will be driven low by the OPB EPC
The following parameter settings apply for the connections shown in Figure 5
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 5 SMSC LAN91C111 Connection to OPB EPC in Asynchronous Mode
igure Top x-ref 5
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]
PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
To System Interrupt Controller
VCC
LCLKResetAENnADSA[151]
nBE[30]
ARDYnRdnWR
D[310]
INTRO
WnRnVLBUSnCYCLE
nRDYRTNnDADACS
nLDEVnSARDY
SMSC LAN91C111
ExternalGlue Logic
PPC
OP
B B
us
FPGA
DS325_05_071406
ExternalReset VCC
External Glue Logic
Special attention must be given while interfacing the OPB EPC to the SMSC LAN91C111 in asynchronous mode The OPB EPC drives the PRH_BE active high while the SMSC LAN91C111 requires the input byte enable to be active low To match this requirement external glue logic is required to invert the PRH_BE signals before they are interfaced with the byte enable signals of the SMSC LAN91C111
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Synchronous Mode
Figure 6 illustrates the SMSC LAN91C111 connection to the OPB EPC in synchronous VL Bus mode with non-multiplexed address and data buses In synchronous mode the device requires an input clock source to the LCLK pin with a maximum operating frequency of 50MHz The local clock generated by the DCM for the peripheral interface must be routed to the LCLK input of SMSC LAN91C111 and PRH_Clk of OPB EPC When the device is accessed PRH_RNW is used as the control signal to indicate a readwrite access When PRH_RNW is high it indicates a read operation and when low it indicates a write operation The SMSC LAN91C111 uses nSRDY signal to indicate the device readiness This signal is connected to PRH_Rdy input of the OPB_EPC As the address and the data bus are not multiplexed PRH_ADS will be driven low
The following parameter settings apply for the connections shown in Figure 6
bull C_PRH_CLK_SUPPORT = 1
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 1
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 6 SMSC LAN91C111 Connection to OPB EPC in Synchronous Mode
igure Top x-ref 6
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
LCLKResetAENnADSA[151]nBE[30]WnRnSRDY
D[310]
nCYCLEnRDYRTN
INTRO
nRdnWR
nDADACSnLDEVARDY
nVLBUS
SMSC LAN91C111
ExternalGlue Logic
DigitalClock
Manager
PP
C
OP
B B
us
FPGA
DS325_06_071406
External Reset
VCC
GND
To System Interrupt Controller
External Glue Logic
The SMSC LAN91C111 device requires two inputs nCYCLE and nRDYRTN to control synchronous operation The definition of these signals is outside the scope of this document and can be found in the documents listed in the Reference Documents section The nCYCLE and nRDYRTN signals are generated in external glue logic nCYCLE may be generated from PRH_CS_n and is driven low for a
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24
single clock cycle on a high to low transition on PRH_CS_n nRDYRTN is simply the registered value of the nSRDY signal
Design Considerations
When the OPB EPC is interfaced to the SMSC LAN91C111 with data width match enabled (C_PRHx_DWIDTH_MATCH = 1) and the internal SRAM of the peripheral is being accessed the device has to be configured in the address auto increment mode Address auto increment mode can be configured by setting AUTO INCR bit in the Bank 2 Pointer Register of SMSC LAN91C111 More information can be obtained by referring the registers of Bank 2 in SMSC LAN91C111 data sheet See the Reference Documents section
Example Cypress Semiconductorrsquos CY7C67300 EZ-Host Programmable Embedded USB HostPeripheral Controller
The Cypress Semiconductorrsquos CY7C67300 EZ-Hosttrade Programmable Embedded USB HostPeripheral Controller is another example of a peripheral device supported by the OPB EPC Since the Cypress USB controller operates in asynchronous mode the OPB EPC must be configured to support asynchronous mode operation
Asynchronous Mode
Figure 7 illustrates the CY7C67300 USB Controller connection to the OPB EPC in asynchronous mode with non-multiplexed address and data buses
The following parameter settings apply for the connection shown in Figure 7
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 4
bull C_PRH0_DWIDTH = 16
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Configuration of CY7C67300 USB Controller
The CY7C67300 USB Controller is configured as a Host Processor Interface (HPI) The boot-up sequence code for the CY7C67300 USB Controller in this particular example is present on the external Compact Flash memory device and is accessed through the OPB SYSACE interface This code is downloaded to the CY7C67300 USB Controller through the HPI interface Once this boot-up sequence is executed by the CY7C67300 USB Controller it becomes ready to operate in normal HPI mode with the external host controller (OPB EPC)
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F
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 7 CY7C67300 USB Controller connection to OPB EPC in asynchronous mode
igure Top x-ref 7
SysACE_mpd_I[015]SysACE_mpd_O[015]SysACE_mpd_T[015]
SysACE_mpweSysACE_mpoe
SysACE_MPA[06]
SysACE_CEN
OPB SYS ACE Cntlr[150][150][150]
[60]
PRH_RstPRH_Rdy
PRH_CS_n
PRH_Data_I[015]PRH_Data_O[015]PRH_Data_T[015]
PRH_ADSPRH_RRNW
PRH_BurstPRH_Rd_nPRH_Wr_n
PRH_Addr[01]
OPB EPC
VCC
Ext
erna
l US
B P
orts
P
ort 1
A 1
B 2
AnCS
nRD
nWR
[D15D0]
[A1A0]
INT
CompactFLASH
TQFP144 SYSTEMACE
System ACE CompactFlash Controller
Ext
erna
l Glu
e Lo
gic
OPBINTC
US
B C
Y7C
6730
0
PP
C
OP
B B
us
FPGA
DS325_07_071406
Sysace_epc_data[150]
HPI interface
Sysace_epc_rd_n
Sysace_epc_wr_n
Sysace_epc_a[10]
DM1B
DP1B
DM2A
DP2A
DM1A
DP1A
External Glue Logic
In the interface diagram shown in Figure 7 the OPB EPC as well as the OPB SYSACE share the interface for data address and control lines on the board This requires external multiplex logic to be placed outside of IP cores in the FPGA The OPB EPC control signals PRH_RD_n and PRH_WR_n are muxed with the MEM_CEN and MEM_WEN signals of the OPB SYSACE When CY7C67300 USB Controller is accessed through the asynchronous mode the rising edge of sysace_epc_rd_n and sysace_epc_wr_n signals are used to control the read and the write operations respectively See the Reference Documents section for more information on OPB SYSACE
Design Constraints
Timing Constraints
Timing constraints must be placed on the system clock and the peripheral clock setting the frequency to meet the bus timing requirements An example is shown in Figure 8
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ust 10 2007 wwwxilinxcom 25ecification
F
OPB External Peripheral Controller (EPC) v100a
26
Figure 8 EPC Timing Constraints
igure Top x-ref 8
Following constraint must be placed on the system clock
TIMESPEC TS_OPB_Clk = PERIOD OPB_Clk 10 ns HIGH 50
NET OPB_Clk TNM_NET = OPB_Clk
If C_PRH_CLK_SUPPORT=1 then the following constraint must be placed on the peripheral clock
TIMESPEC TS_PRH_Clk = PERIOD PRH_Clk 20 ns HIGH 50
NET PRH_Clk TNM_NET = PRH_Clk
DS325_08_071406
Design Implementation
Timing Diagrams
The timing diagrams in the figures below show various OPB transactions and the resulting access cycles on the peripheral interface Timing diagrams are not shown for all possible combinations of generics and the resulting access cycles However the timing diagrams shown are sufficient for the basic understanding of various access cycles supported by the OPB EPC
Figure 9 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 9
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
DS325_09_071206
8
4000000
004
04
Figure 10 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 10
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
04000000
20000004
8
00000000
004
04DS325_10_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 11 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 11
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000000
F
00010203
000 001 002 003
00 01 02 03DS325_11_071206
Figure 12 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 12
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
20000000
F
0000000000000000
000 001 002 003
00 01 02 03DS325_12_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 27ecification
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28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
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ust 10 2007 wwwxilinxcom 29ecification
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
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wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false 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DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT 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ESP 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FRA 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ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR 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ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB 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ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
F
OPB External Peripheral Controller (EPC) v100a
18
Figure 3 OPB EPC Big Endian Data Type
igure Top x-ref 3
2 3
n+2 n+3
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 15
Halfword
MS Byte
LS Bit
LS Byte
MS Bit
0 1
n n+1Byte address
Byte label
Byte significance
Bit label
Bit significance
0 31
Word
Byte
MS Byte
LS BitMS Bit
0
nByte address
Byte label
Byte significance
Bit label
Bit significance
0 7
DS325_03_071406
Unsupported Features
Many peripheral devices have the device specific inputoutput ports such as status remote reset remote wakeup interrupts etc The OPB EPC does not have any provision to support these device specific inputoutput ports Therefore if the external device has any such device specific ports then these inputoutput ports may be connected directly to system general purpose input output controller or to the system interrupt controller If the external device has interrupt capability then the interrupt outputs of the external device should be connected directly to the system interrupt controller
Many peripheral devices support DMA capability However currently OPB EPC is an OPB slave only device and therefore does not support DMA operations from the external peripheral devices
Current version of the OPB EPC does not support burst transactions tofrom the OPB
OPB EPC Latency
The OPB EPC latency calculations are based on the OPB clock The OPB latency is defined as the number of OPB clock cycles elapsed from the time an access is initiated to the time the access is completed (Sln_xferAck is asserted) on the OPB Table 4 shows the latency calculations for asynchronous mode and Table 5 shows the latency calculations for synchronous mode of operation
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 4 Asynchronous Mode OPB EPC Latency
Transaction Type
ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation(1)
OPB Latency
50 MHz
OPB Latency 100 MHz
ReadWrite access to asynchronous device when addressdata bus is not multiplexed
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5)
9(7) 12(7)
1FIFO
Memory
5 + N(2) (T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5))
21(7) 33(7)
ReadWrite access to asynchronous device when addressdata bus is multiplexed (Register access)
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + (T_SETUP(3) + T_ADDR_HOLD(6) + 1 + CONTROL_WIDTH(4) + T_HOLD(5))
11(7) 14(7)
1 FIFO
5 + T_SETUP(3) + T_ADDR_HOLD(6) + 1 + N(2) (CONTROL_WIDTH(4) + T_HOLD(5))
20(7) 29(7)
1 Memory
4 + N(2) (T_SETUP(3) + T_ADDR_HOLD(6) + CONTROL_WIDTH(4) + T_HOLD(5) + 2)
32(7) 44(7)
Notes 1 Latency calculations assumes the device is always ready2 If C_PRHx_DWIDTH_MATCH = 1 then N = Access size on OPB (in bytes)width of peripheral data bus (in
bytes)3 T_SETUP is the setup time requirement on various control signals in terms of number of OPB clocks and is
device specific4 CONTROL_WIDTH represents the required width for readwrite signal in terms of number of OPB clocks and
is device specific 5 T_HOLD is the hold time requirement on various control signals in terms of number of OPB clocks and is
device specific6 T_ADDR_HOLD is the required hold time on the address bus (as specified by generic C_PRHx_ADDR_TH) in
terms of number of OPB clocks and is device specific 7 Calculation are made for typical values of various timing parameters with T_SETUP = 20ns T_HOLD = 10ns
T_ADDR_HOLD = 6ns and STROBE_WIDTH = 40ns
Discontinued IP
ust 10 2007 wwwxilinxcom 19ecification
OPB External Peripheral Controller (EPC) v100a
20
Table 5 Synchronous Mode OPB EPC Latency
Transaction Type ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory 9
1FIFO
Memory 8 + N(2)
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory 11
1 FIFO 10 + N(2)
1 Memory 6 + 5N(2)
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 7 peripheral clocks
1FIFO
Memory
7 OPB clocks + (6+N(2)) peripheral clocks
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 9 peripheral clocks
1 FIFO7 OPB clocks + (8+N(2)) peripheral clocks
1 Memory7 OPB clocks + (4+5N(2)) peripheral clocks
Notes 1 Latency calculations assumes the device is always ready2 N = Access size on the OPB (in bytes)width of peripheral data bus (in bytes) where access size on OPB
equals or less than C_OPB_DWIDTH expressed in terms of bytes3 Latency calculation assumes that the requirement on address setup (C_PRHx_ADDR_TSU) address hold
(C_PRHx_ADDR_TH) and ADS pulse width (C_PRHx_ADS_WIDTH) are all less than one OPB clock
OPB EPC External Peripheral ConnectionsThe OPB EPC interface to the external device is based upon the width of the OPB data bus address and data width of the peripheral subsystem number of peripherals in the system addressdata multiplex support mode of operation (synchronous or asynchronous) and if synchronous device the operating clock for the synchronous data path
Determining Address and Data Width
The address bus width of the peripheral subsystem is the maximum width of the address bus of all peripheral devices connected to the OPB EPC If all devices employ non-multiplexed address and data bus the data bus width of the peripheral subsystem is the maximum of the data bus width of all external devices If any of the devices are configured for multiplexed address and data bus then the data bus width of the peripheral subsystem should be set as the maximum of the data bus and the address bus of the device(s) employing a multiplexed address and data bus
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Endian Considerations
The peripheral address and data bus of the OPB EPC is labeled with big endian bit labeling (D0 is the MSB and D31 is the LSB for a 32-bit bus) while most peripheral devices are either endian agnostic ie they can be connected either way or little endian (D31 is the MSB and D0 is the LSB for a 32-bit bus) Caution must be exercised with the connection to the external peripheral devices to avoid incorrect data and address connections
Clock Generation
When connecting to a synchronous external device the OPB EPC may operate either on the OPB clock (OPB_Clk) or on a peripheral clock (PRH_Clk) The operating clock for the synchronous interface is based on the generic C_PRH_CLK_SUPPORT If C_PRH_CLK_SUPPORT = 1 the peripheral clock is used else the OPB clock is used The external devices connected to the OPB EPC will determine the operating frequency of the peripheral clock The minimum of the operating frequencies of various devices connected to OPB EPC should be used as the operating frequency of the peripheral clock (PRH_Clk)
Figure 4 illustrates a block diagram for generating a device specific clock source clock source using two DCMs The DCM modules are located within the FPGA but are external to the OPB EPC An external clock source is used to generate the OPB clock (OPB_Clk) to the OPB EPC The device clock source (PRH_Clk) is also generated from the same DCM (DCM0) using the CLKFX output and must be routed on the board to be fed back to the FPGA Another DCM (DCM1) is used to synchronize the device peripheral clock to the OPB EPC PRH_Clk
Figure 4 External Peripherals clocked by FPGA output with feedback
igure Top x-ref 4
DS325_04_071406
CLKFB CLK0
CLKFXCLKIN
DCM0
PRH_Clk_FB
PRH_Clk
OPB_Clk
CLKFB CLK0
CLKIN
DCM1
PRH_Clk
OPB_Clk
OPB EPCExternalDevice
CLK
FPGA
Example Peripheral Connections
Example SMSC LAN91C111 10100 non-PCI Ethernet Single Chip MAC + PHY
An example peripheral device supported by the OPB EPC is the SMSC 10100 non-PCI Ethernet Single Chip MAC + PHY LAN91C111 The OPB EPC allows OPB masters to access the device both in synchronous and asynchronous mode The device connections for synchronous and asynchronous mode of operations are outlined in the Asynchronous Mode and Synchronous Mode sections
Discontinued IP
ust 10 2007 wwwxilinxcom 21ecification
OPB External Peripheral Controller (EPC) v100a
22
F
Asynchronous Mode
Figure 5 illustrates the SMSC LAN91C111 connections to the OPB EPC in asynchronous mode with non-multiplexed address and data buses In asynchronous mode the input clock source (PRH_Clk) to the external device must be tied to VCC When the SMSC LAN91C111 is accessed through the asynchronous mode the rising edge of PRH_Rd_n and PRH_Wr_n signals are used to control the read and the write operations respectively As the device uses Asynchronous Ready (ARDY) signal to indicate its readiness in asynchronous mode This signal is connected to the PRH_Rdy input of the OPB EPC Since the address and the data buses are not multiplexed PRH_ADS will be driven low by the OPB EPC
The following parameter settings apply for the connections shown in Figure 5
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 5 SMSC LAN91C111 Connection to OPB EPC in Asynchronous Mode
igure Top x-ref 5
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]
PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
To System Interrupt Controller
VCC
LCLKResetAENnADSA[151]
nBE[30]
ARDYnRdnWR
D[310]
INTRO
WnRnVLBUSnCYCLE
nRDYRTNnDADACS
nLDEVnSARDY
SMSC LAN91C111
ExternalGlue Logic
PPC
OP
B B
us
FPGA
DS325_05_071406
ExternalReset VCC
External Glue Logic
Special attention must be given while interfacing the OPB EPC to the SMSC LAN91C111 in asynchronous mode The OPB EPC drives the PRH_BE active high while the SMSC LAN91C111 requires the input byte enable to be active low To match this requirement external glue logic is required to invert the PRH_BE signals before they are interfaced with the byte enable signals of the SMSC LAN91C111
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Synchronous Mode
Figure 6 illustrates the SMSC LAN91C111 connection to the OPB EPC in synchronous VL Bus mode with non-multiplexed address and data buses In synchronous mode the device requires an input clock source to the LCLK pin with a maximum operating frequency of 50MHz The local clock generated by the DCM for the peripheral interface must be routed to the LCLK input of SMSC LAN91C111 and PRH_Clk of OPB EPC When the device is accessed PRH_RNW is used as the control signal to indicate a readwrite access When PRH_RNW is high it indicates a read operation and when low it indicates a write operation The SMSC LAN91C111 uses nSRDY signal to indicate the device readiness This signal is connected to PRH_Rdy input of the OPB_EPC As the address and the data bus are not multiplexed PRH_ADS will be driven low
The following parameter settings apply for the connections shown in Figure 6
bull C_PRH_CLK_SUPPORT = 1
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 1
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 6 SMSC LAN91C111 Connection to OPB EPC in Synchronous Mode
igure Top x-ref 6
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
LCLKResetAENnADSA[151]nBE[30]WnRnSRDY
D[310]
nCYCLEnRDYRTN
INTRO
nRdnWR
nDADACSnLDEVARDY
nVLBUS
SMSC LAN91C111
ExternalGlue Logic
DigitalClock
Manager
PP
C
OP
B B
us
FPGA
DS325_06_071406
External Reset
VCC
GND
To System Interrupt Controller
External Glue Logic
The SMSC LAN91C111 device requires two inputs nCYCLE and nRDYRTN to control synchronous operation The definition of these signals is outside the scope of this document and can be found in the documents listed in the Reference Documents section The nCYCLE and nRDYRTN signals are generated in external glue logic nCYCLE may be generated from PRH_CS_n and is driven low for a
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OPB External Peripheral Controller (EPC) v100a
24
single clock cycle on a high to low transition on PRH_CS_n nRDYRTN is simply the registered value of the nSRDY signal
Design Considerations
When the OPB EPC is interfaced to the SMSC LAN91C111 with data width match enabled (C_PRHx_DWIDTH_MATCH = 1) and the internal SRAM of the peripheral is being accessed the device has to be configured in the address auto increment mode Address auto increment mode can be configured by setting AUTO INCR bit in the Bank 2 Pointer Register of SMSC LAN91C111 More information can be obtained by referring the registers of Bank 2 in SMSC LAN91C111 data sheet See the Reference Documents section
Example Cypress Semiconductorrsquos CY7C67300 EZ-Host Programmable Embedded USB HostPeripheral Controller
The Cypress Semiconductorrsquos CY7C67300 EZ-Hosttrade Programmable Embedded USB HostPeripheral Controller is another example of a peripheral device supported by the OPB EPC Since the Cypress USB controller operates in asynchronous mode the OPB EPC must be configured to support asynchronous mode operation
Asynchronous Mode
Figure 7 illustrates the CY7C67300 USB Controller connection to the OPB EPC in asynchronous mode with non-multiplexed address and data buses
The following parameter settings apply for the connection shown in Figure 7
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 4
bull C_PRH0_DWIDTH = 16
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Configuration of CY7C67300 USB Controller
The CY7C67300 USB Controller is configured as a Host Processor Interface (HPI) The boot-up sequence code for the CY7C67300 USB Controller in this particular example is present on the external Compact Flash memory device and is accessed through the OPB SYSACE interface This code is downloaded to the CY7C67300 USB Controller through the HPI interface Once this boot-up sequence is executed by the CY7C67300 USB Controller it becomes ready to operate in normal HPI mode with the external host controller (OPB EPC)
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
F
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 7 CY7C67300 USB Controller connection to OPB EPC in asynchronous mode
igure Top x-ref 7
SysACE_mpd_I[015]SysACE_mpd_O[015]SysACE_mpd_T[015]
SysACE_mpweSysACE_mpoe
SysACE_MPA[06]
SysACE_CEN
OPB SYS ACE Cntlr[150][150][150]
[60]
PRH_RstPRH_Rdy
PRH_CS_n
PRH_Data_I[015]PRH_Data_O[015]PRH_Data_T[015]
PRH_ADSPRH_RRNW
PRH_BurstPRH_Rd_nPRH_Wr_n
PRH_Addr[01]
OPB EPC
VCC
Ext
erna
l US
B P
orts
P
ort 1
A 1
B 2
AnCS
nRD
nWR
[D15D0]
[A1A0]
INT
CompactFLASH
TQFP144 SYSTEMACE
System ACE CompactFlash Controller
Ext
erna
l Glu
e Lo
gic
OPBINTC
US
B C
Y7C
6730
0
PP
C
OP
B B
us
FPGA
DS325_07_071406
Sysace_epc_data[150]
HPI interface
Sysace_epc_rd_n
Sysace_epc_wr_n
Sysace_epc_a[10]
DM1B
DP1B
DM2A
DP2A
DM1A
DP1A
External Glue Logic
In the interface diagram shown in Figure 7 the OPB EPC as well as the OPB SYSACE share the interface for data address and control lines on the board This requires external multiplex logic to be placed outside of IP cores in the FPGA The OPB EPC control signals PRH_RD_n and PRH_WR_n are muxed with the MEM_CEN and MEM_WEN signals of the OPB SYSACE When CY7C67300 USB Controller is accessed through the asynchronous mode the rising edge of sysace_epc_rd_n and sysace_epc_wr_n signals are used to control the read and the write operations respectively See the Reference Documents section for more information on OPB SYSACE
Design Constraints
Timing Constraints
Timing constraints must be placed on the system clock and the peripheral clock setting the frequency to meet the bus timing requirements An example is shown in Figure 8
Discontinued IP
ust 10 2007 wwwxilinxcom 25ecification
F
OPB External Peripheral Controller (EPC) v100a
26
Figure 8 EPC Timing Constraints
igure Top x-ref 8
Following constraint must be placed on the system clock
TIMESPEC TS_OPB_Clk = PERIOD OPB_Clk 10 ns HIGH 50
NET OPB_Clk TNM_NET = OPB_Clk
If C_PRH_CLK_SUPPORT=1 then the following constraint must be placed on the peripheral clock
TIMESPEC TS_PRH_Clk = PERIOD PRH_Clk 20 ns HIGH 50
NET PRH_Clk TNM_NET = PRH_Clk
DS325_08_071406
Design Implementation
Timing Diagrams
The timing diagrams in the figures below show various OPB transactions and the resulting access cycles on the peripheral interface Timing diagrams are not shown for all possible combinations of generics and the resulting access cycles However the timing diagrams shown are sufficient for the basic understanding of various access cycles supported by the OPB EPC
Figure 9 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 9
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
DS325_09_071206
8
4000000
004
04
Figure 10 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 10
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
04000000
20000004
8
00000000
004
04DS325_10_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 11 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 11
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000000
F
00010203
000 001 002 003
00 01 02 03DS325_11_071206
Figure 12 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 12
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
20000000
F
0000000000000000
000 001 002 003
00 01 02 03DS325_12_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 27ecification
OPB External Peripheral Controller (EPC) v100a
28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
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ust 10 2007 wwwxilinxcom 29ecification
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 4 Asynchronous Mode OPB EPC Latency
Transaction Type
ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation(1)
OPB Latency
50 MHz
OPB Latency 100 MHz
ReadWrite access to asynchronous device when addressdata bus is not multiplexed
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5)
9(7) 12(7)
1FIFO
Memory
5 + N(2) (T_SETUP(3) + CONTROL_WIDTH(4) + T_HOLD(5))
21(7) 33(7)
ReadWrite access to asynchronous device when addressdata bus is multiplexed (Register access)
OPB_Select to Sln_xferAck
0FIFO
Memory
5 + (T_SETUP(3) + T_ADDR_HOLD(6) + 1 + CONTROL_WIDTH(4) + T_HOLD(5))
11(7) 14(7)
1 FIFO
5 + T_SETUP(3) + T_ADDR_HOLD(6) + 1 + N(2) (CONTROL_WIDTH(4) + T_HOLD(5))
20(7) 29(7)
1 Memory
4 + N(2) (T_SETUP(3) + T_ADDR_HOLD(6) + CONTROL_WIDTH(4) + T_HOLD(5) + 2)
32(7) 44(7)
Notes 1 Latency calculations assumes the device is always ready2 If C_PRHx_DWIDTH_MATCH = 1 then N = Access size on OPB (in bytes)width of peripheral data bus (in
bytes)3 T_SETUP is the setup time requirement on various control signals in terms of number of OPB clocks and is
device specific4 CONTROL_WIDTH represents the required width for readwrite signal in terms of number of OPB clocks and
is device specific 5 T_HOLD is the hold time requirement on various control signals in terms of number of OPB clocks and is
device specific6 T_ADDR_HOLD is the required hold time on the address bus (as specified by generic C_PRHx_ADDR_TH) in
terms of number of OPB clocks and is device specific 7 Calculation are made for typical values of various timing parameters with T_SETUP = 20ns T_HOLD = 10ns
T_ADDR_HOLD = 6ns and STROBE_WIDTH = 40ns
Discontinued IP
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OPB External Peripheral Controller (EPC) v100a
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Table 5 Synchronous Mode OPB EPC Latency
Transaction Type ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory 9
1FIFO
Memory 8 + N(2)
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory 11
1 FIFO 10 + N(2)
1 Memory 6 + 5N(2)
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 7 peripheral clocks
1FIFO
Memory
7 OPB clocks + (6+N(2)) peripheral clocks
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 9 peripheral clocks
1 FIFO7 OPB clocks + (8+N(2)) peripheral clocks
1 Memory7 OPB clocks + (4+5N(2)) peripheral clocks
Notes 1 Latency calculations assumes the device is always ready2 N = Access size on the OPB (in bytes)width of peripheral data bus (in bytes) where access size on OPB
equals or less than C_OPB_DWIDTH expressed in terms of bytes3 Latency calculation assumes that the requirement on address setup (C_PRHx_ADDR_TSU) address hold
(C_PRHx_ADDR_TH) and ADS pulse width (C_PRHx_ADS_WIDTH) are all less than one OPB clock
OPB EPC External Peripheral ConnectionsThe OPB EPC interface to the external device is based upon the width of the OPB data bus address and data width of the peripheral subsystem number of peripherals in the system addressdata multiplex support mode of operation (synchronous or asynchronous) and if synchronous device the operating clock for the synchronous data path
Determining Address and Data Width
The address bus width of the peripheral subsystem is the maximum width of the address bus of all peripheral devices connected to the OPB EPC If all devices employ non-multiplexed address and data bus the data bus width of the peripheral subsystem is the maximum of the data bus width of all external devices If any of the devices are configured for multiplexed address and data bus then the data bus width of the peripheral subsystem should be set as the maximum of the data bus and the address bus of the device(s) employing a multiplexed address and data bus
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Endian Considerations
The peripheral address and data bus of the OPB EPC is labeled with big endian bit labeling (D0 is the MSB and D31 is the LSB for a 32-bit bus) while most peripheral devices are either endian agnostic ie they can be connected either way or little endian (D31 is the MSB and D0 is the LSB for a 32-bit bus) Caution must be exercised with the connection to the external peripheral devices to avoid incorrect data and address connections
Clock Generation
When connecting to a synchronous external device the OPB EPC may operate either on the OPB clock (OPB_Clk) or on a peripheral clock (PRH_Clk) The operating clock for the synchronous interface is based on the generic C_PRH_CLK_SUPPORT If C_PRH_CLK_SUPPORT = 1 the peripheral clock is used else the OPB clock is used The external devices connected to the OPB EPC will determine the operating frequency of the peripheral clock The minimum of the operating frequencies of various devices connected to OPB EPC should be used as the operating frequency of the peripheral clock (PRH_Clk)
Figure 4 illustrates a block diagram for generating a device specific clock source clock source using two DCMs The DCM modules are located within the FPGA but are external to the OPB EPC An external clock source is used to generate the OPB clock (OPB_Clk) to the OPB EPC The device clock source (PRH_Clk) is also generated from the same DCM (DCM0) using the CLKFX output and must be routed on the board to be fed back to the FPGA Another DCM (DCM1) is used to synchronize the device peripheral clock to the OPB EPC PRH_Clk
Figure 4 External Peripherals clocked by FPGA output with feedback
igure Top x-ref 4
DS325_04_071406
CLKFB CLK0
CLKFXCLKIN
DCM0
PRH_Clk_FB
PRH_Clk
OPB_Clk
CLKFB CLK0
CLKIN
DCM1
PRH_Clk
OPB_Clk
OPB EPCExternalDevice
CLK
FPGA
Example Peripheral Connections
Example SMSC LAN91C111 10100 non-PCI Ethernet Single Chip MAC + PHY
An example peripheral device supported by the OPB EPC is the SMSC 10100 non-PCI Ethernet Single Chip MAC + PHY LAN91C111 The OPB EPC allows OPB masters to access the device both in synchronous and asynchronous mode The device connections for synchronous and asynchronous mode of operations are outlined in the Asynchronous Mode and Synchronous Mode sections
Discontinued IP
ust 10 2007 wwwxilinxcom 21ecification
OPB External Peripheral Controller (EPC) v100a
22
F
Asynchronous Mode
Figure 5 illustrates the SMSC LAN91C111 connections to the OPB EPC in asynchronous mode with non-multiplexed address and data buses In asynchronous mode the input clock source (PRH_Clk) to the external device must be tied to VCC When the SMSC LAN91C111 is accessed through the asynchronous mode the rising edge of PRH_Rd_n and PRH_Wr_n signals are used to control the read and the write operations respectively As the device uses Asynchronous Ready (ARDY) signal to indicate its readiness in asynchronous mode This signal is connected to the PRH_Rdy input of the OPB EPC Since the address and the data buses are not multiplexed PRH_ADS will be driven low by the OPB EPC
The following parameter settings apply for the connections shown in Figure 5
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 5 SMSC LAN91C111 Connection to OPB EPC in Asynchronous Mode
igure Top x-ref 5
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]
PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
To System Interrupt Controller
VCC
LCLKResetAENnADSA[151]
nBE[30]
ARDYnRdnWR
D[310]
INTRO
WnRnVLBUSnCYCLE
nRDYRTNnDADACS
nLDEVnSARDY
SMSC LAN91C111
ExternalGlue Logic
PPC
OP
B B
us
FPGA
DS325_05_071406
ExternalReset VCC
External Glue Logic
Special attention must be given while interfacing the OPB EPC to the SMSC LAN91C111 in asynchronous mode The OPB EPC drives the PRH_BE active high while the SMSC LAN91C111 requires the input byte enable to be active low To match this requirement external glue logic is required to invert the PRH_BE signals before they are interfaced with the byte enable signals of the SMSC LAN91C111
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Synchronous Mode
Figure 6 illustrates the SMSC LAN91C111 connection to the OPB EPC in synchronous VL Bus mode with non-multiplexed address and data buses In synchronous mode the device requires an input clock source to the LCLK pin with a maximum operating frequency of 50MHz The local clock generated by the DCM for the peripheral interface must be routed to the LCLK input of SMSC LAN91C111 and PRH_Clk of OPB EPC When the device is accessed PRH_RNW is used as the control signal to indicate a readwrite access When PRH_RNW is high it indicates a read operation and when low it indicates a write operation The SMSC LAN91C111 uses nSRDY signal to indicate the device readiness This signal is connected to PRH_Rdy input of the OPB_EPC As the address and the data bus are not multiplexed PRH_ADS will be driven low
The following parameter settings apply for the connections shown in Figure 6
bull C_PRH_CLK_SUPPORT = 1
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 1
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 6 SMSC LAN91C111 Connection to OPB EPC in Synchronous Mode
igure Top x-ref 6
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
LCLKResetAENnADSA[151]nBE[30]WnRnSRDY
D[310]
nCYCLEnRDYRTN
INTRO
nRdnWR
nDADACSnLDEVARDY
nVLBUS
SMSC LAN91C111
ExternalGlue Logic
DigitalClock
Manager
PP
C
OP
B B
us
FPGA
DS325_06_071406
External Reset
VCC
GND
To System Interrupt Controller
External Glue Logic
The SMSC LAN91C111 device requires two inputs nCYCLE and nRDYRTN to control synchronous operation The definition of these signals is outside the scope of this document and can be found in the documents listed in the Reference Documents section The nCYCLE and nRDYRTN signals are generated in external glue logic nCYCLE may be generated from PRH_CS_n and is driven low for a
Discontinued IP
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OPB External Peripheral Controller (EPC) v100a
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single clock cycle on a high to low transition on PRH_CS_n nRDYRTN is simply the registered value of the nSRDY signal
Design Considerations
When the OPB EPC is interfaced to the SMSC LAN91C111 with data width match enabled (C_PRHx_DWIDTH_MATCH = 1) and the internal SRAM of the peripheral is being accessed the device has to be configured in the address auto increment mode Address auto increment mode can be configured by setting AUTO INCR bit in the Bank 2 Pointer Register of SMSC LAN91C111 More information can be obtained by referring the registers of Bank 2 in SMSC LAN91C111 data sheet See the Reference Documents section
Example Cypress Semiconductorrsquos CY7C67300 EZ-Host Programmable Embedded USB HostPeripheral Controller
The Cypress Semiconductorrsquos CY7C67300 EZ-Hosttrade Programmable Embedded USB HostPeripheral Controller is another example of a peripheral device supported by the OPB EPC Since the Cypress USB controller operates in asynchronous mode the OPB EPC must be configured to support asynchronous mode operation
Asynchronous Mode
Figure 7 illustrates the CY7C67300 USB Controller connection to the OPB EPC in asynchronous mode with non-multiplexed address and data buses
The following parameter settings apply for the connection shown in Figure 7
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 4
bull C_PRH0_DWIDTH = 16
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Configuration of CY7C67300 USB Controller
The CY7C67300 USB Controller is configured as a Host Processor Interface (HPI) The boot-up sequence code for the CY7C67300 USB Controller in this particular example is present on the external Compact Flash memory device and is accessed through the OPB SYSACE interface This code is downloaded to the CY7C67300 USB Controller through the HPI interface Once this boot-up sequence is executed by the CY7C67300 USB Controller it becomes ready to operate in normal HPI mode with the external host controller (OPB EPC)
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
F
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 7 CY7C67300 USB Controller connection to OPB EPC in asynchronous mode
igure Top x-ref 7
SysACE_mpd_I[015]SysACE_mpd_O[015]SysACE_mpd_T[015]
SysACE_mpweSysACE_mpoe
SysACE_MPA[06]
SysACE_CEN
OPB SYS ACE Cntlr[150][150][150]
[60]
PRH_RstPRH_Rdy
PRH_CS_n
PRH_Data_I[015]PRH_Data_O[015]PRH_Data_T[015]
PRH_ADSPRH_RRNW
PRH_BurstPRH_Rd_nPRH_Wr_n
PRH_Addr[01]
OPB EPC
VCC
Ext
erna
l US
B P
orts
P
ort 1
A 1
B 2
AnCS
nRD
nWR
[D15D0]
[A1A0]
INT
CompactFLASH
TQFP144 SYSTEMACE
System ACE CompactFlash Controller
Ext
erna
l Glu
e Lo
gic
OPBINTC
US
B C
Y7C
6730
0
PP
C
OP
B B
us
FPGA
DS325_07_071406
Sysace_epc_data[150]
HPI interface
Sysace_epc_rd_n
Sysace_epc_wr_n
Sysace_epc_a[10]
DM1B
DP1B
DM2A
DP2A
DM1A
DP1A
External Glue Logic
In the interface diagram shown in Figure 7 the OPB EPC as well as the OPB SYSACE share the interface for data address and control lines on the board This requires external multiplex logic to be placed outside of IP cores in the FPGA The OPB EPC control signals PRH_RD_n and PRH_WR_n are muxed with the MEM_CEN and MEM_WEN signals of the OPB SYSACE When CY7C67300 USB Controller is accessed through the asynchronous mode the rising edge of sysace_epc_rd_n and sysace_epc_wr_n signals are used to control the read and the write operations respectively See the Reference Documents section for more information on OPB SYSACE
Design Constraints
Timing Constraints
Timing constraints must be placed on the system clock and the peripheral clock setting the frequency to meet the bus timing requirements An example is shown in Figure 8
Discontinued IP
ust 10 2007 wwwxilinxcom 25ecification
F
OPB External Peripheral Controller (EPC) v100a
26
Figure 8 EPC Timing Constraints
igure Top x-ref 8
Following constraint must be placed on the system clock
TIMESPEC TS_OPB_Clk = PERIOD OPB_Clk 10 ns HIGH 50
NET OPB_Clk TNM_NET = OPB_Clk
If C_PRH_CLK_SUPPORT=1 then the following constraint must be placed on the peripheral clock
TIMESPEC TS_PRH_Clk = PERIOD PRH_Clk 20 ns HIGH 50
NET PRH_Clk TNM_NET = PRH_Clk
DS325_08_071406
Design Implementation
Timing Diagrams
The timing diagrams in the figures below show various OPB transactions and the resulting access cycles on the peripheral interface Timing diagrams are not shown for all possible combinations of generics and the resulting access cycles However the timing diagrams shown are sufficient for the basic understanding of various access cycles supported by the OPB EPC
Figure 9 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 9
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
DS325_09_071206
8
4000000
004
04
Figure 10 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 10
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
04000000
20000004
8
00000000
004
04DS325_10_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 11 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 11
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000000
F
00010203
000 001 002 003
00 01 02 03DS325_11_071206
Figure 12 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 12
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
20000000
F
0000000000000000
000 001 002 003
00 01 02 03DS325_12_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 27ecification
OPB External Peripheral Controller (EPC) v100a
28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 29ecification
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
20
Table 5 Synchronous Mode OPB EPC Latency
Transaction Type ParameterC_PRHx_DWIDTH_MATCH
FIFOMemory
OPB Latency Calculation
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory 9
1FIFO
Memory 8 + N(2)
ReadWrite access to synchronous device operating at OPB frequency and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory 11
1 FIFO 10 + N(2)
1 Memory 6 + 5N(2)
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is not multiplexed(1)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 7 peripheral clocks
1FIFO
Memory
7 OPB clocks + (6+N(2)) peripheral clocks
ReadWrite access to synchronous device operating on external peripheral clock and the addressdata bus is multiplexed(1 3)
OPB_Select to Sln_xferAck
0FIFO
Memory7 OPB clocks + 9 peripheral clocks
1 FIFO7 OPB clocks + (8+N(2)) peripheral clocks
1 Memory7 OPB clocks + (4+5N(2)) peripheral clocks
Notes 1 Latency calculations assumes the device is always ready2 N = Access size on the OPB (in bytes)width of peripheral data bus (in bytes) where access size on OPB
equals or less than C_OPB_DWIDTH expressed in terms of bytes3 Latency calculation assumes that the requirement on address setup (C_PRHx_ADDR_TSU) address hold
(C_PRHx_ADDR_TH) and ADS pulse width (C_PRHx_ADS_WIDTH) are all less than one OPB clock
OPB EPC External Peripheral ConnectionsThe OPB EPC interface to the external device is based upon the width of the OPB data bus address and data width of the peripheral subsystem number of peripherals in the system addressdata multiplex support mode of operation (synchronous or asynchronous) and if synchronous device the operating clock for the synchronous data path
Determining Address and Data Width
The address bus width of the peripheral subsystem is the maximum width of the address bus of all peripheral devices connected to the OPB EPC If all devices employ non-multiplexed address and data bus the data bus width of the peripheral subsystem is the maximum of the data bus width of all external devices If any of the devices are configured for multiplexed address and data bus then the data bus width of the peripheral subsystem should be set as the maximum of the data bus and the address bus of the device(s) employing a multiplexed address and data bus
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Endian Considerations
The peripheral address and data bus of the OPB EPC is labeled with big endian bit labeling (D0 is the MSB and D31 is the LSB for a 32-bit bus) while most peripheral devices are either endian agnostic ie they can be connected either way or little endian (D31 is the MSB and D0 is the LSB for a 32-bit bus) Caution must be exercised with the connection to the external peripheral devices to avoid incorrect data and address connections
Clock Generation
When connecting to a synchronous external device the OPB EPC may operate either on the OPB clock (OPB_Clk) or on a peripheral clock (PRH_Clk) The operating clock for the synchronous interface is based on the generic C_PRH_CLK_SUPPORT If C_PRH_CLK_SUPPORT = 1 the peripheral clock is used else the OPB clock is used The external devices connected to the OPB EPC will determine the operating frequency of the peripheral clock The minimum of the operating frequencies of various devices connected to OPB EPC should be used as the operating frequency of the peripheral clock (PRH_Clk)
Figure 4 illustrates a block diagram for generating a device specific clock source clock source using two DCMs The DCM modules are located within the FPGA but are external to the OPB EPC An external clock source is used to generate the OPB clock (OPB_Clk) to the OPB EPC The device clock source (PRH_Clk) is also generated from the same DCM (DCM0) using the CLKFX output and must be routed on the board to be fed back to the FPGA Another DCM (DCM1) is used to synchronize the device peripheral clock to the OPB EPC PRH_Clk
Figure 4 External Peripherals clocked by FPGA output with feedback
igure Top x-ref 4
DS325_04_071406
CLKFB CLK0
CLKFXCLKIN
DCM0
PRH_Clk_FB
PRH_Clk
OPB_Clk
CLKFB CLK0
CLKIN
DCM1
PRH_Clk
OPB_Clk
OPB EPCExternalDevice
CLK
FPGA
Example Peripheral Connections
Example SMSC LAN91C111 10100 non-PCI Ethernet Single Chip MAC + PHY
An example peripheral device supported by the OPB EPC is the SMSC 10100 non-PCI Ethernet Single Chip MAC + PHY LAN91C111 The OPB EPC allows OPB masters to access the device both in synchronous and asynchronous mode The device connections for synchronous and asynchronous mode of operations are outlined in the Asynchronous Mode and Synchronous Mode sections
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OPB External Peripheral Controller (EPC) v100a
22
F
Asynchronous Mode
Figure 5 illustrates the SMSC LAN91C111 connections to the OPB EPC in asynchronous mode with non-multiplexed address and data buses In asynchronous mode the input clock source (PRH_Clk) to the external device must be tied to VCC When the SMSC LAN91C111 is accessed through the asynchronous mode the rising edge of PRH_Rd_n and PRH_Wr_n signals are used to control the read and the write operations respectively As the device uses Asynchronous Ready (ARDY) signal to indicate its readiness in asynchronous mode This signal is connected to the PRH_Rdy input of the OPB EPC Since the address and the data buses are not multiplexed PRH_ADS will be driven low by the OPB EPC
The following parameter settings apply for the connections shown in Figure 5
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 5 SMSC LAN91C111 Connection to OPB EPC in Asynchronous Mode
igure Top x-ref 5
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]
PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
To System Interrupt Controller
VCC
LCLKResetAENnADSA[151]
nBE[30]
ARDYnRdnWR
D[310]
INTRO
WnRnVLBUSnCYCLE
nRDYRTNnDADACS
nLDEVnSARDY
SMSC LAN91C111
ExternalGlue Logic
PPC
OP
B B
us
FPGA
DS325_05_071406
ExternalReset VCC
External Glue Logic
Special attention must be given while interfacing the OPB EPC to the SMSC LAN91C111 in asynchronous mode The OPB EPC drives the PRH_BE active high while the SMSC LAN91C111 requires the input byte enable to be active low To match this requirement external glue logic is required to invert the PRH_BE signals before they are interfaced with the byte enable signals of the SMSC LAN91C111
Discontinued IP
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OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Synchronous Mode
Figure 6 illustrates the SMSC LAN91C111 connection to the OPB EPC in synchronous VL Bus mode with non-multiplexed address and data buses In synchronous mode the device requires an input clock source to the LCLK pin with a maximum operating frequency of 50MHz The local clock generated by the DCM for the peripheral interface must be routed to the LCLK input of SMSC LAN91C111 and PRH_Clk of OPB EPC When the device is accessed PRH_RNW is used as the control signal to indicate a readwrite access When PRH_RNW is high it indicates a read operation and when low it indicates a write operation The SMSC LAN91C111 uses nSRDY signal to indicate the device readiness This signal is connected to PRH_Rdy input of the OPB_EPC As the address and the data bus are not multiplexed PRH_ADS will be driven low
The following parameter settings apply for the connections shown in Figure 6
bull C_PRH_CLK_SUPPORT = 1
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 1
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 6 SMSC LAN91C111 Connection to OPB EPC in Synchronous Mode
igure Top x-ref 6
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
LCLKResetAENnADSA[151]nBE[30]WnRnSRDY
D[310]
nCYCLEnRDYRTN
INTRO
nRdnWR
nDADACSnLDEVARDY
nVLBUS
SMSC LAN91C111
ExternalGlue Logic
DigitalClock
Manager
PP
C
OP
B B
us
FPGA
DS325_06_071406
External Reset
VCC
GND
To System Interrupt Controller
External Glue Logic
The SMSC LAN91C111 device requires two inputs nCYCLE and nRDYRTN to control synchronous operation The definition of these signals is outside the scope of this document and can be found in the documents listed in the Reference Documents section The nCYCLE and nRDYRTN signals are generated in external glue logic nCYCLE may be generated from PRH_CS_n and is driven low for a
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OPB External Peripheral Controller (EPC) v100a
24
single clock cycle on a high to low transition on PRH_CS_n nRDYRTN is simply the registered value of the nSRDY signal
Design Considerations
When the OPB EPC is interfaced to the SMSC LAN91C111 with data width match enabled (C_PRHx_DWIDTH_MATCH = 1) and the internal SRAM of the peripheral is being accessed the device has to be configured in the address auto increment mode Address auto increment mode can be configured by setting AUTO INCR bit in the Bank 2 Pointer Register of SMSC LAN91C111 More information can be obtained by referring the registers of Bank 2 in SMSC LAN91C111 data sheet See the Reference Documents section
Example Cypress Semiconductorrsquos CY7C67300 EZ-Host Programmable Embedded USB HostPeripheral Controller
The Cypress Semiconductorrsquos CY7C67300 EZ-Hosttrade Programmable Embedded USB HostPeripheral Controller is another example of a peripheral device supported by the OPB EPC Since the Cypress USB controller operates in asynchronous mode the OPB EPC must be configured to support asynchronous mode operation
Asynchronous Mode
Figure 7 illustrates the CY7C67300 USB Controller connection to the OPB EPC in asynchronous mode with non-multiplexed address and data buses
The following parameter settings apply for the connection shown in Figure 7
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 4
bull C_PRH0_DWIDTH = 16
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Configuration of CY7C67300 USB Controller
The CY7C67300 USB Controller is configured as a Host Processor Interface (HPI) The boot-up sequence code for the CY7C67300 USB Controller in this particular example is present on the external Compact Flash memory device and is accessed through the OPB SYSACE interface This code is downloaded to the CY7C67300 USB Controller through the HPI interface Once this boot-up sequence is executed by the CY7C67300 USB Controller it becomes ready to operate in normal HPI mode with the external host controller (OPB EPC)
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wwwxilinxcom DS325 August 10 2007Product Specification
F
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 7 CY7C67300 USB Controller connection to OPB EPC in asynchronous mode
igure Top x-ref 7
SysACE_mpd_I[015]SysACE_mpd_O[015]SysACE_mpd_T[015]
SysACE_mpweSysACE_mpoe
SysACE_MPA[06]
SysACE_CEN
OPB SYS ACE Cntlr[150][150][150]
[60]
PRH_RstPRH_Rdy
PRH_CS_n
PRH_Data_I[015]PRH_Data_O[015]PRH_Data_T[015]
PRH_ADSPRH_RRNW
PRH_BurstPRH_Rd_nPRH_Wr_n
PRH_Addr[01]
OPB EPC
VCC
Ext
erna
l US
B P
orts
P
ort 1
A 1
B 2
AnCS
nRD
nWR
[D15D0]
[A1A0]
INT
CompactFLASH
TQFP144 SYSTEMACE
System ACE CompactFlash Controller
Ext
erna
l Glu
e Lo
gic
OPBINTC
US
B C
Y7C
6730
0
PP
C
OP
B B
us
FPGA
DS325_07_071406
Sysace_epc_data[150]
HPI interface
Sysace_epc_rd_n
Sysace_epc_wr_n
Sysace_epc_a[10]
DM1B
DP1B
DM2A
DP2A
DM1A
DP1A
External Glue Logic
In the interface diagram shown in Figure 7 the OPB EPC as well as the OPB SYSACE share the interface for data address and control lines on the board This requires external multiplex logic to be placed outside of IP cores in the FPGA The OPB EPC control signals PRH_RD_n and PRH_WR_n are muxed with the MEM_CEN and MEM_WEN signals of the OPB SYSACE When CY7C67300 USB Controller is accessed through the asynchronous mode the rising edge of sysace_epc_rd_n and sysace_epc_wr_n signals are used to control the read and the write operations respectively See the Reference Documents section for more information on OPB SYSACE
Design Constraints
Timing Constraints
Timing constraints must be placed on the system clock and the peripheral clock setting the frequency to meet the bus timing requirements An example is shown in Figure 8
Discontinued IP
ust 10 2007 wwwxilinxcom 25ecification
F
OPB External Peripheral Controller (EPC) v100a
26
Figure 8 EPC Timing Constraints
igure Top x-ref 8
Following constraint must be placed on the system clock
TIMESPEC TS_OPB_Clk = PERIOD OPB_Clk 10 ns HIGH 50
NET OPB_Clk TNM_NET = OPB_Clk
If C_PRH_CLK_SUPPORT=1 then the following constraint must be placed on the peripheral clock
TIMESPEC TS_PRH_Clk = PERIOD PRH_Clk 20 ns HIGH 50
NET PRH_Clk TNM_NET = PRH_Clk
DS325_08_071406
Design Implementation
Timing Diagrams
The timing diagrams in the figures below show various OPB transactions and the resulting access cycles on the peripheral interface Timing diagrams are not shown for all possible combinations of generics and the resulting access cycles However the timing diagrams shown are sufficient for the basic understanding of various access cycles supported by the OPB EPC
Figure 9 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 9
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
DS325_09_071206
8
4000000
004
04
Figure 10 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 10
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
04000000
20000004
8
00000000
004
04DS325_10_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 11 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 11
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000000
F
00010203
000 001 002 003
00 01 02 03DS325_11_071206
Figure 12 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 12
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
20000000
F
0000000000000000
000 001 002 003
00 01 02 03DS325_12_071206
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28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
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wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
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Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
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wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
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OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Endian Considerations
The peripheral address and data bus of the OPB EPC is labeled with big endian bit labeling (D0 is the MSB and D31 is the LSB for a 32-bit bus) while most peripheral devices are either endian agnostic ie they can be connected either way or little endian (D31 is the MSB and D0 is the LSB for a 32-bit bus) Caution must be exercised with the connection to the external peripheral devices to avoid incorrect data and address connections
Clock Generation
When connecting to a synchronous external device the OPB EPC may operate either on the OPB clock (OPB_Clk) or on a peripheral clock (PRH_Clk) The operating clock for the synchronous interface is based on the generic C_PRH_CLK_SUPPORT If C_PRH_CLK_SUPPORT = 1 the peripheral clock is used else the OPB clock is used The external devices connected to the OPB EPC will determine the operating frequency of the peripheral clock The minimum of the operating frequencies of various devices connected to OPB EPC should be used as the operating frequency of the peripheral clock (PRH_Clk)
Figure 4 illustrates a block diagram for generating a device specific clock source clock source using two DCMs The DCM modules are located within the FPGA but are external to the OPB EPC An external clock source is used to generate the OPB clock (OPB_Clk) to the OPB EPC The device clock source (PRH_Clk) is also generated from the same DCM (DCM0) using the CLKFX output and must be routed on the board to be fed back to the FPGA Another DCM (DCM1) is used to synchronize the device peripheral clock to the OPB EPC PRH_Clk
Figure 4 External Peripherals clocked by FPGA output with feedback
igure Top x-ref 4
DS325_04_071406
CLKFB CLK0
CLKFXCLKIN
DCM0
PRH_Clk_FB
PRH_Clk
OPB_Clk
CLKFB CLK0
CLKIN
DCM1
PRH_Clk
OPB_Clk
OPB EPCExternalDevice
CLK
FPGA
Example Peripheral Connections
Example SMSC LAN91C111 10100 non-PCI Ethernet Single Chip MAC + PHY
An example peripheral device supported by the OPB EPC is the SMSC 10100 non-PCI Ethernet Single Chip MAC + PHY LAN91C111 The OPB EPC allows OPB masters to access the device both in synchronous and asynchronous mode The device connections for synchronous and asynchronous mode of operations are outlined in the Asynchronous Mode and Synchronous Mode sections
Discontinued IP
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OPB External Peripheral Controller (EPC) v100a
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F
Asynchronous Mode
Figure 5 illustrates the SMSC LAN91C111 connections to the OPB EPC in asynchronous mode with non-multiplexed address and data buses In asynchronous mode the input clock source (PRH_Clk) to the external device must be tied to VCC When the SMSC LAN91C111 is accessed through the asynchronous mode the rising edge of PRH_Rd_n and PRH_Wr_n signals are used to control the read and the write operations respectively As the device uses Asynchronous Ready (ARDY) signal to indicate its readiness in asynchronous mode This signal is connected to the PRH_Rdy input of the OPB EPC Since the address and the data buses are not multiplexed PRH_ADS will be driven low by the OPB EPC
The following parameter settings apply for the connections shown in Figure 5
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 5 SMSC LAN91C111 Connection to OPB EPC in Asynchronous Mode
igure Top x-ref 5
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]
PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
To System Interrupt Controller
VCC
LCLKResetAENnADSA[151]
nBE[30]
ARDYnRdnWR
D[310]
INTRO
WnRnVLBUSnCYCLE
nRDYRTNnDADACS
nLDEVnSARDY
SMSC LAN91C111
ExternalGlue Logic
PPC
OP
B B
us
FPGA
DS325_05_071406
ExternalReset VCC
External Glue Logic
Special attention must be given while interfacing the OPB EPC to the SMSC LAN91C111 in asynchronous mode The OPB EPC drives the PRH_BE active high while the SMSC LAN91C111 requires the input byte enable to be active low To match this requirement external glue logic is required to invert the PRH_BE signals before they are interfaced with the byte enable signals of the SMSC LAN91C111
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Synchronous Mode
Figure 6 illustrates the SMSC LAN91C111 connection to the OPB EPC in synchronous VL Bus mode with non-multiplexed address and data buses In synchronous mode the device requires an input clock source to the LCLK pin with a maximum operating frequency of 50MHz The local clock generated by the DCM for the peripheral interface must be routed to the LCLK input of SMSC LAN91C111 and PRH_Clk of OPB EPC When the device is accessed PRH_RNW is used as the control signal to indicate a readwrite access When PRH_RNW is high it indicates a read operation and when low it indicates a write operation The SMSC LAN91C111 uses nSRDY signal to indicate the device readiness This signal is connected to PRH_Rdy input of the OPB_EPC As the address and the data bus are not multiplexed PRH_ADS will be driven low
The following parameter settings apply for the connections shown in Figure 6
bull C_PRH_CLK_SUPPORT = 1
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 1
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 6 SMSC LAN91C111 Connection to OPB EPC in Synchronous Mode
igure Top x-ref 6
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
LCLKResetAENnADSA[151]nBE[30]WnRnSRDY
D[310]
nCYCLEnRDYRTN
INTRO
nRdnWR
nDADACSnLDEVARDY
nVLBUS
SMSC LAN91C111
ExternalGlue Logic
DigitalClock
Manager
PP
C
OP
B B
us
FPGA
DS325_06_071406
External Reset
VCC
GND
To System Interrupt Controller
External Glue Logic
The SMSC LAN91C111 device requires two inputs nCYCLE and nRDYRTN to control synchronous operation The definition of these signals is outside the scope of this document and can be found in the documents listed in the Reference Documents section The nCYCLE and nRDYRTN signals are generated in external glue logic nCYCLE may be generated from PRH_CS_n and is driven low for a
Discontinued IP
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OPB External Peripheral Controller (EPC) v100a
24
single clock cycle on a high to low transition on PRH_CS_n nRDYRTN is simply the registered value of the nSRDY signal
Design Considerations
When the OPB EPC is interfaced to the SMSC LAN91C111 with data width match enabled (C_PRHx_DWIDTH_MATCH = 1) and the internal SRAM of the peripheral is being accessed the device has to be configured in the address auto increment mode Address auto increment mode can be configured by setting AUTO INCR bit in the Bank 2 Pointer Register of SMSC LAN91C111 More information can be obtained by referring the registers of Bank 2 in SMSC LAN91C111 data sheet See the Reference Documents section
Example Cypress Semiconductorrsquos CY7C67300 EZ-Host Programmable Embedded USB HostPeripheral Controller
The Cypress Semiconductorrsquos CY7C67300 EZ-Hosttrade Programmable Embedded USB HostPeripheral Controller is another example of a peripheral device supported by the OPB EPC Since the Cypress USB controller operates in asynchronous mode the OPB EPC must be configured to support asynchronous mode operation
Asynchronous Mode
Figure 7 illustrates the CY7C67300 USB Controller connection to the OPB EPC in asynchronous mode with non-multiplexed address and data buses
The following parameter settings apply for the connection shown in Figure 7
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 4
bull C_PRH0_DWIDTH = 16
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Configuration of CY7C67300 USB Controller
The CY7C67300 USB Controller is configured as a Host Processor Interface (HPI) The boot-up sequence code for the CY7C67300 USB Controller in this particular example is present on the external Compact Flash memory device and is accessed through the OPB SYSACE interface This code is downloaded to the CY7C67300 USB Controller through the HPI interface Once this boot-up sequence is executed by the CY7C67300 USB Controller it becomes ready to operate in normal HPI mode with the external host controller (OPB EPC)
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
F
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 7 CY7C67300 USB Controller connection to OPB EPC in asynchronous mode
igure Top x-ref 7
SysACE_mpd_I[015]SysACE_mpd_O[015]SysACE_mpd_T[015]
SysACE_mpweSysACE_mpoe
SysACE_MPA[06]
SysACE_CEN
OPB SYS ACE Cntlr[150][150][150]
[60]
PRH_RstPRH_Rdy
PRH_CS_n
PRH_Data_I[015]PRH_Data_O[015]PRH_Data_T[015]
PRH_ADSPRH_RRNW
PRH_BurstPRH_Rd_nPRH_Wr_n
PRH_Addr[01]
OPB EPC
VCC
Ext
erna
l US
B P
orts
P
ort 1
A 1
B 2
AnCS
nRD
nWR
[D15D0]
[A1A0]
INT
CompactFLASH
TQFP144 SYSTEMACE
System ACE CompactFlash Controller
Ext
erna
l Glu
e Lo
gic
OPBINTC
US
B C
Y7C
6730
0
PP
C
OP
B B
us
FPGA
DS325_07_071406
Sysace_epc_data[150]
HPI interface
Sysace_epc_rd_n
Sysace_epc_wr_n
Sysace_epc_a[10]
DM1B
DP1B
DM2A
DP2A
DM1A
DP1A
External Glue Logic
In the interface diagram shown in Figure 7 the OPB EPC as well as the OPB SYSACE share the interface for data address and control lines on the board This requires external multiplex logic to be placed outside of IP cores in the FPGA The OPB EPC control signals PRH_RD_n and PRH_WR_n are muxed with the MEM_CEN and MEM_WEN signals of the OPB SYSACE When CY7C67300 USB Controller is accessed through the asynchronous mode the rising edge of sysace_epc_rd_n and sysace_epc_wr_n signals are used to control the read and the write operations respectively See the Reference Documents section for more information on OPB SYSACE
Design Constraints
Timing Constraints
Timing constraints must be placed on the system clock and the peripheral clock setting the frequency to meet the bus timing requirements An example is shown in Figure 8
Discontinued IP
ust 10 2007 wwwxilinxcom 25ecification
F
OPB External Peripheral Controller (EPC) v100a
26
Figure 8 EPC Timing Constraints
igure Top x-ref 8
Following constraint must be placed on the system clock
TIMESPEC TS_OPB_Clk = PERIOD OPB_Clk 10 ns HIGH 50
NET OPB_Clk TNM_NET = OPB_Clk
If C_PRH_CLK_SUPPORT=1 then the following constraint must be placed on the peripheral clock
TIMESPEC TS_PRH_Clk = PERIOD PRH_Clk 20 ns HIGH 50
NET PRH_Clk TNM_NET = PRH_Clk
DS325_08_071406
Design Implementation
Timing Diagrams
The timing diagrams in the figures below show various OPB transactions and the resulting access cycles on the peripheral interface Timing diagrams are not shown for all possible combinations of generics and the resulting access cycles However the timing diagrams shown are sufficient for the basic understanding of various access cycles supported by the OPB EPC
Figure 9 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 9
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
DS325_09_071206
8
4000000
004
04
Figure 10 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 10
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
04000000
20000004
8
00000000
004
04DS325_10_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 11 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 11
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000000
F
00010203
000 001 002 003
00 01 02 03DS325_11_071206
Figure 12 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 12
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
20000000
F
0000000000000000
000 001 002 003
00 01 02 03DS325_12_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 27ecification
OPB External Peripheral Controller (EPC) v100a
28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 29ecification
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
22
F
Asynchronous Mode
Figure 5 illustrates the SMSC LAN91C111 connections to the OPB EPC in asynchronous mode with non-multiplexed address and data buses In asynchronous mode the input clock source (PRH_Clk) to the external device must be tied to VCC When the SMSC LAN91C111 is accessed through the asynchronous mode the rising edge of PRH_Rd_n and PRH_Wr_n signals are used to control the read and the write operations respectively As the device uses Asynchronous Ready (ARDY) signal to indicate its readiness in asynchronous mode This signal is connected to the PRH_Rdy input of the OPB EPC Since the address and the data buses are not multiplexed PRH_ADS will be driven low by the OPB EPC
The following parameter settings apply for the connections shown in Figure 5
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 5 SMSC LAN91C111 Connection to OPB EPC in Asynchronous Mode
igure Top x-ref 5
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]
PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
To System Interrupt Controller
VCC
LCLKResetAENnADSA[151]
nBE[30]
ARDYnRdnWR
D[310]
INTRO
WnRnVLBUSnCYCLE
nRDYRTNnDADACS
nLDEVnSARDY
SMSC LAN91C111
ExternalGlue Logic
PPC
OP
B B
us
FPGA
DS325_05_071406
ExternalReset VCC
External Glue Logic
Special attention must be given while interfacing the OPB EPC to the SMSC LAN91C111 in asynchronous mode The OPB EPC drives the PRH_BE active high while the SMSC LAN91C111 requires the input byte enable to be active low To match this requirement external glue logic is required to invert the PRH_BE signals before they are interfaced with the byte enable signals of the SMSC LAN91C111
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Synchronous Mode
Figure 6 illustrates the SMSC LAN91C111 connection to the OPB EPC in synchronous VL Bus mode with non-multiplexed address and data buses In synchronous mode the device requires an input clock source to the LCLK pin with a maximum operating frequency of 50MHz The local clock generated by the DCM for the peripheral interface must be routed to the LCLK input of SMSC LAN91C111 and PRH_Clk of OPB EPC When the device is accessed PRH_RNW is used as the control signal to indicate a readwrite access When PRH_RNW is high it indicates a read operation and when low it indicates a write operation The SMSC LAN91C111 uses nSRDY signal to indicate the device readiness This signal is connected to PRH_Rdy input of the OPB_EPC As the address and the data bus are not multiplexed PRH_ADS will be driven low
The following parameter settings apply for the connections shown in Figure 6
bull C_PRH_CLK_SUPPORT = 1
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 1
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 6 SMSC LAN91C111 Connection to OPB EPC in Synchronous Mode
igure Top x-ref 6
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
LCLKResetAENnADSA[151]nBE[30]WnRnSRDY
D[310]
nCYCLEnRDYRTN
INTRO
nRdnWR
nDADACSnLDEVARDY
nVLBUS
SMSC LAN91C111
ExternalGlue Logic
DigitalClock
Manager
PP
C
OP
B B
us
FPGA
DS325_06_071406
External Reset
VCC
GND
To System Interrupt Controller
External Glue Logic
The SMSC LAN91C111 device requires two inputs nCYCLE and nRDYRTN to control synchronous operation The definition of these signals is outside the scope of this document and can be found in the documents listed in the Reference Documents section The nCYCLE and nRDYRTN signals are generated in external glue logic nCYCLE may be generated from PRH_CS_n and is driven low for a
Discontinued IP
ust 10 2007 wwwxilinxcom 23ecification
OPB External Peripheral Controller (EPC) v100a
24
single clock cycle on a high to low transition on PRH_CS_n nRDYRTN is simply the registered value of the nSRDY signal
Design Considerations
When the OPB EPC is interfaced to the SMSC LAN91C111 with data width match enabled (C_PRHx_DWIDTH_MATCH = 1) and the internal SRAM of the peripheral is being accessed the device has to be configured in the address auto increment mode Address auto increment mode can be configured by setting AUTO INCR bit in the Bank 2 Pointer Register of SMSC LAN91C111 More information can be obtained by referring the registers of Bank 2 in SMSC LAN91C111 data sheet See the Reference Documents section
Example Cypress Semiconductorrsquos CY7C67300 EZ-Host Programmable Embedded USB HostPeripheral Controller
The Cypress Semiconductorrsquos CY7C67300 EZ-Hosttrade Programmable Embedded USB HostPeripheral Controller is another example of a peripheral device supported by the OPB EPC Since the Cypress USB controller operates in asynchronous mode the OPB EPC must be configured to support asynchronous mode operation
Asynchronous Mode
Figure 7 illustrates the CY7C67300 USB Controller connection to the OPB EPC in asynchronous mode with non-multiplexed address and data buses
The following parameter settings apply for the connection shown in Figure 7
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 4
bull C_PRH0_DWIDTH = 16
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Configuration of CY7C67300 USB Controller
The CY7C67300 USB Controller is configured as a Host Processor Interface (HPI) The boot-up sequence code for the CY7C67300 USB Controller in this particular example is present on the external Compact Flash memory device and is accessed through the OPB SYSACE interface This code is downloaded to the CY7C67300 USB Controller through the HPI interface Once this boot-up sequence is executed by the CY7C67300 USB Controller it becomes ready to operate in normal HPI mode with the external host controller (OPB EPC)
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
F
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 7 CY7C67300 USB Controller connection to OPB EPC in asynchronous mode
igure Top x-ref 7
SysACE_mpd_I[015]SysACE_mpd_O[015]SysACE_mpd_T[015]
SysACE_mpweSysACE_mpoe
SysACE_MPA[06]
SysACE_CEN
OPB SYS ACE Cntlr[150][150][150]
[60]
PRH_RstPRH_Rdy
PRH_CS_n
PRH_Data_I[015]PRH_Data_O[015]PRH_Data_T[015]
PRH_ADSPRH_RRNW
PRH_BurstPRH_Rd_nPRH_Wr_n
PRH_Addr[01]
OPB EPC
VCC
Ext
erna
l US
B P
orts
P
ort 1
A 1
B 2
AnCS
nRD
nWR
[D15D0]
[A1A0]
INT
CompactFLASH
TQFP144 SYSTEMACE
System ACE CompactFlash Controller
Ext
erna
l Glu
e Lo
gic
OPBINTC
US
B C
Y7C
6730
0
PP
C
OP
B B
us
FPGA
DS325_07_071406
Sysace_epc_data[150]
HPI interface
Sysace_epc_rd_n
Sysace_epc_wr_n
Sysace_epc_a[10]
DM1B
DP1B
DM2A
DP2A
DM1A
DP1A
External Glue Logic
In the interface diagram shown in Figure 7 the OPB EPC as well as the OPB SYSACE share the interface for data address and control lines on the board This requires external multiplex logic to be placed outside of IP cores in the FPGA The OPB EPC control signals PRH_RD_n and PRH_WR_n are muxed with the MEM_CEN and MEM_WEN signals of the OPB SYSACE When CY7C67300 USB Controller is accessed through the asynchronous mode the rising edge of sysace_epc_rd_n and sysace_epc_wr_n signals are used to control the read and the write operations respectively See the Reference Documents section for more information on OPB SYSACE
Design Constraints
Timing Constraints
Timing constraints must be placed on the system clock and the peripheral clock setting the frequency to meet the bus timing requirements An example is shown in Figure 8
Discontinued IP
ust 10 2007 wwwxilinxcom 25ecification
F
OPB External Peripheral Controller (EPC) v100a
26
Figure 8 EPC Timing Constraints
igure Top x-ref 8
Following constraint must be placed on the system clock
TIMESPEC TS_OPB_Clk = PERIOD OPB_Clk 10 ns HIGH 50
NET OPB_Clk TNM_NET = OPB_Clk
If C_PRH_CLK_SUPPORT=1 then the following constraint must be placed on the peripheral clock
TIMESPEC TS_PRH_Clk = PERIOD PRH_Clk 20 ns HIGH 50
NET PRH_Clk TNM_NET = PRH_Clk
DS325_08_071406
Design Implementation
Timing Diagrams
The timing diagrams in the figures below show various OPB transactions and the resulting access cycles on the peripheral interface Timing diagrams are not shown for all possible combinations of generics and the resulting access cycles However the timing diagrams shown are sufficient for the basic understanding of various access cycles supported by the OPB EPC
Figure 9 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 9
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
DS325_09_071206
8
4000000
004
04
Figure 10 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 10
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
04000000
20000004
8
00000000
004
04DS325_10_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 11 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 11
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000000
F
00010203
000 001 002 003
00 01 02 03DS325_11_071206
Figure 12 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 12
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
20000000
F
0000000000000000
000 001 002 003
00 01 02 03DS325_12_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 27ecification
OPB External Peripheral Controller (EPC) v100a
28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 29ecification
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 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UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
F
Synchronous Mode
Figure 6 illustrates the SMSC LAN91C111 connection to the OPB EPC in synchronous VL Bus mode with non-multiplexed address and data buses In synchronous mode the device requires an input clock source to the LCLK pin with a maximum operating frequency of 50MHz The local clock generated by the DCM for the peripheral interface must be routed to the LCLK input of SMSC LAN91C111 and PRH_Clk of OPB EPC When the device is accessed PRH_RNW is used as the control signal to indicate a readwrite access When PRH_RNW is high it indicates a read operation and when low it indicates a write operation The SMSC LAN91C111 uses nSRDY signal to indicate the device readiness This signal is connected to PRH_Rdy input of the OPB_EPC As the address and the data bus are not multiplexed PRH_ADS will be driven low
The following parameter settings apply for the connections shown in Figure 6
bull C_PRH_CLK_SUPPORT = 1
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 16
bull C_PRH0_DWIDTH = 32
bull C_PRH0_SYNC = 1
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Figure 6 SMSC LAN91C111 Connection to OPB EPC in Synchronous Mode
igure Top x-ref 6
PRH_ClkPRH_Rst
PRH_CS_nPRH_ADS
PRH_ADDR[014]PRH_BE[03]
PRH_RNWPRH_Rdy
PRH_Rd_nPRH_Wr_nPRH_Burst
PRH_DATA[031]
OPB EPC
LCLKResetAENnADSA[151]nBE[30]WnRnSRDY
D[310]
nCYCLEnRDYRTN
INTRO
nRdnWR
nDADACSnLDEVARDY
nVLBUS
SMSC LAN91C111
ExternalGlue Logic
DigitalClock
Manager
PP
C
OP
B B
us
FPGA
DS325_06_071406
External Reset
VCC
GND
To System Interrupt Controller
External Glue Logic
The SMSC LAN91C111 device requires two inputs nCYCLE and nRDYRTN to control synchronous operation The definition of these signals is outside the scope of this document and can be found in the documents listed in the Reference Documents section The nCYCLE and nRDYRTN signals are generated in external glue logic nCYCLE may be generated from PRH_CS_n and is driven low for a
Discontinued IP
ust 10 2007 wwwxilinxcom 23ecification
OPB External Peripheral Controller (EPC) v100a
24
single clock cycle on a high to low transition on PRH_CS_n nRDYRTN is simply the registered value of the nSRDY signal
Design Considerations
When the OPB EPC is interfaced to the SMSC LAN91C111 with data width match enabled (C_PRHx_DWIDTH_MATCH = 1) and the internal SRAM of the peripheral is being accessed the device has to be configured in the address auto increment mode Address auto increment mode can be configured by setting AUTO INCR bit in the Bank 2 Pointer Register of SMSC LAN91C111 More information can be obtained by referring the registers of Bank 2 in SMSC LAN91C111 data sheet See the Reference Documents section
Example Cypress Semiconductorrsquos CY7C67300 EZ-Host Programmable Embedded USB HostPeripheral Controller
The Cypress Semiconductorrsquos CY7C67300 EZ-Hosttrade Programmable Embedded USB HostPeripheral Controller is another example of a peripheral device supported by the OPB EPC Since the Cypress USB controller operates in asynchronous mode the OPB EPC must be configured to support asynchronous mode operation
Asynchronous Mode
Figure 7 illustrates the CY7C67300 USB Controller connection to the OPB EPC in asynchronous mode with non-multiplexed address and data buses
The following parameter settings apply for the connection shown in Figure 7
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 4
bull C_PRH0_DWIDTH = 16
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Configuration of CY7C67300 USB Controller
The CY7C67300 USB Controller is configured as a Host Processor Interface (HPI) The boot-up sequence code for the CY7C67300 USB Controller in this particular example is present on the external Compact Flash memory device and is accessed through the OPB SYSACE interface This code is downloaded to the CY7C67300 USB Controller through the HPI interface Once this boot-up sequence is executed by the CY7C67300 USB Controller it becomes ready to operate in normal HPI mode with the external host controller (OPB EPC)
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
F
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 7 CY7C67300 USB Controller connection to OPB EPC in asynchronous mode
igure Top x-ref 7
SysACE_mpd_I[015]SysACE_mpd_O[015]SysACE_mpd_T[015]
SysACE_mpweSysACE_mpoe
SysACE_MPA[06]
SysACE_CEN
OPB SYS ACE Cntlr[150][150][150]
[60]
PRH_RstPRH_Rdy
PRH_CS_n
PRH_Data_I[015]PRH_Data_O[015]PRH_Data_T[015]
PRH_ADSPRH_RRNW
PRH_BurstPRH_Rd_nPRH_Wr_n
PRH_Addr[01]
OPB EPC
VCC
Ext
erna
l US
B P
orts
P
ort 1
A 1
B 2
AnCS
nRD
nWR
[D15D0]
[A1A0]
INT
CompactFLASH
TQFP144 SYSTEMACE
System ACE CompactFlash Controller
Ext
erna
l Glu
e Lo
gic
OPBINTC
US
B C
Y7C
6730
0
PP
C
OP
B B
us
FPGA
DS325_07_071406
Sysace_epc_data[150]
HPI interface
Sysace_epc_rd_n
Sysace_epc_wr_n
Sysace_epc_a[10]
DM1B
DP1B
DM2A
DP2A
DM1A
DP1A
External Glue Logic
In the interface diagram shown in Figure 7 the OPB EPC as well as the OPB SYSACE share the interface for data address and control lines on the board This requires external multiplex logic to be placed outside of IP cores in the FPGA The OPB EPC control signals PRH_RD_n and PRH_WR_n are muxed with the MEM_CEN and MEM_WEN signals of the OPB SYSACE When CY7C67300 USB Controller is accessed through the asynchronous mode the rising edge of sysace_epc_rd_n and sysace_epc_wr_n signals are used to control the read and the write operations respectively See the Reference Documents section for more information on OPB SYSACE
Design Constraints
Timing Constraints
Timing constraints must be placed on the system clock and the peripheral clock setting the frequency to meet the bus timing requirements An example is shown in Figure 8
Discontinued IP
ust 10 2007 wwwxilinxcom 25ecification
F
OPB External Peripheral Controller (EPC) v100a
26
Figure 8 EPC Timing Constraints
igure Top x-ref 8
Following constraint must be placed on the system clock
TIMESPEC TS_OPB_Clk = PERIOD OPB_Clk 10 ns HIGH 50
NET OPB_Clk TNM_NET = OPB_Clk
If C_PRH_CLK_SUPPORT=1 then the following constraint must be placed on the peripheral clock
TIMESPEC TS_PRH_Clk = PERIOD PRH_Clk 20 ns HIGH 50
NET PRH_Clk TNM_NET = PRH_Clk
DS325_08_071406
Design Implementation
Timing Diagrams
The timing diagrams in the figures below show various OPB transactions and the resulting access cycles on the peripheral interface Timing diagrams are not shown for all possible combinations of generics and the resulting access cycles However the timing diagrams shown are sufficient for the basic understanding of various access cycles supported by the OPB EPC
Figure 9 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 9
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
DS325_09_071206
8
4000000
004
04
Figure 10 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 10
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
04000000
20000004
8
00000000
004
04DS325_10_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 11 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 11
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000000
F
00010203
000 001 002 003
00 01 02 03DS325_11_071206
Figure 12 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 12
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
20000000
F
0000000000000000
000 001 002 003
00 01 02 03DS325_12_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 27ecification
OPB External Peripheral Controller (EPC) v100a
28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 29ecification
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
24
single clock cycle on a high to low transition on PRH_CS_n nRDYRTN is simply the registered value of the nSRDY signal
Design Considerations
When the OPB EPC is interfaced to the SMSC LAN91C111 with data width match enabled (C_PRHx_DWIDTH_MATCH = 1) and the internal SRAM of the peripheral is being accessed the device has to be configured in the address auto increment mode Address auto increment mode can be configured by setting AUTO INCR bit in the Bank 2 Pointer Register of SMSC LAN91C111 More information can be obtained by referring the registers of Bank 2 in SMSC LAN91C111 data sheet See the Reference Documents section
Example Cypress Semiconductorrsquos CY7C67300 EZ-Host Programmable Embedded USB HostPeripheral Controller
The Cypress Semiconductorrsquos CY7C67300 EZ-Hosttrade Programmable Embedded USB HostPeripheral Controller is another example of a peripheral device supported by the OPB EPC Since the Cypress USB controller operates in asynchronous mode the OPB EPC must be configured to support asynchronous mode operation
Asynchronous Mode
Figure 7 illustrates the CY7C67300 USB Controller connection to the OPB EPC in asynchronous mode with non-multiplexed address and data buses
The following parameter settings apply for the connection shown in Figure 7
bull C_PRH_CLK_SUPPORT = 0
bull C_PRH_BURST_SUPPORT = 0
bull C_PRH0_AWIDTH = 4
bull C_PRH0_DWIDTH = 16
bull C_PRH0_SYNC = 0
bull C_PRH0_DWIDTH_MATCH = 0
bull C_PRH0_BUS_MULTIPLEX = 0
Configuration of CY7C67300 USB Controller
The CY7C67300 USB Controller is configured as a Host Processor Interface (HPI) The boot-up sequence code for the CY7C67300 USB Controller in this particular example is present on the external Compact Flash memory device and is accessed through the OPB SYSACE interface This code is downloaded to the CY7C67300 USB Controller through the HPI interface Once this boot-up sequence is executed by the CY7C67300 USB Controller it becomes ready to operate in normal HPI mode with the external host controller (OPB EPC)
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
F
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 7 CY7C67300 USB Controller connection to OPB EPC in asynchronous mode
igure Top x-ref 7
SysACE_mpd_I[015]SysACE_mpd_O[015]SysACE_mpd_T[015]
SysACE_mpweSysACE_mpoe
SysACE_MPA[06]
SysACE_CEN
OPB SYS ACE Cntlr[150][150][150]
[60]
PRH_RstPRH_Rdy
PRH_CS_n
PRH_Data_I[015]PRH_Data_O[015]PRH_Data_T[015]
PRH_ADSPRH_RRNW
PRH_BurstPRH_Rd_nPRH_Wr_n
PRH_Addr[01]
OPB EPC
VCC
Ext
erna
l US
B P
orts
P
ort 1
A 1
B 2
AnCS
nRD
nWR
[D15D0]
[A1A0]
INT
CompactFLASH
TQFP144 SYSTEMACE
System ACE CompactFlash Controller
Ext
erna
l Glu
e Lo
gic
OPBINTC
US
B C
Y7C
6730
0
PP
C
OP
B B
us
FPGA
DS325_07_071406
Sysace_epc_data[150]
HPI interface
Sysace_epc_rd_n
Sysace_epc_wr_n
Sysace_epc_a[10]
DM1B
DP1B
DM2A
DP2A
DM1A
DP1A
External Glue Logic
In the interface diagram shown in Figure 7 the OPB EPC as well as the OPB SYSACE share the interface for data address and control lines on the board This requires external multiplex logic to be placed outside of IP cores in the FPGA The OPB EPC control signals PRH_RD_n and PRH_WR_n are muxed with the MEM_CEN and MEM_WEN signals of the OPB SYSACE When CY7C67300 USB Controller is accessed through the asynchronous mode the rising edge of sysace_epc_rd_n and sysace_epc_wr_n signals are used to control the read and the write operations respectively See the Reference Documents section for more information on OPB SYSACE
Design Constraints
Timing Constraints
Timing constraints must be placed on the system clock and the peripheral clock setting the frequency to meet the bus timing requirements An example is shown in Figure 8
Discontinued IP
ust 10 2007 wwwxilinxcom 25ecification
F
OPB External Peripheral Controller (EPC) v100a
26
Figure 8 EPC Timing Constraints
igure Top x-ref 8
Following constraint must be placed on the system clock
TIMESPEC TS_OPB_Clk = PERIOD OPB_Clk 10 ns HIGH 50
NET OPB_Clk TNM_NET = OPB_Clk
If C_PRH_CLK_SUPPORT=1 then the following constraint must be placed on the peripheral clock
TIMESPEC TS_PRH_Clk = PERIOD PRH_Clk 20 ns HIGH 50
NET PRH_Clk TNM_NET = PRH_Clk
DS325_08_071406
Design Implementation
Timing Diagrams
The timing diagrams in the figures below show various OPB transactions and the resulting access cycles on the peripheral interface Timing diagrams are not shown for all possible combinations of generics and the resulting access cycles However the timing diagrams shown are sufficient for the basic understanding of various access cycles supported by the OPB EPC
Figure 9 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 9
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
DS325_09_071206
8
4000000
004
04
Figure 10 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 10
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
04000000
20000004
8
00000000
004
04DS325_10_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 11 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 11
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000000
F
00010203
000 001 002 003
00 01 02 03DS325_11_071206
Figure 12 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 12
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
20000000
F
0000000000000000
000 001 002 003
00 01 02 03DS325_12_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 27ecification
OPB External Peripheral Controller (EPC) v100a
28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 29ecification
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
F
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 7 CY7C67300 USB Controller connection to OPB EPC in asynchronous mode
igure Top x-ref 7
SysACE_mpd_I[015]SysACE_mpd_O[015]SysACE_mpd_T[015]
SysACE_mpweSysACE_mpoe
SysACE_MPA[06]
SysACE_CEN
OPB SYS ACE Cntlr[150][150][150]
[60]
PRH_RstPRH_Rdy
PRH_CS_n
PRH_Data_I[015]PRH_Data_O[015]PRH_Data_T[015]
PRH_ADSPRH_RRNW
PRH_BurstPRH_Rd_nPRH_Wr_n
PRH_Addr[01]
OPB EPC
VCC
Ext
erna
l US
B P
orts
P
ort 1
A 1
B 2
AnCS
nRD
nWR
[D15D0]
[A1A0]
INT
CompactFLASH
TQFP144 SYSTEMACE
System ACE CompactFlash Controller
Ext
erna
l Glu
e Lo
gic
OPBINTC
US
B C
Y7C
6730
0
PP
C
OP
B B
us
FPGA
DS325_07_071406
Sysace_epc_data[150]
HPI interface
Sysace_epc_rd_n
Sysace_epc_wr_n
Sysace_epc_a[10]
DM1B
DP1B
DM2A
DP2A
DM1A
DP1A
External Glue Logic
In the interface diagram shown in Figure 7 the OPB EPC as well as the OPB SYSACE share the interface for data address and control lines on the board This requires external multiplex logic to be placed outside of IP cores in the FPGA The OPB EPC control signals PRH_RD_n and PRH_WR_n are muxed with the MEM_CEN and MEM_WEN signals of the OPB SYSACE When CY7C67300 USB Controller is accessed through the asynchronous mode the rising edge of sysace_epc_rd_n and sysace_epc_wr_n signals are used to control the read and the write operations respectively See the Reference Documents section for more information on OPB SYSACE
Design Constraints
Timing Constraints
Timing constraints must be placed on the system clock and the peripheral clock setting the frequency to meet the bus timing requirements An example is shown in Figure 8
Discontinued IP
ust 10 2007 wwwxilinxcom 25ecification
F
OPB External Peripheral Controller (EPC) v100a
26
Figure 8 EPC Timing Constraints
igure Top x-ref 8
Following constraint must be placed on the system clock
TIMESPEC TS_OPB_Clk = PERIOD OPB_Clk 10 ns HIGH 50
NET OPB_Clk TNM_NET = OPB_Clk
If C_PRH_CLK_SUPPORT=1 then the following constraint must be placed on the peripheral clock
TIMESPEC TS_PRH_Clk = PERIOD PRH_Clk 20 ns HIGH 50
NET PRH_Clk TNM_NET = PRH_Clk
DS325_08_071406
Design Implementation
Timing Diagrams
The timing diagrams in the figures below show various OPB transactions and the resulting access cycles on the peripheral interface Timing diagrams are not shown for all possible combinations of generics and the resulting access cycles However the timing diagrams shown are sufficient for the basic understanding of various access cycles supported by the OPB EPC
Figure 9 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 9
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
DS325_09_071206
8
4000000
004
04
Figure 10 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 10
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
04000000
20000004
8
00000000
004
04DS325_10_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 11 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 11
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000000
F
00010203
000 001 002 003
00 01 02 03DS325_11_071206
Figure 12 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 12
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
20000000
F
0000000000000000
000 001 002 003
00 01 02 03DS325_12_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 27ecification
OPB External Peripheral Controller (EPC) v100a
28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 29ecification
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
F
OPB External Peripheral Controller (EPC) v100a
26
Figure 8 EPC Timing Constraints
igure Top x-ref 8
Following constraint must be placed on the system clock
TIMESPEC TS_OPB_Clk = PERIOD OPB_Clk 10 ns HIGH 50
NET OPB_Clk TNM_NET = OPB_Clk
If C_PRH_CLK_SUPPORT=1 then the following constraint must be placed on the peripheral clock
TIMESPEC TS_PRH_Clk = PERIOD PRH_Clk 20 ns HIGH 50
NET PRH_Clk TNM_NET = PRH_Clk
DS325_08_071406
Design Implementation
Timing Diagrams
The timing diagrams in the figures below show various OPB transactions and the resulting access cycles on the peripheral interface Timing diagrams are not shown for all possible combinations of generics and the resulting access cycles However the timing diagrams shown are sufficient for the basic understanding of various access cycles supported by the OPB EPC
Figure 9 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 9
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
DS325_09_071206
8
4000000
004
04
Figure 10 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 10
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
04000000
20000004
8
00000000
004
04DS325_10_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 11 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 11
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000000
F
00010203
000 001 002 003
00 01 02 03DS325_11_071206
Figure 12 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 12
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
20000000
F
0000000000000000
000 001 002 003
00 01 02 03DS325_12_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 27ecification
OPB External Peripheral Controller (EPC) v100a
28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 29ecification
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 11 Asynchronous Write When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 11
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000000
F
00010203
000 001 002 003
00 01 02 03DS325_11_071206
Figure 12 Asynchronous Read When Bus is not Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 12
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_BE
PRH_ADS
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
20000000
F
0000000000000000
000 001 002 003
00 01 02 03DS325_12_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 27ecification
OPB External Peripheral Controller (EPC) v100a
28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 29ecification
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
28
Figure 13 Asynchronous Write When Bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 13
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20000001
2
01010000
001
001 010DS325_13_071206
Figure 14 Asynchronous Read When bus is Multiplexed and Data Width Matching is Disabled
Figure Top x-ref 14
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
20000001
2
0000000001010000
001
001 010DS325_14_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 29ecification
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 15 Asynchronous Write to Memory When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 15
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_RDY
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
20000000
F
00010203
000 001 002 003
000 000 001 010 002 020 003 030DS325_15_071206
Figure 16 Asynchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 16
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
20000000
F
00000000
000 001 002 003
000 000 001 010 002 002 003 030DS325_16_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 29ecification
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
30
Figure 17 Asynchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 17
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000030
F
00010203
030
030 000 010 020 030DS325_17_071206
Figure 18 Asynchronous Read to FIFO When bus is Multiplexed and Data Width Matching is Enabled
Figure Top x-ref 18
Cycles
OPB_Cl
Opb_Select
Opb_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rd_n
PRH_Wr_n
PRH_Rdy
PRH_Dat
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000030
F
0000000
030
030 000 010 020 030DS325_18_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 19 Synchronous Write when Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 19
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
04050607
004
04DS325_19_071206
Figure 20 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13
20000004
F
00000000 04000000
004
04DS325_20_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 31ecification
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
32
Figure 21 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 21
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
04050607
004 005 006 007 004
04 05 06 07DS325_21_071206
Figure 22 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 22
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20000004
F
0000000004050607
004 005 006 007 004
04 05 06 07DS325_22_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 23 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 23
Cycles
OPB_Cl
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Dat
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
04050607
004
004 040DS325_23_071206
Figure 24 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 24
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
20000004
F
0000000004000000
004
004 040DS325_24_071206
Discontinued IP
ust 10 2007 wwwxilinxcom 33ecification
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
34
Figure 25 Synchronous Write to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 25
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
04050607
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_25_071206
Figure 26 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 26
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
20000004
F
0000000004050607
004 005 006 007 004
004040
005050
006060
007070 DS325_26_071206
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 27 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 27
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
04050607
030
030 040 050 060 070DS325_27_071306
Figure 28 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 28
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
20000030
F
0000000004050607
030
030 040 050 060 070DS325_28_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 35ecification
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
36
Figure 29 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 29
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
20000004
F
04050607
004
04DS325_29_071306
Figure 30 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 30
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0000000020000004
F
000000000000000004000000
004
04DS325_30_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 31 Synchronous Write When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 31
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
20000004
F
04050607
004 005 006 007
04 05 06 07DS325_31_071306
Figure 32 Synchronous Read When Bus is Not Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 32
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
20000004
F
0000000000000000
004 005 006 007 004
04 05 06 07DS325_32_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 37ecification
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
38
Figure 33 Synchronous Write When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 33
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
04050607
004
004 040DS325_33_071306
Figure 34 Synchronous Read When Bus is Multiplexed and Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 34
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_BE
OPB_DBus
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
20000004
F
0000000000000000
004
004 040DS325_34_071306
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Figure 35 Synchronous Write to Memory when Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 35
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 1112131415 16171819 20 2122232425 2726 282930 313233343536373839 40414243 44454647484950 515253545556 57
20000004
04050607
F
004 005 006 007
004 040 005 050 006 060 007 070DS325_35_071306
Figure 36 Synchronous Read to Memory When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 36
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_data
0 1 2 3 4 5 6 7 8 9 10 111213 141516 17 1819 20 2122 23 2425 26 2728 29 30 3132 33 34 35363738 39 4041 4243 44 45 4647 484950 5152 53 54 5556 57
20000004
0000000000000000
F
004 005 006 007 004
004 040 005 050 006 060 007 070DS325_36_071306
Discontinued IP
ust 10 2007 wwwxilinxcom 39ecification
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
40
Figure 37 Synchronous Write to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 37
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
04050607
F
030
030 040 050 060 070DS325_37_071306
Figure 38 Synchronous Read to FIFO When Bus is Multiplexed and Data Width Matching is Enabled (C_PRH_CLK_SUPPORT = 1)
Figure Top x-ref 38
Cycles
OPB_Clk
OPB_Select
OPB_RNW
OPB_ABus
OPB_DBus
OPB_BE
Sln_xferAck
PRH_Clk
PRH_CS_n
PRH_ADS
PRH_Addr
PRH_BE
PRH_RNW
PRH_Burst
PRH_Rdy
PRH_Data
00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
20000030
0000000000000000
F
030
030 040 050 060 070DS325_38_071306
Target Technology
The intended target technology is Spartan-3 Virtex-II Virtex-II Pro Virtex-4 and Virtex-5 family FPGAs
Device Utilization and Performance Benchmarks
Since the OPB EPC module will be used with other design modules in the FPGA the utilization and timing numbers reported in this section are estimates When the OPB EPC module is combined with other designs the utilization of FPGA resources and timing of the OPB EPC design will vary from the
Discontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
results reported here The OPB EPC resource utilization for various parameter combinations measured with Virtex-4 (XC4VLX80-11-FF1148) as the target device are detailed in Table 6
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
s
1 0 0 3 32 0 0 0 127 59 175 155
1 0 1 12 32 1 0 0 125 42 147 162
1 0 0 12 32 0 0 0 134 68 187 156
1 0 0 12 16 0 0 0 108 68 170 149
1 0 0 12 8 0 0 0 112 68 177 151
1 0 0 12 32 0 0 1 156 110 235 158
1(1) 0 0 12 16 0 0 1 155 145 242 158
1(1) 0 0 12 8 0 0 1 164 145 253 148
1(1) 0 0 12 32 0 1 0 144 108 245 150
1(1) 0 0 12 32 1 0 0 122 36 147 173
1(1) 0 0 12 16 1 0 0 99 34 141 168
1(1) 0 0 12 8 1 0 0 96 33 138 176
1(1) 0 0 12 32 1 0 1 121 79 162 158
1(1) 0 0 12 16 1 0 1 116 115 173 149
1(1) 0 0 12 8 1 0 1 137 114 218 147
1(1) 0 0 12 32 1 1 0 124 86 185 145
2(1) 0 0 1212 3232 00 00 00 164 75 247 148
2(1) 0 0 1212 3232 01 00 00 225 138 293 143
2(1) 0 0 1212 3232 11 00 00 119 34 157 150
3(1) 0 0 121212 323232 000 000 000 156 81 228 159
3(1) 0 0 121212 323232 011 000 000 230 133 333 156
3(1) 0 0 121212 323232 100 000 000 217 135 299 145
3(1) 0 0 121212 323232 111 000 000 122 35 159 152
4(1) 0 0 12121212 1681632 0000 0000 0111 254 173 432 146
Discontinued IP
ust 10 2007 wwwxilinxcom 41ecification
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
42
The OPB EPC resource utilization measured with Virtex-5 (XC5VLX85-2-FF676) as the target device is shown in the following Table 7
4(1) 0 0 12121212 881616 0000 0000 0101 250 169 406 146
4(1) 0 0 12121212 161688 1111 0000 1010 205 133 324 152
4(1) 0 0 12121212 3216816 1111 0000 1110 228 148 364 147
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Table 6 Performance and Resource Utilization Benchmarks on Virtex-4 (XC4VLX80-11-FF1148) (Contd)
Parameter ValuesDevice
Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
4-in
pu
t L
UT
sDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Table 7 Performance and Resource Utilization Benchmarks on Virtex-5 (XC5VLX85-2-FF676)
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
Ts
1 0 0 3 32 0 0 0 0 55 170 200
1 0 1 12 32 1 0 0 0 46 137 205
1 0 0 12 32 0 0 0 0 64 178 201
1 0 0 12 16 0 0 0 0 65 160 205
1 0 0 12 8 0 0 0 0 69 160 200
1 0 0 12 32 0 0 1 0 114 235 204
1(1) 0 0 12 16 0 0 1 0 147 241 215
1(1) 0 0 12 8 0 0 1 0 148 239 202
1(1) 0 0 12 32 0 1 0 0 110 227 200
1(1) 0 0 12 32 1 0 0 0 30 129 218
1(1) 0 0 12 16 1 0 0 0 30 109 211
1(1) 0 0 12 8 1 0 0 0 31 110 202
1(1) 0 0 12 32 1 0 1 0 86 174 225
1(1) 0 0 12 16 1 0 1 0 126 182 208
1(1) 0 0 12 8 1 0 1 0 124 181 221
1(1) 0 0 12 32 1 1 0 0 81 166 208
2(1) 0 0 1212 3232 00 00 00 0 73 180 206
2(1) 0 0 1212 3232 01 00 00 0 127 221 201
2(1) 0 0 1212 3232 11 00 00 0 34 141 202
3(1) 0 0 121212 323232 000 000 000 0 83 200 201
3(1) 0 0 121212 323232 011 000 000 0 143 235 204
3(1) 0 0 121212 323232 100 000 000 0 135 232 204
3(1) 0 0 121212 323232 111 000 000 0 44 148 200
4(1) 0 0 12121212 1681632 0000 0000 0111 0 177 351 201
4(1) 0 0 12121212 881616 0000 0000 0101 0 190 323 200
Discontinued IP
ust 10 2007 wwwxilinxcom 43ecification
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
44
4(1) 0 0 12121212 161688 1111 0000 1010 0 158 291 203
4(1) 0 0 12121212 3216816 1111 0000 1110 0 158 323 204
Notes 1 The bus multiplex timing parameters and asynchronous timing parameters are set to typical values for all
devices The values used for various timing parameters are as follows- C_PRHx_ADDR_TSU = 6ns
- C_PRHx_ADDR_TH = 6ns
- C_PRHx_ADS_WIDTH = 10ns
- C_PRHx_CSN_TSU = 6ns
- C_PRHx_CSN_TH = 6ns
- C_PRHx_WRN_WIDTH = 15ns
- C_PRHx_WR_CYCLE = 30ns
- C_PRHx_DATA_TSU = 10ns
- C_PRHx_DATA_TH = 5ns
- C_PRHx_RDN_WIDTH = 15ns
- C_PRHx_RD_CYCLE = 30ns
- C_PRHx_DATA_TOUT = 5ns
- C_PRHx_DATA_TINV = 10ns
- C_PRHx_RDY_TOUT = 10ns
- C_PRHx_RDY_WIDTH = 50ns
Parameter Values Device Resources
f MA
X (M
Hz)
C_N
UM
_PE
RIP
HE
RA
LS
C_P
RH
_BU
RS
T_S
UP
PO
RT
C_P
RH
_CL
K_S
UP
PO
RT
C_P
RH
x_A
WID
TH
C_P
RH
x_D
WID
TH
C_P
RH
x_S
YN
C
C_P
RH
x_B
US
_MU
LTIP
LE
X
C_P
RH
x_D
WID
TH
_MA
TC
H
Slic
es
Slic
e F
lip-
Flo
ps
LU
TsDiscontinued IP
wwwxilinxcom DS325 August 10 2007Product Specification
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice
OPB External Peripheral Controller (EPC) v100a
DS325 AugProduct Sp
Reference DocumentsThe following documents contain information that may be required in understanding the OPB EPC reference design
bull OPB SYSACE Interface Controller v1_00_c Data Sheet Xilinx
bull 10100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet SMSC
bull EZ-Host(TM) Programmable Embedded USB HostPeripheral Controller CY7C67300 Data Sheet Cypress Semiconductor
bull On-Chip Peripheral Bus Architectural Specifications (v20) IBM
bull DS404 OPB IPIF Product Specification (v301a) Xilinx
Revision History
Date Version Revision
021406 10 Initial Xilinx release
061506 11 Updated for Virtex-5 support
071406 12 Converted to new DS template updated images to graphic standards
071806 13 Updated the device utilization table for Virtex-4 and Virtex-5
081007 14Updated the description regarding the level of OPB EPC signals in the OPB EPC IO Signal Description table
Discontinued IP
ust 10 2007 wwwxilinxcom 45ecification
ltlt ASCII85EncodePages false AllowTransparency false AutoPositionEPSFiles true AutoRotatePages All Binding Left CalGrayProfile (Dot Gain 20) CalRGBProfile (sRGB IEC61966-21) CalCMYKProfile (US Web Coated 050SWOP051 v2) sRGBProfile (sRGB IEC61966-21) CannotEmbedFontPolicy Warning CompatibilityLevel 14 CompressObjects Tags CompressPages true ConvertImagesToIndexed true PassThroughJPEGImages true CreateJDFFile false CreateJobTicket false DefaultRenderingIntent Default DetectBlends true DetectCurves 00000 ColorConversionStrategy LeaveColorUnchanged DoThumbnails false EmbedAllFonts true EmbedOpenType false ParseICCProfilesInComments true EmbedJobOptions true DSCReportingLevel 0 EmitDSCWarnings false EndPage -1 ImageMemory 1048576 LockDistillerParams false MaxSubsetPct 100 Optimize true OPM 1 ParseDSCComments true ParseDSCCommentsForDocInfo true PreserveCopyPage true PreserveDICMYKValues true PreserveEPSInfo true PreserveFlatness true PreserveHalftoneInfo false PreserveOPIComments false PreserveOverprintSettings true StartPage 1 SubsetFonts true TransferFunctionInfo Apply UCRandBGInfo Preserve UsePrologue false ColorSettingsFile () AlwaysEmbed [ true ] NeverEmbed [ true ] AntiAliasColorImages false CropColorImages true ColorImageMinResolution 300 ColorImageMinResolutionPolicy OK DownsampleColorImages true ColorImageDownsampleType Bicubic ColorImageResolution 300 ColorImageDepth -1 ColorImageMinDownsampleDepth 1 ColorImageDownsampleThreshold 150000 EncodeColorImages true ColorImageFilter DCTEncode AutoFilterColorImages true ColorImageAutoFilterStrategy JPEG ColorACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt ColorImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000ColorACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000ColorImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasGrayImages false CropGrayImages true GrayImageMinResolution 300 GrayImageMinResolutionPolicy OK DownsampleGrayImages true GrayImageDownsampleType Bicubic GrayImageResolution 300 GrayImageDepth -1 GrayImageMinDownsampleDepth 2 GrayImageDownsampleThreshold 150000 EncodeGrayImages true GrayImageFilter DCTEncode AutoFilterGrayImages true GrayImageAutoFilterStrategy JPEG GrayACSImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt GrayImageDict ltlt QFactor 015 HSamples [1 1 1 1] VSamples [1 1 1 1] gtgt JPEG2000GrayACSImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt JPEG2000GrayImageDict ltlt TileWidth 256 TileHeight 256 Quality 30 gtgt AntiAliasMonoImages false CropMonoImages true MonoImageMinResolution 1200 MonoImageMinResolutionPolicy OK DownsampleMonoImages true MonoImageDownsampleType Bicubic MonoImageResolution 1200 MonoImageDepth -1 MonoImageDownsampleThreshold 150000 EncodeMonoImages true MonoImageFilter CCITTFaxEncode MonoImageDict ltlt K -1 gtgt AllowPSXObjects false CheckCompliance [ None ] PDFX1aCheck false PDFX3Check false PDFXCompliantPDFOnly false PDFXNoTrimBoxError true PDFXTrimBoxToMediaBoxOffset [ 000000 000000 000000 000000 ] PDFXSetBleedBoxToMediaBox true PDFXBleedBoxToTrimBoxOffset [ 000000 000000 000000 000000 ] PDFXOutputIntentProfile () PDFXOutputConditionIdentifier () PDFXOutputCondition () PDFXRegistryName () PDFXTrapped False Description ltlt CHS ltFEFF4f7f75288fd94e9b8bbe5b9a521b5efa7684002000500044004600206587686353ef901a8fc7684c976262535370673a548c002000700072006f006f00660065007200208fdb884c9ad88d2891cf62535370300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c676562535f00521b5efa768400200050004400460020658768633002gt CHT ltFEFF4f7f752890194e9b8a2d7f6e5efa7acb7684002000410064006f006200650020005000440046002065874ef653ef5728684c9762537088686a5f548c002000700072006f006f00660065007200204e0a73725f979ad854c18cea7684521753706548679c300260a853ef4ee54f7f75280020004100630072006f0062006100740020548c002000410064006f00620065002000520065006100640065007200200035002e003000204ee553ca66f49ad87248672c4f86958b555f5df25efa7acb76840020005000440046002065874ef63002gt DAN ltFEFF004200720075006700200069006e0064007300740069006c006c0069006e006700650072006e0065002000740069006c0020006100740020006f007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e007400650072002000740069006c0020006b00760061006c00690074006500740073007500640073006b007200690076006e0069006e006700200065006c006c006500720020006b006f007200720065006b007400750072006c00e60073006e0069006e0067002e0020004400650020006f007000720065007400740065006400650020005000440046002d0064006f006b0075006d0065006e0074006500720020006b0061006e002000e50062006e00650073002000690020004100630072006f00620061007400200065006c006c006500720020004100630072006f006200610074002000520065006100640065007200200035002e00300020006f00670020006e0079006500720065002egt DEU ltFEFF00560065007200770065006e00640065006e0020005300690065002000640069006500730065002000450069006e007300740065006c006c0075006e00670065006e0020007a0075006d002000450072007300740065006c006c0065006e00200076006f006e002000410064006f006200650020005000440046002d0044006f006b0075006d0065006e00740065006e002c00200076006f006e002000640065006e0065006e002000530069006500200068006f00630068007700650072007400690067006500200044007200750063006b006500200061007500660020004400650073006b0074006f0070002d0044007200750063006b00650072006e00200075006e0064002000500072006f006f0066002d00470065007200e400740065006e002000650072007a0065007500670065006e0020006d00f60063006800740065006e002e002000450072007300740065006c006c007400650020005000440046002d0044006f006b0075006d0065006e007400650020006b00f6006e006e0065006e0020006d006900740020004100630072006f00620061007400200075006e0064002000410064006f00620065002000520065006100640065007200200035002e00300020006f0064006500720020006800f600680065007200200067006500f600660066006e00650074002000770065007200640065006e002egt ESP ltFEFF005500740069006c0069006300650020006500730074006100200063006f006e0066006900670075007200610063006900f3006e0020007000610072006100200063007200650061007200200064006f00630075006d0065006e0074006f0073002000640065002000410064006f0062006500200050004400460020007000610072006100200063006f006e00730065006700750069007200200069006d0070007200650073006900f3006e002000640065002000630061006c006900640061006400200065006e00200069006d0070007200650073006f0072006100730020006400650020006500730063007200690074006f00720069006f00200079002000680065007200720061006d00690065006e00740061007300200064006500200063006f00720072006500630063006900f3006e002e002000530065002000700075006500640065006e00200061006200720069007200200064006f00630075006d0065006e0074006f00730020005000440046002000630072006500610064006f007300200063006f006e0020004100630072006f006200610074002c002000410064006f00620065002000520065006100640065007200200035002e003000200079002000760065007200730069006f006e0065007300200070006f00730074006500720069006f007200650073002egt FRA ltFEFF005500740069006c006900730065007a00200063006500730020006f007000740069006f006e00730020006100660069006e00200064006500200063007200e900650072002000640065007300200064006f00630075006d0065006e00740073002000410064006f00620065002000500044004600200070006f007500720020006400650073002000e90070007200650075007600650073002000650074002000640065007300200069006d007000720065007300730069006f006e00730020006400650020006800610075007400650020007100750061006c0069007400e90020007300750072002000640065007300200069006d007000720069006d0061006e0074006500730020006400650020006200750072006500610075002e0020004c0065007300200064006f00630075006d0065006e00740073002000500044004600200063007200e900e90073002000700065007500760065006e0074002000ea0074007200650020006f007500760065007200740073002000640061006e00730020004100630072006f006200610074002c002000610069006e00730069002000710075002700410064006f00620065002000520065006100640065007200200035002e0030002000650074002000760065007200730069006f006e007300200075006c007400e90072006900650075007200650073002egt ITA ltFEFF005500740069006c0069007a007a006100720065002000710075006500730074006500200069006d0070006f007300740061007a0069006f006e00690020007000650072002000630072006500610072006500200064006f00630075006d0065006e00740069002000410064006f006200650020005000440046002000700065007200200075006e00610020007300740061006d007000610020006400690020007100750061006c0069007400e00020007300750020007300740061006d00700061006e0074006900200065002000700072006f006f0066006500720020006400650073006b0074006f0070002e0020004900200064006f00630075006d0065006e007400690020005000440046002000630072006500610074006900200070006f00730073006f006e006f0020006500730073006500720065002000610070006500720074006900200063006f006e0020004100630072006f00620061007400200065002000410064006f00620065002000520065006100640065007200200035002e003000200065002000760065007200730069006f006e006900200073007500630063006500730073006900760065002egt JPN ltFEFF9ad854c18cea51fa529b7528002000410064006f0062006500200050004400460020658766f8306e4f5c6210306b4f7f75283057307e30593002537052376642306e753b8cea3092670059279650306b4fdd306430533068304c3067304d307e3059300230c730b930af30c830c330d730d730ea30f330bf3067306e53705237307e305f306f30d730eb30fc30d57528306b9069305730663044307e305930023053306e8a2d5b9a30674f5c62103055308c305f0020005000440046002030d530a130a430eb306f3001004100630072006f0062006100740020304a30883073002000410064006f00620065002000520065006100640065007200200035002e003000204ee5964d3067958b304f30533068304c3067304d307e30593002gt KOR ltFEFFc7740020c124c815c7440020c0acc6a9d558c5ec0020b370c2a4d06cd0d10020d504b9b0d1300020bc0f0020ad50c815ae30c5d0c11c0020ace0d488c9c8b85c0020c778c1c4d560002000410064006f0062006500200050004400460020bb38c11cb97c0020c791c131d569b2c8b2e4002e0020c774b807ac8c0020c791c131b41c00200050004400460020bb38c11cb2940020004100630072006f0062006100740020bc0f002000410064006f00620065002000520065006100640065007200200035002e00300020c774c0c1c5d0c11c0020c5f40020c2180020c788c2b5b2c8b2e4002egt NLD (Gebruik deze instellingen om Adobe PDF-documenten te maken voor kwaliteitsafdrukken op desktopprinters en proofers De gemaakte PDF-documenten kunnen worden geopend met Acrobat en Adobe Reader 50 en hoger) NOR ltFEFF004200720075006b00200064006900730073006500200069006e006e007300740069006c006c0069006e00670065006e0065002000740069006c002000e50020006f0070007000720065007400740065002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740065007200200066006f00720020007500740073006b00720069006600740020006100760020006800f800790020006b00760061006c00690074006500740020007000e500200062006f007200640073006b0072006900760065007200200065006c006c00650072002000700072006f006f006600650072002e0020005000440046002d0064006f006b0075006d0065006e00740065006e00650020006b0061006e002000e50070006e00650073002000690020004100630072006f00620061007400200065006c006c00650072002000410064006f00620065002000520065006100640065007200200035002e003000200065006c006c00650072002000730065006e006500720065002egt PTB ltFEFF005500740069006c0069007a006500200065007300730061007300200063006f006e00660069006700750072006100e700f50065007300200064006500200066006f0072006d00610020006100200063007200690061007200200064006f00630075006d0065006e0074006f0073002000410064006f0062006500200050004400460020007000610072006100200069006d0070007200650073007300f5006500730020006400650020007100750061006c0069006400610064006500200065006d00200069006d00700072006500730073006f0072006100730020006400650073006b0074006f00700020006500200064006900730070006f00730069007400690076006f0073002000640065002000700072006f00760061002e0020004f007300200064006f00630075006d0065006e0074006f00730020005000440046002000630072006900610064006f007300200070006f00640065006d0020007300650072002000610062006500720074006f007300200063006f006d0020006f0020004100630072006f006200610074002000650020006f002000410064006f00620065002000520065006100640065007200200035002e0030002000650020007600650072007300f50065007300200070006f00730074006500720069006f007200650073002egt SUO ltFEFF004b00e40079007400e40020006e00e40069007400e4002000610073006500740075006b007300690061002c0020006b0075006e0020006c0075006f0074002000410064006f0062006500200050004400460020002d0064006f006b0075006d0065006e007400740065006a00610020006c0061006100640075006b006100730074006100200074007900f6007000f60079007400e400740075006c006f0073007400750073007400610020006a00610020007600650064006f007300740075007300740061002000760061007200740065006e002e00200020004c0075006f0064007500740020005000440046002d0064006f006b0075006d0065006e00740069007400200076006f0069006400610061006e0020006100760061007400610020004100630072006f0062006100740069006c006c00610020006a0061002000410064006f00620065002000520065006100640065007200200035002e0030003a006c006c00610020006a006100200075007500640065006d006d0069006c006c0061002egt SVE ltFEFF0041006e007600e4006e00640020006400650020006800e4007200200069006e0073007400e4006c006c006e0069006e006700610072006e00610020006f006d002000640075002000760069006c006c00200073006b006100700061002000410064006f006200650020005000440046002d0064006f006b0075006d0065006e00740020006600f600720020006b00760061006c00690074006500740073007500740073006b0072006900660074006500720020007000e5002000760061006e006c00690067006100200073006b0072006900760061007200650020006f006300680020006600f600720020006b006f007200720065006b007400750072002e002000200053006b006100700061006400650020005000440046002d0064006f006b0075006d0065006e00740020006b0061006e002000f600700070006e00610073002000690020004100630072006f0062006100740020006f00630068002000410064006f00620065002000520065006100640065007200200035002e00300020006f00630068002000730065006e006100720065002egt ENU (Use these settings to create Adobe PDF documents for quality printing on desktop printers and proofers Created PDF documents can be opened with Acrobat and Adobe Reader 50 and later) gtgt Namespace [ (Adobe) (Common) (10) ] OtherNamespaces [ ltlt AsReaderSpreads false CropImagesToFrames true ErrorControl WarnAndContinue FlattenerIgnoreSpreadOverrides false IncludeGuidesGrids false IncludeNonPrinting false IncludeSlug false Namespace [ (Adobe) (InDesign) (40) ] OmitPlacedBitmaps false OmitPlacedEPS false OmitPlacedPDF false SimulateOverprint Legacy gtgt ltlt AddBleedMarks false AddColorBars false AddCropMarks false AddPageInfo false AddRegMarks false ConvertColors NoConversion DestinationProfileName () DestinationProfileSelector NA Downsample16BitImages true FlattenerPreset ltlt PresetSelector MediumResolution gtgt FormElements false GenerateStructure true IncludeBookmarks false IncludeHyperlinks false IncludeInteractive false IncludeLayers false IncludeProfiles true MultimediaHandling UseObjectSettings Namespace [ (Adobe) (CreativeSuite) (20) ] PDFXOutputIntentProfileSelector NA PreserveEditing true UntaggedCMYKHandling LeaveUntagged UntaggedRGBHandling LeaveUntagged UseDocumentBleed false gtgt ]gtgt setdistillerparamsltlt HWResolution [2400 2400] PageSize [612000 792000]gtgt setpagedevice