OpenMPL: An Open Source Layout Decomposeryibolin.com/publications/papers/DFM_ASICON2019_Li.slides.pdf · 1940 1950 1960 1970 1980 1990 2000 2010 2020 10,000,000,000 1 10 100 1,000

OpenMPL:An Open Source Layout Decomposer

Wei Li1, Yuzhe Ma1, Qi Sun1, Yibo Lin2, Iris Hui-Ru Jiang3,Bei Yu1, David Z. Pan4

1The Chinese University of Hong Kong, 2Peking University,3National Taiwan University, 4University of Texas at Austin

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1940 1950 1960 1970 1980 1990 2000 2010 2020

10,000,000,000

110

1001,000

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Intel Microprocessors

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40048086

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486 Pentium

Pentium IIPentium 4

Core 2 Duo Core i7

Doubles every 2.1 yrs

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AI / Cu / W wires

Planar CMOSLE

Patterning

TransistorsCo

mpl

exity

Interconnect

2005 2010 2015 2020 2025

[Courtesy ARM]

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AI / Cu / W wires

Planar CMOSLE

10 nm 7 nm 5 nm 3 nm

FinFETLELE

W LI

Patterning

TransistorsCo

mpl

exity

Interconnect

2005 2010 2015 2020 2025

[Courtesy ARM]

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AI / Cu / W wires

Planar CMOSLE

HNW

VNW

eNVM

LELELE

SADP

SAQP

EUV LELE


EUV

EUV EBL

EUV DSA

Cu Doping

3D IC

Opto Connect

Graphene

CNT

FinFETLELE

W LI

Patterning

TransistorsCo

mpl

exity

Interconnect

2005 2010 2015 2020 2025

[Courtesy ARM]

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AI / Cu / W wires

Planar CMOSLE

HNW

VNW

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Cu Doping

3D IC

Opto Connect

Graphene

CNT

FinFETW LI

EUV

EUV EBL

EUV DSA

LELELELELE

SADP

SAQP

EUV LELE

Patterning

TransistorsCo

mpl

exity

Interconnect

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[Courtesy ARM]

Multiple Patterning Litho (MPL)

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Multiple Patterning Layout Decomposition

a

b

a

b cd

(a) Original layout

a

b

a

b cd

(b) TPL layout with conflicts

a

b

a

d2

b c1d1

c2

(c) Coloring on layout graph

a

bd

c2

c1

(d) Final decomposed layout

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a

b

a

b cd

(a) Original layout

a

b

a

b cd

(b) TPL layout with conflicts

a

b

a

d2

b c1d1

c2


a

bd

c2

c1


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a

b

a

b cd

(a) Original layout

a

b

a

d2

b c1d1

c2

(b) Layout graph

a

b

a

d2

b c1d1

c2


a

bd

c2

c1


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a

b

a

b cd

(a) Original layout

a

b

a

d2

b c1d1

c2

(b) Layout graph

a

b

a

d2

b c1d1

c2


a

bd

c2

c1


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a

b

a

b cd

(a) Original layout

a

b

a

d2

b c1d1

c2

(b) Layout graph

a

b

a

d2

b c1d1

c2


a

bd

c2

c1


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Mathematical Formulation

I Some conflicts can be solved by Stitch Insertion.

f

b

a

c

d2

d1e2

e1

k Pattern Layout Decomposition

minx

∑eij∈CE

cij + α×∑

eij∈SEsij,

s.t. cij = {xi == xj}, ∀eij ∈ CE,sij = {xi 6= xj}, ∀eij ∈ SE,xi ∈ {0, 1, ..., k}, ∀i ∈ V.

I xi is a variable for the k available colors of the pattern vi.I cij is a binary variable representing conflict edge eij ∈ CE.I sij stands for stitch edge eij ∈ SE.

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Research Trend for Layout DecompositionAn UNDERESTIMATION from Google Scholar

4

75

1012

1112

9

2 10

2

4

6

8

10

12

14

2010 2011 2012 2013 2014 2015 2016 2017 2018 2019

# of Researches Papers

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Challenges in Layout Decomposition ResearchComplicated workflow and huge development overhead

I GDSII parsing and writingI Layout graph construction and stitch insertionI Graph simplification and core solvers

Lack of reusable code and repeatability

I Need to develop from scratchI Only share executable binaries instead of source code

No consistent framework for fair comparison

I Different implementations to the same algorithmI Hard to make detailed comparison in depth

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6 / 21







6 / 21

OpenMPL 2.0: Open-Source Layout Decomposition Tool

https://github.com/limbo018/OpenMPL

7 / 21

https://github.com/limbo018/OpenMPL

Workflow

Layout Graph ConstructionIndependent Component Computation

Input Layout

Stitch Candidate Generation

Decomposition Solver

Graph Simplification

Simplified Graph RecoveryOutput Masks

Merge 4-Cliques

Hide Small Degree

Biconnected Component

Decomposition SDP

ILP

Backtracking

Dancing Links

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Design Principles

I Decoupled design stages

I Graphs for communications amongkernel stages

I Efficiency and generality for differentmask data

Layout Graph ConstructionIndependent Component Computation

Input Layout

Stitch Candidate Generation

Decomposition Solver

Graph Simplification

Simplified Graph RecoveryOutput Masks

Merge 4-Cliques

Hide Small Degree

Biconnected Component

Decomposition SDP

ILP

Backtracking

Dancing Links

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Extensible API to Incorporate New Algorithms

I Create a solver

// A solver classclass InstantColoring

: public Coloring{public:// g is a boost::graphInstantColoring(g);

protected:virtual double coloring(){

// override base function// return cost

}};

I Integrate the solver

// define a solverswitch (algorithm){

case BruteForce:solver = new BruteForce (g);

case InstantColoring:solver = new InstantColoring (g);

...}...// solve coloring(*solver)();

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Extensible API to Incorporate New Algorithms

I Create a solver

// A solver classclass InstantColoring

: public Coloring{public:// g is a boost::graphInstantColoring(g);

protected:virtual double coloring(){

// override base function// return cost

}};

I Integrate the solver

// define a solverswitch (algorithm){

case BruteForce:solver = new BruteForce (g);

case InstantColoring:solver = new InstantColoring (g);

...}...// solve coloring(*solver)();

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We implement several layout decomposition solvers.

I Backtracking: Use DFS algorithm to find the solutions [Yu+,ICCAD’13].

I Integer Linear Programming: Convert the problem into linear programming by binaryencoding of vertex colors [Yu+,ICCAD’11].

I Dancing Links: Treat the problem as an exact cover problem and solve it in the BFSstyle [Chang+,DAC’16].

I Semidefinite Programming: Use SDP to relax the problem and solve it in polynomialtime [Yu+,ICCAD’11].

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Layout Simplification

Reduce the graph size and therefore reduce the computation complexity.

I Level 0: No Simplification. Do not conduct any simplification.

I Level 1: Hide small degree. Temporarily remove nodes with low degree[Yu+,TCAD’15] [Lin+,SPIE’16].

I Level 2: Merge 4-Clique. Detect and merge sub-4-clique structures [Lin+,SPIE’16].

I Level 3: Biconnected component decomposition. Partition original graph intoindependent components [Kahng+,ICCAD’08].

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Additional Features

I Multithreading: Solve components inparallel.

I Stitch Insertion: Insert stitches to solvesome conflicts.

I Shape Friendly: Specify the shape(POLYGON or RECTANGLE) easily.

a e

d

f

c

b

b

c a

b’

df

e2

1

a

b

a

d2

b c1d1

c2

a

b

c

d

e

P

13 / 21

Command Line Options

Selected Options Descriptions-coloring_distance a floating point number indicating number of coloring distance in nanometer-color_num an integer indicating number of masks (colors) < 3|4 >-simplify_level an integer indicating graph simplification level < 0|1|2|3 >-path_layer an integer indicating layer for conflict edges-precolor_layer an integer indicating layer for pre-colored patterns-uncolor_layer an integer indicating layer for coloring-algo algorithm type < ILP|BACKTRACK|LP|SDP >-shape shape mode < RECTANGLE|POLYGON >-use_stitch use stitch to avoid conflict-gen_stitch generate stitch candidate-weight_stitch weight of stitch-thread_num an integer indicating maximum thread number-verbose toggle controlling screen messages-dbg_comp_id debug component id

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Experimental Settings

I Triple Patterning Lithography

I Conducted on modified ISCAS benchmarks from [Yu+,ICCAD’13]

I Coloring distance: 120nm for the first ten cases and 100nm for the last five cases.

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Experimental Results

(a) total_c1, TPLD, SDP coloring process. (b) total_c2, TPLD, SDP coloring process.

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Experimental Results – Quality

0

25

50

75

100

# co

nflic

tsBacktracking ILP SDP Dancing Links

C432

C499

C880

C1355

C1908

C2670

C3540

C5315

C6288

C7552

S148

8

S384

17

S359

32

S385

84

S158

50

050

100150200250

# st

itche

s

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Experimental Results – Runtime

C432

C499

C880

C1355

C1908

C2670

C3540

C5315

C6288

C7552

S148

8

S384

17

S359

32

S385

84

S158

5010 3

10 2

10 1

100

101

102

Runt

ime

(s)

Backtracking ILP SDP Dancing Links

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Quality and Runtime Tradeoffs

Backtracking

ILP

SDP

Dancing Links

Quality Efficiency

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ConclusionOpen-source layout decomposition framework

I Four layout decomposition solvers;

I Four graph simplification strategies;

I Multithreads, stitch insertion supported and shape frinedly.

Future Work

I Efficiency: hardware acceleration.

I Quality: post refinement.

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ConclusionOpen-source layout decomposition framework

I Four layout decomposition solvers;

I Four graph simplification strategies;

I Multithreads, stitch insertion supported and shape frinedly.

Future Work

I Efficiency: hardware acceleration.

I Quality: post refinement.

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Thank YouWei Li ([email protected])

Yuzhe Ma ([email protected])Qi Sun ([email protected])Yibo Lin ([email protected])

Iris Hui-Ru Jiang ([email protected])Bei Yu ([email protected])

David Z. Pan ([email protected])

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mailto:[email protected]







Documents

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