OpenROAD: Foundations and Realization of Open, Accessible

Design

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Webpage: theopenroadproject.org

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https://github.com/The-OpenROAD-Project/

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OpenROAD = Digital Layout Generation

• Demo of capability:DRC-clean RTL-to-GDSpush-button in foundryenablement

• Key first step in a 4-yearjourney

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https://github.com/The-OpenROAD-Project/alpha-release/blob/master/flow/docs/flow.png

Flow Demo

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Other OpenROAD Highlights

• Task 2: Cloud Infrastructure

• Task 4: Parasitic Extraction (PEX)

• Task 6: Power/Signal Integrity

• Tasks 8,9,11 (PCB): PCB Placement and Routing

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Cloud Infrastructure (Task 2 – Brown U.)Run OpenROAD Flow in a Single-Click

https://flow.theopenroadproject.org

- Public Cloudon AWS

- Browser Interface- Scalable

Infrastructure- Integration with

GitHub- Can be deployed

on-prem

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Parasitic Extraction (Task 4)

PEX model Regression Model

Parasitic resistance/capacitance

SPEF formatdesign.spef

(or RSPF file)

Design information

DEF formatdesign.def

PDKTech dataCorners

PEX is a callable functionCalling functionSTA, FP, PL, CTS, PSI

Golden PEX

Proprietary

INPUT

OUTPUT

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PEX ResultsValidation of the regression model parasitics for CMP28 PDK using a timer, experiments include comparison between:

• Arc delays of a cell• Path slacks• Pin transitions

Our Model

Num

ber o

f pat

hs

Path slack

Innovus

Num

ber o

f pat

hs

Path slack

Path slack distribution

Num

ber o

f arc

s

Error (%)

Num

ber o

f pin

s

Error (%)

Norm

alize

d re

sista

nce

Norm

alize

d ca

pacit

ance Length (um)

Length (um)

Max Rise Time Delay Error Distribution

Max Arc Delay Error Distribution

Regression fit (per-unit RC) GF14FF

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Power Integrity (T6): ML-based PDN Synthesis

Power integrity module

Placed DEFCell LEF

Package informationParasitics, C4 locations

Template-based PDN

N stitchable templatesT1, T2, …, TN

ML engineCurrent map

TN

…

T3

T1

CNN

T2

Current distribution:OpenSTA power report

IR drop map

Template definition

C4 bump

4 regions R1 – R4 with different PDN densities

R1R2

R3R4

FlowCongestion estimates

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Power Integrity Results

Width (μm)

Leng

th (μ

m)

• Evaluation of the flow:• Synthesized template-based PDN meets an 8mV static IR drop spec

Width (μm)

Leng

th (μ

m)

Testcase Technology Max IR Congestion improvement

Average number of tracks saved

Rocket Chip TSMC 16FF 6.72mV 2.39% 1,360Black Parrot TSMC 65LP 11.75mV 3.22% 2,148Vanilla Bean TSMC 65LP 8.47mV 3.02% 1,224

Ariane TSMC 65LP 11.58mV 3.31% 2,574

IR d

rop

(V)

Current map of Rocket chip Static IR map of Rocket chip

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PCB Placement & Routing Overall Flow

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• Comparative study of several placement methods and existing packages• Identified simulated annealing as a winner in terms of flexibility and performance

• Cost function: wirelength, overlap, placement & pin/net-aware routability• Routability-based placement minimizes net wire-density term• Weighting routability term yields placements with nets whose components

spread to increase net-area and reduce net wire-density• UCSD Routing (in development)

• Goal: push-button 100% routing completion• Interactions between placement and route engine• Hierarchical fine-grid rip-up and reroute router

• FreeRouting (GPLv3, https://freerouting.org/)• Routing angles: 45-degree, 90-degree and any-angle

PCB Placement & Routing Development

SA-Based placement (BM1):Cumulative airwire distance: 2784 mm

Manual placement (BM1): Cumulative airwire distance: 3640mm

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AAA: Completed work AAA: Work in progress AAA: Stretch goals• 1 Month:

• Additional validation on more PCB cases• Add 45 degree rotation support for placement• Add informative error messages• Explore global and detailed routing algorithms• Integrate UCSD placer and FreeRouting router flow in KiCad format

• 3 Months:• Implement routing algorithms in UCSD router• Identify correlations between SA-placement results and unrouted nets• Implement design rule checker in UCSD router

• 6 Months:• Thorough validation of pipeline and package development• Routability and timing-driven placement• Prototype PCB routing package for manufacturability (layout rules)• Automate tuning of P&R parameters

PCB Layout Future Plans

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WRAP-UP

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Looking Forward (Year 2 = Phase 1B)• V1.0 July 2020 must advance 20 years on EDA industry learning curve

within next 2-3 quarters• 1980’s file-based integration July 2019• 2000’s tight integration on shared incremental substrate July 2020

• Next: architecture, database, build/CI/devops, CAE/PE,• + teaching EDA SW to the OpenROAD/FOSS community

• Professionals on the team: mandatory• Industry veterans who have “done this before”

• Outreach is gaining traction – please help us accelerate it!• (e.g., “Power Users”, “Spec”, design enablement assumptions still needed

+ testcases, calibrations, contributed C++ modules, verification engines …)

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OpenROAD People to Meet This Week

Tutu and Mehdi (Michigan) Design

Advisors, Flow, Release

Abdelrahman (Brown) Cloud Infrastructure

Lukas (UCSD) Architecture and

OptimizationVidya and Jeff (Minnesota) PEX and Power Integrity

Mingyu and Lutong(UCSD) FP/Place and

Detailed Routing

Connie, James, Chester, Devon (UCSD) PCB Place and Route

The views, opinions and/or findings expressed are those of the author and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government 20

Thank You!