2 HEITER, G . L.: 'Characterization o f nonlinearities in microwave devices and systems', ZEEE Trans., 1973, MTT-21, pp. 797-805

3 RAUSCHER, C., and TUCKER, R. S.: 'A method for measuring intermodulation distortion in GaAs FETs' (in preparation)

OPTIMUM DESIGN FOR A BROADBAND MICROSTRIP BALUN

Indexing terms: Baluns, Stripline components

The letter reports calculations of Marchand balun performance which show that bandwidths approaching 5 0 : 1 (for av.s.w.1. d 2 : 1) should be achievable with overlaid microstrip structures. The bandwidth limits (2 8 : 1) reported by previous writers appear to reflect only the inaccessibility o f the true optimum to the semiempirical design methods used and the limitations o f fabrication on single-thickness card. Preliminary experi- mental results confirm the theoretical indications.

The balun design originally proposed by archa and,' and since described by various authors in coaxial2 and m i c r o ~ t r i ~ ~ ~ ~ form, has potential for much greater bandwidth than the published results suggest. The physical symmetry of this balun ensures frequency-independent current balance, leaving impedance variation as the main performance-limiting factor. The dependence of impedance bandwidth on internal impedances has been re-examined to indicate design strategy and performance potential and, incidentally, to suggest why this potential has not been realised in previous designs.

The equivalent circuit for the Marchand balun is shown in Fig. 1. Adopting Marchand's n o m e n c l a t ~ r e , ' ~ ~ ZOT, ZOE are respectively the characteristic impedances of the short- (choke) and open-circuit (phase-compensation) stub lines, Zoc, Z L are the unbalanced and balanced load or source impedances seen by the balun, Zu, Z B are the unbalanced and balanced port impedances and 8 is the electrical length of the choke and phase-compensation lines. The port impedances are

4ZL z & ~ tan2 8 + j ( 2 ~ 2 ZOT tan 8 - 4ZOE ~6~ tan 8 - 2; ZOE cot 8) zu =

4 ~ 6 ~ tan28 + 22

and (1)

2Zor(2Zoc ZOT tan2 8 + j(Z&E cot 8 - 2ZoE ZOT tan 8 + Z& tan 8))

2, = 4 2 h T tan28 + Z& + z & ~ cot26 - 4ZoE ZoT

Two theoretical proposals for maxirnising impedance bandwidth have been made. ~ o b e r t s ' put ZOE = ZOC and 2ZoT = Z L ; this produces a perfect match at two separated frequencies defined by sin2 8 = Zoc/ZL and can be useful when ZL + ZOC, but is unnecessarily poor when ZL = Zoc. In practice, ZL and Zoc can be made equal for a wide range of external circuit impedances by the introduction of a suitable transforming taper into the balanced or unbalanced lines. Substantially greater bandwidth is given by Marchan d's original proposal1

to set

This minirnises the imaginary terms in ZB, ZU at the centre frequency (8 = :n/2) when ZL = ZOC: However, the dominant tan28 term in the denominators of eqns. 1 , 2 is itself sufficient to make the imaginary terms zero at the centre frequency, and it is qualitatively clear that a different choice of ZOE, reducing the imaginary term at the band edges, is required for true bandwidth maximisation. Marchand's result gives no direct indication of the bandwidth to be expected from a balun conforming to eqn. 3, or of the functional dependence of bandwidth on the internal impedances ZOT, ZOE. TO clarify the situation and determine true bandwidth-maximising values for ZOE, the balanced port impedance ZB and its v.s.w.r. when loaded with ZL = ZOC have been calculated for Zoc = 50 52 and various ZOT, ZOE. The results are summarised in Fig. 2, which relates bandwidth to ZOE for v.s.w.r. limits of 1.5 : 1 and 2.0 : 1 and ZOT = 100, 200, 400 a. These curves show that bandwidth is maximised at ZOE values close to (in fact less than) the values suggested by eqn. 3, confirming its usefulness as a design guide. More interestingly, increase in ZOT can give substantial bandwidth enhancement only at near- optimum ZOE; the low value of this optimum for typical Zoc, ZOT (2 to 7 52 for ZOC = 50 52 and ZOT in the range 100- 400 a) has a crucial effect on design procedure and practically attainable bandwidth.

In coaxial structures, a high ZoT requires a large ratio of overall balun diameter to the diameter of the unbalanced input and phasecompensation lines. Since internal cavity dimensions must be limited to avoid higher-order modes, the practical impedance bandwidth limit is probably imposed by construction tolerances: the impedance ZOE must become less well controlled as the conductor gap approaches the

I I I --zu z ~ c l lmil

Fig. 1 Lumped-impedance equivalent circuit

Fig. 2 Computed bandwidth as firnction of ZoTI ZOE for 50 $2 Marchand balun

51 0 ELECTRONICS LETTERS 78th August 7977 Vol. 13 NO. 77

machining tolerance, and from this stage increasing v.s.w.r. can be expected to accompany further increase in ZOT/ZOE. The design by McLaughhn et al. conforms reasonably closely to eqn. 3 and their results can be considered representative for optirnised coaxial structures-13 : 1 bandwidth for v.s.w.r. less (but not much less) than 2 : 1.

Microstrip structures offer greater desi n flexibility, but in the form devised by Bawer and Wolfe3*' their effective ZOT cannot easily be calculated or measured and design is necessarily semiempirical. In fact, the designs cited do not maximise ZOT within the available card area or, generally, approach optimum ZOE. Since the designers apparently attempted to maximise bandwidth-Bawer and Wolfe, for example, discuss3 both the Roberts and Marchand equations-these omissions invite comment. Reference to the illustrations in Bawer and Wolfe's paper shows their ZoT was probably around 200 to 300 52 and their ZOE = ZOC (= 100 52). Fig. 2 suggests that these characteristics place the design well to the high-ZoE side of the bandwidth maximum, in a region where bandwidth is insensitive to both ZOE and ZOT (and can even decrease with increasing ZOT at constant ZOE). Note that the difference between Bawer and Wolfe's Zoc = 100 52 and the Zoc = 50 52 used in computing Fig. 2 precludes direct quantitative comparison. Clearly, an empirical bandwidth optirnisation starting in this part of the Fig. 2 curves will show insensitivity to ZOT and ZOE and is-unlikely to converge reliably towards the true optimum. In this light, Bawer and Wolfe's findings become readily understandable. Largely similar comment is applicable to May's designs.4

Fig. 2 clarifies the initial design characteristics necessary for successful empirical bandwidth maximisation. ZOT should be as large as possible under the constraints of card size (limited by centre frequency) and balanced line conductor width (imposed essentially by transmission loss and v.s.w.r. require- ments through their influence on card thickness and dimensional tolerances). It must be possible t o fabricate low impedance lines: the initial ZOE should be, for Zoc = 50 52, in the range 1-10 52. This impedance range is generally inaccessible using the same substrate as a 50 52 line of reason- able size and has been realised in the present work by trans- posing one conductor through the main card and fabricating the low-impedance line on a thin overlay. This technique considerably enhances design- freedom and allows optimum design, and hitherto unrealisable bandwidths, t o be achieved.

It should be noted that, because both balanced and unbalanced input impedances can readily be transformed in microstrip by tapering the appropriate lines, the designer has some freedom to choose Zoc, ZL independently of the required external impedances. Many balanced antennas have terminal impedances in the range 150-300 52 and it is possible to work at this impedance with the transforming taper in the unbalanced line (to match to 75 or 50 52). The optimum ZOE is then conveniently high (typically 50 52 plus). However, the shunting effect of the choke impedance is greater, and attain- able bandwidth correspondingly less, with high Zoc, ZL. There is a corresponding advantage in working with low Zoc, ZL , but the difficulty of fabricating the phasecompensation line is increased. 50 52 appears to be a practically convenient choice for Zoc, ZL, offering adequate bandwidth for most purposes.

Preliminary experimental results show clear optima in the impedance and length of the phasecompensation line for a given balanced line geometry. An impedance bandwidth exceeding 70-2400 MHz (the limit of measurement) for v.s.w.r. < 2 : 1, referred to 50 52, has been achieved on a 7.5 cm square card. The full bandwidth of this balun probably extends significantly beyond 2400 MHz. Typical inband v.s.w.r. is less than 1.3 : 1, and amplitude and phase balance appear good (within 0.5 dB and 3', respectively). Much of the remaining inband reflection and imbalance can be attributed to the imprecise construction of the experimental units.

It is concluded that the the-oretical results presented here, and supported by experimental evidence, show that optimally designed microstrip Marchand baluns have the bandwidth

potential to meet most balanced antenna-feed requirements in the vb.f. band and above.

O Copyright, Controller, HMSO, 1977

D. M. L. BARTHOLOMEW 27th June 1977

Admiralty Compass Observatory Ditton Park Slough, Berks.. England

References

1 MARCHAND, N.: Transmission line conversion transformers', Electronics, 1944,17, pp. 142-145

2 McLAUGHLIN, J. W., and GROW, R. W.: 'A wide-band balun', IRE Trans., 1958, MTT, pp. 3 14-3 16

3 BAWER, R. and WOLFE, J. J.: 'A printed circuit balun for use with spiral antennas', ibid., 1960, MTT, pp.319-325

4 MAY, D. P. L.: 'Engineered designs for very wide band radio frequency transformers using printed circuit strip line techniques'. Royal Aircraft Establishment Technical Report 70063 (unlimited), 1970

5 ROBERTS, W. K.: 'A new wide-band balun', Proc. IRE, 1957, 45, pp. 1628-1631

MODELLING TECHNIQUE FOR AN F.E.T. CHIP

Indexing terms: Equivalent circuits, Semiconductor-device models

A technique for modelling an f.e.t. chip is presented. First, the device is characterised in its 2-port S-parameters. Then, by choosing a suitable equivalent circuit and reasonable starting values, a simplex optirnisation procedure is employed to obtain optimum component values for the equivalent circuit.

Introduction: Device modelling is useful for investigating the gain and/or noise performance of a circuit incorporating the device. In this letter, we describe a method for modelling an f.e.t. chip. The S-parameters of the chip over the 8-10 GHz range are first determined by a de-embedding technique to r'emove the effect of connectors, bias Ts and adjoining trans- mission lines. The S-parameters are then used in a simplex optimisation procedure t o model the chip. The advantage of simplex over gradient methods, such as the least-squares and Newton-Raphson techniques, is that it does not involve first or second derivatives of the error function for minimisation.

Determination of S-parameters of fie. t. chip: Fig. 1 shows a schematic of the 'jig' used for S-parameter measurements. The f.e.t. chip (Siemens) is fmed with quick-set Araldite on a gold-plated stud which passes through a 1.27 mm hole drilled in the alumina substrate. A more detailed view of the chip in its environment is shown in Fig. 2. The gate and drain pads of the chip are connected via 0-025 mmd.@meter bond wires to the adjoining 50 S2 microstrip lines. Bond wires are also used to connect the two source pads to'the stud, which is in contact with the ground plane.

Referring to Fig. 1, both microstrip lines are connected to OSM-244-4ASF coaxial-to-microstrip connectors, and bias t o the chip is introduced via external Ts. The accessible measure- ment planes are therefore AA' and BB'. It is apparent that the jig transmission matrix [T,], which can be obtained from

ELECTRONICS LETTERS 18th August 1977 Vol. 13 No. 17 51 1