Embed Size (px)
Citation preview
© 2019 Cadence Design Systems, Inc. All rights reserved.
Frank Schirrmeister – Sr. Group Director, Product ManagementVerification FuturesReading, June 13th 2019
Optimizing Verification Throughput in a Connected World of 5G and ML/AI
© 2019 Cadence Design Systems, Inc. All rights reserved.
2020
Challenges & Opportunities in Electronics Innovation
Parallel and Distributed
DeepLearning
Full-flowSolutions
Edge-to-Cloud and 5G
ArtificialIntelligence
SpecializedSoCs
Moore’s Law
1960
Semiconductors and Systems EDA system design enablement
© 2019 Cadence Design Systems, Inc. All rights reserved.
IoT / IndustrialCloud / DatacenterMobile Automotive Aero / Defense Health
Cadence Intelligent System Design
Cloud Enabled — Partnerships with Ecosystem Leaders
SystemInnovation
PervasiveIntelligence
DesignExcellence
• System Analysis• Embedded Software and Security• Device Development
• Verification Suite• Full-Flow Digital• Analog and RF• Interface and Processor IP
• Machine Learning Inside• Machine Learning Outside• Machine Learning Enablement
© 2019 Cadence Design Systems, Inc. All rights reserved.
A Data-driven World
Data
Create
Transmit
Compute
StoreMemory Technology(HDD, DRAM, NAND)
Datacenter, ServersML/AI
Sensors EverywhereInternet of Things
Wireless & Wired Infrastructure5G
© 2019 Cadence Design Systems, Inc. All rights reserved.
Datacenter ChallengesWorkload-optimized, high-performance compute, connectivity, accelerators – AI/ML/DL
Hyperscale Optimization CPU Rack-Level Connectivity Scale Out Clusters
• Workload optimized• Machine learning• Deep learning• Accelerator offloads
• Leaf /spine• Memory pool (HBM)• Connectivity / SiP• Reduced latency• Mesh / 3D-torus / fabric
• DNN• SSD / NVMe• Coherency• VM / containers• Mesh/3D-torus
0
2
4
6
8
10
12
14
2015 2016 2017 2018 2019 2020
Typical Workloads per Server
Traditional Datacenter Cloud DatacenterN
S
EW
© 2019 Cadence Design Systems, Inc. All rights reserved.
Machine Learning / Artificial Intelligence - ChallengesTraining, Inferencing and Specialized IP
• Diverse requirements− Training – High throughput, big designs− Inference – Flexibility− Specific IP
• Key Challenges− Significant software content− Big Designs – Emulation throughput, debug− Physical and virtual interfaces− Specific I/O – HBM− Virtualization− System Use Case Test Development− Multi-core speed VIP: I/F & MEM
© 2019 Cadence Design Systems, Inc. All rights reserved.
The Promise of 5G – Where to Start?
© 2019 Cadence Design Systems, Inc. All rights reserved.
5G — New Bandwidth, New Subsystems5G mmWave and C-RAN
Internet Backbone
‘Fixed wireless’ replaces ‘last mile’ copper to homesFemtoCells
Edge Computing Fronthaul (Optical)
Fronthaul (Coax)
MastBaseband
Ultra-Low Latency and Massive AI
MastRadiohead
Backhaul
Distributed Radioheads
Small Cells
Every 2-3Km
Every 200m
4G and 5G
SharedBaseband
>24GHz<6GHz
© 2019 Cadence Design Systems, Inc. All rights reserved.
5G Ecosystem Opportunities and Requirements 1/2
Enhanced mobile broadband• Needs
− Faster speed, Lower latency, Greater capacity − On-the-go, ultra-high-definition video, virtual reality,
and other advanced applications.
• Design characteristics− traditional large (>200MG), complex designs− requiring full-chip execution for SW - Emulation
Internet of Things• Needs
− Existing networks struggling− 5G unlocks (IoT) - more connections at once− Additional monthly revenues for carriers− IoT revenues smaller because of low usage− 5G competes against Wi-Fi and Zigbee.
• Design characteristics− much smaller (<32MG), very power sensitive− performance system dependent− multi-device simulation / emulation for QoS and
performance validation
© 2019 Cadence Design Systems, Inc. All rights reserved.
5G Ecosystem Opportunities and Requirements 1/2
Mission-critical & control• Needs
− absolute reliability in medical, vehicle safety− Latency limiting factor− 5G delivering lower latency− New use cases in healthcare, utilities, traffic
management, and other time-critical contexts− Operators expect only incremental revenue
• Design characteristics− Small-to-medium designs (<200MG)− Functional safety drives need for system emulation
Fixed wireless access• Needs
− 5G, millimeter wave spectrum, capable of delivering speeds of more than 100 Mbps to the home
− Viable alternative to wired broadband− New revenue stream for wireless operators in areas
with less fiber/cable access
• Design characteristics− Extension to traditional base-station developers− More complexity requiring system emulation− Design size expected to be large (>200MG)
© 2019 Cadence Design Systems, Inc. All rights reserved.
Design Start Market: Bifurcation
Source: IBS 2014 to 2018
© 2019 Cadence Design Systems, Inc. All rights reserved.
The Unifying Challenge: Verification and SoftwarePr
ojec
t cos
t ($M
)
Source: IBS 2018
$- $50
$100 $150 $200 $250 $300 $350 $400 $450 $500
SoftwareVerificationPhysicalArchitectureIP qualification
VERIFICATION &
SOFTWARE
2NExpandingVerificationOpportunity
ExpandingSoftware
Opportunity
© 2019 Cadence Design Systems, Inc. All rights reserved.
So How Do You Win a Race?
© 2019 Cadence Design Systems, Inc. All rights reserved.
Raw Performance
© 2019 Cadence Design Systems, Inc. All rights reserved.
MultipleEngines
© 2019 Cadence Design Systems, Inc. All rights reserved.
Smart Logistics
© 2019 Cadence Design Systems, Inc. All rights reserved.
The Verification Race!
© 2019 Cadence Design Systems, Inc. All rights reserved.
Enable Early Software Development
Cadence Verification Mission
Be #1 in VerificationThroughput2N
© 2019 Cadence Design Systems, Inc. All rights reserved.
Multi-Level Abstraction
RTLLevel
SoftwareLevel
TransistorLevel
GateLevel
Cycles per $ per DayRaw Performance
PerformanceOptimization
ScalableArchitecture
Bare MetalCompute
Bugs per $ per Day
Smart Bug Hunting
DebugCoverage & Metrics
Formaland Lint
PortableStimulusVIP
Cadence Verification Mission: Verification Throughput
© 2019 Cadence Design Systems, Inc. All rights reserved.
Multi-Level Abstraction
RTLLevel
SoftwareLevel
TransistorLevel
GateLevel
Cycles per $ per DayRaw Performance
PerformanceOptimization
ScalableArchitecture
Bare MetalCompute
Bugs per $ per Day
Smart Bug Hunting
DebugCoverage & Metrics
Formaland Lint
PortableStimulusVIP
Raw Performance
© 2019 Cadence Design Systems, Inc. All rights reserved.
Xcelium™Simulation
Protium™ S1Prototyping
Performance
Debug Flexibility & Compile Time
FPGA
X86 Server
Palladium® Z1Emulation
CustomProcessor
Bare Metal Compute
Arm Server2018
© 2019 Cadence Design Systems, Inc. All rights reserved.
Xcelium next-generation high performance simulator
COMPILE Incremental Build Parallel Build
Rocketick multi-core technologyNext-generation single core kernel
COMPUTE
LONG TEST LATENCY FULL REGRESSION THROUGHPUT
X86 Arm Cloud
Up to 10X speed-up
Up to 2X speed-up Up to 4X speed-up
© 2019 Cadence Design Systems, Inc. All rights reserved.
Multi-Core and Simulation Regressions
Actual finish time of regression = Desired finish time of regressionSimulation Regression with Xcelium Single-Core
Multi-Core Simulation: 3x faster using 8 cores
© 2019 Cadence Design Systems, Inc. All rights reserved.
What’s the Emulation story“processor based”
vs. “FPGA based”
all about?
© 2019 Cadence Design Systems, Inc. All rights reserved.
Build
Allocate
Run
Debug
Compile
Dispatch
Execute
Debug
Build
Allocate
Run
Debug
The Verification Productivity Loop
© 2019 Cadence Design Systems, Inc. All rights reserved.
1MHzFast compilePredictable compile(“If it compiles it runs”)“Full Vision” debug
Simple left-to-rightstream processing
logic
logic
logic logic
logic
regi
ster
s
regi
ster
s
logic
Level 1 Level 2 Level 3 Level 4
ASIC-style fullPlace & Route
Place + opt
Clock + opt
Route + opt
5-20MHzSlow compile
Compile may need tuning toclose timing/routing violations
Limited debug
logic
logic
logic logic
logic
regi
ster
s
regi
ster
s
logic
EP
EP EP
EPSwitchfabric
EP
EP DebugEngine EP
PalladiumEmulation Processor
lut lut lut lut lut lut lutlut lut lut lut lut lut lutlut lut lut lut lut lut lutlut lut lut lut lut lut lutlut lut lut lut lut lut lutlut lut lut lut lut lut lut
ProtiumXilinx FPGA
lut lut lut lut lut lut lut
Hardware debug Rapid bug hunting
Software bring-upDeep bug hunting
Emulation and Prototyping!
© 2019 Cadence Design Systems, Inc. All rights reserved.
Unified Frontend for Emulation and Prototyping
Compile
RTL
Protium™ S1 / X1 • Highest performance• SW development• Regressions
Congruency and common environment
Palladium® Z1• Best debug• SoC integration & accel• Rich use models
Speed & SW development
Debug & Rich use models
© 2019 Cadence Design Systems, Inc. All rights reserved.
EP
EP
EP
EP
Switchfabric
EP
EP
DebugEngine
EP
lut lut lut lut lut lut lutlut lut lut lut lut lut lutlut lut lut lut lut lut lutlut lut lut lut lut lut lutlut lut lut lut lut lut lutlut lut lut lut lut lut lut
lut lut lut lut lut lut lut
Tag Team
PalladiumEmulation Processor
ProtiumXilinx FPGA
Graphics – ADASAI/ML
5G NetworkingMobile - Server Storage Networking
Storage
Palladium Emulation AND Protium Prototyping
© 2019 Cadence Design Systems, Inc. All rights reserved.
Unified Flow for Emulation and Prototyping(Source: Toshiba, CDN-Live 2019)
Palladium and Protium used togetherHardware verification and firmware development
Protium at 4.6x of Palladium, 45 interations of P&R
http://bit.ly/2VXCjcC
© 2019 Cadence Design Systems, Inc. All rights reserved.
Hardware Portfolio - Now with Multi-MHz @ BG
• Palladium Z1− Best debug throughput, multi-user− Target: HW Verification
HW Verification HW Regression SW DevelopmentHybrid & SW Bring-Up
Palladium Z1EMULATION
PerformanceProtium S1-G
Protium X1ENTERPRISE PROTOTYPING
Capacity
200 MG
600 MG
6.8 BG
1-2 BG
MC- Multi-ChassisSC- Single Chassis
• Protium X1− Congruency with Z1− Highest performance @ large capacity− Multi-user (48 per rack)− HW debug and SW debug
• Protium S1 SC (200MG)− Congruency with Z1, auto-compile, S/W debug− Target: SW Verification
• Protium S1 MC− Congruency with Z1, auto-compile, some HW debug− Target: HW Regressions
Protium S1DESKTOP PROTOTYPING
© 2019 Cadence Design Systems, Inc. All rights reserved.
New: Protium X1 Enterprise Prototyping System
• Performance• Enabling early firmware and software development, automated bring-up• Up to 50MHz for single FPGA; up to 5MHz on billion gate designs
• Capacity• Advanced blade architecture scales to billions of gates• Ideal for AI, ML, 5G, mobile, and graphics applications
• Fast Bring-up• Unified Palladium® Z1 / Protium™ X1 compile ensures DUT congruency • Enables transition from emulation to prototyping in days
• Multi-user• Single-FPGA granularity assures high utilization and efficiency• Ideal for storage, automotive, image, consumer and medical applications
© 2019 Cadence Design Systems, Inc. All rights reserved.
Xcelium™Simulation
Protium™ S1/X1Prototyping
Performance
Debug Flexibility & Compile Time
FPGA
X86 Server
Palladium® Z1Emulation
Scalable Bare Metal Compute – Users & Capacity
Arm Server2018
CustomProcessor
© 2019 Cadence Design Systems, Inc. All rights reserved.
Multi-Level Abstraction
RTLLevel
SoftwareLevel
TransistorLevel
GateLevel
Cycles per $ per DayRaw Performance
PerformanceOptimization
ScalableArchitecture
Bare MetalCompute
Bugs per $ per Day
Smart Bug Hunting
DebugCoverage & Metrics
Formaland Lint
PortableStimulusVIP
Multi-Level Abstraction
© 2019 Cadence Design Systems, Inc. All rights reserved.
Users Care About Many, Often Conflicting Requirements
AccuracyMore is better
SpeedFaster is better
Time of availabilityEarlier is better
Execution Control
System Connections
Software Debug
Development Cost
Less is better
ReplicationCost
Less is better
CapacityMore is better
Hardware Debug
Value Links(Power,
Performance)
Bring-up TimeLess is better
© 2019 Cadence Design Systems, Inc. All rights reserved.
Wouldn’t it Be Nice if “One Tool Would Rule Them All”?
© 2019 Cadence Design Systems, Inc. All rights reserved.
Wouldn’t it Be Nice if “One Tool Would Rule Them All”?
Eierlegende Wollmilchsau"egg-laying wool-milk-sow“
• Perfect farm animal uniting several qualities:− chickens (laying eggs)− sheep (producing wool)− cows (giving out milk) and − pigs (can be turned into bacon).
• Produces all the daily necessities and is tasty to boot, it is an animal that only has good sides to it … Source: Wikimedia Commons: http://bit.ly/2fFtsK1
© 2019 Cadence Design Systems, Inc. All rights reserved.
A Continuum of Dynamic EnginesVerification and software platforms need to interoperate
SDK OS SimulationHighest speed
Earliest in flowIgnores HW
Easy replication
Cross-compile
Virtual Platform
Almost @ speedPre-RTL
Less accurateTLM HW DebugGreat SW debugEasy replication
Less HW detailSlower with detail
HDL Simulation
KHz RangeEarly RTL
Golden ReferenceBest HW debug
Limited SW DebugEasy replication
Mixed-abstractions Slow SW execution
AccelerationEmulation
MHz RangeEarly RTL
Min RTL modsDetailed HW debug
Great SW DebugHarder to replicate
Datacenter accessContested Resource
FPGA Prototype
10’s of MHz Later RTL
Some RTL modsSome HW debugGreat SW DebugOK to replicate
Harder Bring-up
Prototyping Board
Real time speedFully accurateActual Silicon
Difficult HW debugOK SW Debug
Easy to replicate
HW changes hard
© 2019 Cadence Design Systems, Inc. All rights reserved.
Hardware/Software Co-Verification during SoC Design
Applications(Basic to Complex)
Bare-metal SW
OS and Drivers(Linux, Android)
System on Chip
Middleware(Graphics, Audio)
ChipProduction
SiliconBringup
Post SiFab
Software based hardware tests
Functional Simulation
FPGAPrototyping
Virtual SystemPlatform 1st Silicon Board
ArchitectureExploration
&Spec
DefinitionPhase
RTLSystem-C RTL RTL
„VSP“ „Xcelium“ „Palladium Z1“
HW/SWEmulation
„Protium“
Frontend Design & Functional Verification Place&Route,
Tape Out
SoC Development
6 month 12 month 4 month 3 monthTypical Duration:
© 2019 Cadence Design Systems, Inc. All rights reserved.
Raw PerformanceXcelium Simulation Palladium Emulation Protium S1 Prototyping
Multi-Level AbstractionPe
rfor
man
ce t
hrou
gh A
bstr
acti
on
CPU GPU
Periph 1IP 1 IP 2
NOC
CPU GPU
Periph 1IP 1 IP 2
NOC
CPU GPU
Periph 1IP 1 IP 2
NOCHybrid
Virtual(Software Model)
CPU GPU
Periph 1IP 1 IP 2
NOC
CPU GPU
Periph 1IP 1 IP 2
NOC
CPU GPU
Periph 1IP 1 IP 2
NOCRTL
© 2019 Cadence Design Systems, Inc. All rights reserved.
Virtualization with Emulation Enables SW Shift-LeftUsing virtual platforms and hybrids to accelerate SW development and HW/SW validation
All RTL, SiliconFinal HW/SW Validation
All VirtualPre-RTL SW Development
SoC Virtual Platform
OS SoC Drivers
Tests and Benchmarks
IPRTL
IP HybridPre-SoC IP / Driver
Validation & OptimizationRTL – Palladium or Xcelium
RTLMemory
CPU Virtual Platform
OS IP Driver
RTL IP
Tests and Benchmarks
SoC RTL
SOC HybridPre-Tapeout HW/SW
Validation
DDR3
Display
INTCTimer CSI
DSI
UART
GPUMC
SATAUSB3
…
SystemBoot
USB2
Ethernet
MMP IP 2
CPU Virtual Platform
OS SoC Drivers
Tests and Benchmarks
OS SoC Drivers
Tests and Benchmarks
Design FlowShift Left
Virtual Models - VSP
SW stack
RTL Models -
Color Code
DDR3
Display
INTCTimer CSI
DSI
UART
GPUMC
SATAUSB3
…
SystemBoot
USB2
Ethernet
Mem IP 2
CPU CPU
Emulation, FPGA ProtoPre-Tapeout Fully
Accurate HW/SW Validation
SoC RTL
OS SoC Drivers
Tests and Benchmarks
DDR3
Display
INTCTimer CSI
DSI
UART
GPUMC
SATAUSB3
…
SystemBoot
USB2
Ethernet
Mem IP 2
CPU CPU
© 2019 Cadence Design Systems, Inc. All rights reserved.
IP and SoC Hybrid Examples
Source: Emulation Enabling Automotive Designs, http://bit.ly/2yR12r8
IP Hybrid complementing RTL verification with real SW drivers, develop, execute and debug large amount of software, 6 users in parallel
SoC Hybrid with faster OS boots, smoother SoC bring-up once silicon is back, SW ready to demo
product earlier, OpenGL test suites pre-silicon
Source: DAC
© 2019 Cadence Design Systems, Inc. All rights reserved.
Cadence Virtual/Hybrid Prototyping Environment
Virtual and Hybrid platform and SW Bring-Up Services
TLMLibraries
3rd PartyDebuggers
Platform Assembly
Create, integrate, Extend
Run TimeEnvironment
Heterogenous, multi-process, multi-system
IEEE 1666 SystemC Enginebased on Xcelium
Native DebugSystemC, SW
SimVisionHybrid Connections to RTL Engines
Xcelium, Palladium Z1, Protium
External IFVirtual Device Models
Base Libraries
Modeling Automation
Processors Peripherals
Interconnect
Open & Standard’s based
CommonComponents
Peripheral Models Connected to Platform
Built in TLM DebugLow Level SW Debug
Software Debug
Create Platform Use Platform for Software Development
Smart Memory, Transactors
© 2019 Cadence Design Systems, Inc. All rights reserved.
ChipProduction
SiliconBringup
Post SiFab
ArchitectureExploration
&Spec
DefinitionPhase
SoC Development
More Robust Hardware and Software!Greatly accelerated Time-to-Market!
Test 100s of SW Scenarios
Before Tape Out!
CadenceEmulation Chamber
SoC User
SoC Developer
FPGA Prototyping
(Tensof users)
Virtual SystemPlatform
(Hundredsof users)
SW development starts 6-9 month earlier,Silicon bring up time greatly accelerated!
System on Chip
SiliconBringup
Post Si
Applications(Basic to Complex)
Bare-metal SW
OS and Drivers(Linux, Android)
Middleware(Graphics, Audio)
© 2019 Cadence Design Systems, Inc. All rights reserved.
Multi-Level Abstraction
RTLLevel
SoftwareLevel
TransistorLevel
GateLevel
Cycles per $ per DayRaw Performance
PerformanceOptimization
ScalableArchitecture
Bare MetalCompute
Bugs per $ per Day
Smart Bug Hunting
DebugCoverage & Metrics
Formaland Lint
PortableStimulusVIP
Smart Bug Hunting – Putting It All Together
© 2019 Cadence Design Systems, Inc. All rights reserved.
VIP Catalog - Latest Protocols Support
3
PCIExpress
4.0 DDR4, DDR5ETHN
400GSAS 24G
USB 3.1 w OTG
NVM Express
HBM 2.0HMC
Cloud/Data Center
CCIX CHI.B
Mobile/Consumer
LPDDR4LPDDR5
Wide I/O 2
AXI/AHB/ACE
USB 3.2
USB Type C
MIPI DSI 2
MIPI CSI-2
MIPI SoundWire
eMMC 5.0
UFS 2.1
Display Port 8K
SD Card 4.0
ARM AMBA4/5
Bluetooth ®
WiFi®
MIPI I3C
UFS
ENET AVB
ENET 10/100/1G/10G LIN
CAN FD
DDR 2,3,4 NOR
FLASH
Flash ONFIENET
TSN
MIPI DSIMIPI
I3CMIPI
SoundWireI2C
SPI OctaRam
Automotive
1.3
1.4
CHI-D
5
© 2019 Cadence Design Systems, Inc. All rights reserved.
© 2019 Cadence Design Systems, Inc. All rights reserved.
Perspec Standardization, Recognition, and Multi-Vendor Support
2014: Accellera adopts the Perspec vision for PSS (Portable Stimulus Standard)
2016: Accellera chooses Perspec concepts asbaseline for PSS
June 2017: PSS review version releasedJune 2018: Released version 1.0 (working on 1.1)
© 2019 Cadence Design Systems, Inc. All rights reserved.
vManager: Verification Predictability, Productivity, QualityWith better automation
Testing
CPU Subsystem
AISubsystem
BUS
IPBlock
IPBlock
IP Block
IP Block
IP Block
IP Block
testbench
Requirements
Planning
Regression Management
Analysis
Traceability
Tracking
Clie
nt
MetricsJasperGold®FORMAL
Xcelium™SIMULATION
Palladium® Z1EMULATION
Protium™ S1FPGA PROTO
Database
Public REST APIServ
er
CoverageCoverage
Goals
Tests
Integration
© 2019 Cadence Design Systems, Inc. All rights reserved.
Indago Debug
Scalability to SOC level• Performance and capacity
Driver tracing• accuracy and speed
Smartlog• unified context aware Log File
Advanced Search• Fast and Complete
Palladium Debug• On demand signal expansion ++
Low Power debug• Usability and capabilities
© 2019 Cadence Design Systems, Inc. All rights reserved.
ML-enabled Smart JasperGoldThird-generation JasperGold formal verification platform
“We measured 2x faster proofs out-of-the-box, 5x faster regressions and non-converged properties reduced by 50%”-Mirella Negro Marcigaglia, digital design verification manager, STMicroelectronics
Smart Proof Technology
ML for solver inference and multi-advisor orchestration
Advanced Design Scalability
2x design capacity increase and 50% memory footprint reduction
SoC
Signoff-quality Formal Coverage
Signoff-accurate formal coverage with new intuitive analysis GUI
CustomSolver
A B … NTrainingData
Third-Generation JasperGold® Formal Verification Platform
© 2019 Cadence Design Systems, Inc. All rights reserved.
vManager Indago
• RTL and gate level• UVM testbench• Assertions• Constraints• Embedded software• Virtual platform• Cross-platform
• Requirements tracing• Verification planning• Regression mgmt and
optimization• Failure triage• Coverage analysis across
engines• Safety planning
• Accellera PSS 1.0• Auto-generates C-based
tests• Scenario-based
randomized tests• ISA libraries e.g. ArmV8• Portable across all
engines
• C for performance• Portable & scalable• All methodologies,
languages and simulators• Consistent across protocols• TripleCheck: vPlan, test
suite, coverage
• ML-enabled smart proof• Adv. design scalability• Sign-off accurate coverage• Deep bug, deadlock hunting• Visualize debug / IP expl.• Widest range of formal apps
Perspec
Smart Bug Hunting
DebugCoverage & Metrics
PortableStimulus
Formal& LintVIP
VIP Catalog JasperGold
Smart Bug Hunting Leadership
© 2019 Cadence Design Systems, Inc. All rights reserved.
Summary … What’s Next?
© 2019 Cadence Design Systems, Inc. All rights reserved.
Multi-Level Abstraction
RTLLevel
SoftwareLevel
TransistorLevel
GateLevel
Cycles per $ per DayRaw Performance
PerformanceOptimization
ScalableArchitecture
Bare MetalCompute
Bugs per $ per Day
Smart Bug Hunting
DebugCoverage & Metrics
Formaland Lint
PortableStimulusVIP
Cadence Verification Mission: Verification Throughput
© 2019 Cadence Design Systems, Inc. All rights reserved.
Cadence Leadership in Machine Learning
ML Inside• Better PPA, faster engines• Improved testing / diagnostics
ML Outside• Automated design flows• Productivity improvements
ML Enablement• Hardware / software co-design• Tensilica® IP for Machine Learning
© 2019 Cadence Design Systems, Inc. All rights reserved.
And then there are Digital Twins …
Aerospace
• A digital twin is a digital representation of the current state of a manufactured product or system at any given point in time.
• A digital thread is a digital record of all states of a manufactured product or system over time from conception to disposal.
Verification
• A digital twin is a digital representation of a product or system under development representing a functionally correct, predictable and reproducible representation of the product or system at the appropriate level of fidelity to perform verification, performance analysis and system validation tasks.
© 2019 Cadence Design Systems, Inc. All rights reserved.
Data-Transfer for Digital Twins
SDK OS Simulation
Virtual Platform
HDL Simulation
AccelerationEmulation
FPGA Prototype
Prototyping Board
SiliconSystemsof Systems
Refinement of Data – Forward Optimization
Actual Data Sets Applied to Earlier Representations
Performance
Debug Flexibility & Compile Time
Abstraction
© 2019 Cadence Design Systems, Inc. All rights reserved.
Completely New Verification Challenges Ahead!
• How to verify ML/AI• Security• Safety• Ownership of data• New ways to communicate• Multi-Domain Execution
• 99% exciting and 1% scared?• 1% exciting and 99% scaled?
© 2019 Cadence Design Systems, Inc. All rights reserved.
Strategic Partnership with Green Hills Software
• Rapid growth in hyper-connected embedded systems
• $3B+ embedded safety and security market opportunity
• Deliver integrated solutions for hardware and software aspects of safety and security
• Furthers Cadence’s system design enablement strategy by moving up system stack
AUTO A & D
Cadence Verification Suite
DriversOperating System
ApplicationsMiddleware
Firmware / HAL
Software
SoC interconnect fabric
PHY
SATA
MIPI
HDMI
WLAN
LTE
PMU
MIPI
JTAG
INTC
I2C
SPI
Timer
GPIO
Display
UART
Boot CPU
Modem
USB
3.0PHY
2.0PHY
PCIe
PHY
EthernetPHY
Board, SoC, Sub-System or IP
Low-SpeedPeripherals
General Purpose
Peripherals
High Speed,Wired Interface
Peripherals
ComputeSub-System GFX
Application-Specific ComponentsDSP
GHSINTEGRITY RTOS
MULTI DebuggerIDE
Optimizing Compilers
Super TraceProbe
Formal Simulation Emulation Prototyping
Cadence
Green Hills
© 2019 Cadence Design Systems, Inc. All rights reserved.
Strong Verification Partnerships
Design to Test SoC Instrumentation & Debug
Virtual & Physical Ethernet Testing Security
© 2019 Cadence Design Systems, Inc. All rights reserved.
The Cadence Verification Suite
© 2019 Cadence Design Systems, Inc. All rights reserved.
IoT / IndustrialCloud / DatacenterMobile Automotive Aero / Defense Health
Cadence Intelligent System Design
Cloud Enabled — Partnerships with Ecosystem Leaders
SystemInnovation
PervasiveIntelligence
DesignExcellence
• System Analysis• Embedded Software and Security• Device Development
• Verification Suite• Full-Flow Digital• Analog and RF• Interface and Processor IP
• Machine Learning Inside• Machine Learning Outside• Machine Learning Enablement
© 2019 Cadence Design Systems, Inc. All rights reserved.
