Outer Tracker Electronics

ASDTDC

L0 BufferL1 Buffer

bias L0 BX L150 fC

DAQ

chamber counting room

~100m

Ulrich Uwer

University of Heidelberg

LHCb Electronics Workshop

CERN, 05/02/2003

TFC

TFC

ECS

ECS

Power (HV,LV)

Power (HV,LV)TQ-distribox

TFC

TFC

ECS

ECS

Power (HV,LV)

Power (HV,LV)

Fibers to L1 Buffer

Fibers to L1 BufferFibers to L1 Buffer

Fibers to L1 Buffer

TrackerQuadrant

TQ-distribox TQ-distribox

TQ-distribox

ASDBLR

OTIS

GOL

ASDBLR

OTIS

HV board

ASDBLR ASDBLR

LV Reg

L1

TFC ECS LVHV

Module End:

128 channels

16 ASDBLR chips

4 OTIS TDC chips

1 optical link: 1.28 Gbit/s

Outer Tracker: T1…3

56000 channels

432 optical links

tot. dose < 10krad

9 modules

X 1

X 2

X 4X 8

GOL/Aux Board

TDC boards

HV boardsASD boards

boards number

GOL/Aux 432

TDC 1732

ASD 3456

HV 1728

Front-end boards:

OTIS TDC chip

A.Berkien

H.Deppe U.Stange

Services:

TFC:

TTCrx + Rst Decoder → LVDS Signals → modules

ECS:

SPECS Slave → I2C bus lines → modules

→ JTAG → ADCs → LV sensing

Low Voltage:

passive +/- 5V distribution → modules

High Voltage:

passive distribution → 2 connections/modules

Service Box

1 service box / 2-stereo-layer quadrant:

→ 4 x 2 x 3 = 24 Service Boxes T.Sluijk, A.Zwart

ECS: Expected Data Volume

I2C: OTIS Initialization 8 Byte/OTIS at start-up

32 Byte/module

576 Byte/service-box

GOL Initialization 4 Byte/GOL at start-up

72 Byte/service-box

JTAG: LV/Tmp readout 4 (20) Byte/ADC ~1/min (start)

18 ALICE ADCs 72 (360) Byte/service-box

From OTIS to L1 Buffer

1.28 (1.6) Gbits/s

Trigger

GOL

Module

OTIS

32 bits

optical link

GOL

Module

OTIS

32 bits

GOL

Module

OTIS

32 bits

1 2 3 4 5 6 7 8 9

101112

DAQ

L1 Buffer

PreProc for L1 Trig

L1 Buffering and zero

suppression<15 MB/s

Total data volume:

• 432 opt links → 36 L1 boards

• total data flow at 40 KHz: 380 MB/s

<100 MB/s

Test bench for optical link

TI TLK2501 evaluation boardGOL Test board: GOL + VCSEL

GOL

STRATOS optical transceiver

VCSEL

Error rate < 10-13A.Rausch, D.Wiedner

Common

proje

ct

Velo, IT

, OT

Outer Tracker

L1 Buffer Board:

G.Haefeli et al.

OT Receiver:

O-RxCard

A.Rausch, D.Wiedner

PP FPGA

PP FPGA

PP FPGA

PP FPGA

Sync FPGAOccup. Data/event

2% (av.) 155 bit

4% (max) 278 bit

Hit mask 416 bit

3 GOL = 12 OTIS = 384 Ch

L1T fragment link:

@1.

1MH

z

Occup. Data/link tot evnt

0% 204 Byte 7.3 kByte

2% (av.) 266 Byte 9.6 kByte

4 %(max) 328 Byte 11.8 kByte

DAQ Link: 10.6 MByte/s @ 40kHz (2%)L1T Link: 680 Mbit/s

@ 1.1MHz (2%)

L1T/DAQ Data size:

x 36

Outer Tracker Electronics: Time Schedule

2004 20052003

07/03 Validation of OTIS baseline

10/03 Delivery of OTIS1.1

06/04 Pre-series finished: start mounting

01/05 Delivery of OTIS1.2

03/05 Start Mass Prod

03/04 Start pre-series production