Outline - Auburn Universitystrouce/class/elec4200/FPGAs.pdf · Programmable systemProgrammable system--oonn--chip chip. Programming Technologies PLAs were mask programmable ... FPGA

OutlineOutline��Field Programmable Gate ArraysField Programmable Gate Arrays

��Historical perspectiveHistorical perspective

��Programming TechnologiesProgramming Technologies��ArchitecturesArchitectures

��PALs, PLDs, and CPLDsPALs, PLDs, and CPLDs

C. Stroud 8/06 FPGAs 1

��PALs, PLDs, and CPLDsPALs, PLDs, and CPLDs��FPGAsFPGAs

��Programmable logicProgrammable logic��Interconnect networkInterconnect network��I/O buffersI/O buffers��Specialized coresSpecialized cores

��Programming InterfacesProgramming Interfaces

HistoryHistory��Programmable Logic Arrays ~ 1970Programmable Logic Arrays ~ 1970

��Implement any set of sumImplement any set of sum--ofof--products logic equationsproducts logic equations��Incorporated in VLSI devicesIncorporated in VLSI devices

��Programmable Logic Devices ~ 1980Programmable Logic Devices ~ 1980��MMI Programmable Array Logic (PAL)MMI Programmable Array Logic (PAL)

��16L8 16L8 –– combinational logic onlycombinational logic only��16R8 16R8 –– sequential logic onlysequential logic only


��16R8 16R8 –– sequential logic onlysequential logic only��AMD 22V10 and Lattice 16V8AMD 22V10 and Lattice 16V8��Complex PLDs Complex PLDs –– arrays of PLDs with routing networkarrays of PLDs with routing network

��Field Programmable Gate Arrays ~ 1985Field Programmable Gate Arrays ~ 1985��Xilinx Logic Cell Array (LCA)Xilinx Logic Cell Array (LCA)

��CPLD & FPGA architectures became similar ~2000CPLD & FPGA architectures became similar ~2000��Incorporation of RAMs and other specialized coresIncorporation of RAMs and other specialized cores

��Programmable systemProgrammable system--onon--chipchip

Programming TechnologiesProgramming Technologies��PLAs were mask programmablePLAs were mask programmable��PALs used fuses for programmingPALs used fuses for programming��Early PLDs & CPLDs used floating gate Early PLDs & CPLDs used floating gate

technologytechnology��Erasable Programmable Read Only Memory Erasable Programmable Read Only Memory

(EPROM)(EPROM)��UltraUltra--violet erasable (UVEPROM)violet erasable (UVEPROM)


��UltraUltra--violet erasable (UVEPROM)violet erasable (UVEPROM)��Electrically erasable (EEPROM)Electrically erasable (EEPROM)��Flash memory came later and was used for CPLDsFlash memory came later and was used for CPLDs

��FPGAs used RAM for programmingFPGAs used RAM for programming��Later trendsLater trends

��Fuses were replaced with antiFuses were replaced with anti--fusesfuses��Better reliabilityBetter reliability

��Large CPLDs went to RAMLarge CPLDs went to RAM--based programmingbased programming

Programming TechnologiesProgramming Technologies��RAMRAM

��Volatile Volatile –– must configure after powermust configure after power--upup��InIn--System ReSystem Re--programmable (ISR)programmable (ISR)��RunRun--Time Reconfiguration (RTR)Time Reconfiguration (RTR)

��dynamic reconfiguration while system is operatingdynamic reconfiguration while system is operating

��Floating gate technologiesFloating gate technologies��NonNon--volatile but revolatile but re--usableusable


��NonNon--volatile but revolatile but re--usableusable��UV EPROM, EEPROM, and flash memoryUV EPROM, EEPROM, and flash memory

��InIn--System Programmable (ISP)System Programmable (ISP)��EEPROM and flash memoryEEPROM and flash memory

��InIn--System ReSystem Re--programmable (ISR)programmable (ISR)��Flash memoryFlash memory

��Fuse/antiFuse/anti--fusefuse��NonNon--volatile but not revolatile but not re--usableusable��One Time Programmable (OTP)One Time Programmable (OTP)

PALsPALs16L8 16L8 –– combinational logiccombinational logic�� 10 to 16 inputs, each with 10 to 16 inputs, each with

true and complement true and complement signalsignal

�� 2 to 8 outputs, each with2 to 8 outputs, each with�� 7 product terms can AND 7 product terms can AND

any of up to 16 inputs or any of up to 16 inputs or


their complementstheir complements�� TriTri--state control product state control product

term for inverting output term for inverting output bufferbuffer��When output in triWhen output in tri--state, state,

I/O pin can be used as I/O pin can be used as inputinput�� High impedance High impedance

output with no signal output with no signal drivendriven

PALsPALs16R8 16R8 –– sequential logicsequential logic�� 8 inputs, each with true & 8 inputs, each with true &

complementcomplement�� 8 outputs, each with8 outputs, each with

��D flipD flip--flopflop��With feedback for FSMsWith feedback for FSMs

��8 product terms that can 8 product terms that can AND any of:AND any of:


AND any of:AND any of:��8 inputs or their 8 inputs or their

complementscomplements��8 feedbacks or their 8 feedbacks or their

complements from D flipcomplements from D flip--flopsflops

�� One clock for all FFsOne clock for all FFs�� One triOne tri--state control for all state control for all

outputsoutputs

PLDsPLDs22V10 replaced all PALs22V10 replaced all PALs�� Combinational and/or Combinational and/or

sequential logicsequential logic�� Macrocell program bits C0, C1Macrocell program bits C0, C1

�� Up to 22 inputs w/complementUp to 22 inputs w/complement�� Up to 10 outputs, each withUp to 10 outputs, each with

�� MacrocellMacrocell�� 88--16 product terms16 product terms�� TriTri--state control product termstate control product term


�� TriTri--state control product termstate control product term�� GlobalGlobal

�� preset & clear PTspreset & clear PTs�� clockclock

PLDsPLDs��16V816V8��Up to 16 inputs (bit & bitbar)Up to 16 inputs (bit & bitbar)��Up to 8 outputs, each withUp to 8 outputs, each with

��8 product terms (PTs), or8 product terms (PTs), or��7 with tri7 with tri--state control (PT)state control (PT)��Macrocell similar to 22V10Macrocell similar to 22V10

��More programming options More programming options ��Ability to select adjacent pinAbility to select adjacent pin

��Allows embedded registersAllows embedded registers


CPLDsCPLDsCypress Semiconductor 374 CPLD Architecture

84-pin package w/~6 Vcc and 8 Gnd pins36 inputs to AND-plane w/84 PTs and partially programmable OR-plane


CPLDsCPLDs�� An array of PLDsAn array of PLDs

�� Global routing resources Global routing resources for connectionsfor connections�� PLDs to other PLDsPLDs to other PLDs�� PLDs to/from I/O pinsPLDs to/from I/O pins

�� Example: Cypress 39KExample: Cypress 39K�� Each Logic Block (LB) Each Logic Block (LB)

similar to a 22V10similar to a 22V10

I/O Block

4096 bitRAM

Dual-PortFIFO

LB

PIM

8192 bitRAM

LB

LB

LB

LB

8192 bitRAM

LB

LB

LB

I/O B

lock

I/O B

lock

I/O Block

4096 bitRAM

Dual-PortFIFO

LB

PIM

8192 bitRAM

LB

LB

LB

LB

8192 bitRAM

LB

LB

LB

I/O Block

4096 bitRAM

Dual-PortFIFO

LB

PIM

8192 bitRAM

LB

LB

LB

LB

8192 bitRAM

LB

LB

LB

GCLK[3:0]

GCLK[3:0]


similar to a 22V10similar to a 22V10�� Each cluster of 8 LBs Each cluster of 8 LBs

has two 8K RAMs & one has two 8K RAMs & one 4K dual4K dual--port RAM/FIFOport RAM/FIFO�� Programmable Programmable

Interconnect Modules Interconnect Modules (PIMs) provide (PIMs) provide interconnectionsinterconnections

�� Array of up to 24 Array of up to 24 clusters with global clusters with global routingrouting

4096 bitRAM

Dual-PortFIFO

LB

PIM

8192 bitRAM

LB

LB

LB

LB

8192 bitRAM

LB

LB

LBI/O

Blo

ck

I/O B

lock

4096 bitRAM

Dual-PortFIFO

LB

PIM

8192 bitRAM

LB

LB

LB

LB

8192 bitRAM

LB

LB

LB

4096 bitRAM

Dual-PortFIFO

LB

PIM

8192 bitRAM

LB

LB

LB

LB

8192 bitRAM

LB

LB

LB

I/O Block I/O Block I/O Block

GCLK[3:0]

CNTL[3:0]4

4

8

PLLs &Clock Mux

Ranges of ResourcesRanges of Resources

FPGA ResourceFPGA Resource Small FPGASmall FPGA Large FPGALarge FPGA

LogicLogicPLBs per FPGAPLBs per FPGA 256256 25,92025,920

LUTs and flipLUTs and flip--flops per PLBflops per PLB 11 88

RoutingRoutingWire segments per PLBWire segments per PLB 4545 406406

PIPs per PLBPIPs per PLB 139139 3,4623,462


RoutingRoutingPIPs per PLBPIPs per PLB 139139 3,4623,462

SpecializedSpecializedCoresCores

Bits per memory coreBits per memory core 128128 36,86436,864

Memory cores per FPGAMemory cores per FPGA 1616 576576

DSP coresDSP cores 00 512512

OtherOtherInput/output cellsInput/output cells 6262 1,2001,200

Configuration memory bitsConfiguration memory bits 42,10442,104 79,704,83279,704,832

Basic PLB ArchitectureBasic PLB Architecture��LookLook--up Table (LUT) implements truth tableup Table (LUT) implements truth table��Memory elements:Memory elements:

��FlipFlip--flop/latchflop/latch��Some FPGAs Some FPGAs -- LUTs can also implement small LUTs can also implement small

RAMsRAMs


RAMsRAMs

��Carry & control logic implements fast Carry & control logic implements fast adders/subtractorsadders/subtractors

carry in

LUT/RAM Carry &

ControlLogic

Flip-flop/Latch

4

carry out

3

Control

OutputQ output

Input[1:4]

clock, enable, set/reset

A Simple PLBA Simple PLB�� Two 3Two 3--input LUTsinput LUTs

�� Can implement any Can implement any 44--input combinational input combinational logic functionlogic function

�� 1 flip1 flip--flopflop�� Programmable:Programmable:

�� Active levelsActive levels�� Clock edgeClock edge

C0C1C2C3C4C5C6C7

111 110 101 100 011 010 001 000D2-0

outLUTCoutLUT C

8x1


�� Clock edgeClock edge�� Set/resetSet/reset

�� 22 configuration 22 configuration memory bitsmemory bits�� 8 per LUT8 per LUT

�� C0C0--77�� S0S0--77

�� 6 controls6 controls�� CB0CB0--77

D2-0

D3

FF

CB4

Clock

Set/Reset

Sout01

CB3

01

01

01

Clock Enable

CB = ConfigurationMemory Bit

Smux

CEmux SRmux

SOmux

CB5

CB1CB0 CB2

8x1

LUT S8x1

3

Combinational Logic FucntionsCombinational Logic Fucntions��Gates are combined to Gates are combined to

create complex circuitscreate complex circuits��Multiplexer exampleMultiplexer example

��If S = 0, Z = AIf S = 0, Z = A��If S = 1, Z = BIf S = 1, Z = B

A

S

B

Z

Truth table


��If S = 1, Z = BIf S = 1, Z = B��Very common digital Very common digital

circuitcircuit��Heavily used in FPGAsHeavily used in FPGAs

��S input controlled by S input controlled by configuration memory bitconfiguration memory bit

��We’ll see it againWe’ll see it again

0

1

A

B

S

Z

Logic symbol

01

S A B Z0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 01 0 1 11 1 0 01 1 1 1

Truth table

LookLook--up Tablesup Tables��Recall multiplexer Recall multiplexer

exampleexample��Configuration Configuration

memory holds memory holds outputs for truth outputs for truth tabletable

��Internal signals Internal signals

0

1

A

B

S

Z

Multiplexer

S A B Z0 0 0 0

Truth table0 Z

0

1

0

1

0

1

0

0

1

1

1


��Internal signals Internal signals connect to control connect to control signals of signals of multiplexers to multiplexers to select value of select value of truth table for any truth table for any given input valuegiven input value

0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 01 0 1 11 1 0 01 1 1 1

B A S

1

0

1

0

1

0

1

0

1

0

1

1 0 1

1

Data In

Add

ress

Dec

oder

In0

In1

ck0

ck1

ck2

ck3

LookLook--up Table Based RAMsup Table Based RAMs��Normal LUT mode Normal LUT mode

performs read performs read operationsoperations

��Address decoder Address decoder with write enable with write enable 0 Z

0

1

0

1

0

1

0

0

1

1


Add

ress

Dec

oder

WriteEnable

In2 ck4

ck5

ck6

ck7

with write enable with write enable generates clock generates clock signals to latches signals to latches for write operationsfor write operations

��Small RAMs but Small RAMs but can be combined can be combined for larger RAMsfor larger RAMs

In0 In1 In2

1

0

1

0

1

0

1

0

1

0

1

Interconnect NetworkInterconnect Network��Wire segments of varying lengthWire segments of varying length

��xxNN = = NN PLBs in lengthPLBs in length��1, 2, 4, and 6 are most common1, 2, 4, and 6 are most common

��xH = half the array in lengthxH = half the array in length��xL = length of full arrayxL = length of full array

��Programmable Interconnect Points (PIPs)Programmable Interconnect Points (PIPs)


��Programmable Interconnect Points (PIPs)Programmable Interconnect Points (PIPs)��Also known as Configurable Interconnect Points (CIPs)Also known as Configurable Interconnect Points (CIPs)

��Transmission gate connects to 2 wire segmentsTransmission gate connects to 2 wire segments��Controlled by configuration memory bitControlled by configuration memory bit

��0 = wires disconnected0 = wires disconnected��1 = wires connected1 = wires connected

configbit

Wire A

Wire B

PIPsPIPs��BreakBreak--point PIPpoint PIP

��Connect or isolate 2 wire segmentsConnect or isolate 2 wire segments

��CrossCross--point PIPpoint PIP��Turn cornersTurn corners

��Multiplexer PIPMultiplexer PIP��Directional and bufferedDirectional and buffered


��Directional and bufferedDirectional and buffered��Select 1Select 1--ofof--NN inputs for outputinputs for output

��Decoded MUX PIP Decoded MUX PIP –– NN config bits select from 2config bits select from 2NN inputsinputs��NonNon--decoded MUX PIP decoded MUX PIP –– 1 config bit per input1 config bit per input

��Compound crossCompound cross--point PIPpoint PIP��Collection of 6 breakCollection of 6 break--point PIPspoint PIPs

��Can route to two isolated signal netsCan route to two isolated signal nets

Spartan 3 Routing ResourcesSpartan 3 Routing Resources

PLB consistsof 4 slices

switch matrixover 2,400 PIPs

mostly MUX PIPs

x6 wiresegments


x2 wiresegments

xH & xL wiresegments

over 450total wire

segmentsin PLB

FPGAsFPGAs��Recent trend Recent trend -- incorporate specialized coresincorporate specialized cores

��RAMs RAMs –– singlesingle--port, dualport, dual--port, FIFOsport, FIFOs��128 bits to 36K bits per RAM128 bits to 36K bits per RAM��4 to 575 per FPGA4 to 575 per FPGA

��DSPs DSPs –– 18x1818x18--bit multiplier, 48bit multiplier, 48--bit accumulator, bit accumulator, etc.etc.


etc.etc.��up to 512 per FPGAup to 512 per FPGA

��Microprocessors and/or microcontrollersMicroprocessors and/or microcontrollers��up to 2 per FPGAup to 2 per FPGA

��Hard core processorHard core processor

��Support soft core processorsSupport soft core processors��Synthesized from HDL into programmable resourcesSynthesized from HDL into programmable resources

FPGA ArchitecturesFPGA Architectures��4000/Spartan4000/Spartan

�� NNxxNN array of unit cellsarray of unit cells��Unit cell = CLB + routingUnit cell = CLB + routing

�� Special routing along center axesSpecial routing along center axes�� I/O cells around perimeterI/O cells around perimeter

��Virtex/SpartanVirtex/Spartan--22�� MMxxNN array of unit cellsarray of unit cells


�� MMxxNN array of unit cellsarray of unit cells�� Added block 4K RAMs at edgesAdded block 4K RAMs at edges

��VirtexVirtex--2/Spartan2/Spartan--33�� Block 18K RAMs in arrayBlock 18K RAMs in array�� Added 18x18 multipliers with each RAMAdded 18x18 multipliers with each RAM�� Added PowerPCs in VirtexAdded PowerPCs in Virtex--2 Pro2 Pro

��VirtexVirtex--4/Virtex4/Virtex--55�� Added 48Added 48--bit DSP cores w/multipliersbit DSP cores w/multipliers�� I/O cells along columns for BGAI/O cells along columns for BGA

PC PC

PC

PC

Specialized CoresSpecialized Cores

250

300

350

400

450R

AM

s/m

ult

iplier

s

Virtex and Spartan II Virtex II and Spartan 3


0

50

100

150

200

2S15

2S30

2S50

2S10

02S

150

2S20

0V

50V

100

V15

0V

200

V30

0V

400

V60

0V

800

V10

003S

503S

200

3S40

03S

1000

3S15

003S

2000

3S40

003S

5000

2V40

2V80

2V25

02V

500

2V10

002V

1500

2V20

002V

3000

2V40

002V

6000

2V80

002V

P2

2VP

42V

P7

2VP

202V

PX

202V

P30

2VP

402V

P50

2VP

702V

PX

702V

P10

0

RA

Ms/

mu

ltip

lier

s

4K-bit RAMs 18K-bit RAMs and 18×18-bit multipliers

Virtex and Spartan II Virtex II and Spartan 3

Programmable RAMsProgrammable RAMs��18 Kbit dual18 Kbit dual--port RAMport RAM��Each port independently configurable asEach port independently configurable as

��512 words x 36 bits512 words x 36 bits��32 data bits + 4 parity bits32 data bits + 4 parity bits

��1K words x 18 bits1K words x 18 bits��16 data bits + 2 parity bits16 data bits + 2 parity bits

��2K words x 9 bits2K words x 9 bits


��2K words x 9 bits2K words x 9 bits��8 data bits + 1 parity bit8 data bits + 1 parity bit

��4K words x 4 bits (no parity)4K words x 4 bits (no parity)��8K words x 2 bits (no parity)8K words x 2 bits (no parity)��16K words x 1 bit (no parity)16K words x 1 bit (no parity)

��Each port has independently programmableEach port has independently programmable��clock edgeclock edge��active levels for write enable, RAM enable, resetactive levels for write enable, RAM enable, reset

Specialized CoresSpecialized Cores

300

400

500

600C

ore

s

18K bit RAMsXtreme DSPs


0

100

200

4VLX

15

4VLX

25

4VLX

40

4VLX

60

4VLX

80

4VLX

100

4VLX

160

4VLX

200

4VS

X25

4VS

X35

4VS

X55

4VF

X12

4VF

X20

4VF

X40

4VF

X60

4VF

X10

0

4VF

X14

0

Virtex 4

Co

res

FPGA Configuration MemorysFPGA Configuration Memorys��PLB addressablePLB addressable

��Good for partial reconfigurationGood for partial reconfiguration��XX--Y coordinates of PLB location to be writtenY coordinates of PLB location to be written

��Requires tag to identify which resources will be Requires tag to identify which resources will be configuredconfigured

��Frame addressableFrame addressable


��Frame addressableFrame addressable��Vertical or horizontal frameVertical or horizontal frame��Access to all PLBs in frameAccess to all PLBs in frame

��Only portion of logic and routing resources Only portion of logic and routing resources accessible in a given frameaccessible in a given frame

��Many frames to configure PLBsMany frames to configure PLBs��Major address for column, minor address for frameMajor address for column, minor address for frame

Frame LengthFrame LengthN

umbe

r of

32

Num

ber

of 3

2--bi

t wor

ds p

er fr

ame

bit w

ords

per

fram

e

200

250

300

350

Very large frame lengthsVery large frame lengthsfor large devicesfor large devices

Day #1 FPGA Verfication Course 26

Num

ber

of 3

2N

umbe

r of

32

0

50

100

150

XC2S

15

XC2S

30

XC2S

50/V

50/E

XC2S

100/

V10

0

XC2S

150/

V15

0

XCV20

0/E

XCV30

0/E

XCV40

0/E/4

05

XCV60

0/E

XCV80

0/81

2E

XCV10

00/E

XCV16

00E

XCV20

00E

XCV26

00E

XCV32

00E

XC2V

P2

XC2V

P4

XC2V

P7

XC2V

P20

/X

XC2V

P30

XC2V

P40

XC2V

P50

XC2V

P70

/X

XC2V

P10

0

XC3S

50

XC3S

200

XC3S

400

XC3S

1000

XC3S

1500

XC3S

2000

XC3S

4000

XC3S

5000

Frames vs. Column TypeFrames vs. Column TypeN

umbe

r of

Fra

mes

Num

ber

of F

ram

es

40

50

60

70

80

Virtex1/Spartan2Virtex2proSpartan3Virtex4


Num

ber

of F

ram

esN

umbe

r of

Fra

mes

0

10

20

30

40

CLB IOB/TERM IOI/DSP RAMrouting RAMcontent center

VirtexVirtex--4 Architectures4 Architectures


PowerPClocation

Tile Map for VirtexTile Map for Virtex--4 LX154 LX15

IOBsIOBs

CLBsCLBs

RAMsRAMs

DSPsDSPs

centercenter

Tile coordinatesTile coordinates

C. Stroud 8/06 FPGAs 29XDL coordinatesXDL coordinates

Configuration MemoryConfiguration Memory�� Frame orderFrame order

�� CLBs, IOBs, DSPs, & center CLBs, IOBs, DSPs, & center column form main portioncolumn form main portion

�� BRAMs come afterBRAMs come after

�� Frames span 16 rows (Frames span 16 rows (V5=20V5=20))�� 2.5 words per row (2.5 words per row (V5=2V5=2))�� All columns have INT switch box All columns have INT switch box

routingroutingN1 2 3

2NN+1 N+2 N+3

XN+NXN+1 XN+2 XN+3

(X+1)N(X+1)N (X+1)N (X+1)N


routingrouting�� 3,312 PIPs 3,312 PIPs ≈≈ first 18.5 framesfirst 18.5 frames

�� Total frames/columnTotal frames/column�� CLBs = 22 framesCLBs = 22 frames�� DSPs = 21 columnsDSPs = 21 columns�� Center column = 33 framesCenter column = 33 frames�� IOBs = 30 framesIOBs = 30 frames

�� Left & right cols in LX & SXLeft & right cols in LX & SX

�� BRAMs & GTs = 20 framesBRAMs & GTs = 20 frames�� 2 frames at end of row2 frames at end of row

(X+1)N+N

(X+1)N+1

(X+1)N+2

(X+1)N+3

(X+2)N+N

(X+2)N+1

(X+2)N+2

(X+2)N+3

(2X+1)N+N

(2X+1)N+1

(2X+1)N+2

(2X+1)N+3

N N = # columns= # columnsX X = (# rows/16)= (# rows/16)--11

VirtexVirtex--5 Architectures5 Architectures��Similar architecture, Similar architecture, frame structure and orderframe structure and order

��I/O cells not along outside column on right sideI/O cells not along outside column on right side��“Center” column (Xs) not in center of array“Center” column (Xs) not in center of array

��More columns to right side of “center” columnMore columns to right side of “center” column

��Similar top/bottom and config row formatSimilar top/bottom and config row format��41 words (3241 words (32--bit) per framebit) per frame

��Hamming bits in middle word of frameHamming bits in middle word of frame


partpart #rows#rows LX & LXT Legend3030 8080 O 4 R 2 D 8 X 8 R 4 O 4 T C #=#CLBcols5050 120120 O 4 R 2 D 8 X 8 R 4 O 4 T C D=DSPs8585 120120 O 4 R10R 2 D 8 X12R10R 4 O 4 T C R=RAMs

110110 160160 O 4 R10R 2 D 8 X12R10R 4 O 4 T C O=I/O cells220220 160160 O 4 R22R 2 D 2 D 2 R20 X20R 6 R22R 4 O 4 T C X=IO&DCM330330 240240 O 4 R22R 2 D 2 D 2 R20 X20R 6 R22R 4 O 4 T C T/C=T only

SXT3535 8080 O 4 R 2 D 2 D 2 R 2 D 2 D 2 R 2 X 2 R 2 D 2 D 2 R 4 O 4 T C5050 120120 O 4 R 2 D 2 D 2 R 2 D 2 D 2 R 2 X 2 R 2 D 2 D 2 R 4 O 4 T C95 O 4 R 2 D 2 D 2 R 2 D 2 D 2 R 2 D 2 D 2 R 2 X 2 R 2 D 2 D 2 R 2 D 2 D 2 R 4 O 4 T C

160

��Hamming bits in middle word of frameHamming bits in middle word of frame

VirtexVirtex--5 FX30T5 FX30T��5,120 slices5,120 slices

��4 FFs & 64 FFs & 6--input LUTsinput LUTs

��68 DPRAMs/FIFOs68 DPRAMs/FIFOs��36Kbits36Kbits

��64 DSPs64 DSPs��64 DSPs64 DSPs��24x18 24x18 multmult & 48& 48--bit ALUbit ALU

��1 PowerPC 4401 PowerPC 440��1 PCI Express1 PCI Express��4 Ethernet MACs4 Ethernet MACs��8 Gigabit 8 Gigabit XceiversXceivers


FPGA Configuration MemorysFPGA Configuration Memorys��PLB addressablePLB addressable

��Good for partial reconfigurationGood for partial reconfiguration��XX--Y coordinates of PLB location to be writtenY coordinates of PLB location to be written

��Requires tag to identify which resources will be Requires tag to identify which resources will be configuredconfigured

��Frame addressableFrame addressable


��Frame addressableFrame addressable��Vertical or horizontal frameVertical or horizontal frame��Access to all PLBs in frameAccess to all PLBs in frame

��Only portion of logic and routing resources Only portion of logic and routing resources accessible in a given frameaccessible in a given frame

��Many frames to configure PLBsMany frames to configure PLBs��Major address for column, minor address for frameMajor address for column, minor address for frame

Hybridi.e.:

Virtex-4Virtex-5Virtex-6

Tile Map for VirtexTile Map for Virtex--4 LX154 LX15

IOBsIOBs

CLBsCLBs

RAMsRAMs

DSPsDSPs

centercenter

Tile coordinatesTile coordinates

C. Stroud 8/06 FPGAs 34XDL coordinatesXDL coordinates

Configuration InterfacesConfiguration Interfaces�� Master Master –– FPGA retrieves its own configuration from FPGA retrieves its own configuration from

ROM after powerROM after power--upup�� Serial or Parallel optionsSerial or Parallel options

�� Slave Slave –– FPGA configured by external source (i.e., a FPGA configured by external source (i.e., a µµP)P)�� Serial or Parallel optionsSerial or Parallel options�� Used for dynamic reconfigurationUsed for dynamic reconfiguration�� Can also read configuration memory contentsCan also read configuration memory contents

�� Boundary Scan InterfaceBoundary Scan Interface

clock

PROM withConfiguration

Data

data out

CCLK

FPGA inMasterMode

Din Dout

CCLK

FPGA inSlaveMode

Din Dout

CCLK

FPGA inSlaveMode

Din Dout


�� Boundary Scan InterfaceBoundary Scan Interface�� 44--wire IEEE standard serial interface for testingwire IEEE standard serial interface for testing�� Write and read access to configuration memoryWrite and read access to configuration memory

�� Not available in all FPGAsNot available in all FPGAs�� Used for dynamic partial reconfigurationUsed for dynamic partial reconfiguration

�� Interfaces to FPGA coreInterfaces to FPGA core�� Not available in all FPGAsNot available in all FPGAs�� Connections between Boundary Scan Interface and internal routing Connections between Boundary Scan Interface and internal routing

network and PLBs (Xilinx provides 2network and PLBs (Xilinx provides 2--4 of these ports)4 of these ports)

�� Other configuration interfaces in some FPGAsOther configuration interfaces in some FPGAs

Xilinx Configuration Interface PinsXilinx Configuration Interface Pins


Spartan Spartan 3 3

Master Master ModesModes


Master modeMaster mode��Configuration Configuration

sequence during sequence during powerpower--up of deviceup of device��Typically fromTypically from

��Serial EPROMSerial EPROM��Master SerialMaster Serial


��Master SerialMaster Serial��Parallel EPROMParallel EPROM

��Master ParallelMaster Parallel�� 88--bitbit�� 3232--bitbit

Spartan 3 Slave ConfigurationSpartan 3 Slave Configuration


Spartan 3 Spartan 3 Daisy Daisy

ChainsChains


Configuration TechniquesConfiguration Techniques��Full configuration & readbackFull configuration & readback

��Simple configuration interfaceSimple configuration interface��Internal automatic calculation of frame addressInternal automatic calculation of frame address

��Long download time for large FPGAsLong download time for large FPGAs

��Partial reconfiguration & readbackPartial reconfiguration & readback��Only change portions of configuration memory with Only change portions of configuration memory with

respect to reference designrespect to reference design


respect to reference designrespect to reference design��Reduces download time for reconfigurationReduces download time for reconfiguration

��Requires more complicated interfaceRequires more complicated interface��Command Register (CMR)Command Register (CMR)��Frame Length Register (FLR)Frame Length Register (FLR)��Frame Address Register (FAR)Frame Address Register (FAR)��Frame Data RegisterFrame Data Register

�� Input (FDRI) Input (FDRI) –– for downloadfor download��Output (FDRO) Output (FDRO) –– for readback (for readback (note separate accessnote separate access))

Configuration TechniquesConfiguration Techniques��Compressed configurationCompressed configuration

��Requires multiple frame write capabilityRequires multiple frame write capability��Write identical frames of config data to multiple frame addressesWrite identical frames of config data to multiple frame addresses

��Extension of partial reconfiguration interface Extension of partial reconfiguration interface capabilitiescapabilities


��Frame address is much smaller than frame of configuration dataFrame address is much smaller than frame of configuration data

��Reduces download time for initial configuration Reduces download time for initial configuration depending ondepending on��Regularity of system function designRegularity of system function design��% utilization of array% utilization of array

��Unused portions written with default configuration dataUnused portions written with default configuration data

Full Configuration ExampleFull Configuration Example� Dummy Word 0xFFFFFFFF� Synchronize Word 0xAA995566� CMD Write 0x30008001

� Reset CRC 0x00000007� FLR Write 0x30016001

� FLR = 0x00000024�� Frame length = 37 wordsFrame length = 37 words

�� 1,184 bits 1,184 bits ÷÷ 32 bits/word32 bits/word� COR Write 0x30012001

� COR Write 0x00003FE5� IDCODE Write 0x3001C001

Xilinx ASCII BitstreamCreated by Bitstream I.32Design name: s3mod7.ncdArchitecture: spartan3Part: 3s50tq144Date: Tue Sep 04 15:50:09 2007Bits: 439264111111111111111111111111111111111010101010011001010101010110011000110000000000001000000000000001000000000000000000000000000001110011000000000001011000000000000100000000000000000000000000100100


� IDCODE Write 0x3001C001� Device ID = 0x0140D093 (3S50)

� MASK Write 0x3000C001� MASK = 0x00000000

� CMD Write 0x30008001� Switch CCLK 0x00000009

� FAR Write 0x30002001� FAR = 0x00000000 (full config)

� CMD Write 0x30008001� Write CFG 0x00000001

� FDRI Write 0x30004000� # words to write 0x50003555

000000000000000000000000001001000011000000000001001000000000000101000000000000000011111111100101001100000000000111000000000000010000000101000000110100001001001100110000000000001100000000000001000000000000000000000000000000000011000000000000100000000000000100000000000000000000000000001001001100000000000000100000000000010000000000000000000000000000000000110000000000001000000000000001000000000000000000000000000000010011000000000000010000000000000001010000000000000011010101010101start of actual configuration data

Partial Reconfiguration ExamplePartial Reconfiguration Example

� Dummy Word 0xFFFFFFFF� Synchronization Word 0xAA995566� CMD Write 0x30008001

� Reset CRC 0x00000007� IDCODE Write 0x3001C001

� Device ID = 0x0140D093 (3S50) � COR Write 0x30012001

� COR Write Packet Data 0x00003FE5� CMD Write 0x30008001

� Shutdown 0x0000000B

……Bits: Bits: 26656266561111111111111111111111111111111111111111111111111111111111111111101010101001100101010101011001101010101010011001010101010110011000110000000000001000000000000001001100000000000010000000000000010000000000000000000000000000011100000000000000000000000000000111001100000000000111000000000000010011000000000001110000000000000100000001010000001101000010010011000000010100000011010000100100110011000000000001001000000000000100110000000000010010000000000001010000000000000000111111111001010100000000000000001111111110010100110000000000001000000000000001001100000000000010000000000000010000000000000000000000000000101100000000000000000000000000001011


� Shutdown 0x0000000B� CRC Write 0x30000001

� CRC = 0x00002CE9� CMD Write 0x30008001

� AGhigh 0x00000008� CMD Write 0x30008001

� WCFG 0x00000001� FAR Write 0x30002001

� FAR = 0x00080000 (partial config)� Part Reconfig Reg Write 0x3001E001

� Null 0x00000000� FDRI Write 0x300042E4

� #words to write 0x000002E4

000000000000000000000000000010110000000000000000000000000000101100110000000000000000000000000001001100000000000000000000000000010000000000000000001011001110100100000000000000000010110011101001… 4 NOOPs 0x20000000… 4 NOOPs 0x2000000000110000000000001000000000000001001100000000000010000000000000010000000000000000000000000000100000000000000000000000000000001000001100000000000010000000000000010011000000000000100000000000000100000000000000000000000000000001000000000000000000000000000000010011000000000000001000000000000100110000000000000010000000000001000000000000100000000000000000000000000000001000000000000000000000110000000000011110000000000001001100000000000111100000000000010000000000000000000000000000000000000000000000000000000000000000… 16 NOOPs 0x20000000… 16 NOOPs 0x200000000011000000000000010001100000000000001000010111001000001011100100start of actual configuration datastart of actual configuration data

Documents

Outline - Auburn Universitystrouce/class/elec4200/FPGAs.pdf · Programmable systemProgrammable system--oonn--chip chip. Programming Technologies PLAs were mask programmable ... FPGA