22
1 FPGA Implementation of a PID Controller with DC Motor Application Members Paul Leisher Christopher Meyers Advisors Dr. Stewart Dr. Dempsey This project aims to implement a digital PID controller by means of an FPGA. This system will be used to control a DC motor (driven by a PWM signal) which has a high degree of non- linearity and serves to test the performance of the controller. Our preliminary research has primarily focused on simulating the ent ire system, although recently we have begun work on the VHDL code to program the FPGA. Upon completion of the VHDL, we will begin testing and improving the overall system. Outline Functional Description Division of Labor Matlab and Simulink Work Hardware Interfacing VHDL Work Achievements and Complications Closing

Outline - Bradley University

  • Upload
    others

  • View
    1

  • Download
    0

Embed Size (px)

Citation preview

Page 1: Outline - Bradley University

1

FPGA Implementation of a PID Controller

with DC Motor ApplicationMembers

Paul LeisherChristopher Meyers

AdvisorsDr. Stewart

Dr. Dempsey

This project aims to implement a digital PID controller by means of an FPGA. This system will be used to control a DC motor (driven by a PWM signal) which has a high degree of non-linearity and serves to test the performance of the controller. Our preliminary research has primarily focused on simulating the ent ire system, although recently we have begun work on the VHDL code to program the FPGA. Upon completion of the VHDL, we will begin testing and improving the overall system.

Outline

Functional DescriptionDivision of LaborMatlab and Simulink WorkHardware InterfacingVHDL WorkAchievements and ComplicationsClosing

Page 2: Outline - Bradley University

2

Outline

Functional DescriptionDivision of LaborMatlab and Simulink WorkHardware InterfacingVHDL WorkAchievements and ComplicationsClosing

Functional Description

This project will implement a digital “Proportional-Integral-Derivative” (or PID) controller in an existing DC motor system. The DC motor system will be controlled by a PWM signal. The system will be implemented in ‘closed’loop form, which will correct the non-linearity and unreliability of the change in loads on the DC motor.

The entire system will be programmed in VHDL, and implemented on a FPGA Development Board. This will allow the user to input a desired RPM and be able to monitor the speed of the DC motor. It will also provide an economical solution to DC motor control.

Page 3: Outline - Bradley University

3

System Inputs and Outputs

Speed Command Signal

Motor Shaft VelocitySystem Display

Inputs Outputs

System Block Diagram

Digital PID Controller

PWMSystem

DC MotorSystem

Motor Shaft

Velocity

SpeedCommand

Signal

Frequency to Digital

Page 4: Outline - Bradley University

4

Digital PID Controller

Digital PIDController

PWMCommand

Signal

ErrorSignal

•Error Signal combination of desired input and motor shaft velocity•PWM Command Signal computed based on Error signal to ensure linearity

PWM System

PWM System

PWMSignal

PWM Command

Signal

•PWM Command Signal used to create desired percent duty cycled signal

Page 5: Outline - Bradley University

5

DC Motor System

DC Motor System

MotorShaft

Velocity

PWM Signal

•PWM Signal used with hardware to control DC Motor System•Motor Shaft Velocity produced by encoder

Frequency to Digital Converter

Frequency to Digital

DigitalSpeedSignal

MotorShaft

Velocity

•Motor Shaft Velocity sent from encoder on DC motor•Digital Speed Signal is a digital representation of motor shaft velocity

Page 6: Outline - Bradley University

6

Modes of Operation

Full SpeedOff0 to 860 RPM via user

FPGA Development Board

Brett Marshall – 2000/2001 Senior Project

Page 7: Outline - Bradley University

7

Outline

Functional DescriptionDivision of LaborMatlab and Simulink WorkHardware InterfacingVHDL WorkAchievements and ComplicationsClosing

Page 8: Outline - Bradley University

8

Division of Labor

• Due to highly theoretical nature of project, most parts will be completed together.

Paul Leisher

• VHDL Framework

• VHDL Display and Encoder

• PID Controller

Christopher Meyers

• VHDL PWM Subsystem

• Hardware Interfacing

• PID Controller

Outline

Functional DescriptionDivision of LaborMatlab and Simulink WorkHardware InterfacingVHDL WorkAchievements and ComplicationsClosing

Page 9: Outline - Bradley University

9

Matlab Design Program

Shows uncompensated system plotsShows compensated system plotsDetermine Digital PID Controller coefficients

Simulink System Model

Page 10: Outline - Bradley University

10

Outline

Functional DescriptionDivision of LaborMatlab and Simulink WorkHardware InterfacingVHDL WorkAchievements and ComplicationsClosing

Hardware Interface

Hardware was needed to? Interface FPGA to motor? Protect FPGA Development Board

Page 11: Outline - Bradley University

11

Hardware Block Diagram

FPGABoard

Motor

Hardware Interface

PowerTransistor

LogicIsolator

Outline

Functional DescriptionDivision of LaborMatlab and Simulink WorkHardware InterfacingVHDL WorkAchievements and ComplicationsClosing

Page 12: Outline - Bradley University

12

VHDL Work

PWM SystemEncoder to 7-bit numberPID SystemDisplay SystemError Signal & Command Input System

VHDL Work

PWM SystemEncoder to 7-bit numberPID SystemDisplay SystemError Signal & Command Input System

Page 13: Outline - Bradley University

13

PWM System

Receives a number from the PID controller between 0-128 (7-bits)Uses internal counters along with the clock input to determine the PWM signal, by number comparisonIncludes out of range checks

PWM System

INPUTS7-BIT Unsigned NumberClockNegative Trigger

OUTPUTSPulse Width Modulated Signal

Page 14: Outline - Bradley University

14

PWM System

ProblemsUsage of an External Clock? Solution

Designed a VHDL block to divide an internal clock signal

PWM System Schematic

PWMBlock

InternalFPGAClock

ClockDivider

CLK8MHz

OutputPWM Signal

NegativeTrigger from

PID Controller

7-bitInput

Page 15: Outline - Bradley University

15

VHDL Work

PWM SystemEncoder to 7-bit numberPID SystemDisplay SystemError Signal & Command Input System

Encoder to 7-Bit Number System

This system converts the rotary encoder output of the motor (512 pulses per revolution) to a 7 bit number (0 to 86) where that number is one-tenth the speed of the motor shaft in RPM.Because the system sampling frequency is 500 Hz, this system is not fully accurate.

Page 16: Outline - Bradley University

16

Encoder to 7-Bit Number System

Divide Down

Counter

100 MHzOscillator

MotorEncoderOutput

Fs(500 Hz)

SRPM/10(7-Bit)

Encoder to 7-Bit Number System

This system works by counting the number of pulses that occur within T=2ms (fs=500Hz).This system is not performing well enough for our application.This system will be redesigned to measure pulse duration rather than to count pulses.This redesign will improve resolution, and hopefully, system performance.

Page 17: Outline - Bradley University

17

VHDL Work

PWM SystemEncoder to 7-bit numberPID SystemDisplay SystemError Signal & Command Input System

PID System

First tried proportional control only? Results were “ok”? Results did not correlate very well to Simulink

results, however, the general property of increasing proportional gain decreases steady-state error was observed

Tried very basic PI controller? Results were horribleWork on PID system halted until Encoder-to-RPM block is redesigned.

Page 18: Outline - Bradley University

18

VHDL Work

PWM SystemEncoder to 7-bit numberPID SystemDisplay SystemError Signal & Command Input System

Display System

This system allows for the display of either the current command input signal or the current motor speed (both in RPM).The user can switch between either display by means of an onboard toggle.This system utilizes three of the four onboard seven-segment displays.This system was rewritten so LED refresh rate is fast, but RPM displayed is ~1 sec. (This serves to allow the user to read the display more easily).

Page 19: Outline - Bradley University

19

VHDL Work

PWM SystemEncoder to 7-bit numberPID SystemDisplay SystemError Signal & Command Input System

Error Signal & Command Input System

This system simply takes the input command from the toggles and subtracts off the output of the Encoder-to-RPM block to make an “error signal.”

Speed Command(7 bit unsigned)

Error Signal(8 bit signed)

Current Motor Speed(7 bit unsigned)

Page 20: Outline - Bradley University

20

Outline

Functional DescriptionDivision of LaborMatlab and Simulink WorkHardware InterfacingVHDL WorkAchievements and ComplicationsClosing

Complications

Low resolution from Encoder-to-RPM block is proving to be quite a problem.Proportional control does not correlate very well to Simulink results.Preliminary PID controller does not work.Lack of one “central” computer to do all work at has slowed progress considerably.

Page 21: Outline - Bradley University

21

Achievements

All preliminary VHDL is working.Hardware design is completed.Motor runs!

Outline

Functional DescriptionDivision of LaborMatlab and Simulink WorkHardware InterfacingVHDL WorkAchievements and ComplicationsClosing

Page 22: Outline - Bradley University

22

Closing

We are on schedule.? Motor is running.? All systems have been designed.? In the “test and redesign” phase of project

We don’t foresee any more obstacles that will prevent us from completing the project successfully.

Questions?