Overview of Chapter 5

° Circuits require memory to store intermediate data

° Sequential circuits use a periodic signal to determine when to store values.

• A clock signal can determine storage times

• Clock signals are periodic

° Single bit storage element is a flip flop

° A basic type of flip flop is a latch

° Latches are made from logic gates• NAND, NOR, AND, OR, Inverter

The story so far ...

° Logical operations which respond to combinations of inputs to produce an output. • Call these combinational logic circuits.

° For example, can add two numbers. But:• No way of adding two numbers, then adding a third (a

sequential operation);

• No way of remembering or storing information after inputs have been removed.

° To handle this, we need sequential logic capable of storing intermediate (and final) results.

Sequential Circuits

Combinational circuit Flip

Flops

OutputsInputs

Nextstate Present

state

Timing signal (clock)

Clock

Clock

a periodic external event (input)

Clock

a periodic external event (input)

synchronizes when current state changes happen keeps system well-behaved

makes it easier to design and build large systems

synchronizes when current state changes happen keeps system well-behaved

makes it easier to design and build large systems

Cross-coupled Inverters

0

1

1

0

State 1 State 2

° A stable value can be stored at inverter outputs

S-R Latch with NORs

1 11 00 10 0

S R Q Q’

0 1

1 0 Set

1 0 Stable

0 1 Reset

0 0 Undefined

R (reset)

Q

Q

S (set)

° S-R latch made from cross-coupled NORs

° If Q = 1, set state

° If Q = 0, reset state

° Usually S=0 and R=0

° S=1 and R=1 generates unpredictable results

S-R Latch with NANDs

S

R

Q

Q’

0 00 11 01 1

S R Q Q’

0 1

1 0 Set

1 0 Store

0 1 Reset

1 1 Disallowed

° Latch made from cross-coupled NANDs

° Sometimes called S’-R’ latch

° Usually S=1 and R=1

° S=0 and R=0 generates unpredictable results

S-R Latches

S-R Latch with control input

° Occasionally, desirable to avoid latch changes

° C = 0 disables all latch state changes

° Control signal enables data change when C = 1

° Right side of circuit same as ordinary S-R latch.

Latch operation Latch operation enabled byenabled by

CC

Latch operation Latch operation enabled byenabled by

CC

Input sampling enabled by gatesInput sampling

enabled by gates

NOR S-R Latch with Control Input

R’

S’Q’

Q

C’

Outputs change Outputs change when C is low:when C is low:

RESET and SETRESET and SETOtherwise: HOLDOtherwise: HOLD

Outputs change Outputs change when C is low:when C is low:

RESET and SETRESET and SETOtherwise: HOLDOtherwise: HOLD

Latch is Latch is level-sensitivelevel-sensitive, in regards to C, in regards to CLatch is Latch is level-sensitivelevel-sensitive, in regards to C, in regards to C

Only stores data if C’ = 0Only stores data if C’ = 0

D Latch

Q

Q’

C

D S

R

X

Y X Y C Q Q’

0 0 1 Q0 Q0’ Store 0 1 1 0 1 Reset1 0 1 1 0 Set1 1 1 1 1 DisallowedX X 0 Q0 Q0’ Store

0 1 0 11 1 1 0X 0 Q0 Q0’

D C Q Q’

° Q0 indicates the previous state (the previously stored value)

D Latch

Q

Q’

C

D S

R

X

Y

0 1 0 11 1 1 0X 0 Q0 Q0’

D C Q Q’

° Input value D is passed to output Q when C is high

° Input value D is ignored when C is low

Symbols for Latches

° SR latch is based on NOR gates

° S’R’ latch based on NAND gates

° D latch can be based on either.

° D latch sometimes called transparent latch

Summary of The D Latch

° Latches are based on combinational gates (e.g. NAND, NOR)

° Latches store data even after data input has been removed

° S-R latches operate like cross-coupled inverters with control inputs (S = set, R = reset)

° With additional gates, an S-R latch can be converted to a D latch (D stands for data)

° D latch is simple to understand conceptually• When C = 1, data input D stored in latch and output as Q

• When C = 0, data input D ignored and previous latch value output at Q

° Next time: more storage elements!

Clocking Event

Lo-HiLo-Hi edgeHi-LoHi-Lo edge

° What if the output only changed on a C transition?

C

D Q

Q’

0 0 11 1 0X 0 Q0 Q0’

D C Q Q’

Positive edge triggered

Master-Slave D Flip Flop

° Consider two latches combined together

° Only one C value active at a time

° Output changes on falling edge of the clock

D Flip-Flop

D gets latched to Q on the rising edge of the clock.

° Stores a value on the positive edge of C

° Input changes at other times have no effect on output

C

D Q

Q’

0 0 11 1 0X 0 Q0 Q0’

D C Q Q’

Positive edge triggered

Clocked D Flip-Flop

° Stores a value on the positive edge of C

° Input changes at other times have no effect on output

Positive and Negative Edge D Flip-Flop

° D flops can be triggered on positive or negative edge

° Bubble before Clock (C) input indicates negative edge trigger

Lo-HiLo-Hi edge Hi-LoHi-Lo edge

Clocked J-K Flip Flop

° Two data inputs, J and K

° J -> set, K -> reset, if J=K=1 then toggle output

Characteristic Table

Asynchronous Inputs

• J, K are synchronous inputs

o Effects on the output are synchronized with the CLK input.

• Asynchronous inputs operate independently of the synchronous inputs and clock

o Set the FF to 1/0 states at any time.

Asynchronous Inputs

Asynchronous Inputs

• Note reset signal (R) for D flip flop

• If R = 0, the output Q is cleared

•This event can occur at any time, regardless of the value of the CLK

Parallel Data Transfer

° Flip flops store outputs from combinational logic

° Multiple flops can store a collection of data

Designing Finite State Machine

° Understanding flip flop state:• Stored values inside flip flops

° Clocked sequential circuits:• Contain flip flops

° Representations of state:• State equations

• State table

• State diagram

° Finite state machines• Mealy machine

• Moore machine

State Table° Sequence of outputs, inputs, and flip flop states

enumerated in state table

° Present state indicates current value of flip flops

° Next state indicates state after next rising clock edge

° Output is output value on current clock edge

0 0 0 11 01 1

Present State

Next State

x=0 x=1

00 10 0 0 10 10 0 000 11 0 010 11 0 1

Q1(t) Q0(t) Q1(t+1) Q0(t+1)

x=0 x=1

Output

State Table

State Table° All possible input combinations enumerated

° All possible state combinations enumerated

° Separate columns for each output value.

° Sometimes easier to designate a symbol for each state.

Present State

Next State

x=0 x=1

s0 s2 0 0 s2 s2 0 0 s0 s3 0 0 s2 s3 0 1

x=0 x=1

Output

s0

s1

s2

s3

Let:s0 = 00s1 = 01s2 = 10s3 = 11

Mealy Machine

Comb.Logic

X(t)

Q(t+1)

Q(t)Y(t)

clk

present state

present input

nextstate

Comb.Logic

• Output based on state and present input

FlipFlops

Moore Machine

Comb.Logic

X(t)

Q(t+1)

Q(t)

Y(t)

clk

present state

present input

nextstate

Comb.Logic

• Output based on state only

FlipFlops

OutputsOutputLogic

Combina-tional

Combina-tional

LogicInput

MemoryElement

Inputs

Mealy Model

OutputsOutputLogic

Combina-tional

Combina-tional

LogicInput

MemoryElement

Inputs

Moore Model

Mealy versus Moore

State Diagram with One Input & One Mealy Output

° Mano text focuses on Mealy machines

° State transitions are shown as a function of inputs and current outputs.

S1

S2

S3

S4

1/0

1/01/0

1/1

Input(s)/Output(s) shown in transition

0/0

0/0e.g. 1

0/00/0

State Diagram with One Input & a Moore Output

° Moore machine: outputs only depend on the current state

° Outputs cannot change during a clock pulse if the input variables change

° Moore Machines usually have more states.

° No direct path from inputs to outputs

° Can be more reliable

Clocked Synchronous State-machine Analysis – next class

Given the circuit diagram of a state machine:

1 Analyze the combinational logic to determine flip-flop input (excitation) equations: Di = Fi (Q, inputs)

• The input to each flip-flop is based upon current state and circuit inputs.

2 Substitute excitation equations into flip-flop characteristic

equations, giving transition equations: Qi(t+1) = Hi( Di )

3 From the circuit, find output equations: Z = G (Q, inputs)• The outputs are based upon the current state and possibly the inputs.

4 Construct a state transition/output table from the transition and

output equations:• Similar to truth table.• Present state on the left side.• Outputs and next state for each input value on the right side.

• Provide meaningful names for the states in state table, if possible.

5 Draw the state diagram which is the graphical representation of state table.

Concept of the State MachineComputer Hardware = Datapath + Control

RegistersCombinational Functional Units (e.g., ALU)Busses

FSM generating sequences of control signalsInstructs datapath what to do next

Qualifiers

Control

Control

Datapath

State

ControlSignalOutputs

QualifiersandInputs

Designing Finite State Machines

° Specify the problem with words

° (e.g. Design a circuit that detects three consecutive 1 inputs)

° Assign binary values to states

° Develop a state table

° Use K-maps to simplify expressions

° Flip flop input equations and output equations

° Create appropriate logic diagram

° Should include combinational logic and flip flops

Example: Detect 3 Consecutive 1 inputs

° State S0 : zero 1s detected

° State S1 : one 1 detected

° State S2 : two 1s detected

° State S3 : three 1s detected

0

° Note that each state has 2 output arrows

° Two bits needed to encode state

State Table for Sequence Detector

° Sequence of outputs, inputs, and flip flop states enumerated in state table

° Present state indicates current value of flip flops

° Next state indicates state after next rising clock edge

° Output is output value on current clock edge

Present State

Next State

A B x A B y

0 0 0 0 0 0

0 0 1 0 1 00 1 0 0 0 00 1 1 1 0 01 0 0 0 0 0

1 0 1 1 1 01 1 0 0 0 11 1 1 1 1 1

OutputInput

° S0 = 00

° S1 = 01

° S2 = 10

° S3 = 11

Finding Expressions for Next State and Output Value

° Create K-map directly from state table (3 columns = 3 K-maps)

° Minimize K-maps to find SOP representations

° Separate circuit for each next state and output value

Circuit for Consecutive 1s Detector

° Note location of state flip flops

° Output value (y) is function of state

° This is a Moore machine.

Concept of the State Machine

Example: Odd Parity Checker

Even [0]

Odd [1]

Reset

0

0

1 1

Assert output whenever input bit stream has odd # of 1's

StateDiagram

Present State Even Even Odd Odd

Input 0 1 0 1

Next State Even Odd Odd Even

Output 0 0 1 1

Symbolic State Transition Table

Output 0 0 1 1

Next State 0 1 1 0

Input 0 1 0 1

Present State 0 0 1 1

Encoded State Transition Table

° Note: Present state and output are the same value

° Moore machine

Concept of the State Machine

Example: Odd Parity Checker

Next State/Output Functions

NS = PS xor PI; OUT = PS

D

R

Q

Q

Input

CLK PS/Output

\Reset

NS

D FF Implementation

Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0

Clk

Output

Input 1 0 0 1 1 0 1 0 1 1 1 0

1 1 0 1 0 0 1 1 0 1 1 1

Mealy and Moore Machines

Solution 1: (Mealy)0/0

Even

Odd

1/11/0

0/1

0Even

11

0

Reset[0]

Odd [1]

Output

InputOutput

Input

Transition Arc

Output is dependent only on current state

O/P is dependenton current state andinput in Mealy

Solution 2: (Moore)

Mealy Machine: Output is associated with the state transition- Appears before the state transition is completed (by the next clock pulse).

Moore Machine: Output is associatedwith the state-Appears after the state transition takes place.

Vending Machine FSM

Step 1. Specify the problemStep 1. Specify the problemStep 1. Specify the problemStep 1. Specify the problem

Vending Machine

FSM

N

D

Reset

Clk

OpenCoin

SensorGum

Release Mechanism

Deliver package of gum after 15 cents deposited

Single coin slot for dimes, nickels

No change

Design the FSM using combinational logic and flip flops

Vending Machine FSM

State DiagramState DiagramState DiagramState Diagram

Reset

N

N

N, D

[open]

15¢

0¢

5¢

10¢

D

D

Reuse statesReuse stateswhenever possiblewhenever possible

Reuse statesReuse stateswhenever possiblewhenever possible

Symbolic State TableSymbolic State Table

Present State

0¢

5¢

10¢

15¢

D

0 0 1 1 0 0 1 1 0 0 1 1 X

N

0 1 0 1 0 1 0 1 0 1 0 1 X

Inputs Next State

0¢ 5¢ 10¢ X 5¢ 10¢ 15¢ X

10¢ 15¢ 15¢ X

15¢

Output Open

0 0 0 X 0 0 0 X 0 0 0 X 1

Vending Machine FSM

State EncodingState EncodingState EncodingState Encoding

Next State D 1 D 0

0 0 0 1 1 0 X X 0 1 1 0 1 1 X X 1 0 1 1 1 1 X X 1 1 1 1 1 1 X X

Present State Q 1 Q 0

0 0

0 1

1 0

1 1

D

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

N

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Inputs Output Open

0 0 0 X 0 0 0 X 0 0 0 X 1 1 1 X

How many flip-flops are needed?

Vending Machine FSM

Determine F/F implementationDetermine F/F implementationDetermine F/F implementationDetermine F/F implementation

K-map for OpenK-map for D0 K-map for D1

Q1 Q0D N

Q1

Q0

D

N

Q1 Q0D N

Q1

Q0

D

N

Q1 Q0D N

Q1

Q0

D

N

D Q

QR

D Q

QR

Q0

N

N

Q0

Q1

N

Q1

D

D0

D1 Q1

OPEN

D

0Q

NCLK

CLK

Vending machine FSM implementation based on D flip-flops(Moore).

0Q

1Q

Q1

Q0

Reset

Reset

Minimized Implementation

Summary

° Finite state machines form the basis of many digital systems

° Designs often start from clear specifications

° Develop state diagram and state table

° Optimize using combinational design techniques

° Mealy or Moore implementations possible• Can model approach using HDL.