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UNIVERSITI MALAYSIA SARAWAK 943(X". Kota Samarahan

DESIGN OF BUFFER TO DRIVE LARGE CAPACITIVE LOAD WITH MINIMUM DELAY

P. KHIDMATMAKLUMATAKADEMIK UNIMAS

I ummmimuuani 1000125649

KHADIJAH BINTI USAINI

This project is submitted in partial fulfillment of the requirements for the degree of Bachelor of Engineering with Honours

(Electronics and Telecommunication Engineering)

Faculty of Engineering UNIVERSITI MALAYSIA SARAWAK

2004

To my beloved. father, mother, brothers and sister.

ACKNOWLWEDGEMENT

The author would like to express her appreciation to her project supervisor, Encik

Norhuzaimin Julai for giving guidelines, advice and support throughout this project.

Also, to her second supervisor, Professor Shafi Qureshi, for giving her this topic,

and helping out on the buffer design from the beginning to the end. A lot of new things

has been learned from this project.

The author would like to thank her VLSI lecturer, Mr. Ng Liang Yew, for giving

guidance and helping through her design.

Lastly, a huge gratitude to all her wonderful friends and course mates whom are

always being there for the author and keep holding her up high when she started feeling

down.

11

ABSTRAK

Di zaman ini, para pereka cipta berlumba-lumba bersaing untuk mereka cipta

pembalik yang berprestasi tinggi dan litar integrasi berkos efektif. Untuk itu, ilmu

pengetahuan dari semua aspek reka cipta digital adalah sangat diperlukan. Para pereka

harus mempertimbangkan perihal aplikasi algoritma kepada pembentukan dan pakej.

Mereka cipta sebuah litar yang berupaya memacu muatan kapasitan dalam tempoh yang

minimum adalah sangat penting untuk rekacipta litar berkonsepkan VLSI. Sekiranya

hanya satu pembalik yang digunakan untuk memacu muatan kapasitan, Cl�,,! dari kapasitor,

tempoh masa yang di ambil adalah agak lama sekiranya nilai kapasitan adalah besar.

Maka, tujuan projek ini adalah untuk mereka cipta beberapa siri pembalik bagi memacu

muatan kapasitan yang besar dengan tempoh masa yang minimum. Tempoh masa yang

lama dapat dikurangkan dengan beberapa siri pembalik ini. Saiz pembalik bagi setiap siri

dibesarkan lebarnya dengan faktor nisbah setiap peringkat, A. Rekaan ini dihasilkan

dengan menggunakan Program Microwind.

iv

ABSTRACT

Nowadays, designers competing each other in designing inverters with high

performance and cost-effective integrated circuit which demands knowledge of all aspects

of digital design. Designers consider the application algorhythm to fabrication and

packaging. Designing a circuit to drive a large capacitance load with minimum delay is

important for Very Large Scale Integration (VLSI) circuit design. When a single inverter

is used to drive a capacitance load, Cload from a capacitor, the delay would be large if the

capacitance load is large. Therefore, the intention of this project is to design a cascade of

inverters, known as buffer to drive a large capacitance load with a minimum delay. When

moving toward the load, the delay time can be significantly reduced by cascading N

numbers of inverters. Each inverter for each stage is larger by width, W than the previous

by a factor of stage ratio, A. The layout design is done by using Microwind Layout Tools.

V

ý, ti

TABLE OF CONTENTS

Content

DEDICATION

ACKNOWLEDGEMENT

ABSTRAK

ABSTRACT

LIST OF TABLES

LIST OF FIGURES

Page

iv

V

Xll

Xlll

1 INTRODUCTION I

1.1 Introduction To Very Large Scale Integration 1

1.1.1 Very Large Scale Integration Technology 1

1.1.2 Very Large Scale Integration Technology Scale Down 2

1.1.3 Very Large Scale Integration Design as a System Design 4

Discipline

1.1.3.1 A systematic design methodology 4

reaching from circuits to architecture

1.1.3.2 Emphasis on top-down design starting 4

from high-level models

1.1.3.3 Testing and design-for-testability 4

1.1.3.4 Design algorithms 5

vi

1.2 Complementary Metal Oxide Silicon (CMOS) Technology

1.2.1 CMOS Circuit Techniques

1.2.2 CMOS Logic

1.3 Project Overview

2 LITERATURE REVIEW

2.1 The Complementary Metal Oxide Silicon Inverter

2.1.1 Noise Margins

2.1.2 Power Dissipation in CMOS Inverter

2.2 Propagation Delay

2.2.1 Delay and Transition Time

2.3 Driving Large Capacitance Load

2.3.1 Cascaded Inverters as Drivers

2.4 Buffer

2.5 Design Rules

2.5.1 CMOS Colour Scheme

2.5.2 Lambda-Based Rule

2.5.3 Basic Design Rules Used in CMOS Design

2.5.4 Design Rule Checker

2.6 Materials Used for Buffer

2.6.1 Silicon Wafer

2.6.2 N-Well

2.6.3 Ceramic Like Semiconductors Oxide

2.6.3.1 Alumina - Aluminium Oxide

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vii

2.5.3.2 Magnesia-Magnesium Oxide (MgO)

2.6.4 Metal Substrate

2.6.4.1 Copper

2.6.4.2 Nickel

2.6.4.3 Platinum

2.6.5 Polysilicon

2.7 Thin and Thick Film

2.7.1 Thin Film

2.7.2 Thin Film Process

2.7.3 Thin Film Heater Elements

2.7.4 Thick Film

2.7.5 Thin Film Versus Thick Film

3 DESIGN METHODOLOGIES

3.1 Silicon Micromachining

3.1.1 Deposition of Thin Film

3.1.2 Patterning by Wet Etching and Dry Etching

3.2 CMOS Fabrication Process

3.2.1 CMOS Process at a Glance

3.2.2 CMOS Process Walk Through

3.3 Microwind2

3.3.1 The CMOS Layout Editor/Simulator

3.4 Buffer Design

3.4.1 The First Inverter

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3.4.1.1 Mask Layout

3.4.1.2 A-A Cross Section

3.4.1.3 B-B Cross Section

3.4.1.4 Three-dimensional for First Inverter

3.4.2 Insertion of Second Inverter

3.4.2.1 C-C Cross Section

3.4.2.2 Three-dimensional View

3.4.3 Insertion of the Third Inverter

3.4.3.1 D-D Cross Section

3.4.3.2 Three-dimensional View

3.4.4 Insertion of the Fourth Inverter

3.4.4.1 E-E Cross Section

3.4.4.2 Three-dimensional View

3.4.5 Insertion of the Fifth Inverter

3.4.5.1 F-F Cross Section

3.4.5.2 Three-dimensional View

3.4.6 Insertion of the Sixth Inverter

3.4.6.1 G-G Cross Section

3.4.6.2 Three-dimensional View

3.4.7 The Buffer

3.4.7.1 H-H Cross Section

3.4.7.2 I-I Cross Section

3.4.7.3 Three-dimensional View

3.5 Process in Three Dimension

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ix

4 RESULTS AND DISCUSSION

4.1 The Results

4.1.1 Buffer with Three Stage Inverter

4.1.2 Buffer with Five Stage Inverter

4.1.3 Buffer with Seven Stage Inverter

4.2 Discussion

5 CONCLUSION

5.1 Project Conclusion

5.2 Problems Encountered

5.3 Future Prospects

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REFERENCES 81

APPENDIXES 83

APPENDIX A: Flowchart for the CMOS IC design process 83

APPENDIX B: Design Rules 84

APPENDIX C: Microwind2 Menus 89

APPENDIX D: Microwind2 Simulation Menus 92

APPENDIX E: Inverter Simulation 93

APPENDIX F: System Levels Interconnects 95

APPENDIX G: ASIC Implementation Technology 97

APPENDIX H: Towards Nano Scale 98

X

LIST OF TABLES

Table Page

1.1 A set of key parameters, and the revolution with the technology 3 2.1 Colour scheme for each of the materials used in VLSI design 21 3.1 The inverter Wp/W� ratio in lambda for the 7 stage buffer: 49

X1

LIST OF FIGURES

Figure Page

1.1 The Reduction of the VLSI Design Scaling 3 1.2 Three Different Topologies for an Inverter 6 1.3 Logic Levels for typical CMOS logic circuits 7 2.1 CMOS Inverter 9 2.2 Inverter Circuit Diagram 10 2.3 The IN Characteristics 12 2.4 (a) The Inverter Transfer Characteristics 13

(b) The Current Spike Flows at Inverter Output 13 2.5 A Piece-wise Linear Approximation for the Voltage Transfer 14

Characteristics (VTC) 2.6 Propagation Delay 16 2.7 CMOS Propagation Delay Approach 1 17 2.8 CMOS Transient Response 17 2.9 Cascade of inverters used to drive a large capacitance load 18 2.10 Tri-State Buffer 20 2.11 N-type MOS Layout 23 2.12 P-type MOS Layout 23 2.13 Spacing Between Materials 24 2.14 The contact minimum width, the spacing between two 25

contacts, the extra diffusion over contact, extra polysilicon over contact and the distance between contact and polysilicon gate.

2.15 The Design Rule Checker 25 2.16 Thin Film Process 33 3.1 Etching of Silicon Wafer 39 3.2 Silicon Diaphragm 50µm 39 3.3 Thinner Diaphragm 20µm 39 3.4 Bridge and Beam 40 3.5 Silicon wafers 41 3.6 Microwind2 Layout Menus 46 3.7 The Simulator 47 3.8 MOS Generator 48 3.9 (a) The First Inverter Layout 50 3.9 (b) A-A Cross Section of PMOS 50 3.9 (c) B-B Cross Section of NMOS 51 3.9 (d) Three Dimension for First Inverter 51

3.10 (a) Two Stage Inverters Layout 52 3.10 (b) C-C cross section which cross the left side of the p- 53

channel MOS and n-channel MOS for the second inverter.

xii

3.10 (c) Three Dimension of Two Stage Inverters 53 3.11 (a) Three Stage Inverters Layout 54 3.11 (b) D-D cross section which cross the right side of the p- 55

channel MOS and n-channel MOS for the third inverter. 3.11 (c) Three Dimension of Three Stage Inverters 55 3.12 (a) Four Stage Inverters Layout 56 3.12 (b) E-E cross section which cross the p-channel MOS and n- 57

channel MOS second, third and fourth inverter, and cross the VDD bus at the first inverter.

3.12 (c) Three Dimension of Four Stage Inverters 57 3.13 (a) Five Stage Inverters Layout 58 3.13 (b) F-F cross section which cross p-channel MOS and n- 59

channel MOS for the forth and fifth inverter. 3.13 (c) Three Dimension of Five Stage Inverters 59 3.14 (a) Six Stage Inverters Layout 60 3.14 (b) G-G cross section which cross p-channel MOS for the 61

sixth inverter. 3.14 (c) Three Dimension of Six Stage Inverters 61 3.15 (a) The Buffer Layout 62 3.15 (b) H-H cross section across the interconnection for all seven 63

stages. 3.15 (c) I-I cross section across p-channel MOS or PMOS for all 63

the seven stages. 3.15 (d) Three Dimension of the buffer 64 4.1 Three types of buffer with different inverter stages 69 4.2 (a) The simulation for buffer with three stage inverter: 70

voltage versus time 4.2 (b) The simulation results for current, mA versus time, ns. 71 4.2 (c) The simulation result for Vin, (VDD) versus V;,,. 71 4.3 (a) The simulation for buffer with five stage inverter: voltage 72

versus time. 4.3 (b) The simulation results for current, mA versus time, ns. 73 4.3 (c) The simulation result for V;,,,, (VDD) versus V;,,. 74 4.4 (a) The simulation for buffer with complete seven stage 75

inverter: voltage versus time. 4.4 (b) The simulation results for current, mA versus time, ns. 75

4.4 (c) The simulation result for V;,, v (VDD) versus V;,,. 76

4.4 (d) The simulation result for frequency, in giga hertz versus 76

time, ns. 4.5 The delay differences between three-stage buffer, five-stage 77

buffer and seven-stage buffer.

xiii

CHAPTER I

INTRODUCTION

1.1 INTRODUCTION TO VERY LARGE SCALE INTEGRATION DESIGN

Very Large Scale Integration is well known as VLSI is system design disciplines

that can be consider as somewhat different set of areas than does the study of circuit

design. Today's VLSI design projects are, in many cases, mega-chips which not only

attain tens (soon hundreds and thousands) of million transistors, but must also run at very

high frequency.

Beyond being large and fast, modern VLSI systems must frequently be designed

for low power consumption. Low-power design is of course critical for battery operated

devices, but the sheer size of those VLSI system means that excessive power

consumption can lead to heat problems. Like testing, low-power design costs across all

levels of abstraction.

1.1.1 Very Large Scale Integration Technology

Very Large Scale Integration or VLSI is the integration of many small transistors

on a single chip (Chen, 1990). Shrinking the transistor size for VLSI implementation is

another driving force for CMOS because, as transistors dimension are reduced, the

current delivered by a p-channel transistor approaches the current provided by an n-

channel device of the same size. The speed of VLSI depends more on the actual circuit

I

design rather than the moderate difference in device driving ability. Furthermore, as the

design cost increases rapidly for VLSI, process complexity, makes much less impact on

total cost. On the other hand, the turnaround times maybe a much important aspect. This

feature is especially critical for Application Specific Integrated Circuits (ASICs). A brief

explanation about the ASIC's implementation can be refer to APPENDIX G.

1.1.2 Very Large Scale Integration Technology Scale Down

The evolution of integrated circuit (IC) fabrication techniques is a unique fact in

the history of modern industry. The improvements in terms of speed, density and cost

have kept constant for more than 30 years.

For example, in August 2002, there were three companies debuting the industry's

first 90nm (0.09 micron) CMOS design platform and cell libraries for system on chip

solution. The three companies are, Motorola, Phillips and STMicroelectronics. This new

scale system is to start next generation system-on-chip (SoC) product development for

low power, wireless, networking, consumer and high speed applications. The multiple

threshold-based library elements can be selected at the design level and used in the same

design block. This will provide users of the platform greater flexibility to optimize

performance and power consumption. The capability enables faster development for

used in high performance and power-sensitive products. Refer to APPENDIX H.

The figure below shows the evolution of scaling down from 130 nm to 90 nm.

The smaller the scaling will improve the logic density, save power per gate and reducing

the delay of the gate.

2

-9

"

ý

1000

100

10/i 1107 1ffIM 1ffl 2000 OM 10002 200: 1 2000 MM

P1bt Pfroductl0n

to

Figure 1.1 The Reduction of VLSI Design Scaling

"rtRs et, MC

The table 1.1 below lists a set of key parameters, and their revolution with the

technology. The increased number of metal inter connects the reduction of the power

supply VDD and the reduction of the gate oxide down to atomic scale values. Table 1.1

also shows the slow decrease of the threshold voltage of the MOS device and the

increasing number of the input or output pads available on a single die.

Lithography Year Metal La ers

Core su ly (V)

Core oxide (nm)

Chip size (mm)

Input/Output pads

Microwind 2 rule file

1.2 m 1986 2 5.0 25 5x5 250 Cmosl2. rul 0.7 m 1988 2 5.0 20 7x7 350 Cmos08. rul 0.5 m 1992 3 3.3 12 I Ox lO 600 Cmos06. rul 0.35 pm 1994 5 3.3 7 15x15 800 Cmos035. rul 0.25 m 1996 6 2.5 5 17x17 1000 Cmos025. rul 0.18 m 1998 6 1.8 3 20x20 1500 Cmos018. rul 0.12 m 2001 6-8 1.2 2 22x20 1800 CmosOl2. rul 90nm 2003 6-10 1.0 1.8 25x20 2000 Cmos90n. rul 65nm 2005 6-12 0.8 1.6 25x20 3000 Cmos70n. rul

Table 1.1 A set of key parameters, and the revolution with the technology

3

1.1.3 Very Large Scale Integration Design as a System Design Discipline

1.1.3.1 A systematic design methodology reaching from circuits to architecture

Modern logic design includes more than the traditional topics of adder design and

two-level minimization-register-transfer design, scheduling, and allocation are all

essential tools for the design and complex digital systems. Circuit and layout design tells

which logic and architectural designs make the most sense for CMOS VLSI.

1.1.3.2 Emphasis on top-down design starting from high-level models

While no high-performance chip can be designed completely top-down, it is

excellent discipline to start from a complete description of what the chip is to do; a

number of experts estimate half of the application-specific ICs designed execute their

delivery tests but do not work in their target system because the designer did not work

from a complete specification.

1.1.3.3 Testing and design-for-testability

The customers demand both high quality and short design turnaround. Every

designer must understand how chips are tested and what makes them hard to test.

Relatively small changes to the architecture can make a chip drastically easier to test,

while a poorly designed architecture cannot be adequately tested by even the best testing

engineer.

4

1.1.3.4 Design algorithms

Analysis and synthesis tools must be used to design almost any type of chip: large

chips, to be able to complete them at all; relatively small ASICs, to meet performance

and time-to-market goals. Making the best use of those tools requires understanding how

the tools work and exactly what the design problem they are intended to solve.

1.2 COMPLEMENTARY METAL OXIDE SILICON (CMOS) TECHNOLOGY

1.2.1 Complementary Metal Oxide Silicon Circuit Techniques

The most important difference between fabrication technologies is the types of

transistors they can produce. Different transistor types require different circuit designs

for Boolean logic and memory functions, which have very different speed and power

characteristics.

Figure 1.2 shows three different circuit topologies for an inverter, logic gate NOT,

using different transistor types. A bipolar transistor circuit can be used along with a

inverter to build an inverter. An n-channel enhancement mode MOS transistor can be

coupled with an n-channel depletion mode transistor to create a static nMOS gate. While,

a pair of p-type and n-type enhancement mode MOS transistors is used to build a static

complementary, or CMOS inverter. The power for consumption for these circuits'

decreases from left to right: the bipolar circuit requires a great deal of power, the nMOS

circuit uses considerably less but still not negligible amounts, while the CMOS circuit

requires very little power. While the bipolar transistor and the nMOS consume power in

a steady state, the CMOS circuit consumes no steady state power.

5

Figure 1.2 Three Different Topologies for an Inverter

1.2.2 CMOS Logic

Logic elements process binary digits, 0 and 1. In any logic circuit, there is a

range of voltages that is interpreted as a logic 0, and another, non-overlapping range that

is interpreted as a logic 1.

A typical CMOS Logic circuit operates from a 5-volt power supply. Such a

circuit may interpret any voltage in the range 0-1.5 V as logic 0, and in the range 3.5-5.0

V as a logic 1. Thus, the definition of LOW and HIGH for 5-volt CMOS logic is shown

in Figure 1.3. Voltages in the intermediate range (1.5-3.5 V) are not expected to occur

except during signal transitions, and yield undefined logic values. CMOS circuits using

other power-supply voltages, such as 3.3 or 2.7 volts, partition the voltage range

similarly.

6

5.0 V

3.3 V

1.5V

0.0 V

undefined logic level

Figure 1.3 Logic Levels for typical CMOS logic circuits.

1.3 PROJECT OVERVIEW

In high-speed digital VLSI design, bounding the load capacitance at gate outputs

is a well-known part of today's electrical correctness methodologies. Bounds on load

capacitance improve coupling noise immunity, reduce degradation of signal transition

edges, and reduce delay.

The objective of this project is to design buffer to drive large capacitive load with

a minimum delay. As the feature size of integrated circuits decreases, gate delays

decrease and interconnect delays increase. The overall logic-stage delay consists of a gate

delay component plus an interconnect delay component. The gate delay component

could be estimated by modeling the entire interconnect tree at the gate output as a simple

lumped capacitance. Currently, with increased interconnect resistance and larger

interconnect trees, the lumped capacitance approximation results in pessimistic delay and

rise time calculations. Accurate estimation of gate delay and rise time closely depends on

7

the model for the driving point admittance of a load interconnect tree at the output of a

gate.

The formula to calculate the delay and number of inverter will be discussed more

in Chapter 2. Chapter 2 will also concern on the characteristics of CMOS inverter and

the power dissipation. Chapter 3 discusses the design methodologies and shows the

design for each of the inverter in each stages, the cross section views and the 3-

dimensional views of the design. Software program named Microwind is used to design

the buffer. Chapter 4 focuses on the results and the discussion from the simulation of the

design. The conclusion for the project is in Chapter 5 which covers the future prospects

and difficulties in doing this project.

8

CHAPTER 2

LITERATURE REVIEW

2.1 THE COMPLEMENTARY METAL OXIDE SILICON INVERTER

The inverter is known as the nucleus of all digital designs. It is the basic building

block for the digital circuit design. The electrical behavior of these complex circuits can

be almost completely derived by extrapolating the results obtained for inverters. The

analysis for inverters can be extended to explain the behaviour of more complex gates such

as NAND, NOR or XOR, which in turn form the building blocks of modules such as

multipliers and processors.

In 0

Figure 2.1 CMOS Inverter

9

The inverter performs the logic operation of A to A. When the input to the inverter

is connected to the ground, the output is pulled to 5V through the p-channel transistor.

When the input terminal is connected to VDD, the output is pulled to the ground through the

n-channel MOSFET.

There are several important characteristics of the CMOS inverter:

i. Its output voltage swings from VDD to ground unlike other logic families

that never quite reach the supply levels,

ii. The static power dissipation of the CMOS inverter is practically zero,

iii. The inverter can be sized to give equal sourcing and sinking capabilities,

and

iv. The logic switching threshold can be set by changing the size of the device.

The common symbol for the inverter and the diagram in Figure 2.2 shows the

normally used inverter circuit diagram.

Input

Input

Output

Output

vs s (logic "0'ý

Figure 2.2 Inverter Circuit Diagram

The standard CMOS inverter is quite simple: one p-type transistor connected to the

power rail joined at the inverter output to one n-type connected to the ground with rail with

their common gates connected to the inverter input.

10

" p-type is always used to make output logic "I" (VDD)

" n-type is always used to make output logic "0" (Vss)

The key to full voltage levels of the CMOS inverter output is that the output is a

drain of both of the transistors.

If there is OV on the input to this inverter, the p-type is switched ON and the n-type

is switched OFF; thus, there is a connection between the power rail and the output, and so

charge flows onto the output. If there is 5V on the input, the p-type is OFF and n-type is

ON; any charge on the output flows through the channel in the n-type to the ground rail. A

HIGH voltage on the input leads to a LOW voltage on the output; a LOW voltage on the

input leads leads to a HIGH voltage on the output: we have an electrical implementation of

NOT gate.

Input ý0

p-type ON

n-type OFF

output ýI

0 OFF ON 0

Referring to Figure 2.1, CMOS inverter consists of a p-channel and an n-channel

driver, both are enhancement mode devices. The source and substrate of the p-channel are

connected to VDD, whereas the source and the substrate of the n-channel are grounded.

This arrangement ensures that VBS =0 for both devices. Thus, no body effect exists in the

CMOS inverter. The input of the inverter (V;,, ) is connected to both p- and n-channel gates

and the drain areas of the two devices are also tied together for output (V,,,,, ). If the input is

at VDD, the n-channel device is on and the p-channel is off. When the input is switched to

zero, the channel device is off, while the p-channel load device is on because VGS in p-

channel is now at -VDD.

11