P1500 IEEEgrouper.ieee.org/groups/1500/date98/ctag_status.pdf · 1998-02-21 · P1500IEEE Scalable Architecture Task Force 3 Embedded Core Test Mission statement Goal of IEEE P1500

Scalable Architecture Task Force

IEEEP1500Embedded Core Test

IEEEP1500Embedded Core TestScalable Architecture Task Force 2

Task Force Members

❏ Lee Whetsel (Texas Instruments, chair)

❏ Saman Adham (Nortel) ❏ Jim Monzel (IBM)

❏ Sandeep Bhatia (Duet Technologies) ❏ Fidel Muradali (Hewlett-Packard)

❏ C.J. Clark (Intellitech) ❏ Mike Ricchetti (Synopsys)

❏ Mike Collins (Cisco) ❏ Todd Rockoff (Advantest)

❏ Tom Eberle (Mentor Graphics) ❏ Jon Udell (Palmchip)

❏ Grady Giles (Motorola) ❏ Norbert Valverde (Intellitech)

❏ Alan Hales (Texas Instruments) ❏ Prab Varma (Duet Technologies)

❏ Erik Jan Marinissen (Philips Research) ❏ Sitaram Yadavalli (Intel)

❏ Teresa McLaurin (Motorola) ❏ Yervant Zorian (LogicVision)


Mission statement

Goal of IEEE P1500 Standardize test interface (access and control) between a non-mergeableembedded core and its host (the system-on-chip or next level of core), inorder to facilitate core TEST interoperability (plug-and-play) and henceimprove the efficiency of core providers, users and manufacturers.

Objectives of ScalableArchitecture TaskForce

❏ Develop/identify standard Test Control Mechanisms for embeddedcores (allowing test protocol and multiple mode control)

❏ Develop/identify standard expandable Test Access Mechanisms forembedded cores (allowing serial access, parallel access, etc.)

❏ Reduce time-to-market by enabling test reuse for embedded cores*

Considerations forScalable Architecture(control and access)

* - change since ITC’97

❏ Design simple architecture

❏ Maximize use of existing standards

❏ Use synchronous control protocols

❏ Support multiple modes of test and diagnosis for use in factory andfield test

❏ Support hierarchical cores


Objectives

❏ Use Plug-N-Play-Like feature

❏ Support Hierarchical Core Reuse

❏ Support Hierarchical Test Reuse

❏ Support factory Core Test Enablement,Silicon Debug, and Fault Diagnosis*

❏ Support a diverse range of extended core test schemes

❍ Core Mux Testing

❍ Core Collar Testing

❍ Core Scan Testing

❍ Core Parallel Scan Testing

❍ IDDQ Testing

❍ At Speed Testing

❍ Functional Testing

❍ Delay Testing

❏ Provide flexibility to enable core integrator to make trade-offs between testaccess bandwidth and silicon area*

* - change since ITC’97


Requirements

❏ Provide a standard test interface mechanism

❏ Provide extendible test data access bandwidth (1 bit to n bits wide)

❏ Provide extendible test control bandwidth


Task Force History

❏ Scalable Architecture Task Force created in April 1997

❏ Little progress initially

❍ Some early proposals, but no consensus from task force

❍ Tried to solve everything at once

❍ Only visible accomplishment by ITC’97 was creation of MissionStatement, Objectives, and Requirements

❏ Proposals by Erik Jan Marinissen and Prab Varma during Task Forcemeeting at ITC

❍ Solid foundation for future development

❏ Much more progress since ITC’97

❍ Divided problem into three major sections

❍ Addressing one section at a time

❍ Also limited scope of what we are looking at

❍ Weekly Conference Calls


Philips’ Proposal for Scalable Architecture (November 1997)

shell

IPfunction

input

directtest input

TestRailinput

functionoutput

directtest output

TestRailoutput

n n

shell

IPfunctioninput

IP teststimulus

functionoutput

external internal

intercon.response

IP testresponse

intercon.stimulus

bypa

sstest

control


Philips’ Proposal for Scalable Architecture

16

Core A

host

Core CCore B

Core DCore E

Core F10

3

10

7

3

1010

16

1616

16 16

16



Core A

host

Core CCore B

Core DCore E

Core F



❏ Variable width TestRail distributes test data to embedded cores.

❏ Cores daisy-chained together

❏ Each core has bypass register for efficient test access to other cores

❏ Single scan chain for test control access

❏ Full presentation is at:

http://grouper.ieee.org/groups/1500/itc97/marinissen.9711.pdf


Test Signal Types

Static test control ❏ Signals change very infrequently

❏ Test enable signal

❏ Mode selection

Dynamic test control ❏ Signals change more frequently

❏ Clock signal

❏ Scan enable signal

Test data ❏ Scan input and output data

❏ RAM test stimulus and response


Static Test Control

❏ Signals change very infrequently

❏ Small number of control signals for each core

❏ Total number of control signals will not be high, even for large ICs with many cores

❏ Mode selection

❍ Functional mode

❍ Scan test

❍ Interconnect test

❍ Safe state

❍ IDDQ test

❏ Fast access is not required

❏ Must support hierarchical designs


Static Test Control Proposals

DISCLAIMER: We are considering these proposals for inclusion as part of anofficial P1500 architecture proposal. At this point, none ofthese proposals have been endorsed by the ScalableArchitecture Task Force.

❏ Flat test control via internal shift register

❏ Flat test control via external shift register

❏ Hierarchical test control with bypass

❏ Hierarchical test control with core selection


Static Test Control

Static Test Control Signals

DATA IN DATA OUT

SHIFT/UPDATE

CLOCK

RESET

Core

RESET RESET RESET RESET


Flat Internal Static Test Control

DATA IN

DATA OUT

SHIFT/UPDATE

CLOCK

RESET

Core 1Core 3 Core 4Core 2

Core 7Core 6Core 5


Flat Internal Static Test Control

DATA IN

DATA OUT


Flat Internal Static Test ControlAdvantages and Disadvantages

Advantages ❏ Can control multiple cores simultaneously

❏ Fixed overall shift register length (compatible with IEEE 1149.1)

❏ Simple to implement

❏ Test patterns easy to create and debug

❏ Simplifies failure analysis

Disadvantages❏ Complete shift register must be scanned to set control bits for one core

❏ Variable number of bits before and after core for each instantiation, so testpatterns need to be modified

❏ No way to bypass “bad” sections of shift register

❍ Impact on silicon debug and failure analysis

❍ No impact on production test


Flat External Static Test Control

DATA OUT

Core 1Core 3 Core 4Core 2

Core 7Core 6Core 5

DATA IN

SHIFT/UPDATE

CLOCK

RESET


Flat External Static Test ControlAdvantages and Disadvantages

Advantages ❏ Easier to eliminate clock skew problems because shift register is localized

❏ Can control multiple cores simultaneously




Disadvantages❏ More work for core integrator, especially when there is a lot of hierarchy

❏ More connections to each core

❏ Complete shift register must be scanned to set control bits for one core






Hierarchical Static Test Control with Bypass

DATA IN DATA OUT

ENABLE

RESET

RESET RESET RESET RESET

DATA INDATA OUT

SHIFT/UPDATE

ENABLE

RESET

RESETCLOCK

0

1



DATA INDATA OUT

SHIFT/UPDATE

CLOCK

RESET

Core 1 Core 3 Core 4Core 2

Core 7Core 6Core 5

1



DATA INDATA OUT

SHIFT/UPDATE

CLOCK

RESET


Core 7Core 6Core 5

1



DATA INDATA OUT

SHIFT/UPDATE

CLOCK

RESET


Core 7Core 6Core 5

1



DATA INDATA OUT

SHIFT/UPDATE

CLOCK

RESET


Core 7Core 6Core 5

1


Hierarchical Static Test Control with BypassAdvantages and Disadvantages

Advantages ❏ ”Bad” sections of shift register can be bypassed for silicon debug (notuseful for production test)

❏ Shorter shift register length to access single core

❏ Hierarchy can be flattened by enabling all cores

Disadvantages❏ Control and data are mixed in same shift register

❏ Not compatible with IEEE 1149.1 (variable-length data registers are notallowed)

❏ More complex implementation

❏ More complex test patterns

❏ Silicon debug and failure analysis is more complicated


❏ Additional “enable” connection to every core


Hierarchical Static Test Control with Core Selection

❏ More complex control logic which enables each core to be selectedindividually

❏ Core selection control uses a separate shift register

❏ Standard 6 pin interface to core

❏ Compatible with IEEE 1149.1


Hierarchical Static Test Control with Core SelectionAdvantages and Disadvantages

Advantages ❏ Hierarchy control and test control are isolated

❏ ”Bad” sections of shift register can be bypassed for silicon debug (notuseful for production test)

❏ Shorter shift register length to access single core

❏ Fixed number of bits before and after core for each instantiation, so testpatterns do not need to be modified

Disadvantages❏ Difficult to select several cores simultaneously

❏ Implementation is more complex

❏ Test patterns are more complex

❏ Silicon debug and failure analysis are more complicated

❏ Ability to completely bypass other cores via muxes could limit themaximum speed of this method


Static Test ControlPotential Functionality Problems

❏ Clock skew within a core

❏ Clock skew between cores

❏ Weak signals

❏ Process variations

❏ Random defects in control logic


Clock Skew

A B C D

A

B

C

D

A

B

C

D

1 2 3

1

2

3

1

2

3

Normal operation Skewed clock to flip-flop 2


Clock Skew

A B C D

A

B

C

D

1

2

3

Normal operation Skewed clock to flip-flop 2

1 2 3

A

B

C

D

1

3

2


Flat Internal Static Test ControlAdvantages and Disadvantages (revised)

Advantages ❏ Can control multiple cores simultaneously


❏ Simple to implement



Disadvantages❏ Complete shift register must be scanned to set control bits for one core




❍ NO impact on silicon debug and failure analysis



Current Status

❏ We have looked at static test control

❍ We have several proposals

❍ All of the proposals are technically feasible

❍ Each proposal has its advantages and disadvantages

❍ We will look at test data access before we make a decision on statictest control

❏ Static Test Control is the easy part of the problem

❍ We still have to address dynamic test control and test data access

❏ We will look at test data access next


What Are We Not Currently Addressing?

❏ IEEE 1149.1

❍ IEEE 1149.1 compatibility temporarily being ignored until we makefurther progress

❏ Mixed-Signal Designs

❍ We will focus on digital first and tackle mixed signal later


Scalable Architecture Task ForceInternet Resources

❏ The IEEE P1500 Embedded Core Test Web site has moved. It is now at:

http://grouper.ieee.org/groups/1500/

❏ This Scalable Architecture Task Force presentation is available at:

http://grouper.ieee.org/groups/1500/date98/ctag_status.pdf

❏ You can contact Lee Whetsel (the Task Force chairman) at:

[email protected]

❏ You can contact the whole task force by sending email to:

[email protected]

Documents

P1500 IEEEgrouper.ieee.org/groups/1500/date98/ctag_status.pdf · 1998-02-21 · P1500IEEE Scalable Architecture Task Force 3 Embedded Core Test Mission statement Goal of IEEE P1500