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PAGE 10: FPGA TRANSCEIVERSPAGE 11: BOARD MANAGEMENTPAGE 12: GBE PHYPAGE 13: FPGA DECOUPLING CAPACITORSPAGE 14: MLVDS FOR MTCA.4 + LEVEL TRANSLATORS
PAGE 15: POWERING
PAGE 05: FMC#1PAGE 06: FMC#2PAGE 07: CONFIGURATION
PAGE 02: SRAMSPAGE 03: FPGA PART1PAGE 04: FPGA PART2
PAGE 08: CLOCK DISTRIBUTION 1 OF 2PAGE 09: CLOCK DISTRIBUTION 2 OF 2
1/15LAST_MODIFIED=Tue Apr 26 17:33:29 2011
Project file:glib.cpm
PCB by: PV DATE: nn/nn/nnnn
1/15
SYSTEM: SPB15.x
Design by: P.VICHOUDIS
MODULE:glib
EDA-02180-V3-0 PROJECT:GLIB
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
1211 GENEVA 23SWITZERLAND
Project:Sheet:
Module:European Organizationfor Nuclear Research
4
EN/ICE
--------+-----+-----+-----+-----+-----+-----+----+
WHEN THE PLATFORM FLASH IS USEDTHE CE2 GOES LOW, DISABLING THE SRAM2
FLASH WR| 0 | 0 | 1 | X | 0 | X | 1 |FLASH RD| 0 | 1 | 0 | X | 0 | X | 1 |
--------+-----+-----+-----+-----+-----+-----+----+C9-C8
CAPACITORS
CAPACITORS
3. FPGA IO -> CE1_B
1. FCS_B -> CE2
C4-C3
M5-M4
D8-D7D5-D4
M8-M7
N4-N3
SRAMS
N9-N8
PLACEMENT:
D8-D7
C9-C8
DECOUPLING
M8-M7
N4-N3
M5-M4
PLACEMENT:
N9-N8
D5-D4
4. OE_B -> NOT CE2
2. FWE_B -> WE_B
SRAM2 WR| 1 | X | 1 | 0 | 1 | 0 | X |SRAM2 RD| 1 | X | 1 | 0 | 1 | 1 | 0 |--------+-----+-----+-----+-----+-----+-----+----+
C4-C3
DECOUPLING
ACT\SIG: FCS_B FWE_B FOE_B CE1_B CE2 WE_B OE_B
2/15LAST_MODIFIED=Thu Jul 05 08:09:26 2012
Project file:glib.cpm
PCB by: PV DATE: nn/nn/nnnn
2/15
SYSTEM: SPB15.x
Design by: P.VICHOUDIS
MODULE:glib
EDA-02180-V3-0 PROJECT:GLIB
41
2
IC15
R21R101
TP10
C214
C93
C94
C98
C97C100
C99
C95
C96
C215
C216
C220
C219C222
C221
C217
C218
R20R19
H11
B7
R5P7P5
R7
B8
A1P11
B1
P1
R1
N1
C1
C11
N11
M2M1L2L1K2K1J2J1
G2G1F2F1E2E1D2D1
G11G10F11F10E11E10D11D10
M11M10L11L10K11K10J11J10
B6A7
A6B3A3
B4A4A5B5
A8R11R10R9R8R4R3R2
P10P9P8P4P3P2
B10B9B2
A10A9A2P6R6
IC5
H11
B7
R5P7P5
R7
B8
A1P11
B1
P1
R1
N1
C1
C11
N11
M2M1L2L1K2K1J2J1
G2G1F2F1E2E1D2D1
G11G10F11F10E11E10D11D10
M11M10L11L10K11K10J11J10
B6A7
A6B3A3
B4A4A5B5
A8R11R10R9R8R4R3R2P10P9P8P4P3P2B10B9B2A10A9A2P6R6
IC6
VCC=P2V5SRAM2_CE2
SRAM2_ADV_LD_LSRAM2_CLKSRAM2_CEN_LSRAM2_WE_L
SN74AHC1G00DBV
SRAM2_BWDSRAM2_BWC
CY7C1470V25-200BZXCVSS=GND;VDD=P2V5;VDDQ=P2V5
SRAM1_A20
SRAM1_DQD3SRAM1_DQD4
SRAM2_DQD6
0R0
SRAM2_DQD4
SRAM2_DQD1SRAM2_DQD0
SRAM2_DQD2
SRAM2_A19
SRAM2_A4
SRAM2_A6SRAM2_A5
SRAM2_DQPD
SRAM2_DQC6SRAM2_DQC7
SRAM2_DQC5SRAM2_DQC4SRAM2_DQC3SRAM2_DQC2SRAM2_DQC1SRAM2_DQC0SRAM2_DQPCSRAM2_DQB7
SRAM2_DQB5SRAM2_DQB4SRAM2_DQB3SRAM2_DQB2
SRAM2_DQPBSRAM2_DQB0SRAM2_DQB1
SRAM2_DQA7SRAM2_DQA6SRAM2_DQA5
SRAM2_DQA3SRAM2_DQA4
SRAM2_DQA2SRAM2_DQA1SRAM2_DQA0SRAM2_DQPA
SRAM2_DQD3
SRAM2_A0
SRAM2_A3SRAM2_A2SRAM2_A1
SRAM2_A12SRAM2_A13
SRAM2_DQD7
SRAM2_DQD5
SRAM2_DQB6
FPBGA
SRAM2_TCKSRAM2_TMS
SRAM2_TDISRAM2_TDO
SRAM2_A7SRAM2_A8SRAM2_A9SRAM2_A10
200MHZ
33 33
10V
220NF10V
220NF10V
220NF10V
220NF10V
220NF10V
220NF10V
220NF10V
220NF10V
220NF10V
220NF10V
220NF10V
220NF
220NF10V
220NF10V
220NF10V
200MHZ
SRAM1_DQD1SRAM1_DQD0
SRAM1_A19SRAM1_A18SRAM1_A17SRAM1_A16SRAM1_A15
SRAM1_A10
SRAM1_A8
SRAM1_A6
SRAM1_DQPD
SRAM1_DQC6
SRAM1_DQC4
SRAM1_DQC2SRAM1_DQC1
SRAM1_DQPCSRAM1_DQB7
SRAM1_DQB5SRAM1_DQB4SRAM1_DQB3SRAM1_DQB2
SRAM1_DQPBSRAM1_DQB0SRAM1_DQB1
SRAM1_DQA7SRAM1_DQA6SRAM1_DQA5
SRAM1_DQA3SRAM1_DQA4
SRAM1_DQA2SRAM1_DQA1SRAM1_DQA0SRAM1_DQPA
SRAM1_A3SRAM1_A2
SRAM1_A9
SRAM1_A11SRAM1_A12SRAM1_A13
SRAM1_DQD7
SRAM1_DQD5
220NF
SRAM1_DQB6
10V
SRAM1_A14
SRAM1_A7
0R0
SRAM2_A11
SRAM2_A14
SRAM2_A16
SRAM1_DQD6
SRAM1_A5SRAM1_A4
SRAM1_A1SRAM1_A0
SRAM1_TCKSRAM1_TMSSRAM1_TDOSRAM1_TDI
SRAM1_MODE
SRAM1_OE_L
SRAM1_BWASRAM1_CE1_L
SRAM2_A15
SRAM2_A17SRAM2_A18
SRAM2_A20
SRAM1_BWBSRAM1_BWCSRAM1_BWD
SRAM1_DQC3
SRAM1_DQC5
SRAM1_DQC7
SRAM2_BWB
SRAM1_DQC0
SRAM1_WE_LSRAM1_CEN_LSRAM1_CLKSRAM1_ADV_LD_L
FPBGA SRAM2_MODE
220NF
SOT23
VSS=GND;VDD=P2V5;VDDQ=P2V5CY7C1470V25-200BZXC
SRAM2_CE1_LSRAM2_BWA
SRAM1_DQD2
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
1211 GENEVA 23SWITZERLAND
Project:Sheet:
Module:European Organizationfor Nuclear Research
4
EN/ICE
DQB<6>
MODEZZ
CE1*
CE3*
BWA*
CE2
BWD*
OE*
BWB*BWC*
DQD<6>DQD<5>
DQD<7>
NC/576MNC/1G
A<13>A<12>A<11>
A<9>
TDOTDI
TCKTMS
A<1>A<2>A<3>
A<0>
DQD<3>
DQPADQA<0>DQA<1>DQA<2>
DQA<4>DQA<3>
DQA<5>DQA<6>DQA<7>
DQB<1>DQB<0>
DQPB
DQB<2>DQB<3>DQB<4>DQB<5>
DQB<7>DQPC
DQC<0>DQC<1>DQC<2>DQC<3>DQC<4>DQC<5>
DQC<7>DQC<6>
DQPD
A<5>A<6>A<7>A<8>
A<10>
NC/288M
A<4>
A<14>A<15>A<16>A<17>A<18>A<19>A<20>ADV/LDCLK
WE*CEN*
NC/144M
DQD<2>
DQD<0>DQD<1>
DQD<4>
GND
GND
P2V5
GND GND
P2V5
GND GND
P2V5
P2V5
P2V5
GND
GND
DQB<6>
MODEZZ
CE1*
CE3*
BWA*
CE2
BWD*
OE*
BWB*BWC*
DQD<6>DQD<5>
DQD<7>
NC/576MNC/1G
A<13>A<12>A<11>
A<9>
TDOTDI
TCKTMS
A<1>A<2>A<3>
A<0>
DQD<3>
DQPADQA<0>DQA<1>DQA<2>
DQA<4>DQA<3>
DQA<5>DQA<6>DQA<7>
DQB<1>DQB<0>
DQPB
DQB<2>DQB<3>DQB<4>DQB<5>
DQB<7>DQPC
DQC<0>DQC<1>DQC<2>DQC<3>DQC<4>DQC<5>
DQC<7>DQC<6>
DQPD
A<5>A<6>A<7>A<8>
A<10>
NC/288M
A<4>
A<14>A<15>A<16>A<17>A<18>A<19>A<20>ADV/LDCLK
WE*CEN*
NC/144M
DQD<2>
DQD<0>DQD<1>
DQD<4>
see UG370 p34
33R CLOSE TO IC
BANK 23: UNCONDITIONAL SWAP
SWAP BETWEEN BANKS 13,14,15,16,22,23,25,26,32,33,35 IS ALLOWED
FPGA PART1
BANK 16:DIFF.IMPEDANCE 100R
SWAP AA34,AA33 BY PAIR ONLY
BANK 13: UNCONDITIONAL SWAP
SWAP BY PAIR
BANK 0: NO SWAP
DIFF.IMPEDANCE 100RBANK 14:
DIFF.IMPEDANCE 100RSWAP BY PAIR
BANK 15:
SWAP BY PAIR
NO SWAP V32, V33SWAP _CC PAIRS ONLY BETWEEN THEM
BANK 12:
R.DIV.O.D.
DIFF.IMPEDANCE 100RSWAP BY PAIR
BANK 22: UNCONDITIONAL SWAP
EXCEPT AA34,AA33,AD30,AC30,AE33
SWAP _CC PAIRS ONLY BETWEEN THEM
AS LONG AS ALL INDIVIDUAL RESTRICTIONS ARE RESPECTED 3/15LAST_MODIFIED=Thu Jul 05 08:09:26 2012
Project file:glib.cpm
PCB by: PV DATE: nn/nn/nnnn
3/15
SYSTEM: SPB15.x
Design by: P.VICHOUDIS
MODULE:glib
EDA-02180-V3-0 PROJECT:GLIB
R91
C134C153
C137
L10
L9
R122
R177
R179
R178
R90
R174
R172
R18R17
R70
R61
R56
R51
R89R87
R69
R60
R59
R54
R92
R96R55
R50
R73
R64
R171R170R88
AN27
AP20
K26
N28
AM27
AP21
K27
N29
AH25
AF19
D34
N32
AJ25
AE19
C34
P32
L28
AN28
AM20
K28
M28
AM28
AL20
J29
L33
AL28
AC20
C33
M32
AK28
AD20
B34
N27
AN29
AN19
G31
P27
AP29
AN20
H30
AL29
AK22
A33
P31
AK29
AJ22
B33
P30
M26
AP30
AP19
F30
M27
AP31
AN18
G30
K32
AG25
AG22
E32
K31
AG26
AH22
E33
AN30
AM18
J26
N25
AM30
AL18
J27
M25
AP25
AP22
J31
P29
AP24
AN23
J32
R29
AK23
AG20
L25
N34
AL24
AG21
L26
P34
AN25
AM22
G32
M30
AN24
AN22
H32
N30
K34
AM25
AK21
K33
L34
AL25
AJ21
J34
R26
AP27
AM23
D31
T26
AP26
AL23
D32
AJ24
AC19
H34
R31
AK24
AD19
H33
R32
R28
AL26
AM21
J30
R27
AM26
AL21
K29
AK26
AJ20
E34
P25
AJ26
AH20
F34
P26
AH23
AF20
F31
L29
AH24
AF21
E31
L30
AK27
AK19
F33
N33
AJ27
AL19
G33
M33
AH27
AE21
C32
M31
AH28
AD21
B32
L31
IC2
V18
U17
U18
V17
Y8
N8
AF8
AC8
AD8
AE8
G8
L8
V8W8
U8
V30
AD30
AG27W30
AC30
AG28
U31
AE34
AN33U30
AF34
AN34
U28
AA28
AH29V29
AA29
AH30
U33
AA25
AL34U32
Y26
AK34
U26
AE31
AF28U27
AD31
AF29
T33
AC33
AJ34T34
AB33
AH34
T30
AB30
AE28T31
AB31
AE29
R33
AD34
AH33R34
AC34
AH32
T28
AA30
AE27T29
AA31
AD27
W27
AB25
AL30W26
AC25
AM31
W25
AG31
AP32V25
AF31
AP33
Y28
AA26
AN32Y27
AB26
AM32
W31
AG33
AM33W32
AG32
AL33
W29
AB27
AL31Y29
AC27
AK31
Y33
AD32
AK33Y34
AE32
AK32
Y32
AB28
AJ29Y31
AC28
AJ30
V32
AB32
AJ31V33
AC32
AJ32
V28
AD29
AF26V27
AC29
AE26
V34
AE33
AF30W34
AF33
AG30
U25
AA34
AD25T25
AA33
AD26
P8
M8
W18W17
AA8
R8
H8
F8
K8
T17T18
IC2
060310K
BLM15HD601SN1330
FMC1_HB05_P
FMC1_HB04_PFMC1_HB04_N
FMC1_LA33_P FMC1_LA09_P
XC6VLX130T-1FFG1156C
FMC1_HA09_NFMC1_LA19_PFMC1_LA19_NFMC1_LA01_P_CCFMC1_LA01_N_CCFMC1_LA18_P_CCFMC1_LA18_N_CC
FMC1_HA01_N_CC
V6_CPLD_0
FMC1_LA33_N
FMC1_HA02_PFMC1_LA02_NFMC1_LA02_PFMC1_HA11_N
SN2
V6_CDCE_REF_SELFMC2_PRSNT_M2C_LFMC1_PRSNT_M2C_LV6_ICS874003_OE 4.7K
SRAM1_DQA6SRAM1_DQA0
SRAM1_DQB2
SRAM1_DQB6
SRAM1_A7
BGA
FMC1_LA08_NFMC1_LA08_P
FMC1_LA30_N
FMC1_HB03_P
V6_CPLD_2
FMC1_HA22_N
FMC1_HA04_P
V6_TO_TRANSLATOR_5TRANSLATOR_TO_V6_1
FPGA_CCLK
0R0
FMC1_LA17_P_CCFMC1_LA17_N_CC
FMC1_LA00_N_CCFMC1_LA00_P_CC
FMC1_LA30_P
FMC1_LA24_NFMC1_LA24_P
FMC1_LA04_PFMC1_LA04_NFMC1_LA28_P
FMC1_LA03_P
SRAM1_A11SRAM1_DQC6SRAM1_DQD1
SRAM1_BWB
SRAM1_DQA3SRAM1_A20
SRAM1_DQB1SRAM1_DQA4
SRAM1_DQB7
SRAM1_DQB4
SRAM1_DQB5
SRAM1_ADV_LD_LSRAM1_DQD3
SRAM1_DQA7
SRAM1_DQA5SRAM1_DQPBSRAM1_DQB0
SRAM1_A16
FMC1_HA02_NFMC1_HA08_P
FMC1_HA05_N
FMC1_LA27_N
33
SN5
FMC1_HA07_N
FMC1_HA05_PFMC1_LA25_N
FMC1_HA14_NFMC1_HA14_P
V6_LED3V6_LED2V6_LED1
V6_CPLD_5
FMC1_HA04_N
FMC1_LA28_N
FMC1_LA13_N
FMC1_LA26_P
FMC1_HB02_N
FMC1_HB13_N
BLM15HD601SN1
1K4.7K
MONGND
XC6VLX130T-1FFG1156C
TRANSLATOR_TO_V6_7V6_TO_TRANSLATOR_12V6_TO_TRANSLATOR_15TRANSLATOR_TO_V6_5V6_TO_TRANSLATOR_6V6_TO_TRANSLATOR_1
V6_TO_TRANSLATOR_7V6_TO_TRANSLATOR_4
V6_TO_TRANSLATOR_11
FMC1_HB20_P
V6_CPLD_4
FMC1_HA11_P
FMC1_LA13_P
SRAM1_DQB3
SN3
SRAM1_A12
SRAM1_A4
SRAM1_DQA2
SRAM1_DQPASRAM1_A19
SRAM1_DQA1
FMC1_HA08_NFMC1_HA07_P
FMC1_LA09_NFMC1_HA06_P
FMC1_HA17_P_CCFMC1_HA17_N_CC
FMC1_LA03_NFMC1_HA10_PFMC1_HA10_NFMC1_LA12_PFMC1_LA12_NFMC1_LA11_PFMC1_LA11_NSN0SN1FMC1_HA21_P
V6_XPOINT1_S41V6_XPOINT1_S40SFP4_MOD_ABSSFP4_TXFAULTSFP1_MOD_ABS
FMC1_LA10_NFMC1_LA10_PFMC1_HA06_N
SN4
SN7SN6
FMC1_HA13_PFMC1_HA12_NFMC1_HA12_PFMC1_HA21_N
FMC1_HA01_P_CC
FMC1_HA15_PFMC1_HA15_N
FMC1_LA25_PFMC1_LA31_NFMC1_LA31_PFMC1_LA21_NFMC1_LA21_P
VRN_14
FMC1_HA00_P_CCFMC1_HA00_N_CC
49.9VRP_14
1%
SRAM1_A10
V6_TCLKB
FMC1_HA13_NFMC1_HA18_PFMC1_HA18_N
FMC1_LA32_PFMC1_LA32_N
FMC1_LA29_N
FMC1_LA26_NFMC1_LA16_PFMC1_LA16_NFMC1_HA03_PFMC1_HA03_N
33
4.7K
SFP3_MOD_ABSSFP2_RXLOSSFP1_TXFAULTSFP3_RXLOSSFP2_MOD_ABSSFP4_RXLOSSFP3_TXFAULTSFP1_RXLOS
FPGA_SDAFPGA_SCLV6_CDCE_SPI_MOSIV6_CDCE_PWR_DOWN
V6_XPOINT1_S10
V6_XPOINT2_S11
V6_CDCE_SYNC
CDCE_SPI_MISOCDCE_PLL_LOCKV6_XPOINT1_S11
V6_XPOINT1_S30V6_XPOINT1_S21
V6_XPOINT2_S10V6_TCLKB_DR_ENV6_XPOINT1_S20
V6_TO_TRANSLATOR_14TRANSLATOR_TO_V6_6
VN1.0UF
FPGA_TMS
V6_XPOINT1_S31
V6_ICS874003_FSEL
V6_ICS874003_MRV6_CDCE_SPI_LEV6_CDCE_SPI_CLK
FPGA_DXN
TRANSLATOR_TO_V6_2
FPGA_M0FPGA_PROGRAM_B
FPGA_CLKOUT
FMC1_HB03_N
FMC1_HA09_PFMC1_HA23_NFMC1_HA23_P
FMC1_LA22_N
FMC1_HA19_N
FMC1_LA27_P
FMC1_LA22_P
FMC1_HA19_P
FMC1_HA22_P
FMC1_LA05_P
FMC1_HA20_NFMC1_HA20_PFMC1_LA06_NFMC1_LA06_PFMC1_LA15_NFMC1_LA15_P
FMC1_LA05_N
FMC1_HA16_PFMC1_HA16_NFMC1_LA20_PFMC1_LA20_N
FPGA_INIT_BFPGA_DONEFPGA_M1
4.7K4.7K
TRANSLATOR_TO_V6_4V6_TO_TRANSLATOR_10
FPGA_TDO
TRANSLATOR_TO_V6_0V6_TO_TRANSLATOR_2TRANSLATOR_TO_V6_3
POWER_ON_RESET_BFPGA_RESET_B
V6_TO_TRANSLATOR_0
V6_CPLD_3
FMC1_HB13_P
FMC1_HB15_P
FMC1_HB20_N
V6_CPLD_1
V6_TO_TRANSLATOR_13V6_TO_TRANSLATOR_9
V6_TO_TRANSLATOR_8
SRAM1_A6SRAM1_A18
SRAM1_A17SRAM1_A3
4.7K
SFP2_TXFAULT
BGA
SRAM1_DQD2
SRAM1_DQD0SRAM1_DQC7
SRAM1_DQC5
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K
4.7K4.7K
4.7K
4.7K4.7K
4.7K
VCC0_12<3..0>
0123FMC1_VIO_B_M2C
FPGA_M2
FMC1_LA29_P
FMC1_LA07_NFMC1_LA07_P
VP
FPGA_DXP
10NF10NF
FPGA_TDI
FPGA_TCK
MONVCC
4.7K
V6_TO_TRANSLATOR_3
49.91%
FMC1_HB21_PFMC1_HB21_N
FMC1_HB11_PFMC1_HB11_N
FMC1_HB19_NFMC1_HB19_PFMC1_HB09_NFMC1_HB09_P
FMC1_HB18_NFMC1_HB18_PFMC1_HB16_N
FMC1_HB05_N
FMC1_HB16_PFMC1_HB12_NFMC1_HB12_P
FMC1_HB17_N_CCFMC1_HB17_P_CCFMC1_HB00_N_CCFMC1_HB00_P_CC
FMC1_HB06_P_CCFMC1_HB08_NFMC1_HB08_P
FMC1_HB14_NFMC1_HB14_P
FMC1_HB02_P
FMC1_HB06_N_CC
FMC1_HB01_PFMC1_HB01_N
FMC1_HB15_N
FMC1_HB10_PFMC1_HB10_NFMC1_HB07_PFMC1_HB07_N
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
1211 GENEVA 23SWITZERLAND
Project:Sheet:
Module:European Organizationfor Nuclear Research
4
EN/ICE
P2V5
P2V5
GND
P2V5
P2V5
P2V5
P2V5
P2V5
+ -
BANK 16 BANK 23
BANK 22BANK 15
Sym 2/5
IO_L0P_22IO_L0N_22IO_L1P_22
IO_L2P_22IO_L1N_22
IO_L2N_22IO_L3P_22IO_L3N_22
IO_L4N_VREF_22IO_L4P_22
IO_L5P_22IO_L5N_22IO_L6P_22
IO_L7P_22IO_L6N_22
IO_L7N_22IO_L8P_SRCC_22IO_L8N_SRCC_22
IO_L9N_MRCC_22IO_L9P_MRCC_22
IO_L10P_MRCC_22IO_L10N_MRCC_22IO_L11P_SRCC_22IO_L11N_SRCC_22IO_L12P_VRN_22IO_L12N_VRP_22
IO_L13N_22IO_L13P_22
IO_L14P_22IO_L14N_VREF_22
IO_L15P_22IO_L15N_22IO_L16P_22IO_L16N_22IO_L17P_22IO_L17N_22
IO_L18N_22IO_L18P_22
IO_L19P_22IO_L19N_22
IO_L0P_15
IO_L1P_15IO_L0N_15
IO_L1N_15
IO_L2N_SM8N_15IO_L2P_SM8P_15
IO_L3N_SM9N_15IO_L4P_15
IO_L3P_SM9P_15
IO_L4N_VREF_15IO_L5P_SM10P_15
IO_L6N_SM11N_15
IO_L5N_SM10N_15IO_L6P_SM11P_15
IO_L7N_SM12N_15IO_L7P_SM12P_15
IO_L8P_SRCC_15IO_L8N_SRCC_15IO_L9P_MRCC_15
IO_L10P_MRCC_15IO_L9N_MRCC_15
IO_L10N_MRCC_15IO_L11P_SRCC_15IO_L11N_SRCC_15
IO_L12N_SM13N_15IO_L12P_SM13P_15
IO_L13P_SM14P_15IO_L13N_SM14N_15IO_L14P_15IO_L14N_VREF_15
IO_L15N_SM15N_15IO_L15P_SM15P_15
IO_L16P_VRN_15IO_L16N_VRP_15
IO_L17N_15IO_L17P_15
IO_L18P_15IO_L18N_15IO_L19P_15IO_L19N_15
IO_L0P_23
IO_L1P_23IO_L0N_23
IO_L1N_23IO_L2P_23IO_L2N_23
IO_L3N_23IO_L4P_23
IO_L3P_23
IO_L4N_VREF_23IO_L5P_23IO_L5N_23IO_L6P_23IO_L6N_23IO_L7P_23IO_L7N_23
IO_L8N_SRCC_23IO_L9P_MRCC_23
IO_L8P_SRCC_23
IO_L9N_MRCC_23IO_L10P_MRCC_23IO_L10N_MRCC_23IO_L11P_SRCC_23IO_L11N_SRCC_23
IO_L12N_VRP_23IO_L12P_VRN_23
IO_L13P_23
IO_L14P_23IO_L13N_23
IO_L15N_23
IO_L14N_VREF_23IO_L15P_23
IO_L16P_23IO_L16N_23
IO_L18P_23IO_L17N_23IO_L17P_23
IO_L19P_23IO_L18N_23
IO_L19N_23
IO_L0P_16IO_L0N_16IO_L1P_16IO_L1N_16
IO_L2N_16IO_L2P_16
IO_L3N_16IO_L4P_16
IO_L3P_16
IO_L4N_VREF_16IO_L5P_16
IO_L6N_16
IO_L5N_16IO_L6P_16
IO_L7N_16IO_L7P_16
IO_L9P_MRCC_16IO_L8N_SRCC_16IO_L8P_SRCC_16
IO_L9N_MRCC_16IO_L10P_MRCC_16IO_L10N_MRCC_16IO_L11P_SRCC_16IO_L11N_SRCC_16
IO_L12N_VRP_16IO_L12P_VRN_16
IO_L13P_16
IO_L14P_16IO_L13N_16
IO_L15P_16IO_L14N_VREF_16
IO_L15N_16IO_L16P_16IO_L16N_16
IO_L17N_16IO_L18P_16
IO_L17P_16
IO_L19P_16IO_L18N_16
IO_L19N_16
VCCO_22[5]VCCO_15[5]
VCCO_23[4]VCCO_16[6]
GND
GND
BANK 12
BANK 0Sym 1/5
BANK 14
BANK 13
IO_L0P_13
IO_L1N_13IO_L1P_13IO_L0N_13
IO_L2P_13IO_L2N_13IO_L3P_13
IO_L4P_13IO_L3N_13
IO_L4N_VREF_13
IO_L5N_13IO_L5P_13
IO_L6P_13IO_L6N_13IO_L7P_13IO_L7N_13
IO_L8P_SRCC_13
IO_L9P_MRCC_13IO_L8N_SRCC_13
IO_L10P_MRCC_13IO_L9N_MRCC_13
IO_L10N_MRCC_13IO_L11P_SRCC_13IO_L11N_SRCC_13IO_L12P_VRN_13
IO_L13P_13IO_L12N_VRP_13
IO_L13N_13IO_L14P_13
IO_L14N_VREF_13
IO_L15N_13IO_L15P_13
IO_L16P_13IO_L16N_13IO_L17P_13IO_L17N_13IO_L18P_13IO_L18N_13IO_L19P_13IO_L19N_13
VCCO_13[5]
IO_L0P_14IO_L0N_14IO_L1P_14IO_L1N_14IO_L2P_14IO_L2N_14IO_L3P_14
IO_L4P_14IO_L3N_14
IO_L4N_VREF_14IO_L5P_14IO_L5N_14
IO_L6N_14IO_L6P_14
IO_L7P_14IO_L7N_14
IO_L8P_SRCC_14
IO_L9P_MRCC_14IO_L8N_SRCC_14
IO_L9N_MRCC_14IO_L10P_MRCC_14IO_L10N_MRCC_14
IO_L11N_SRCC_14IO_L11P_SRCC_14
IO_L12P_VRN_14IO_L12N_VRP_14
IO_L13P_14IO_L13N_14IO_L14P_14
IO_L14N_VREF_14
IO_L15N_14IO_L15P_14
IO_L16P_14IO_L16N_14IO_L17P_14IO_L17N_14IO_L18P_14IO_L18N_14IO_L19P_14
VCCO_14[4]
IO_L19N_14
INIT_B_0DONE_0M1_0M2_0HSWAPEN_0PROGRAM_B_0M0_0AVSS_0AVDD_0
VREFP_0VP_0
VN_0VREFN_0DXP_0DXN_0VBATT_0DIN_0RDWR_B_0CSI_B_0
CCLK_0DOUT_BUSY_0
TDO_0TCK_0TMS_0TDI_0VFS_0
VCCO_0[2]
IO_L0P_12IO_L0N_12IO_L1P_12IO_L1N_12IO_L2P_12IO_L2N_12IO_L3P_12
IO_L4P_12IO_L3N_12
IO_L4N_VREF_12IO_L5P_12IO_L5N_12IO_L6P_12IO_L6N_12IO_L7P_12IO_L7N_12IO_L8P_SRCC_12
IO_L9P_MRCC_12IO_L8N_SRCC_12
IO_L9N_MRCC_12IO_L10P_MRCC_12IO_L10N_MRCC_12IO_L11P_SRCC_12IO_L11N_SRCC_12IO_L12P_VRN_12IO_L12N_VRP_12IO_L13P_12IO_L13N_12IO_L14P_12IO_L14N_VREF_12
IO_L15N_12IO_L15P_12
IO_L16P_12IO_L16N_12IO_L17P_12IO_L17N_12IO_L18P_12IO_L18N_12IO_L19P_12
VCCO_12[4]
IO_L19N_12
P2V5
GND
P2V5P2V5
GND
GND
P2V5
GND
P2V5
BANK 34: NO SWAP
FPGA PART2
DIFF.IMPEDANCE 100RSWAP BY PAIR EXCEPT H28,H29,B31,A31
FD15FD14FD13
BANK 33:DIFF.IMPEDANCE 100R
FA5
33R CLOSE TO IC
SWAP BY PAIR
BANK 35:
SWAP BY PAIR
FD11
FD6
NO SWAPBANK 24:
SWAP _CC PAIRS ONLY BETWEEN THEMSWAP BY PAIRDIFF.IMPEDANCE 100R
EXCEPT AC15
FD4
FD8
FD12
FA4
FA6FA7FA8FA9FA10FA11FA12FA13FA14FA15
BANK 36:
FD3
AS LONG AS ALL INDIVIDUAL RESTRICTIONS ARE RESPECTED
BANK 26:
FD5
FD9FD10
L18P_24
FD7
UNCONDITIONAL SWAP
SWAP _CC PAIRS ONLY BETWEEN THEMSWAP BY PAIR DIFF.IMPEDANCE 100RBANK 26:
FWE_BFOE_B
SWAP BETWEEN BANKS 13,14,15,16,22,23,25,26,32,33,35 IS ALLOWED
33R CLOSE TO IC
FA21FA20FA19FA18FA17FA16
FA1FA0
FA22
DIFF.IMPEDANCE 100R
SWAP _CC PAIRS ONLY BETWEEN THEM
FD2FD1
BANK 25:
FD0FCS_B
FA2FA3
4/15LAST_MODIFIED=Thu Jul 05 08:09:26 2012
Project file:glib.cpm
PCB by: PV DATE: nn/nn/nnnn
4/15
SYSTEM: SPB15.x
Design by: P.VICHOUDIS
MODULE:glib
EDA-02180-V3-0 PROJECT:GLIB
R210
R211
R102R103
R98R99
R100R68 AC15
B20
C28
J25
AD15
C19
B28
J24
AH17
F19
D24
T24
AG17
F20
E24
T23
H25
AP16
A20
B27
H24
AP15
A21
C27
R24
AJ17
E22
G26
P24
AJ16
E23
G27
H23
AN15
B21
B26
G23
AM15
B22
A26
N23
AG16
J20
D27
N24
AF16
J21
E27
F24
AL15
B23
B25
F23
AL14
C23
A25
M23
AJ15
G21
E26
L24
AH15
G22
F26
K24
AK14
A23
C24
K23
AJ14
A24
C25
B31 AL16
C22AC22
A31 AK16
D22AD22
H28 AE18
L20AC23
H29 AF18
L21AC24
AE23
AK18
B18
C30
AE22
AK17
C18
D30
E29
AA23
AD17
K21
F29
AB23
AE17
K22
AF23
AM17
A18
A30
AG23
AM16
A19
B30
Y24
AJ19
H22
F28
AA24
AH19
J22
E28
AF25
AN17
E19
A28
AF24
AP17
D19
A29
AH18
D21V24
H27AG18
E21W24
G28
AC18
H19
F25
AD24
AC17
H20
G25
AE24
AE16
F21
C29
U23
AD16
G20
D29
V23
L23
AG15
C20
D25
M22
AF15
D20
D26
IC2
K16
L13
L10
AC13
L16
M13
M10
AC12
G18
K14
L9
AJ10
H18
J14
K9
AH10
B12
B8 M18
AL11B13
C8 M17
AM11
H10
E8 K19
AG11G10
E9 J19
AG10
F14
A9 C17
AM10E14
A8 B17
AL10
C9 L19
G12AF11
D9 L18
H13AE11
A13
C10 H17
AK12A14
D10 G17
AJ12
G11
F9 K18
AD14F11
F10 K17
AC14
A10 E18
D14AJ11
B10 D17
C14AK11
AN10
D11
D15
AP14
AP10
E11
C15
AN14
K13
AG8 H15
AH13K12
AH8 J15
AH14
AN9 M16
D12AK13
AP9 M15
E12AL13
K11
AF9 G15
AG12L11
AF10 F15
AH12
E13
AK9 A15
AN13F13
AL9 B15
AM13
AD9 J17
J11AE14
AE9 J16
J10AF14
A11
AK8 E16
AM12B11
AL8 D16
AN12
F16
AF13 H12
AD10G16
AG13 J12
AC9
A16
C13
AH9
AP11
B16
C12
AJ9
AP12
L15
M12
AC10
AD12
L14
M11
AB10
AD11
J9 F18
G13AE13
H9 E17
H14AE12
IC2
XPOINT1_CLK1_PXPOINT1_CLK1_N
XPOINT1_CLK3_N
SRAM2_A13
FMC2_HB02_NFMC2_HB02_PFMC2_HB17_N_CCFMC2_HB17_P_CC
FMC1_LA23_NFMC1_LA23_PFMC2_HA05_N
SRAM1_DQPCSRAM1_BWCSRAM1_A0SRAM1_A1GBE_SCL
SRAM2_DQPCSRAM2_DQPDSRAM2_DQD4SRAM2_DQD3
SRAM1_CE1_L
SRAM1_DQC1
SRAM1_A13
VRN_24
SRAM2_WE_LSRAM2_OE_L
SRAM2_DQA0
SRAM2_DQA3
SRAM2_DQC1SRAM2_DQC2SRAM2_DQC3
VRP_24
SRAM2_DQD5FPGA_RS0
SRAM2_DQA1SRAM2_DQA2
CDCE_OUT4_PCDCE_OUT4_NFMC1_CLK2_BIDIR_PFMC1_CLK2_BIDIR_N
FMC2_HA18_P
AMC_P13_RX_PAMC_P13_RX_N
AMC_P15_TX_PAMC_P15_TX_N
FMC2_HB08_P
FMC2_HB14_NFMC2_HB13_PFMC2_HB13_N
FMC2_HB14_P
FMC2_HB06_N_CCFMC2_HB06_P_CCFMC2_HB00_N_CCFMC2_HB00_P_CCFMC2_HB04_NFMC2_HB04_PFMC2_HB03_N
FMC2_HB05_PFMC2_HB05_NFMC2_HB03_P
FMC2_HA10_NFMC2_HA10_PFMC2_HA20_NFMC2_HA20_PFMC2_LA19_NFMC2_LA19_PFMC2_LA16_NFMC2_LA16_PFMC2_HA14_N
AMC_P15_RX_N
FMC2_LA32_N
SRAM2_DQA4
SRAM2_DQA6
SRAM2_DQB1
SRAM1_A5
SRAM1_DQD5
SRAM2_BWB
SRAM1_DQD7
SRAM1_CEN_L
SRAM2_BWA
SRAM1_DQD6SRAM2_A0SRAM2_DQD6SRAM2_BWDSRAM2_BWC
FPGA_A22FPGA_A21
SRAM2_A1
FMC1_CLK1_M2C_P
FMC1_CLK0_M2C_XPOINT2_P
SRAM2_DQC0
SRAM1_A8
FMC2_LA07_P
FMC2_LA11_NFMC2_LA11_PFMC1_LA14_NFMC1_LA14_P
SRAM2_CEN_LSRAM2_MODE
SRAM1_WE_L
SRAM1_A9
FMC2_CLK1_M2C_NFMC2_CLK1_M2C_PFMC1_CLK3_BIDIR_NFMC1_CLK3_BIDIR_PCDCE_SEC_REF_NCDCE_SEC_REF_PFMC2_HA04_NFMC2_HA04_PFMC2_HA03_N
FMC2_LA03_P
FMC2_HA03_P
FMC2_HA01_P_CCFMC2_HA01_N_CC
FMC2_HA11_N
AMC_P15_RX_P
FMC2_LA32_P
SRAM2_CLK
SRAM2_A9SRAM2_A8SRAM2_A7
FMC2_LA30_NFMC2_LA30_PFMC2_HA18_N
SRAM2_DQC5SRAM2_DQC6
FMC2_LA12_N
FPGA_RS1
FMC2_HA16_N
FMC2_LA05_NFMC2_LA09_P
49.949.9
SRAM2_A12
XPOINT1_CLK3_P
SRAM2_A15SRAM2_A14
SRAM2_A11SRAM2_A10
SRAM2_A6SRAM2_A5SRAM2_A4
VRN_34VRP_34
FMC2_HA12_P
FMC2_LA23_P
FMC2_LA26_PFMC2_LA26_NFMC2_LA10_PFMC2_LA10_NFMC2_LA02_PFMC2_LA02_NFMC2_HA15_PFMC2_HA15_N
FMC2_LA14_PFMC2_LA14_NFMC2_LA13_PFMC2_LA13_NFMC2_HA19_PFMC2_HA19_NFMC2_LA22_PFMC2_LA22_NFMC2_LA18_P_CCFMC2_LA18_N_CC
FMC2_LA00_N_CCFMC2_LA01_P_CCFMC2_LA01_N_CC
FMC2_LA23_NFMC2_LA25_PFMC2_LA25_N
FMC2_HA08_PFMC2_HA08_NFMC2_HB20_PFMC2_HB20_NFMC2_LA04_PFMC2_LA04_NFMC2_LA20_PFMC2_LA20_N
FMC2_LA27_NFMC2_LA27_PFMC2_HA07_N
SRAM1_DQD4SRAM1_DQPDGBE_INT_NGBE_SDASRAM1_DQC0SRAM1_DQC4SRAM1_A14SRAM1_MODESRAM1_A2
GBE_RESET_N
SRAM1_CLK
4.7K
SRAM2_DQB0
SRAM2_DQB3
SRAM2_DQB5
FMC2_LA24_N
FMC2_HA23_NFMC2_LA08_P
FMC2_HA11_P
AMC_P12_TX_P
FMC2_HB09_P
FMC2_LA06_NFMC2_HA13_PFMC2_HA13_NFMC2_HA09_P
FMC2_HA05_PFMC2_LA07_N
FMC2_LA03_N
FMC2_HB19_N
FMC2_HB11_N
33
FMC2_HA22_N
FMC2_HB08_N
FMC2_HA09_N
FMC2_LA06_PFMC2_LA09_N
FMC2_LA05_P
AMC_P13_TX_P
FMC2_HA16_P
49.9
SRAM2_CE2
FMC2_HB21_NFMC2_HB21_P
FMC2_LA33_N
FMC2_LA21_N
FMC2_HA14_P
FMC2_HA06_PFMC2_HA06_N
FMC2_LA21_P
AMC_P2_TX_NAMC_P2_TX_P
49.9
FMC2_LA24_P
FMC2_HA23_P
SRAM2_DQB2
SRAM2_DQB4
SRAM2_DQB6SRAM2_DQB7
4.7K
FMC2_HA02_N
SRAM2_DQA7
SRAM2_DQA5
FMC2_VIO_B_M2C
33
3 012
SRAM2_DQC4
SRAM2_DQC7
FMC2_HA02_P
FMC2_LA00_P_CC
FMC2_HA07_P
BGABGA VCC0_36<3..0>
FMC2_HB15_PFMC2_HB15_N
FMC2_HB18_PFMC2_HB18_N
FMC2_HB12_NFMC2_HB12_P
FMC2_HB11_P
FMC2_HB19_P
FMC2_HB01_N
AMC_P14_RX_PAMC_P14_TX_NAMC_P14_TX_P
AMC_P13_TX_N
AMC_P12_RX_N
AMC_P12_TX_NAMC_P12_RX_P
AMC_P3_RX_NAMC_P3_RX_PAMC_P3_TX_N
AMC_P2_RX_NAMC_P3_TX_P
SRAM2_DQPASRAM2_DQPB
FMC2_LA31_PFMC2_LA31_NFMC2_HA21_PFMC2_HA21_NFMC2_LA28_PFMC2_LA28_NFMC2_LA15_PFMC2_LA15_NFMC2_LA29_PFMC2_LA29_NFMC2_LA17_P_CCFMC2_LA17_N_CCFMC2_HA17_P_CCFMC2_HA17_N_CCFMC2_LA12_P
FMC2_LA33_P
FMC2_HA12_N
FMC2_HB01_P
AMC_P2_RX_P
SRAM2_ADV_LD_LSRAM2_DQD7SRAM2_A3SRAM2_A2
SRAM2_A16SRAM2_A17SRAM2_A18SRAM2_A19SRAM2_A20
FMC2_HA22_PFMC2_LA08_N
FMC2_HB10_NFMC2_HB10_PFMC2_HB07_NFMC2_HB07_PFMC2_HB09_N
XC6VLX130T-1FFG1156C XC6VLX130T-1FFG1156C
AMC_P14_RX_N
FMC2_HA00_N_CCFMC2_HA00_P_CC
SRAM2_DQD0SRAM2_DQD1
SRAM2_CE1_LFMC1_CLK0_M2C_XPOINT2_N
FMC1_CLK1_M2C_N
FMC2_HB16_PFMC2_HB16_N
SRAM2_DQD2
SRAM1_DQC3SRAM1_DQC2
SRAM1_OE_L
SRAM1_A15SRAM1_BWASRAM1_BWD
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
1211 GENEVA 23SWITZERLAND
Project:Sheet:
Module:European Organizationfor Nuclear Research
4
EN/ICE
P2V5
P2V5
P2V5
P2V5 P2V5
P2V5
P2V5
GND
GND
BANK 32
BANK 24 BANK 26Sym 3/5
BANK 25
IO_L16N_26IO_L16P_26
IO_L8P_SRCC_24IO_L8N_SRCC_24IO_L9P_MRCC_24IO_L9N_MRCC_24
IO_L8P_SRCC_32IO_L8N_SRCC_32
IO_L19N_GC_25
VCCO_25[4]
IO_L18N_GC_25IO_L19P_GC_25
IO_L17P_25IO_L17N_25IO_L18P_GC_25
IO_L16N_VRP_25IO_L16P_VRN_25IO_L15N_25
IO_L14N_VREF_25IO_L15P_25
IO_L13N_25IO_L14P_25
IO_L12P_25
IO_L13P_25IO_L12N_25
IO_L11N_SRCC_25IO_L11P_SRCC_25IO_L10N_MRCC_25IO_L10P_MRCC_25IO_L9N_MRCC_25
IO_L8P_SRCC_25IO_L8N_SRCC_25IO_L9P_MRCC_25
IO_L7P_25IO_L7N_25
IO_L6P_25IO_L5N_25
IO_L6N_25
IO_L5P_25IO_L4N_VREF_25
IO_L3P_25IO_L3N_25IO_L4P_25
IO_L2P_25IO_L2N_25
IO_L1N_25IO_L1P_25IO_L0N_25IO_L0P_25
VCCO_24[6]
IO_L18N_24IO_L19P_24IO_L19N_24
IO_L18P_24IO_L17N_VRP_24IO_L17P_VRN_24
IO_L16P_RS0_24IO_L16N_CSO_B_24
IO_L15P_FWE_B_24IO_L15N_RS1_24
IO_L13N_D0_FS0_24
IO_L14N_VREF_FOE_B_MOSI_24
IO_L14P_FCS_B_24
IO_L12N_D2_FS2_24IO_L13P_D1_FS1_24
IO_L12P_D3_24IO_L11N_SRCC_24IO_L11P_SRCC_24
IO_L10P_MRCC_24IO_L10N_MRCC_24
IO_L7P_D5_24IO_L7N_D4_24
IO_L6N_D6_24IO_L6P_D7_24
IO_L4N_VREF_D10_24
IO_L5N_D8_24IO_L5P_D9_24
IO_L3N_D12_24IO_L4P_D11_24
IO_L3P_D13_24IO_L2N_D14_24IO_L2P_D15_24IO_L1N_GC_24IO_L1P_GC_24IO_L0N_GC_24IO_L0P_GC_24
IO_L19N_32
VCCO_32[5]
IO_L18N_32IO_L19P_32
IO_L17P_32IO_L17N_32IO_L18P_32
IO_L16P_32IO_L16N_32
IO_L15N_32
IO_L14N_VREF_32IO_L15P_32
IO_L13N_32IO_L14P_32
IO_L12P_VRN_32
IO_L13P_32IO_L12N_VRP_32
IO_L11N_SRCC_32IO_L11P_SRCC_32IO_L10N_MRCC_32
IO_L9N_MRCC_32IO_L10P_MRCC_32
IO_L9P_MRCC_32
IO_L7P_32IO_L7N_32
IO_L6P_32IO_L5N_32
IO_L6N_32
IO_L5P_32IO_L4N_VREF_32
IO_L3P_32
IO_L4P_32IO_L3N_32
IO_L2P_32IO_L2N_32
IO_L1N_32IO_L1P_32IO_L0N_32IO_L0P_32
VCCO_26[5]
IO_L18N_26IO_L19P_26IO_L19N_26
IO_L18P_26IO_L17N_26IO_L17P_26
IO_L15P_26IO_L15N_26
IO_L13N_26IO_L14P_26
IO_L14N_VREF_26
IO_L12N_VRP_26IO_L13P_26
IO_L12P_VRN_26IO_L11N_SRCC_26IO_L11P_SRCC_26
IO_L9N_MRCC_26IO_L10P_MRCC_26IO_L10N_MRCC_26
IO_L8N_SRCC_26IO_L9P_MRCC_26
IO_L8P_SRCC_26
IO_L7P_26IO_L7N_26
IO_L6N_26IO_L6P_26
IO_L4N_VREF_26IO_L5P_26IO_L5N_26
IO_L3N_26IO_L4P_26
IO_L3P_26IO_L2N_26IO_L2P_26IO_L1N_26IO_L1P_26IO_L0N_26IO_L0P_26
P2V5
Sym 4/5BANK 35BANK 33
BANK 36BANK 34
IO_L19N_VRP_34IO_L19P_VRN_34IO_L18N_A16_34
IO_L17N_A18_34IO_L18P_A17_34
IO_L17P_A19_34IO_L16N_A20_34IO_L16P_A21_34
IO_L15P_A23_34IO_L15N_A22_34
IO_L14N_VREF_A24_34IO_L14P_A25_34IO_L13N_A00_D16_34
IO_L12N_A02_D18_34IO_L13P_A01_D17_34
IO_L12P_A03_D19_34IO_L11N_SRCC_34IO_L11P_SRCC_34
IO_L10P_MRCC_34IO_L10N_MRCC_34
IO_L9N_MRCC_34IO_L9P_MRCC_34IO_L8N_SRCC_34IO_L8P_SRCC_34IO_L7N_A04_D20_34IO_L7P_A05_D21_34
IO_L6P_A07_D23_34IO_L6N_A06_D22_34
IO_L5N_A08_D24_34IO_L5P_A09_D25_34IO_L4N_VREF_A10_D26_34
IO_L3N_A12_D28_34IO_L4P_A11_D27_34
IO_L3P_A13_D29_34IO_L2N_A14_D30_34IO_L2P_A15_D31_34
IO_L1P_GC_34IO_L1N_GC_34
IO_L0N_GC_34IO_L0P_GC_34
IO_L0P_33IO_L0N_33IO_L1P_33IO_L1N_33
IO_L2N_33IO_L2P_33
IO_L3P_33
IO_L4P_33IO_L3N_33
IO_L4N_VREF_33IO_L5P_33
IO_L6P_33IO_L5N_33
IO_L6N_33
IO_L7N_33IO_L7P_33
IO_L9P_MRCC_33IO_L8N_SRCC_33IO_L8P_SRCC_33
IO_L10P_MRCC_33IO_L9N_MRCC_33
IO_L10N_MRCC_33IO_L11P_SRCC_33IO_L11N_SRCC_33
IO_L13P_33
IO_L12P_VRN_33IO_L12N_VRP_33
IO_L13N_33IO_L14P_33
IO_L15P_33IO_L14N_VREF_33
IO_L15N_33IO_L16P_33IO_L16N_33
IO_L18P_33
IO_L17P_33IO_L17N_33
IO_L18N_33IO_L19P_33IO_L19N_33
IO_L0N_35IO_L0P_35
IO_L1P_35
IO_L2P_SM0P_35IO_L1N_35
IO_L3N_SM1N_35IO_L3P_SM1P_35IO_L2N_SM0N_35
IO_L4N_VREF_35IO_L4P_35
IO_L5P_SM2P_35IO_L5N_SM2N_35IO_L6P_SM3P_35IO_L6N_SM3N_35IO_L7P_SM4P_35
IO_L8N_SRCC_35IO_L8P_SRCC_35IO_L7N_SM4N_35
IO_L9P_MRCC_35IO_L9N_MRCC_35IO_L10P_MRCC_35IO_L10N_MRCC_35IO_L11P_SRCC_35
IO_L12N_SM5N_35IO_L12P_SM5P_35IO_L11N_SRCC_35
IO_L13P_SM6P_35IO_L13N_SM6N_35
IO_L14N_VREF_35IO_L14P_35
IO_L15P_SM7P_35IO_L15N_SM7N_35IO_L16P_VRN_35
IO_L17N_35IO_L17P_35
IO_L16N_VRP_35
IO_L18P_GC_35IO_L18N_GC_35
IO_L19N_GC_35IO_L19P_GC_35
IO_L19N_36IO_L19P_36IO_L18N_36
IO_L17P_36IO_L17N_36IO_L18P_36
IO_L16P_36IO_L16N_36
IO_L15N_36
IO_L14N_VREF_36IO_L15P_36
IO_L14P_36IO_L13N_36IO_L13P_36
IO_L12P_VRN_36IO_L12N_VRP_36
IO_L11N_SRCC_36IO_L11P_SRCC_36IO_L10N_MRCC_36
IO_L9N_MRCC_36IO_L10P_MRCC_36
IO_L8P_SRCC_36IO_L8N_SRCC_36IO_L9P_MRCC_36
IO_L7N_36IO_L7P_36IO_L6N_36IO_L6P_36IO_L5N_36
IO_L4N_VREF_36IO_L5P_36
IO_L3P_36IO_L3N_36IO_L4P_36
IO_L2N_36IO_L2P_36IO_L1N_36IO_L1P_36IO_L0N_36IO_L0P_36
VCCO_36[4]VCCO_34[6]
VCCO_35[5\]VCCO_33[5]
P2V5 P
2V5
P2V5
UNUSED
FMC#1
FMC1_VADJFMC1_VADJ
FMC1_VREF_B_M2C
FMC1_VADJFMC1_VADJ
FMC1_RES0
FMC1_33P3VAUX
FMC1_VREF_A_M2C
FMC1_GA1FMC1_GA0
33R CLOSE TO CONNECTOR
FMC1_TRST_L
I2C ADDRESS
IS POWERED BY 3V3AUXTHE I2C EEPROM OF THE FMC
10100 GA0 GA1
5/15LAST_MODIFIED=Thu Jul 05 08:09:27 2012
Project file:glib.cpm
PCB by: PV DATE: nn/nn/nnnn
5/15
SYSTEM: SPB15.x
Design by: P.VICHOUDIS
MODULE:glib
EDA-02180-V3-0 PROJECT:GLIB
21
R86
K40K39K38K37K36K35K34K33K32K31K30K29K28K27K26K25K24K23K22K21K20K19K18K17K16K15K14K13K12K11K10K9K8K7K6K5K4K3K2K1
J40J39J38J37J36J35J34J33J32J31J30J29J28J27J26J25J24J23J22J21J20J19J18J17J16J15J14J13J12J11J10J9J8J7J6J5J4J3J2J1
J2
H40H39H38H37H36H35H34H33H32H31H30H29H28H27H26H25H24H23H22H21H20H19H18H17H16H15H14H13H12H11H10H9H8H7H6H5H4H3H2H1
G40G39G38G37G36G35G34G33G32G31G30G29G28G27G26G25G24G23G22G21G20G19G18G17G16G15G14G13G12G11G10G9G8G7G6G5G4G3G2G1
J2
F40F39F38F37F36F35F34F33F32F31F30F29F28F27F26F25F24F23F22F21F20F19F18F17F16F15F14F13F12F11F10F9F8F7F6F5F4F3F2F1
E40E39E38E37E36E35E34E33E32E31E30E29E28E27E26E25E24E23E22E21E20E19E18E17E16E15E14E13E12E11E10E9E8E7E6E5E4E3E2E1
J2
D40D39D38D37D36D35D34D33D32D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1
C40C39C38C37C36C35C34C33C32C31C30C29C28C27C26C25C24C23C22C21C20C19C18C17C16C15C14C13C12C11C10C9C8C7C6C5C4C3C2C1
J2
B40B39B38B37B36B35B34B33B32B31B30B29B28B27B26B25B24B23B22B21B20B19B18B17B16B15B14B13B12B11B10B9B8B7B6B5B4B3B2B1
A40A39A38A37A36A35A34A33A32A31A30A29A28A27A26A25A24A23A22A21A20A19A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1
J2
R84
SEAF-40-06.5-S-10-2-A SEAF-40-06.5-S-10-2-A
SEAF-40-06.5-S-10-2-ASEAF-40-06.5-S-10-2-ASEAF-40-06.5-S-10-2-A
FMC1_DP1_C2M_PFMC1_DP1_C2M_N
FMC1_DP2_C2M_PFMC1_DP2_C2M_N
FMC1_DP3_C2M_PFMC1_DP3_C2M_N
GND
GND
GND
FMC1_GBTCLK1_M2C_N
GNDGNDFMC1_LA10_NFMC1_LA10_PGNDGNDFMC1_LA06_NFMC1_LA06_PGNDGNDFMC1_DP0_M2C_NFMC1_DP0_M2C_P
FMC1_DP0_C2M_P
GND
FMC1_LA03_N
FMC1_LA08_P
FMC1_LA28_PFMC1_LA28_N
FMC1_LA30_P
FMC1_HB01_PGNDFMC1_HA22_N
FMC1_HA18_N
FMC1_HA14_P
FMC1_HA11_P
FMC1_HA07_N
FMC1_HA03_N
GND
FMC1_CLK3_BIDIR_P
P3V3
GND
FMC1_CLK3_BIDIR_N
FMC1_HA03_P
FMC1_HA07_P
GNDFMC1_LA13_N
FMC1_LA17_P_CCFMC1_LA17_N_CC
FMC1_HB09_N
FMC1_HB13_P
FMC1_HB19_N
FMC1_HB21_P
P3V3
GND
FMC1_TDIFMC1_TCK
33
FMC1_TMS
FMC1_PRSNT_M2C_L
P3V3FMC1_HB19_P
FMC1_LA13_P
FMC1_HB03_PFMC1_HB03_NGNDFMC1_HB05_PFMC1_HB05_N
FMC1_HB09_P
GNDFMC1_HA20_N
FMC1_LA09_PFMC1_LA09_N
GND
GND
FMC1_DP1_M2C_P
FMC1_LA20_N
FMC1_LA29_P
FMC1_LA25_N
FMC1_LA22_P
GND
FMC1_GBTCLK1_M2C_P
100KFMC1_CLK_DIR
GND
GNDGND
GND
FMC1_LA14_NFMC1_LA14_PGND
GND
FMC1_LA31_P
FMC1_LA11_N
FMC1_LA07_N
FMC1_LA04_N
GND
FMC1_LA18_N_CCGNDGNDFMC1_LA27_PFMC1_LA27_NGNDGNDMMC_SCLMMC_SDAGNDGND
P3V3
GND
GNDFMC1_HB13_N
FMC1_GBTCLK0_M2C_P
FMCX_PG_C2M
FMC1_GBTCLK0_M2C_N
FMC1_LA01_P_CC
GNDGND
GND
GND
FMC1_LA05_NFMC1_LA05_P
FMC1_LA01_N_CC
GND
GND
FMC1_LA26_P
FMC1_LA00_N_CC
GND
GNDFMC1_LA12_P
GND
GNDGND
GND
FMC1_LA23_P
GND
FMC1_CLK0_M2C_N
FMC1_LA02_N
FMC1_HA22_P
FMC1_HB01_N
FMC1_HB07_PFMC1_HB07_N
FMC1_HB11_PFMC1_HB11_N
GND
FMC1_HA11_NGND
FMC1_HA14_N
FMC1_HA18_P
FMC1_LA24_P
FMC1_LA21_N
FMC1_LA00_P_CC
FMC1_CLK1_M2C_NFMC1_CLK1_M2C_PGND
FMC1_CLK2_BIDIR_PFMC1_CLK2_BIDIR_NGND
FMC1_LA19_P
FMC1_LA15_NFMC1_LA15_P
GND
GND
FMC1_TDO
FMC1_LA26_N
GND
GND
GND
GND
FMC1_LA23_N
GND
GND
GND
GNDGND
GND
GND
FMC1_LA18_P_CCGNDGND
GNDFMC1_DP0_C2M_N
GND
P3V3
GNDFMC1_HB15_P
FMC1_HB18_N
FMC1_CLK0_M2C_P
GND
GNDGND
FMC1_HA00_P_CCGNDGND
FMC1_HA16_N
FMC1_HA20_P
GNDFMC1_HB20_NFMC1_HB20_PFMC1_HB21_NGNDFMC1_HB16_NFMC1_HB16_PGNDFMC1_HB12_NFMC1_HB12_PGNDFMC1_HB08_NGNDFMC1_HB08_PGNDFMC1_HB04_NGNDFMC1_HB04_PGNDFMC1_HB02_NFMC1_HB02_PGNDFMC1_HA19_NFMC1_HA19_PGNDFMC1_HA15_NGNDFMC1_HA15_PGNDFMC1_HA16_PFMC1_HA12_NGNDFMC1_HA12_PFMC1_HA13_NGNDFMC1_HA13_PFMC1_HA08_NGNDFMC1_HA08_PFMC1_HA09_NGNDFMC1_HA09_PFMC1_HA04_NGNDFMC1_HA04_PFMC1_HA05_NGNDFMC1_HA05_PFMC1_HA00_N_CCGND
GNDFMC1_HA01_N_CCFMC1_HA01_P_CC
FMC1_PG_M2C
GNDGNDFMC1_LA32_NGNDFMC1_LA32_PFMC1_LA33_NGNDFMC1_LA33_PFMC1_LA30_NGND
FMC1_LA31_NGND
GNDFMC1_LA29_N
GNDFMC1_LA24_NGND
GNDFMC1_LA25_PGND
FMC1_LA21_PFMC1_LA22_NGNDFMC1_LA19_NGND
GNDFMC1_LA20_PGNDFMC1_LA16_N
GNDFMC1_LA16_P
FMC1_LA11_PFMC1_LA12_NGND
FMC1_LA07_PFMC1_LA08_NGND
FMC1_LA04_PGNDFMC1_LA03_P
FMC1_LA02_PGND
GNDGND
FMC1_VIO_B_M2CGNDGNDFMC1_VIO_B_M2CFMC1_HB17_N_CCGNDFMC1_HB17_P_CCGNDFMC1_HB18_PFMC1_HB14_NGNDFMC1_HB14_PFMC1_HB15_NGNDFMC1_HB10_NFMC1_HB10_PGNDFMC1_HB06_N_CCFMC1_HB06_P_CCGNDFMC1_HB00_N_CCGNDFMC1_HB00_P_CCGNDFMC1_HA23_NFMC1_HA23_P
FMC1_HA21_NGNDFMC1_HA21_PGNDFMC1_HA17_N_CCGNDFMC1_HA17_P_CCGNDFMC1_HA10_NFMC1_HA10_PGNDFMC1_HA06_NGNDFMC1_HA06_PGNDFMC1_HA02_NGNDFMC1_HA02_P
GND
GNDGND
GND
FMC1_DP1_M2C_NGNDGNDFMC1_DP2_M2C_PFMC1_DP2_M2C_N GND
GNDFMC1_DP3_M2C_PFMC1_DP3_M2C_NGNDGND
GND
GND
GNDGND
GNDGND
GNDGND
GND
GND
GND
GNDGND
GND
GND
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
1211 GENEVA 23SWITZERLAND
Project:Sheet:
Module:European Organizationfor Nuclear Research
4
EN/ICE
K40J40K39J39K38J38K37J37K36J36K35J35K34J34K33J33K32J32K31J31K30J30K29J29K28J28K27J27K26J26K25J25K24J24K23J23K22J22K21J21K20J20K19J19K18J18K17J17K16J16K15J15K14J14K13J13K12J12K11J11K10J10K9J9K8J8K7J7K6J6K5J5K4J4K3J3K2J2K1J1
H40G40H39G39H38G38H37G37H36G36H35G35H34G34H33G33H32G32H31G31H30G30H29G29H28G28H27G27H26G26H25G25H24G24H23G23H22G22H21G21H20G20H19G19H18G18H17G17H16G16H15G15H14G14H13G13H12G12H11G11H10G10H9G9H8G8H7G7H6G6H5G5H4G4H3G3H2G2H1G1
F40E40F39E39F38E38F37E37F36E36F35E35F34E34F33E33F32E32F31E31F30E30F29E29F28E28F27E27F26E26F25E25F24E24F23E23F22E22F21E21F20E20F19E19F18E18F17E17F16E16F15E15F14E14F13E13F12E12F11E11F10E10F9E9F8E8F7E7F6E6F5E5F4E4F3E3F2E2F1E1
D39D40
D37D38
D36D35D34
D32D33
D31D30D29D28D27D26D25D24D23D22D21D20D19
D17D18
D16
D14D15
D11
D13D12
D9D10
D8D7D6D5D4D3D2D1
C40C39
C37C38
C32C33C34
C36C35
C31
C28C27
C29C30
C23C22
C26
C24C25
C21
C18
C20C19
C17C16
C12C13C14C15
C11
C7
C9C8
C6C5C4C3C2C1
C10
B40A40B39A39B38A38B37A37B36A36B35A35B34A34B33A33B32A32B31A31B30A30B29A29B28A28B27A27B26A26B25A25B24A24B23A23B22A22B21A21B20A20B19A19B18A18B17A17B16A16B15A15B14A14B13A13B12A12B11A11B10A10B9A9B8A8B7A7B6A6B5A5B4A4B3A3B2A2B1A1
P2V5
GND
GND
P2V5
P2V5
P2V5
P12V
P12V
UNUSED
33R CLOSE TO CONNECTOR
FMC2_VREF_A_M2C
FMC2_GA0
FMC2_3P3VAUX
FMC#2
FMC2_ADJ
FMC2_VADJFMC2_ADJ
FMC2_VREF_B_M2C
FMC2_ADJ
FMC2_GA1FMC2_TRST_L
FMC2_RES0
I2C ADDRESS
IS POWERED BY 3V3AUXTHE I2C EEPROM OF THE FMC
10100 GA0 GA1
6/15LAST_MODIFIED=Thu Jul 05 08:09:27 2012
Project file:glib.cpm
PCB by: PV DATE: nn/nn/nnnn
6/15
SYSTEM: SPB15.x
Design by: P.VICHOUDIS
MODULE:glib
EDA-02180-V3-0 PROJECT:GLIB
21
R81
H40H39H38H37H36H35H34H33H32H31H30H29H28H27H26H25H24H23H22H21H20H19H18H17H16H15H14H13H12H11H10H9H8H7H6H5H4H3H2H1
G40G39G38G37G36G35G34G33G32G31G30G29G28G27G26G25G24G23G22G21G20G19G18G17G16G15G14G13G12G11G10G9G8G7G6G5G4G3G2G1
J1
K40K39K38K37K36K35K34K33K32K31K30K29K28K27K26K25K24K23K22K21K20K19K18K17K16K15K14K13K12K11K10K9K8K7K6K5K4K3K2K1
J40J39J38J37J36J35J34J33J32J31J30J29J28J27J26J25J24J23J22J21J20J19J18J17J16J15J14J13J12J11J10J9J8J7J6J5J4J3J2J1
J1
F40F39F38F37F36F35F34F33F32F31F30F29F28F27F26F25F24F23F22F21F20F19F18F17F16F15F14F13F12F11F10F9F8F7F6F5F4F3F2F1
E40E39E38E37E36E35E34E33E32E31E30E29E28E27E26E25E24E23E22E21E20E19E18E17E16E15E14E13E12E11E10E9E8E7E6E5E4E3E2E1
J1
D40D39D38D37D36D35D34D33D32D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1
C40C39C38C37C36C35C34C33C32C31C30C29C28C27C26C25C24C23C22C21C20C19C18C17C16C15C14C13C12C11C10C9C8C7C6C5C4C3C2C1
J1
B40B39B38B37B36B35B34B33B32B31B30B29B28B27B26B25B24B23B22B21B20B19B18B17B16B15B14B13B12B11B10B9B8B7B6B5B4B3B2B1
A40A39A38A37A36A35A34A33A32A31A30A29A28A27A26A25A24A23A22A21A20A19A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1
J1
R85
SEAF-40-06.5-S-10-2-ASEAF-40-06.5-S-10-2-A
SEAF-40-06.5-S-10-2-ASEAF-40-06.5-S-10-2-ASEAF-40-06.5-S-10-2-A
GNDGND
FMC2_CLK_DIR
GND
GND
GNDGND
100K
FMC2_LA18_P_CC
FMC2_LA26_PFMC2_LA26_NGNDFMC2_TCK
33
FMC2_TMS
P3V3
P3V3
GND
FMC2_LA10_N
P3V3
FMC2_PRSNT_M2C_L
FMC2_LA08_NFMC2_LA08_P
FMC2_LA03_NFMC2_LA03_P
GND
GND
GND
GNDGND
GNDGND
GND
GND
GNDGND
GND
FMC2_LA27_P
GND
GNDGND
GND
FMC2_LA20_P
FMC2_LA02_N
GND
GNDGNDFMC2_LA00_P_CC
FMC2_LA12_P
FMC2_LA16_N
FMC2_LA20_N
FMC2_LA33_N
FMC2_LA31_N
FMC2_LA29_N
FMC2_LA25_NFMC2_LA25_P
FMC2_VIO_B_M2C
FMC2_HB17_P_CC
FMC2_HB14_P
FMC2_HB10_P
FMC2_HB06_N_CC
FMC2_HA02_NFMC2_HA02_P
GNDFMC2_HA13_NFMC2_HA13_P
FMC2_HA09_P
FMC2_LA17_P_CC
FMC2_CLK1_M2C_N
FMC2_LA00_N_CCGND
FMC2_HB11_P
FMC2_HB07_P
FMC2_LA07_N
FMC2_LA04_N
GND
FMC2_CLK1_M2C_P
GNDFMC2_HB14_N
FMC2_HA06_PFMC2_HA06_N
FMC2_HA10_PFMC2_HA10_N
FMC2_HA17_P_CCFMC2_HA17_N_CC
GND
FMC2_LA05_N
FMC2_TDI
GND
GND
GND
FMC2_DP0_C2M_N
FMC2_LA11_NFMC2_HA18_PFMC2_HA18_N
FMC2_HB02_N
FMC2_HB04_PFMC2_HB04_N
FMC2_HB05_P
FMC2_LA17_N_CC
FMC2_TDOP3V3
FMC2_HA11_PFMC2_HA11_N
FMC2_HA14_NGND
FMC2_HA22_PFMC2_HA22_N
FMC2_LA15_P
FMC2_DP0_M2C_N
GND
FMC2_LA10_P
GND
GND
GNDFMC2_LA23_NFMC2_LA23_P
GND
FMC2_LA13_PFMC2_LA13_N
GND
FMC2_LA09_PFMC2_LA09_N
FMC2_LA05_P
GND
FMC2_LA01_N_CCGND
FMC2_LA01_P_CCGNDGND
GNDGNDFMCX_PG_C2M
GND
GND
GND
FPGA_SDA
GNDFMC2_LA27_N
FPGA_SCL
FMC2_LA18_N_CC
GND
GND
FMC2_LA14_P
GNDFMC2_LA14_N
GNDGND
GNDFMC2_LA06_N
GNDGND
FMC2_DP0_M2C_PGND
FMC2_DP0_C2M_PGND
FMC2_LA06_P
GND
FMC2_HA03_PFMC2_HA03_N
FMC2_HA07_PFMC2_HA07_N
GND
FMC2_HB05_NGNDFMC2_HB09_PFMC2_HB09_NGNDFMC2_HB13_P
GND
GND
FMC2_HB07_N
FMC2_HB11_N
FMC2_VIO_B_M2C
GND
GNDGND
GNDGND
GNDGND
GND
GND
GNDGND
GNDGND
GNDGND
GNDGND
GNDGND
GNDGND
GND
GNDGNDFMC2_HB20_NGNDFMC2_HB20_PFMC2_HB21_NGNDFMC2_HB21_PFMC2_HB16_NGNDFMC2_HB16_PFMC2_HB19_NGNDFMC2_HB19_PFMC2_HB12_NFMC2_HB12_PFMC2_HB13_NGNDFMC2_HB08_NFMC2_HB08_PGND
GND
FMC2_HB02_PFMC2_HB03_NGNDFMC2_HB03_PFMC2_HA19_NGNDFMC2_HA19_PFMC2_HA20_NGNDFMC2_HA20_PFMC2_HA15_NGNDFMC2_HA15_PFMC2_HA16_NGNDFMC2_HA16_PFMC2_HA12_NFMC2_HA12_PGNDFMC2_HA08_NGNDFMC2_HA08_PFMC2_HA09_NGNDFMC2_HA04_NGNDFMC2_HA04_PFMC2_HA05_NGNDFMC2_HA05_PFMC2_HA00_N_CCGNDFMC2_HA00_P_CCGNDGNDFMC2_HA01_N_CCGNDFMC2_HA01_P_CCFMC2_PG_M2CGND
GNDGNDFMC2_HB17_N_CCGND
FMC2_HB18_NFMC2_HB18_PGNDFMC2_HB15_N
GNDFMC2_HB15_PFMC2_HB10_NGND
GNDGND
FMC2_HB06_P_CCGNDFMC2_HB00_N_CCGNDFMC2_HB00_P_CCFMC2_HB01_NGNDFMC2_HB01_PFMC2_HA23_NGNDFMC2_HA23_PGNDFMC2_HA21_NGNDFMC2_HA21_PGND
GNDFMC2_HA14_PGND
GNDGND
GNDGND
GNDGNDGND
GND
GNDGNDFMC2_LA32_NGNDFMC2_LA32_PGNDFMC2_LA33_PFMC2_LA30_NGNDFMC2_LA30_PGNDFMC2_LA31_PFMC2_LA28_NGNDFMC2_LA28_P
FMC2_LA29_PFMC2_LA24_NGNDFMC2_LA24_PGNDFMC2_LA21_NGNDFMC2_LA21_PFMC2_LA22_NGNDFMC2_LA22_PFMC2_LA19_NGNDFMC2_LA19_PGNDFMC2_LA15_NGND
GNDFMC2_LA16_PGND
FMC2_LA11_PFMC2_LA12_NGND
FMC2_LA07_PGND
FMC2_LA04_PGND
FMC2_LA02_P
FMC2_CLK0_M2C_NFMC2_CLK0_M2C_PGND
GND
P3V3
P3V3
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
1211 GENEVA 23SWITZERLAND
Project:Sheet:
Module:European Organizationfor Nuclear Research
4
EN/ICE
H40G40H39G39H38G38H37G37H36G36H35G35H34G34H33G33H32G32H31G31H30G30H29G29H28G28H27G27H26G26H25G25H24G24H23G23H22G22H21G21H20G20H19G19H18G18H17G17H16G16H15G15H14G14H13G13H12G12H11G11H10G10H9G9H8G8H7G7H6G6H5G5H4G4H3G3H2G2H1G1
K40J40K39J39K38J38K37J37K36J36K35J35K34J34K33J33K32J32K31J31K30J30K29J29K28J28K27J27K26J26K25J25K24J24K23J23K22J22K21J21K20J20K19J19K18J18K17J17K16J16K15J15K14J14K13J13K12J12K11J11K10J10K9J9K8J8K7J7K6J6K5J5K4J4K3J3K2J2K1J1
F40E40F39E39F38E38F37E37F36E36F35E35F34E34F33E33F32E32F31E31F30E30F29E29F28E28F27E27F26E26F25E25F24E24F23E23F22E22F21E21F20E20F19E19F18E18F17E17F16E16F15E15F14E14F13E13F12E12F11E11F10E10F9E9F8E8F7E7F6E6F5E5F4E4F3E3F2E2F1E1
D39D40
D37D38
D36D35D34
D32D33
D31D30D29D28D27D26D25D24D23D22D21D20D19
D17D18
D16
D14D15
D11
D13D12
D9D10
D8D7D6D5D4D3D2D1
C40C39
C37C38
C32C33C34
C36C35
C31
C28C27
C29C30
C23C22
C26
C24C25
C21
C18
C20C19
C17C16
C12C13C14C15
C11
C7
C9C8
C6C5C4C3C2C1
C10
B40A40B39A39B38A38B37A37B36A36B35A35B34A34B33A33B32A32B31A31B30A30B29A29B28A28B27A27B26A26B25A25B24A24B23A23B22A22B21A21B20A20B19A19B18A18B17A17B16A16B15A15B14A14B13A13B12A12B11A11B10A10B9A9B8A8B7A7B6A6B5A5B4A4B3A3B2A2B1A1
P2V5
P2V5
P2V5
P2V5
P12V
P12V
PGOOD ARE OPEN DRAIN
LEDS EG L29K G2J1
WHEN FMC PRESENT, PRSNT_M2C -> LOW
R121 R122 R123 are not mounted
OFF ON
NO PULL-UPS
OFF ON
ON OFF
PLACEMENT AS IN SCHEMATICZERO LENGTH STUBS
OFF ON
OFF ON
ON OFF
OFF OFF
OFF ON
I/O BANK1: ALL SWAPPABLE EXCEPT PIN22I/O BANK2: ALL SWAPPABLE
DRIVEN BY PLUGGABLE JTAG DEVICESPULL-UP/DOWN RESISTORS ARE USED FOR LINES
JTAG DRIVER PINS HAVE 33R IN SERIES
- JTAG HEADER FOR V6 & MMC
33R CLOSE TO IC
JTAG "MASTERS" ARE:
- JTAG FSM DRIVEN BY V6
JTAG SCHEME
- CPLD JTAG HEADER
JTAG "SLAVES" ARE:
- AMC JTAG- MMC JTAG
- V6, FMCS, SRAMS, GBE
MASTERPULL-UPS
R124 R125 are not mounted
FOR PLATFORM FLASH XL WITH
UG438, PAGE34, FIGURE 3-2
M[2:0]=010
INDIRECT PROGRAMMINS SUPPORT
"L18P24"
"FCS""FWE"
B2-A6CONFIGURATION
PLACEMENT:
"FOE"
CAPACITORS
H3-H6
DECOUPLING
BPI-UP CONFIGURATION MODE
G4-H4
OFF OFF
OFF ON -------V2 |V3
SLAVE
7/15LAST_MODIFIED=Thu Jul 05 08:09:27 2012
Project file:glib.cpm
PCB by: PV DATE: nn/nn/nnnn
7/15
SYSTEM: SPB15.x
Design by: P.VICHOUDIS
MODULE:glib
EDA-02180-V3-0 PROJECT:GLIB
21 R108
21 R106
21 R107
R105
21 R104
21 R113
21 R112
21 R111
21 R109
R126R125R124
R110
ST2
ST3
ST1
R95
R93
R94
TP9
C230
C237
C231
C235
C236
C234
C232
C233
R133
R153
R134R132
R131
R135
R138R137R136R139R140
R141
R144
R145R146
R147
R148
R149R151R150
R152
R154
R143R142
R156R155R157R158
R15R14
R16
5
4783
4548
49505253
4142434446
81807978
8987868582
77
5859606163
545556
64
70686766
7674737271
65
33323029
403937363534
28
959697
9091929394
2199
1817161514
19
27
2322
24
9101112
678
13
43
IC3
C227
C225C226
R121
TP11
2468
1357
SW3
R75
R76
R77
R78
R123R119R120R117R114R118
2468
1357
SW2
R10
R11
R12
R13
R213
R66
R214
R212
R67
R65
R128R127
14 1312 1110 98 76 54 32 1
J12
14 1312 1110 98 76 54 32 1
J13
G2
G8
H4
A4
G4
D4
B8
H1F1
F8B4
E7G7H5F5F4F3E3E1H7G6G5E5E4G3E2F2
G1A8C8C7B7A7D8D7C5B5A5C4D3C3B3A3C2A2D2D1C1B1A1
IC4
10K
XCF128XFTG64C
CPLD_HEADER_TCKCPLD_HEADER_TDOCPLD_HEADER_TMS
0R0 CPLD_RS1_IN
V6_CPLD_4V6_CPLD_3V6_CPLD_5FPGA_RESET_BV6_CPLD_0V6_CPLD_1V6_CPLD_2
10K10K10K
FMC1_PRSNT_M2C_L
FPGA_PROGRAM_B
SRAM2_TMS
SRAM1_TCKSRAM1_TDO
GBE_TMSCPLD_RS1_IN
GBE_TDIGBE_TCK
FPGA_TDOGBE_TDO
XTAL_CPLDPGOOD_2V5PGOOD_3V3PGOOD_1V0PGOOD_1V5
FMC2_PRSNT_M2C_L
FPGA_INIT_BFPGA_DONESRAM1_TDISRAM1_TMS
SRAM2_TDI
SRAM2_TDOSRAM2_TCK
CPLD_A21_INCPLD_A22_INCPLD_RS0_IN
CPLD_A22_OUTCPLD_A21_OUT
CPLD_A21_OUTFPGA_A21
CPLD_A22_OUT
CPLD_A21_IN
CPLD_A22_IN
CPLD_RS0_IN
0R0FPGA_A22 SRAM2_A22
FPGA_RS0
0R0
FPGA_RS1
0R0
0R00R00R0
SRAM2_A21
0R0
0R0
0R0
0R0
0R0
0R0 220NF
4.7K
10VSRAM2_A22
CPLD_HEADER_TMSCPLD_HEADER_TCKCPLD_HEADER_TDICPLD_HEADER_TDO
MOLEX_87831
33
SRAM2_DQB7SRAM2_DQB6SRAM2_DQB5SRAM2_DQB4SRAM2_DQB3
FPGA_M1
SRAM2_A21
SRAM2_A16SRAM2_A17SRAM2_A18SRAM2_A19SRAM2_A20
SRAM2_A15SRAM2_A14SRAM2_A13SRAM2_A12
SRAM2_A3
SRAM2_A5
FPGA_TCKFPGA_TMS
CPLD_HEADER_TDI
10K
RTM_3.3V_EN
RTM_12V_ENMMC_LOW_VOLTAGE_POKRTM_PS
220NF10V
JTAG_HEADER_TDO
FMC1_TDO
FMC2_TCK
MMC_FPGA_1_INIT_DONEMMC_FPGA_2_INIT_DONEMMC_RESET_FPGA_NMMC_RELOAD_FPGAS_N
33
AMC_TDOAMC_TMSAMC_TCK
MMC_PG4
JTAG_HEADER_TMS
FMC2_TDIFMC1_TMSFMC1_TDIFMC1_TCK
CPLD_LED2
220NF
SW2SW1
FMC1_PG_M2C
MMC_TDO
10K
FPGA_TDI 33SW3
JTAG_HEADER_TDI
JTAG_HEADER_TCK
10K
220NF
FMC2_PG_M2C
CPLD_LED3FMC2_TMS
CPLD_LED1
RTM_I2C_EN
33
333333
33
33
AMC_TDI
MMC_TDI
10K
MMC_TCK
10K
220NF
10K
FMC2_TDO
10K
10K
10K
10K
10K
220NF
SRAM2_DQA6SRAM2_DQA5SRAM2_DQA4
SRAM2_DQA7SRAM2_DQB0SRAM2_DQB1SRAM2_DQB2
10K
SRAM2_A2SRAM2_A1SRAM2_A0
SRAM2_WE_L
SRAM2_OE_LFPGA_PROGRAM_B
SRAM2_CE1_LFPGA_CCLK
220NF100
JTAG_HEADER_TMS
MOLEX_87831
10K
10K
220NF
10V
10V220NF
10K
10K
33
33
10K10K
33
10K
10K
1%
10K
10K
10K
10K
10K
MMC_TMS
SW4
SW3
FTG64C
SW4
SW2SW1
P3V3
4.7K
SFPX_TXDISSFPX_RS1SFPX_RS0
220NF
FPGA_M2
4.7K
FPGA_M0
220NF
FPGA_INIT_B
1/16W330
JTAG_HEADER_TCKJTAG_HEADER_TDIJTAG_HEADER_TDO
SRAM2_DQA3SRAM2_DQA2SRAM2_DQA1SRAM2_DQA0
10K
FMCX_PG_C2M
10K
MMC_PE6
10K
4.7K4.7K4.7K
4.7K4.7K
100
SRAM2_CE2
SRAM2_A4
SRAM2_A6SRAM2_A7SRAM2_A8SRAM2_A9SRAM2_A10SRAM2_A11
33
4.7K
10V
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
1211 GENEVA 23SWITZERLAND
Project:Sheet:
Module:European Organizationfor Nuclear Research
4
EN/ICE
P3V3A
GND
GND
GND
P2V5
GND
GND
P2V5A
P1V8A
GND
P3V3A
P3V3A
GND
GND
P2V5A
I/O BANK 2
I/O BANK 1
XC2C128_VQ100
(2) (3) (2) (1)
B7_MC6
B8_MC3
VCCIO2
TDI
B2_MC2
B2_MC11
B2_CDRST_MC15
TCK
TMSTDO
B8_MC2B6_MC16B6_MC14B6_MC12
B6_MC4B6_MC3B6_MC2B6_MC1
B4_MC15B4_MC16
B4_MC14
B4_MC12B4_MC13
B4_MC6B4_MC7B4_MC11
B4_MC5B4_MC4
B2_GCK2_MC16
B2_GCK1_MC14
B2_MC5B2_MC6
B2_MC4B2_MC3
B1_MC1B1_MC3B1_MC4B1_MC5B1_MC6
B1_MC11B1_MC12B1_MC13
B1_GTS1_MC15
B3_GTS3_MC2B1_GTS0_MC16
B3_MC5
B3_GTS2_MC3B3_GSR_MC4
B3_MC6B3_MC7
B3_MC14
B3_MC11B3_MC13
B3_MC16B3_MC15
B5_MC1B5_MC2B5_MC3
B5_MC7B5_MC5
B5_MC11B5_MC12B5_MC13
B5_MC15B5_MC14
B7_MC1
B8_MC6B8_MC4
B8_MC12B8_MC13
B8_MC15B8_MC16
B7_MC15B7_MC16
B7_MC14B7_MC13
B7_MC5
B7_MC11
B7_MC4B7_MC2
VCC VAUX
B8_MC14
B2_GCK0_MC13
B4_DGE_MC1
VCCIO1
B6_MC6B6_MC5
P1V8
GND
P3V3A
P2V5
GND
1412
810
413
79
1113
56
2
GND
GND
1412
810
413
79
1113
56
2
P2V5
P2V5
P2V5
GND
GND
P1V8
GNDGND
P2V5
A<22>
E*G*
VDD<1-0>VDDQ
VPP
READY_WAIT
K
WP*RP*
L*
W*
A<21>A<20>A<19>A<18>A<17>A<16>A<15>A<14>A<13>A<12>A<11>A<10>A<9>A<8>A<7>A<6>A<5>A<4>A<3>A<2>A<1>A<0>
DQ<15>DQ<14>DQ<13>DQ<12>DQ<11>DQ<10>DQ<9>DQ<8>DQ<7>DQ<6>DQ<5>DQ<4>DQ<3>DQ<2>DQ<1>DQ<0>
VSSQVSS<1-0>
GND
P2V5
P3V3A
P3V3A
P3V3A
WHEN S10=0 & S11=0 => 1A/1B -> 1Y/1Z
CLOCK DISTRIBUTION 1 OF 2
CLOSE TO DS90LV001PLACE ICS874003
125MHZ (DEFAULT) OR 250MHZ
FOR VDD, VDDO
S40 pulled-down & S41 pulled-up (see page 14)default: XTAL (2A/2B) -> CDCE_PRI_REF (4Y/4Z)
WHEN S20=0 & S21=0 => 1A/1B -> 2Y/2Z
WHEN S10=1 & S11=0 => 3A/3B -> 1Y/1Z
WHEN S30=0 & S31=1 => 2A/2B -> 3Y/3Z
10NF DECOUPLING CAPS
DIFF.IMPEDANCE 100R FOR ALL DIFF PAIRS
SS[1:0]=11 : NO SPREAD S[1:0]=10 : 125MHZ
PIN7-PIN16
PIN13-PIN12
FCLKA JUMPER FOR
ON:HCSL, OFF:MLVDSTERMINATION SELECTION
1-2: XTAL AS LOCALCLK IN3-4: LEMO AS FPGACLK OUT2-3: LEMO AS LOCALCLK INLOCAL CLK JUMPER SETTINGS
USE SMA INSTEAD?
DRIVE ONLY
CLOSE TO ICS874003
WHEN S10=0 & S11=1 => 2A/2B -> 1Y/1Z
HIGH PRIORITY ROUTING
HCSL LEVELS
(WHEN DR_EN->1)
MINIMIZE THE STUB
USE SN65MLVD201: SOIC8, Type1, 200Mbps or SN65MLVD206: SOIC8, Type2, 200Mbps
PLACE THE TWO SN65LVDS1 & THE 33R VERY CLOSE
8/15LAST_MODIFIED=Thu Jul 05 08:09:28 2012
Project file:glib.cpm
PCB by: PV DATE: nn/nn/nnnn
8/15
SYSTEM: SPB15.x
Design by: P.VICHOUDIS
MODULE:glib
EDA-02180-V3-0 PROJECT:GLIB
21 R185
2
134
76
IC29
35
32
26
23
36
33
27
24
2
6
15
19
1
5
14
18
34
31
25
22
4
8
13
17
3
7
12
16
IC23
21 R188
21 R18921 R5
C319
C329
C326
C63
C323
C318
C320
C322
C321
C1C281
C315
C314
C313
C316
54
16 12
83
21
69
7 13
1011
1415
IC32
R197R196
R192R193
R48
11
14
16
19
12
15
17
20
76
8
3
2
54
IC30
R49
35
32
26
23
36
33
27
24
2
6
15
19
1
5
14
18
34
31
25
22
4
8
13
17
3
7
12
16
IC28
R186
R187
4321 J14
6
7
3
28
IC33
21
J8
1
SMA1
C328
R190R191
C327
R200810
1718
20143
15
11
5
14
1696
1312
IC31
R195
C325 C324
C62C61
3
45 IC11
4
31
QZ2
31
QZ4
ICS874003AG-02LFTSSOP
FXO-HC736R-40.000
XTAL
LEMO_CLKFPGA_CLKOUT
GND=GNDVCC=P3V3
P3V3
ICS874003_MR
ICS874003_OE
SN65LVDT125ADBTSN65LVDT125ADBT
VCC=P3V3TSSOP
10UF_X5R
P3V3
10NF16V_GEN
SMD
49.9
VCC=P3V3SOIC
TCLKB_DR_EN
I276
220NF
AMC_TCLKB_P
SN65LVDS1DBV
220NF
ICS8543BGLF
4.7K
33
XTAL_P
XTAL_N
XTAL_CPLD
P3V3
220NF
P3V3
PCIe_CLK_P
P3V3
AMC_TCLKA_P
100
XPOINT1_S30
LVDS_FCLKA_NLVDS_FCLKA_P
XPOINT1_S31
XPOINT1_S20
XPOINT1_CLK1_P
XPOINT1_CLK3_NXPOINT1_CLK3_P
P3V3
P3V3
FMC2_CLK0_M2C_XPOINT2_PFMC2_CLK0_M2C_XPOINT2_N
XTAL_N
XPOINT1_S10
100
CLK125_1_PCLK125_1_NCLK125_2_PCLK125_2_N100
XPOINT1_CLK1_N
XPOINT1_S40
P3V3
220NF
VDD=P3V3
P3V3
ICS557G-03LF
TSSOP
P3V3
DS90LV001TM
XPOINT2_S10
1%
FMC2_CLK0_M2C_P
P3V3
TCLKB
AMC_TCLKB_N
CDCE_PRI_REF_P
VCC=P3V3
FMC1_CLK0_M2C_XPOINT2_P
XPOINT2_S11
FMC1_CLK0_M2C_N
LVDS_FCLKA_P
FMC1_CLK0_M2C_XPOINT2_N
P3V3
100
220NF
P3V3
LVDS_FCLKA_N
220NF
XPOINT2_CLK1_P
PCIe_CLK_N
VCC=P3V3
51
100
220NF
XPOINT1_S41
CDCE_PRI_REF_N
TSSOP
220NF
220NF
P3V3
P3V3
P3V3
P3V3
P3V3
2PF50V
TSSOP
P3V3
SMA_142_0701
P3V3
AMC_FCLKA_NAMC_FCLKA_P
25MHZ
511%
49.91%1%
4751/16W
1%
220NF
220NF
220NF
220NF
50V
220NF
P3V3
P3V3
FMC1_CLK0_M2C_PXPOINT1_S11
15PF
220NF
10
10NF
49.9
TSX-3225
XPOINT2_CLK1_N
49.949.9
2PF
1%
P3V3
FMC2_CLK0_M2C_N
P3V3
P3V3
XTAL_P
AMC_TCLKA_NAMC_TCLKC_NAMC_TCLKC_P
XPOINT1_S21
ICS874003_FSEL
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
1211 GENEVA 23SWITZERLAND
Project:Sheet:
Module:European Organizationfor Nuclear Research
4
EN/ICE
GND
ICS874003_02
QA0QA0*QA1
QA1*
QB0QB0*
F_SEL2
CLKCLK*
OEBMR VDDO[2]
VDDVDDA
GND
F_SEL1
OEAF_SEL0
P3V3
GND GND
GNDGND
GND
GND
GNDGND
VDD GND
OUTE/D
SN65MLVD204
ADDE
B
R
RE*GND
GND
1B
S111A
S10
2B
S212A
3B3AS31S30
S41S40
1Z*1Y
1DE
2Y2Z*
2DE
4Y4Z*
3Z*
4DE
S20
3Y
3DE
4B4A
CLK0CLK0*
CLK1*CLK1
S0S1
SS0SS1
X1/ICLKX2
VDDXDGNDXD GNDODA
VDDODA
OEIREF
GND
GND
GND
GND
QQ*
Q*
Q*Q
Q
QQ*
OE
PCLKPCLK*CLK_SEL
CLK_ENCLKCLK*
1B
S111A
S10
2B
S212A
3B3AS31S30
S41S40
1Z*1Y
1DE
2Y2Z*
2DE
4Y4Z*
3Z*
4DE
S20
3Y
3DE
4B4A
GND
GND
GND
GND
GND
GND
GND
1234
DR
DS90LV001
12
GND
GND
GND
EN/D OUT
GND GND
GND
R184 is not mounted
DRIVEN FROM VIRTEX6
DRIVEN FROM XPOINT1
220NF DECOUPLING CAPS FOR VCC_OUT & VCC_AUXOUT
CLOCK DISTRIBUTION 2 OF 2
220NF DECOUPLING CAPS FOR VCC_VCO
220NF DECOUPLING CAPS FOR VCC1_PLL & VCC2_PLL
220NF DECOUPLING CAPS FOR VCC_IN_PRI, VCC_IN_SEC & VCC_AUXIN
HIGH PRIORITY ROUTING
SPI_LE pulled-up (see page 14)
9/15LAST_MODIFIED=Thu Jul 05 08:09:29 2012
Project file:glib.cpm
PCB by: PV DATE: nn/nn/nnnn
9/15
SYSTEM: SPB15.x
Design by: P.VICHOUDIS
MODULE:glib
EDA-02180-V3-0 PROJECT:GLIB
21
C312C3174
3
2
1
QZ3
TP6
R183
C301
C300
C293
C306
C307
C296
C305
C304
C291
C289
C290
C297
C298
C299
C288
C292
21
L13
C309
21
L11
C294
C302
C311R184
C310
C303
C308C295
R180
R182
R181
21
L12
147
15
44
5
48
76
109
1716
2019
2827
3033
14
2322
2524
23
384
3112
4645
37
36
49
4140
13
43
IC27
FXO-HC736R-40.000
CDCE_SYNC
CDCE_REF_SEL
CDCE_PRI_REF_NCDCE_PRI_REF_P
CDCE_OUT3_N
SMD
10NF16V_GEN
I109
15PFP3V3
CDCE_PLL_LOCK
EXT_LFN
CDCE_OUT2_P
CDCE_OUT1_N
VCC_VCO
CDCE_SPI_LECDCE_SPI_CLKCDCE_SPI_MISOCDCE_SPI_MOSI
CDCE_SEC_REF_PCDCE_SEC_REF_N
CDCE_OUT3_P
CDCE_OUT2_N
CDCE_OUT0_N
CDCE_OUT1_P
CDCE_OUT0_P
CDCE_OUT4_PCDCE_OUT4_N
EXT_LFNEXT_LFP
VCC_IN
VCCVCO<1..0>
VCC2_PLL<1..0>
CDCE_PWR_DOWN
QFN
CDCE62005RGZ
VCC_PLL
EXT_LFP
P3V3
270
1.0UF
10UF_X5R
10UF_X5R
330
P3V3
1
XX220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
10UF_X5R
10UF_X5R
10UF_X5R
10UF_X5R10UF_X5R
100
1K
BLM15HD102SN1
BLM15HD102SN1
BLM15HD102SN1
P3V3
P3V3
P3V3
VCC_IN
VCC_VCO
VCC_PLL
010
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
1211 GENEVA 23SWITZERLAND
Project:Sheet:
Module:European Organizationfor Nuclear Research
4
EN/ICE
GND
GND
GND
GND
GND
GND GND
GND
GNDGND
VDD GND
OUTE/D
VCC_OUT[7]
PRI_REF-SEC_REF+
U3PU3N
U2N
U1N
U0N
U1P
U0P
U4PU4N
U2PAUX_IN
SEC_REF-
EXT_LFNEXT_LFP
PRI_REF+
VCC_AUXIN
VCC_IN_SECVCC_IN_PRIVCC_VCO[2]
VCC2_PLL[2]VCC1_PLL
VCC_AUXOUT
GND_VCCO
PLL_LOCK
AUX_OUT
TEST_MODE
REG_CAP2TESTOUTA
REG_CAP1
REF_SELPWR_DOWN*SYNC*
SPI_LE
SPI_MISOSPI_CLK
SPI_MOSI
PAD/GND
VBB
SFP CAGE
ALL DIFF. PAIRS OF BANKS 112,113,114,115,116
TO THE THE RESISTOR PINS MUST BE EQUAL IN LENGTH & GEOMETRYTRACE LENGTH FROM THE FPGA PINS MGTRREF AND MGTVTTRCAL
HIGHEST PRIORITY ROOTING - HIGH SPEED LINES ~5GBPS
MUST HAVE DIFF. IMPEDANCE 100 OHM.
SEE NOTE1 BELOW
NO SWAP
BANK[112..116]: DIFF.IMPEDANCE 100R
NOTE2
NOTE1
NO SWAPPING POSSIBLE
SERIAL INTERFACES
HIGH SPEED: ALL AMC_*, FMC*, SFP*, GBE*HIGH PRIORITY ROUTING
100NF CLOSE TO FPGA
10/15LAST_MODIFIED=Thu Jul 05 08:09:23 2012
Project file:glib.cpm
PCB by: PV DATE: nn/nn/nnnn
10/15
SYSTEM: SPB15.x
Design by: P.VICHOUDIS
MODULE:glib
EDA-02180-V3-0 PROJECT:GLIB
C26C27
20171
141110
9
16 15
23
1918
1213
7
456
8
J18
20171
141110
9
16 15
23
1918
1213
7
456
8
J17
20171
141110
9
16 15
23
1918
1213
7
456
8
J16
C23
C24
R72R71
R63R62
R58R57
R53R52
R221R222
R220
C66
C72
C84
C78
C80
C68
C74
C86
20171
141110
9
16 15
23
1918
1213
7
456
8
J15SFP1
C255C254
L1
L3
L5
L7
L6 L8
L4L2
C75
C76
C87
C88
C81
C82
C83
C85
C77
C79
C65
C67
C71
C73
C70
C69
R97
C241C240
C238C239
C265C264
C244C245
C250C251
C253C252
C104C103
C14C13
C242
C243
C247
C246
C248
C249
C263
C262
C261
C260
C259
C258
C257
C256
C16
C15
C18
C17
C19
C20
C22
C21
9697
9091
6665
6059
5150
4544
3635
162163
3029
156157
150151
144145
132133
126127
120121
114115
108109
102103
2120
1211
166168169
13813913513678777574
165
7156
9394
8788
6968
6362
5453
4847
3938
159160
3332
153154
147148
141142
129130
123124
117118
111112
105106
99100
2423
1514
86
4
26175
8180
167
38341
J3
A3
F1
P1
AB1
AK1
B1
H1
T1
AD1
AM1
C3
K1
V1
AF1
AN3
D1
M1
Y1
AH1
AP1
A4
F2
P2
AB2
AK2
B2
H2
T2
AD2
AM2
C4
K2
V2
AF2
AN4
D2
M2
Y2
AH2
AP2
B5
J3
R3
AC3
AJ3
D5
K5
U3
AE3
AL3
E3
L3
W3
AF5
AM5
G3
N3
AA3
AG3
AP5
B6
J4
R4
AC4
AJ4
D6
K6
U4
AE4
AL4
E4
L4
W4
AF6
AM6
G4
N4
AA4
AG4
AP6
AN7
F6
M6
T6
AB6
AH6
F5
M5
T5
AB5
AH5
H6
P6
V6
AD6
AK6
H5
P5
V5
AD5
AK5AP7
IC2
2007135-1
XC6VLX130T-1FFG1156C
AMC_P0_TX_NAMC_P0_RX_NAMC_P0_TX_PAMC_P0_RX_PAMC_P1_TX_N
AMC_P1_RX_P
4.7UH
6.3V
SFP1_VCCT
SFP3_VCCR
4.7K
SFP3_RXN
SFP2_RXP
SFP2_RXNSFP2_TXN
CDCE_OUT0_PSFP3_RXP
CLK125_1_P
SFP3_RXN
SFP4_TXP
1888247-1
SFPX_RS0
2007132
SFP3_RXLOS
SFP3_VCCT
SFP1_VCCT
SFPX_RS1
SFP1_TXFAULTSFPX_TXDIS
EDGE
AMC_GA1FMC1_DP0_M2C_P
FMC1_DP0_C2M_N
100NF
AMC_P8_TX_NAMC_P8_RX_N
SFP1_RXP
SFP1_RXN
CLK125_1_N
CDCE_OUT0_N
SFP1_RXP
SFP4_TXN
16 23 170 1301 000
AMC_P8_RX_N
CDCE_OUT2_P
FMC2_DP0_C2M_P
AMC_P18_RX_P
AMC_P7_TX_N
FMC1_DP1_M2C_N
FMC1_DP1_M2C_PFMC1_DP1_C2M_N
AMC_P7_RX_N
AMC_P14_RX_PAMC_P14_RX_N
AMC_P4_TX_P
AMC_P3_RX_P
AMC_P1_RX_PAMC_P1_RX_N
AMC_P0_RX_N
AMC_FCLKA_PAMC_FCLKA_N
AMC_P5_RX_P
AMC_P6_TX_N
AMC_P6_TX_PAMC_P6_RX_P
AMC_P5_RX_P
AMC_P5_RX_N
100NF
100NF
100NF
AMC_TDI
100NF
FMC2_DP0_C2M_N
FMC2_DP0_M2C_P100NF100NF100NF
100NF
CDCE_OUT2_N
100NF
100NF
100NF
100NF 6.3V
GBE_SOUT_N
AMC_P1_TX_P
GBE_SOUT_P
BGA
GBE_SIN_N
100NF
100NF
PCIe_CLK_N
100NF
100NF
100NF
100NF
100NF
100NF
GBE_SIN_P
100NF
100NF
100NF
AMC_P5_TX_PAMC_P5_RX_N
AMC_P11_RX_NAMC_P11_RX_PAMC_P12_RX_NAMC_P12_RX_PAMC_P13_RX_NAMC_P13_RX_P
100NF
0.1%_GEN
AMC_P4_RX_PAMC_P5_TX_N
100NF
AMC_P2_RX_PAMC_P2_RX_N
AMC_P0_RX_P
AMC_GA2
SFP4_RXN
100NF
SFP4_RXP
P3V3
100NF
100NF
AMC_P4_RX_NAMC_P4_TX_N
AMC_P3_RX_N
FMC1_DP0_C2M_PFMC1_DP0_M2C_N
AMC_P17_RX_P
AMC_P14_TX_N
AMC_P15_TX_NAMC_P15_TX_P
AMC_P20_TX_P
AMC_P11_TX_N
AMC_MPAMC_PS1_NAMC_PS0_N
AMC_P15_RX_N
AMC_P18_RX_N
AMC_P19_RX_NAMC_P19_RX_P
AMC_P20_RX_PAMC_P20_RX_N
AMC_P0_TX_N
AMC_P1_TX_NAMC_P0_TX_P
AMC_P1_TX_PAMC_P2_TX_NAMC_P2_TX_PAMC_P3_TX_N
AMC_P4_TX_NAMC_P3_TX_P
AMC_P4_TX_PAMC_P5_TX_NAMC_P5_TX_P
AMC_P6_TX_PAMC_P6_TX_N
AMC_P7_TX_NAMC_P7_TX_PAMC_P8_TX_NAMC_P8_TX_PAMC_P9_TX_NAMC_P9_TX_PAMC_P10_TX_NAMC_P10_TX_P
AMC_P11_TX_P
AMC_P12_TX_PAMC_P12_TX_N
AMC_P13_TX_NAMC_P13_TX_P
AMC_GA0
100NF
100NF
100NF
100NF
SFP2_TXP
100NF100NF
6.3V
22UF
6.3V
22UF
6.3V
22UF
6.3V
22UF
22UF
100NF100NF
100NF
100NF
100NF
100NF
100NF 100NF
100NF
100
33
33
4.7UH
4.7UH
AMC_TDOAMC_TMS
P3V3
P3V3
SFP4_VCCT
SFP2_VCCT
SFP1_TXP
SFP1_TXN
100NF
100NF
4.7UH
100NF
SFP3_TXNSFP4_RXP
P3V3
4.7UH
4.7UH
22UF
6.3V
22UF
4.7UHSFP1_VCCR
4.7K4.7K
P3V3
1888247-1
SFP2_TXN
SFP2_RXLOS
SFP2_RXN
SFPX_RS0
SFP2_RXP
4.7K4.7K
SFP3_TXFAULT
SFPX_RS1
SFPX_TXDIS
4.7K
1888247-1
SFP4_RXN
SFP4_VCCR
4.7K4.7K
P3V3
SFP4_VCCT
SFP4_TXFAULT
SFP4_TXN
CLK125_2_P AMC_P17_RX_NAMC_P15_RX_PCLK125_2_N
1888247-1
SFP2_TXP
SFP2_TXFAULT
SFP3_TXN
SFPX_RS1
100NF
SFP3_VCCT
100NF
AMC_TCK
P3V3
100NF
SFPX_RS0
SFPX_RS1
SFPX_TXDIS
SFP1_TXP
SFP1_RXLOS
SFP1_TXN
AMC_P10_RX_PAMC_P10_RX_NAMC_P9_RX_PAMC_P9_RX_NAMC_P8_RX_P
100NF
SFP3_TXP
SFP4_TXP
SFPX_TXDIS
SFP4_RXLOS
P3V34.7UH
100NF
AMC_P1_RX_N
SFP4_MOD_ABS PCIe_CLK_P
GBERX_P
AMC_TCLKA_NAMC_TCLKB_P
33
FMC2_DP0_M2C_N
GBETX_N
AMC_TCLKB_N
AMC_TCLKC_NAMC_TCLKC_P
AMC_TCLKA_P
P3V3
SFP2_MOD_ABS
SFPX_RS0
SFP1_MOD_ABS
SFP1_RXN
GBERX_NGBETX_P
AMC_SDAAMC_SCL
AMC_ENABLE_N
AMC_P4_RX_NAMC_P4_RX_P
FMC1_GBTCLK1_M2C_P
FMC1_DP1_C2M_P
FMC1_DP2_C2M_N
AMC_P6_RX_N
FMC1_GBTCLK1_M2C_N100NF
AMC_P20_TX_N
AMC_P14_TX_P
AMC_P19_TX_PAMC_P19_TX_NAMC_P18_TX_PAMC_P18_TX_NAMC_P17_TX_PAMC_P17_TX_N
AMC_P6_RX_NAMC_P6_RX_PAMC_P7_RX_NAMC_P7_RX_P
FMC1_GBTCLK0_M2C_N
CDCE_OUT3_PCDCE_OUT3_N
FMC1_DP2_M2C_P
FMC1_GBTCLK0_M2C_P
FMC1_DP2_M2C_NFMC1_DP2_C2M_PFMC1_DP3_M2C_NFMC1_DP3_C2M_NFMC1_DP3_M2C_PFMC1_DP3_C2M_P
AMC_P7_TX_PAMC_P7_RX_P
SFP3_TXP100NF
P3V3 AMC_P11_RX_P
AMC_P9_RX_NAMC_P9_TX_NAMC_P8_RX_P
AMC_P9_TX_P
AMC_P10_RX_PAMC_P11_TX_NAMC_P11_RX_NAMC_P11_TX_P
100NF
100NF
SFP2_VCCT
AMC_P8_TX_P
100NFAMC_P10_TX_PAMC_P10_RX_NAMC_P10_TX_N
CDCE_OUT1_NCDCE_OUT1_P
P3V3
SFP3_MOD_ABS
SFP3_RXP AMC_P9_RX_P
100NFFMC2_CLK0_M2C_XPOINT2_PFMC2_CLK0_M2C_XPOINT2_N
100NF 22UF
6.3V
100NF
P3V3
SFP2_VCCR
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
1211 GENEVA 23SWITZERLAND
Project:Sheet:
Module:European Organizationfor Nuclear Research
4
EN/ICE
POWER
JTAG
TCLKD+TCLKD-
GND[56]
RX8-RX8+RX9-RX9+RX10-
RX17+
TX14-
TX15-TX15+
TX18-TX18+TX19-TX19+
TX20+
TX11-
TCLKC-
MPPS1*PS0*
RSRVD8RSRVD6
RX0-RX0+RX1-RX1+RX2-RX2+RX3-RX3+RX4-
RX5-RX4+
RX5+RX6-RX6+RX7-RX7+
RX10+RX11-RX11+RX12-RX12+RX13-
RX14-RX13+
RX14+
RX15+RX15-
RX17-
RX18-RX18+RX19-RX19+
RX20+RX20-
TX0-
TX1-TX0+
TX1+TX2-TX2+TX3-
TX4-TX3+
TX4+TX5-TX5+
TX6+TX6-
TX7-TX7+TX8-TX8+TX9-TX9+
TX10-TX10+
TX11+
TX12+TX12-
TX13-TX13+
TX14+
TX17+TX17-
TX20-
GA0
ENABLE*
FCLKA+FCLKA-
GA1GA2
TDO
SCL_LSDA_L
TCLKA+TCLKA-TCLKB+TCLKB-TCLKC+
TCK
TRST*
TDITMS
PWR[8]
GND
GND
GND
GND
GND
GND
GND
GND
VTT
P2V5P1V0
VTT
VCCA
VCCA
VTT
GND
TX_DISABLE
RD+
RS1 RS0
SDASCL
MOD_ABS
VCCR
VEET
RD-
VEERVEER
VEERVEETVEETVCCT
TX_FAULTLOS
TD-TD+
TX_DISABLE
RD+
RS1 RS0
SDASCL
MOD_ABS
VCCR
VEET
RD-
VEERVEER
VEERVEETVEETVCCT
TX_FAULTLOS
TD-TD+
TX_DISABLE
RD+
RS1 RS0
SDASCL
MOD_ABS
VCCR
VEET
RD-
VEERVEER
VEERVEETVEETVCCT
TX_FAULTLOS
TD-TD+
TX_DISABLE
RD+
RS1 RS0
SDASCL
MOD_ABS
VCCR
VEET
RD-
VEERVEER
VEERVEETVEETVCCT
TX_FAULTLOS
TD-TD+
SFP1
SFP4
SFP3
SFP2
GND
GND
GND
GND
GND
GND
GND
GND
P12V
Sym 5/5BANK 115BANK 112
BANK 113
BANK 116
BANK 114NA
MGTAVTT_S[9..0]
MGTAVCC_S[9..0]
MGTAVCC_N[5..0]
MGTAVTT_N[5..0]
MGTTXP0_114MGTRXP0_114
MGTRXN0_114
MGTRXP1_114MGTTXN0_114
MGTTXP1_114
MGTTXN1_114MGTRXN1_114
MGTREFCLK0N_114MGTREFCLK0P_114MGTRXP2_114MGTREFCLK1N_114MGTREFCLK1P_114
MGTTXN2_114
MGTTXP2_114MGTRXN2_114
MGTTXP3_114MGTRXP3_114
MGTTXN3_114MGTRXN3_114
VCCINT[54..0]
GND[252..0]
VCCAUX[12..0]
MGTRXP0_116
MGTTXN0_116
MGTTXP0_116MGTRXN0_116
MGTTXP1_116MGTRXP1_116
MGTRXN1_116MGTTXN1_116
MGTREFCLK0N_116MGTREFCLK0P_116
MGTRXP2_116MGTREFCLK1N_116
MGTTXP2_116MGTREFCLK1P_116
MGTRXN2_116
MGTRXP3_116MGTTXN2_116
MGTTXP3_116
MGTTXN3_116MGTRXN3_116
MGTRXN0_113
MGTRXP0_113MGTTXP0_113
MGTRXP1_113MGTTXN0_113
MGTTXP1_113MGTRXN1_113MGTTXN1_113
MGTREFCLK0P_113MGTRXP2_113
MGTREFCLK0N_113
MGTREFCLK1P_113MGTREFCLK1N_113
MGTTXN2_113MGTRXN2_113MGTTXP2_113
MGTRXP3_113MGTTXP3_113
MGTTXN3_113MGTRXN3_113
MGTRXP0_112MGTTXP0_112MGTRXN0_112
MGTRXP1_112MGTTXN0_112
MGTTXP1_112
MGTTXN1_112MGTRXN1_112
MGTREFCLK0N_112MGTREFCLK0P_112MGTRXP2_112
MGTREFCLK1P_112MGTREFCLK1N_112
MGTTXP2_112MGTRXN2_112MGTTXN2_112MGTRXP3_112MGTTXP3_112
MGTTXN3_112MGTRXN3_112
MGTRXP0_115MGTTXP0_115
MGTRXP1_115MGTTXN0_115MGTRXN0_115
MGTTXP1_115MGTRXN1_115MGTTXN1_115
MGTREFCLK0N_115MGTREFCLK0P_115
MGTRREF_115MGTAVTTRCAL_115
MGTRXP2_115
MGTREFCLK1P_115MGTREFCLK1N_115
MGTRXN2_115MGTTXP2_115
MGTTXN2_115MGTRXP3_115MGTTXP3_115MGTRXN3_115MGTTXN3_115
TD=2.1US ??? FASTER RESET SUPERVISOR?
PLEASE PLACE THEM IN ORDERSN7 LEFT, SN0 RIGHT
1010 A2 A1 A0MODULE MANAGEMENT
FPGA TEMPERATURE
0101010I2C ADDRESS
MEASUREMENT
MMC_REG_ENABLE
I2C ADDRESS
I2C ADDRESS
MICROSWITCH
FRONT PANEL'S LED1
FRONT PANEL'S
1001110
FRONT PANEL'S LED2
FRONT PANEL'S BLUE LED
1010110: GLIB EEPROMI2CBUS2: I2C MASTER: FPGA
XXXXX11: FMC#2XXXXX00: FMC#11001110: GLIB BOARD TEMPERATURE #20011010: GLIB BOARD TEMPERATURE #10101010: GLIB FPGA TEMPERATURE
I2CBUS1: I2C MASTER: MMC
I2C ADDRESSING
VISIBLE AT FRONT PANELBOTTOM SIDE UNDER FMC1
TRI-LEVEL I2C ADDRESSING
I2C ADDRESS0011010
33R CLOSE TO CONNECTOR
EN internally pulled up
PROJECT:GLIBProject file:glib.cpm
LAST_MODIFIED=Thu Jul 05 08:09:24 2012
SYSTEM: SPB15.x
EDA-02180-V3-0
DATE: nn/nn/nnnn
11/15
PCB by: PV
11/15MODULE:glib
Design by: P.VICHOUDIS
72 5
631
IC14
C46
2 1LD3
2 1LD4
2 1LD5
2 1LD6
2 1LD7
2 1LD8
1213
IC8 1011
IC8 89
IC8 65
IC8 43
IC8 21
IC82
1
R198
3
2
1R38
3
2
1R37
3
2
1R36
3
2
1R35
3
2
1R34
3
2
1R33
3
2
1R32
3
2
1R31
C266
C267
81
6372
5
IC18
40393837363534333231302928272625242322212019181716151413121110987654321
J7DCBA
SW1
DCBA
SW4
21 R8221 R83
2
R194
C101
C64C45C268
C280
48
56
321
IC22
21
J6
TP4TP5
TP1TP2TP3
LD2
LD9R74
R22
R23LD1
C102
R199
R80
2
16
1214
11
34
610
IC7
2
16
1214
11
34
610
IC12
2
16
1214
11
34
610
IC19
VDD=P2V5
POWER_ON_RESET_B
SOIC
TLC7725ID
SN0
FPGA_SDA
24AA025E48
MMC_SDAMMC_SCL
100PF
MSOP
CRITICAL_TEMP_B
MMC_SDAMMC_SCL
P3V3
LNJ926W8CRA
LGL29K-G2J1-24
220NF
MMC_BLUE_LED_NMMC_GREEN_LED_NMMC_RELOAD_FPGAS_NMMC_RESET_FPGA_N
CPLD_LED2
CPLD_LED3
V6_LED3
SML-311DT
220NF
FPGA_SDA
MMC_PE5_INT5MMC_PE4_INT4MMC_PE6
SML-311DT
AMC_SDA
MMC_RED_LED_N
RTM_3.3V_ENRTM_12V_EN
AMC_PS0_NAMC_PS1_N
SML-311UT
MMC_TDO
SML-311DT
SML-311DT
SML-311DT
330
0402
SN2
AMC_GA24.7K
MMC_SDA
MMC_PG4
MMC_GREEN_LED_N
MMC_RED_LED_N
330
330
MMC_MICROSWITCH_CLOSED_N
20849-209
4.7K
FPGA_SCL
4.7K4.7K
SOIC
0402
SN3
SN7
SN6
SN5
SN4
SN1
I368
I369
I372
000402
I371
000402
I370
000402
000402
000402
I367
000402
I366
00
00
RTM_I2C_EN
33
MMC_SCL
MMC_DCDC_ENABLE
220NF220NF220NF
CRITICAL_TEMP_B FPGA_DXN
QSOPQSOPQSOP
MMC_SCL
20849-209
MMC_SCLMMC_SDA
AMC_SCLMMC_LOW_VOLTAGE_POKAMC_GA1AMC_GA0
RTM_PS
MMC_SDA
FPGA_SCL
220NF
MMC_FPGA_1_INIT_DONE
MMC_BLUE_LED_N
V6_LED1
V6_LED2
SML-311DT
CPLD_LED1
220NF
P3V3
I381
I380
I379
I378
I377
I376
VCC=P3V3
VCC=P3V3VCC=P3V3VCC=P3V3VCC=P3V3VCC=P3V3
MMC_PF1_ADC1
MMC_FPGA_2_INIT_DONE 100K220NF
MMC_TMSMMC_TCK
MMC_PG4MMC_TDI
MMC_PF3_ADC3MMC_PF2_ADC2
AMC_ENABLE_N
MMC_DCDC_ENABLE
SS4-20-3.00-L-D-K-TR
PCA9517DGKR
FPGA_DXP CRITICAL_TEMP_B
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
1211 GENEVA 23SWITZERLAND
Project:Sheet:
Module:European Organizationfor Nuclear Research
4
EN/ICE
GND
P3V3A
LM82
ADD[0]ADD[1]
GND VCC
T_CRIT_A*
INT*
SMBDSMBCLK
D+D-
LM82
ADD[0]ADD[1]
GND VCC
T_CRIT_A*
INT*
SMBDSMBCLK
D+D-
GND
GND
RESETRESET
CONTROL
SENSERESINCT
GND
GND
LCX04
LCX04
LCX04
LCX04
LCX04
LCX04
P3V3A
GND
+ -
+ -
+ -
+ -
+ -
+ -
+ -
P2V5
+ -
P3V3A
GND
GND
P2V5
P3V3A
P2V5
ENVCCBVCCA
SDDA SDABSCLBSCLA
531
7911 1213 1415 1617 1819 20
2
21 2223 2425 2627 2829 3031 3233 3435 3637 3839 40
468
10
P3V3A
P3V3A
GND
GND
P12V
P3V3AGND
GND
GNDGND
GND
P2V5
A2A1A0
VCC VSS
SDASCL
P3V3A
P3V3A
P3V3AP3V3AP3V3A
P3V3A
P3V3A
P3V3A G
ND
12
P2V5
P2V5
P2V5
P2V5
GND
GND
GND
GND
GND
LM82
ADD[0]ADD[1]
GND VCC
T_CRIT_A*
INT*
SMBDSMBCLK
D+D-
000: GND
CFG0: PHYADR[2] PHYADR[1] PHYADR[0] :111CGF1: ENA PAUSE PHYADR[4] PHYADR[3] :000CFG2: AUTONEG[3] AUTONEG[2] AUTONEG[1] :111CFG3: AUTONEG[0] ENABLE XC DIS125MHZ :111 CFG4: HWCFGMD[2] HWCFGMD[1] HWCFGMD[0] :100CGF5: DISABLE FC DIS SLEEP HWCFGMD[3] :110CFG6: SEL_TWSI INT_POL 75/50 OHM :X10
010: LED_RX011: LED_DUPLEX100: LED_LINK1000101: LED_LINK100110: LED_LINK10111: VCC2V5
001: LED_TX
GBE PHY
12/15LAST_MODIFIED=Thu Jul 05 08:09:25 2012
Project file:glib.cpm
PCB by: PV DATE: nn/nn/nnnn
12/15
SYSTEM: SPB15.x
Design by: P.VICHOUDIS
MODULE:glib
EDA-02180-V3-0 PROJECT:GLIB3
2
1R6
C333
C331
C335
C339
C337
R9
TP7TP8
R7
R8
R4R201R3
J9
H9
H7
J2J1H3H1H2G3G2F1
F2
E1D1
M9L8
K8
L7
L9
H8
A8
A7
A4A3
A6A5
C5A2A1C4B3C3D3B2
D2
B1
C1
K3M2
M1
N9N8N7N6N4N3N2N1
L3
D9C9
A9B8C8
E8
L1
M6M5
E2
B5G8G9F9G7F8E9D8
L4
B6
K2
IC1
L14
R219
R218
21 R215
C342
C346
C347
C343
R203
R206
R209
R204
R202
R207
R208
R205
C341
C345
C348
C344
9
87
65
4
3
2
1211
10
1
1617
15
1314
J11
C340
C332
C334
C338
C336
C330
C29 C303
QZ1
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
MPZ1608S221A
GBE_INT_NGBE_SDA
GBE_XTAL2
LED_LINK10
LED_TX4.99K
1G18
51
51
RJ45
51
220NF
220NF
220NF
1 0
51
MDI2_N
MDI1_N
MDI0_P
220NFMDI1_P51
220NFMDI0_N51
MDI3_N220NF
51
LED_LINK1000
MDI2_P220NF
51
50V9PF
25MHZ
50V9PF
GBE_XTAL2
SH<1..0>
51
LED_RX
51
LED_TX
51
GBE_XTAL1
MDI3_P
TSX-3225
220NF
MDI2_N
MDI0_NMDI1_PMDI1_NMDI2_P
MDI3_PMDI3_N
0R0
220NF
4.7K
4.7K
1368398-2
MDI0_P
4.7K
GBE_SOUT_N
LED_LINK1000
LED_RX
LED_RX
GBE_SCL
GBE_XTAL133
GBE_TCKGBE_TRST_BGBE_TMSGBE_TDI
GBE_RESET_N
GBE_TDO
TFBGA
LED_LINK10LED_LINK1000
GBE_SIN_NGBE_SIN_P
CONFIG6
CONFIG6
LED_LINK10
040200
GBE_SOUT_P
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
1211 GENEVA 23SWITZERLAND
Project:Sheet:
Module:European Organizationfor Nuclear Research
4
EN/ICE
P2V5
GND
GNDGND
EN/D OUT
+ -
P2V5P1V0
GND
GND
GND
P1V0 P2V5
P2V5
P2V5
GND
GND
GND
P2V5
88E1111_TFBGA
VSSC<1>
RX_CLKRX_ER
INTNMDIO
MDI0+
MDI2+MDI2-MDI3+MDI3-
LED_TXXTAL2
LED_RX
LED_LINK1000LED_DUPLEX
LED_LINK100LED_LINK10
S_OUT+COLCRS
RXD7
RXD5RXD6
RXD4RXD3
RXD1RXD2
RXD0
S_OUT-RX_DV
DVDD<8>
TX_ER
TX_ENGTX_CLK
TXD0TXD1TXD2
TXD4TXD3
TXD5TXD6
COMA
TXD7MDC
RESETRESETN
TDITMSTRSTN
TDOTCK
XTAL1CONFIG6CONFIG5
CONFIG3CONFIG4
CONFIG2
CONFIG0CONFIG1
S_IN-S_CLK-S_CLK+
VSS<23>
S_IN+HSDAC-HSDAC+SEL_FREQ
MDI1-MDI1+MDI0-
VDDO<3>
125CLKTX_CLK
VDDOH<3>AVDD<6>
VDDOX<2>
GND
GND
GND
GND
GND
GND
GND
GND
P2V5
P2V5
GND
RJ-5RJ-6
RJ-4RJ-3
RJ-1RJ-2
RJ-8RJ-7
LED2C2LED2COMLED2C1
P9P7P8
P1P2
P3
P5
P4P6
P10P12P11
LED1ALED1C
SH[2]
VCCIO_15VCCIO_14 VCCIO_16
FPGA VCCIO (PAGE3)
MGT_AVCC (PAGE10)
VCCIO_35
VCCIO_22
2.2UF,10V,X7R220NF,10V,X7R
TANT,2.5V
VCCAUX (PAGE10)
FPGA VCCIO (PAGE4)
VCCIO_12VCCIO_0
FPGA VCCINT (PAGE10)
VCCIO_33 VCCIO_34
VCCIO_36 VCCIO_25 VCCIO_32
VCCIO_23
VCCIO_24 VCCIO_26
MGT_AVTT (PAGE10)
FPGA DECOUPLING CAPS
DO THE MGT_AVTT & MGT_AVCC DECOUPLING AS IN UG366 PAGE286
FPGA DECOUPLING CAPS PLACEMENT RULES:330UF,47UF,33UF,22UF,10UF: ANYWHERE ON BOARD BUT AS CLOSE AS POSSIBLE TO FPGA22ONF: NO MORE THAN 1" FROM PERIPHERY OF FPGA BUT AS CLOSE AS POSSIBLE2.2UF: NO MORE THAN 3" FROM PERIPHERY OF FPGA BUT AS CLOSE AS POSSIBLE
VCCIO_13
LAST_MODIFIED=Thu Jul 05 08:09:29 2012
C206
C205
C192
C196
C177
C161
C162
C197
C195
C147
C107C108 C160
C135
C133
C169
C170
C156
C141
C154
C151
C136
C165
C190
C128
C117
C186
C200
C185
C184
C202
C203
C193
C204C125
C111C130
C131C149C115C176
C159
C168
C182
C194C114
C113C109C126
C150
C164
C167
C166
C155
C139
C138
C163
C152
C210
C118
C129
C121
C120
C142
C144
C145
C158
C172
C188
C187
C173
C199
C198
C212
C209
C157
C213
C119
C34
C122
C124
C143
C146
C174
C189
C201
C175
C211
C123
C31
C89
C140
C207 C208 C116 C179
C91
C90
C110 C106 C112 C183
C191
C181C105C132C148
C36
C33
C127
C32C92
C178
C25
C35
C171
C37
C28
C180
330uF
330uF
330uF
47UF
2.2uF
2.2uF
2.2uF
2.2uF2.2uF
2.2uF
220NF
220NF
220NF
220NF
220NF
220NF 220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
4V
4V
4V
220NF
220NF
220NF
220NF
FMC1_VIO_B_M2C
220NF
220NF
220NF
220NF
220NF
220NF
4V4.7UF
220NF
220NF
4V
4V
4.7UF
4.7UF
4.7UF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF 220NF 220NF 220NF
220NF220NF220NF
220NF
220NF220NF220NF
220NF
220NF220NF
220NF220NF
47UF 47UF
47UF
GIGABIT LINK INTERFACE BOARD
GLIB
1 XX X
220NF
220NF
220NF
4.7UF
4.7UF
220NF
220NF
220NF
220NF
220NF
220NF
FMC2_VIO_B_M2C47UF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
PAGE:
DATE:1211 GENEVA 23
REF:
ETUDE:
5
D
B
1
D
8
8 7
7 6
6 5
4
4 3
3 2
2
1
CC
B
AA
EE
PCB: SYSTEM:REF:EDMS
IT/CE
SWITZERLAND
DIV.
DESSIN:
VERSION:
DRAWING
P2V5P2V5P2V5P2V5P2V5
P2V5P2V5
P2V5P2V5P1V0
P2V5P2V5P2V5
+
GND
GND
++
+
GND
GND
GND
GND
+
GNDGND
GND
GNDGNDGND
GND
GND
GNDGND
P2V5P2V5
VCCA
GND
+
GND
+
VTT
GND
GND
VTT
GND
+
VCCA
P2V5
GND
GND
SWAP BY PAIR ("NET" WITH THE CORRESPONDING "V6_NET")
UNCONDITIONAL SWAP OF BUS TRANSLATOR_TO_MLVDS
AMC MLVDS, LEVEL TRANSLATORS
NOTE: PHYSICS PROFILE SUGGESTION
SWAP BY PAIR ("NET" WITH THE CORRESPONDING "V6_NET")
PULLUP SPI_LE TO DISABLE UNCONTROLLED SPI TRAFFIC
SWAP BY PAIR ("NET" WITH THE CORRESPONDING "V6_NET")
UNCONDITIONAL SWAP OF BUS MLVDS_TO_TRANSLATOR
WHEN S40=0 & S41=1 => 2A/2B -> 4Y/4Z
14/15LAST_MODIFIED=Thu Jul 05 08:09:30 2012
Project file:glib.cpm
PCB by: PV DATE: nn/nn/nnnn
14/15
SYSTEM: SPB15.x
Design by: P.VICHOUDIS
MODULE:glib
EDA-02180-V3-0 PROJECT:GLIB
21
R176
21
R175
21
R173
C8
C4
C10
C5
C9
C11
C12
C6
C7
C2
C3
C284
C285
C286
C287 C283
C282
222
1415161718192021
109876543
IC37
222
1415161718192021
109876543
IC36
222
1415161718192021
109876543
IC35
222
1415161718192021
109876543
IC24
222
1415161718192021
109876543
IC26
222
1415161718192021
109876543
IC25
3356
59
50
53
44
47
38
41
2
1
4
3
30
29
32
31
57
58
51
52
45
46
39
40
9
7
15
13
21
19
27
25
8
6
14
12
20
18
26
24
IC38
V6_ICS874003_OE
220NF
ICS874003_MR
ICS874003_OE
TCLKB_DR_ENTCLKBV6_TCLKB
VCCA=P2V5;VCCB=P3V3
V6_TCLKB_DR_EN
TSSOP VCCA=P2V5;VCCB=P3V3
V6_CDCE_SPI_CLKV6_CDCE_SPI_LEV6_CDCE_SPI_MOSI
V6_CDCE_PWR_DOWN
V6_XPOINT1_S41V6_XPOINT1_S40
4.7K
V6_CDCE_REF_SEL
V6_CDCE_SYNC
TSSOP
VCCA=P2V5;VCCB=P3V3
V6_XPOINT2_S11XPOINT1_S41
P3V3
4.7K
V6_XPOINT1_S31V6_XPOINT1_S30
V6_XPOINT1_S20
4.7K
V6_TO_TRANSLATOR_2
V6_TO_TRANSLATOR_6V6_TO_TRANSLATOR_4
V6_TO_TRANSLATOR_7V6_TO_TRANSLATOR_1
V6_TO_TRANSLATOR_5
TRANSLATOR_TO_MLVDS_13
AMC_P19_TX_P
CDCE_PWR_DOWN
XPOINT2_S10XPOINT2_S11 CDCE_REF_SEL
CDCE_SPI_CLKXPOINT1_S20
V6_XPOINT1_S21
V6_XPOINT1_S10
220NF
TRANSLATOR_TO_V6_0
TRANSLATOR_TO_MLVDS_15
MLVDS_TO_TRANSLATOR_7
TRANSLATOR_TO_MLVDS_12MLVDS_TO_TRANSLATOR_6
TRANSLATOR_TO_MLVDS_11TRANSLATOR_TO_MLVDS_10MLVDS_TO_TRANSLATOR_5
TRANSLATOR_TO_MLVDS_9
MLVDS_TO_TRANSLATOR_4
TRANSLATOR_TO_MLVDS_6
TRANSLATOR_TO_MLVDS_4MLVDS_TO_TRANSLATOR_2
TRANSLATOR_TO_MLVDS_3
220NF
TSSOP
V6_TO_TRANSLATOR_14
220NF
220NF
TRANSLATOR_TO_V6_1
TRANSLATOR_TO_V6_3TRANSLATOR_TO_V6_2
TRANSLATOR_TO_MLVDS_5
MLVDS_TO_TRANSLATOR_3
TRANSLATOR_TO_MLVDS_7
TRANSLATOR_TO_MLVDS_8
VCC=P3V3
XPOINT1_S11
XPOINT1_S40
XPOINT1_S10
XPOINT1_S30XPOINT1_S31
P3V3
V6_TO_TRANSLATOR_3
AMC_P19_TX_N
TRANSLATOR_TO_MLVDS_14
P3V3
TRANSLATOR_TO_V6_5
P3V3
V6_TO_TRANSLATOR_11V6_TO_TRANSLATOR_9V6_TO_TRANSLATOR_15V6_TO_TRANSLATOR_13
P3V3
MLVDS_TO_TRANSLATOR_0
MLVDS_TO_TRANSLATOR_1
VCCA=P2V5;VCCB=P3V3
V6_TO_TRANSLATOR_12
TSSOP
V6_TO_TRANSLATOR_8V6_TO_TRANSLATOR_10
TRANSLATOR_TO_MLVDS_0
TRANSLATOR_TO_MLVDS_2
AMC_P20_RX_P
AMC_P20_TX_P
AMC_P19_RX_P
AMC_P18_RX_P
AMC_P17_TX_P
AMC_P18_TX_P
AMC_P17_RX_P
AMC_P17_TX_N
AMC_P17_RX_N
AMC_P18_TX_N
AMC_P18_RX_N
AMC_P19_RX_N
AMC_P20_TX_N
AMC_P20_RX_N
P3V3
TRANSLATOR_TO_V6_4TRANSLATOR_TO_V6_7TRANSLATOR_TO_V6_6
VCCA=P2V5;VCCB=P3V3TSSOP
VCCA=P2V5;VCCB=P3V3TSSOP
TRANSLATOR_TO_MLVDS_1
V6_TO_TRANSLATOR_0
CDCE_SPI_MOSICDCE_SYNC
220NF
220NF220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
220NF
CDCE_SPI_LEXPOINT1_S21
P3V3
V6_ICS874003_MRV6_ICS874003_FSEL ICS874003_FSEL
V6_XPOINT2_S10
220NF
V6_XPOINT1_S11
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
1211 GENEVA 23SWITZERLAND
Project:Sheet:
Module:European Organizationfor Nuclear Research
4
EN/ICE
GND
P2V5
P2V5
GND
GND
GND
GND
GND
SN65MLVD080
B
B
B
B
B
B
B
B
A
ADE
A
D
D
DE
R
R
DEDR
DEDR
DEDR
R
D
A
A
A
A
A
DDE
D
R
DE
DE
RRE*
GND
P2V5P2V5
OE
74AVC8T245
B6
BBBBBB
DIR
AAAAAAA 6543210
543210
7B
7A
OE
74AVC8T245
B6
BBBBBB
DIR
AAAAAAA 6543210
543210
7B
7A
OE
74AVC8T245
B6
BBBBBB
DIR
AAAAAAA 6543210
543210
7B
7A
GND
GND
P2V5
GND
OE
74AVC8T245
B6
BBBBBB
DIR
AAAAAAA 6543210
543210
7B
7A
P2V5
P2V5
GND
GNDP2V5
GND
GND
GND
P2V5
OE
74AVC8T245
B6
BBBBBB
DIR
AAAAAAA 6543210
543210
7B
7A
GNDP2V5
OE
74AVC8T245
B6
BBBBBB
DIR
AAAAAAA 6543210
543210
7B
7A
P2V5
GNDGND
P2V5
GNDGND
GNDGND
P2V5
PLACE THE GND TESTPOINTS
1.8V POWER
P3V3 IS THE MASTER TRACKING VOLTAGE
90K6 IS NEEDED BUT NOT EXISTING.
2.5V POWER MANAGEMENT POWER (3.3V, 2.5V, 1.8V)
3V3MP
1.0V POWER
IN DIFFERENT LOCATIONSPREFERABLY IN COMPONENT SIDE
MGT POWER
1V8MP
POWERING
SELECT 3V3MP SOURCEAMC_MP OR LTM4606 3V3
2V5MP
3.3V POWER
for 12V fan, mount 0R
ESD PROTECTION
HEATSINK POWER
90K6 IS NEEDED BUT NOT EXISTING.
EXTERNAL POWERATX COMPATIBLE
15/15LAST_MODIFIED=Thu Jul 05 08:09:25 2012
Project file:glib.cpm
PCB by: PV DATE: nn/nn/nnnn
15/15
SYSTEM: SPB15.x
Design by: P.VICHOUDIS
MODULE:glib
EDA-02180-V3-0 PROJECT:GLIBRESD1
RESD2
R1
SS_1V0
SS_1V5
SS_2V5SS_3V3
R163
R26
R40
R168
R45
R42
C273
C47
C39
C57
C58
C60
C59
C53
C54
C55
C56
C229
C228
C350
C349
C224
C223
R30
R24
R27
R41
R169
R166
R161
C278
C50C51
C42C43
C276C277
C271C272
C48
C49
C40
C41
C274
C275
C269
C270
321
J4
4321
J9
R116 5
6
2
8
4
3
IC16
R115
R129
R130
R216
R217
C38
C44
R25
R159
R162
R167
C279
R164
R165
R28
R29
C52
R39R47
R46
R43
R44
R160
321
J10
R2321
J5
R791
10
3 7654
92
IC13
5
6
2
8
4
3
IC34
5
6
2
8
4
3
IC17
F12
A9
B9A10
A8
G12
B11A12
C11D12C12
A7
B12
M12D11A11
IC10
F12
A9
B9A10
A8
G12
B11A12
C11D12C12
A7
B12
M12D11A11
IC21
12
1110987
15
654321
14
13
17
16
RG2
12
1110987
15
654321
14
13
17
16
RG1
F12
A9
B9A10
A8
G12
B11A12
C11D12C12
A7
B12
M12D11A11
IC9
L12
F12A9
H12
A10
J12
A8
G12
M12A12
D12C12
A7
B12
E12 K12
A11
IC20
13.3k1/16W 1%
40.2k
40.2k
0.003
MOLEX_87427-0443
100UF_X5R
POWER_ENABLE
100UF_X5R
1K
60.4K
19K1
(GND:1,7)
(GND:1,7)
LTM4606EV#PBF
10UF_LESR
100PF
0.003
PGOOD_2V5
0R0
10M
10UF_X5R
VD_2V5<1..0>
0
ESD3
ESD2
POWER_ENABLE
INTVCC_2V5
PGOOD_1V5
VD_3V3<1..0>
DRVCC_3V3<2..0>
CLKSYNC2
1 0
2 1 02 0
01
0
1
12
DRVCC_2V5<2..0>
CLKSYNC3
CLKSYNC2CLKSYNC3CLKSYNC4
CLKSYNC1
PGOOD_1V0
PGOOD_3V3
MSOPLTC6902IMS
LGA
LGA
LTM4606EV#PBF
LGA
QFN
LGA
P3V3
QFN
DVDD
SS_3V3SS_2V5
60.4K
19K1
20K
160K
20K
160K59K
100K
0R0
0R0
0R0
0R0
0R0
0R0
1K
60.4K
1K
1K
1K
100PF
100PF
10NF
25V
25V
10UF_LESR
10UF_LESR
100UF_X5R
100UF_X5R
100UF_X5R
100UF_X5R
100UF_X5R
100UF_X5R
10NF
10UF_X5R
10UF_X5R
6.3V
6.3V
10UF_X5R
6.3V
10UF_X5R
10UF_X5R
10UF_X5R
10UF_LESR
10UF_LESR
10UF_X5R
10UF_X5R
0.003
POWER_ENABLE
10UF_LESR
P3V3
0.003P3V3
POWER_ENABLE
10UF_LESR
10UF_LESR
10UF_LESR
MMC_DCDC_ENABLE
1
AMC_MP
10UF_X5R
DRVCC_1V5<2..0>
VD_1V5<1..0>
LTM4601EV#PBF
POWER_ENABLE
SS_1V5
MOLEX_22_27_2031LTM4606EV#PBF
10UF_LESR
10UF_LESR
10UF_LESR
CLKSYNC4
ESD1
10M
20K
10UF_X5R
6.3V
1%
6.3V10UF_X5R
(GND:1,7)
10UF_X5R
232k
56
1.4k
90.9k
SS_1V0 90.9k
E E
A A
B
C C
2
23
3456
67
78
8
D
1
B
D
5 1
1211 GENEVA 23SWITZERLAND
Project:Sheet:
Module:European Organizationfor Nuclear Research
4
EN/ICE
VCCA
GND
GND
P1V5
P1V5
GND GND
GNDGND
GND
GND
PGND[39..0]
VFBMARG0MARG1
VOUT_LCLDIFFVOUT
MPGM
SGND FSET
RUNCOMPINTVCCDRVCC
TRACK/SS
VOSNS+VOSNS-
PLLIN
PGOOD VOUT[42..0]
VIN
P1V5
P1V5
GND
GND
GND
P12V
P12V
P3V3A
P3V3A
P3V3A
P2V5A
P1V8A
P3V3A
GND
GND
21
3
GND
P2V5
P3V3B
P3V3B
P3V3B
P1V5
P2V5
P1V5B
P2V5B P3V3B
RES_SENSE
RES_SENSE
RES_SENSE
RES_SENSE
GND
GND
GND
GNDP3V3A
GND
GND
GND
GND
P12V
GND
GND
21
3
GNDGND
GND
GND
GND
P12V
GND
P1V0
P12V
GND
P12V
GND
P12V
GND
GND
21
3
GND
P12V
1234
P1V8
P2V5
P1V8
P2V5
GND
LT3021ES8
PGNDAGNDIN
OUT
SHDN*
ADJ
GND
GND
GND
SETV+
PHDIVMOD
OUT1
OUT4OUT3OUT2
P1V0
VCCAVTT
P12V
P3V3AP2V5A
P1V8A
LT3021ES8
PGNDAGNDIN
OUT
SHDN*
ADJ
P1V5
LT3021ES8
PGNDAGNDIN
OUT
SHDN*
ADJ
TRACK/SS
MARG0FCB
MARG1MARG1MPGMMPGM
PGND[45]SGND[2]
VD[2]
FSETDRVCC[3]INTVCC
COMP2COMP1
RUN1RUN2
PGOOD
VIN[18]
VFB
VOUT[44]
PLLIN
GND
TRACK/SS
MARG0FCB
MARG1MARG1MPGMMPGM
PGND[45]SGND[2]
VD[2]
FSETDRVCC[3]INTVCC
COMP2COMP1
RUN1RUN2
PGOOD
VIN[18]
VFB
VOUT[44]
PLLIN
GND
GND
GND GNDGND
MAX8556OUT1
OUT3OUT2
OUT4OUT5
POK
EPGND NC
IN2IN1
IN3IN4
IN6IN5
ENFB
P12V
MAX8556OUT1
OUT3OUT2
OUT4OUT5
POK
EPGND NC
IN2IN1
IN3IN4
IN6IN5
ENFB
GND
GND
GND
GND GNDGND
P12V
GND
GND
GND
GNDGNDGND
P12V
VTT
TRACK/SS
MARG0FCB
MARG1MARG1MPGMMPGM
PGND[45]SGND[2]
VD[2]
FSETDRVCC[3]INTVCC
COMP2COMP1
RUN1RUN2
PGOOD
VIN[18]
VFB
VOUT[44]
PLLIN
