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Page 1EL/CCUT T.-C. Huang May 2004
TCH
CCUT
Introduction to IC TestIntroduction to IC Test
Tsung-Chu Huang(黃宗柱 )
Department of Electronic Eng.Chong Chou Institute of Tech.
Email: [email protected]
2004/05/10
Page 2EL/CCUT T.-C. Huang May 2004
TCH
CCUT
Syllabus & Chapter PrecedenceIntroduction
Modeling
Logic Simulation Fault Modeling
Fault Simulation
Testing for Single Stuck Faults
Test Compression
Built-In Self-Test
Design for Testability
Page 3EL/CCUT T.-C. Huang May 2004
TCH
CCUT
Aliasing
Test Generator
Good Circuit
Bad Circuit
Correct Response
Correct Response
Unobservable
Aliasing
Testable
Test Generator
Good Circuit
Bad Circuit
Correct Response
Error Response
Compress
Compress
Test Generator
Good Circuit
Bad Circuit
Correct Response
Error Response
Non-alias
Compress
Compress
Test Generator
Good Circuit
Bad Circuit
Correct Response
Error Response
Page 4EL/CCUT T.-C. Huang May 2004
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CCUT
Compression RateOriginal Digital Signal
with N Bytes
Compressed filewith Nc Bytes
Uncompressed filewith M Bytes
%100
N
NNR cwith distortion
Original Test Vectorsfor Fault Set, F, with N patterns
Compressed Vectorsfor Fault Set, G, with Nc patterns
%100
N
NNR c
Test (Vector) Compression
Original Test Resultsfor Fault Set, F, with N patterns
Compressed Resultsfor Fault Set, G, with Nc patterns
%100
N
NNR c
Test Signature Compression
Aliased iff F≠G, alias rate = %100\\
F
FGGFa
Page 5EL/CCUT T.-C. Huang May 2004
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CCUT
Test Compression Techniques
1. One-Counting• #1’s in response sequence
2. Transition Counting• Transition btw responses rt and rt+1
3. Parity Checking• 0-parity or 1-parity
4. Syndrome Checking 1-Counting; 1-ratio in the K-map
5. Signature Analysis• Based on CRC (Cyclic Redundancy Check) usi
ng LFSR (Linear Feedback Shift Register)
Page 6EL/CCUT T.-C. Huang May 2004
TCH
CCUT
One-Counting
Circuit under Test(CUT)
101101
1001
110001
1010
001100
0111
111111
1110
000100
1000
Transition-Counting
1C=11
Parity Check → Odd
Compression Rate: n
nlog1
Compression Rate: n
11
21
12
1
nPan
nr Aliasing Rate:
Page 7EL/CCUT T.-C. Huang May 2004
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CCUT
Syndrome Test
• The Syndrome S is the normalized number of ones in the result bit stream based on exhausting test.
• That is, the one-count in the deterministic K-map.• The syndrome probability can be calculated.
AND
OR
NAND
NOR
XOR
S1S2
S1+S2-S1S2
1-S1S2
1-S1-S2+S1S2
S1+S2-2S1S2
S1
S2
S
• Not practical in circuitry with many inputs.
Page 8EL/CCUT T.-C. Huang May 2004
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CCUT
Linear Logic Circuit
• A linear (logic) circuit preserved the principle of superposition and is constructed from:
• Delay Flipflops
• Modulo-2 Adder
• Modulo-2 Scalar Multiplier
Dx y = Dx
x
c
cx x cxc x cxc
x
y
x+y x
y
x+y
Page 9EL/CCUT T.-C. Huang May 2004
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CCUT
Linear Feedback Shift Register, LFSR• An LFSR can be mapped into a feedback linear circuit with D
FFs & XORs in a modulo-2 domain.• Canonical Forms:
Type I (Direct Form, External Form):
Type II (Indirect Form, Internal Form):
D1
C1
+
D2
C2
+
D3
C3
+
D4
C4
+
Dn-1
Cn-1
+
Dn
Cn=1
D1 D2 D3 D4 Dn-1 Dn
Cn=1 Cn-1
+
Cn-2
+
Cn-3
+
Cn-4
+
C1
+
Page 10EL/CCUT T.-C. Huang May 2004
TCH
CCUT
Example
D1 D2
+
D3
So= 0 0 1
S1= 1 0 0
S2= 0 1 0
S3= 1 0 1
S4= 1 1 0
S5= 1 1 1
S6= 0 1 1
S7= 0 0 1
So= 1 0 0
1 0 0 1 0 1 1 1 0
Generating Function
Page 11EL/CCUT T.-C. Huang May 2004
TCH
CCUT
Why LFSR ?
• Simple and Regular Structure• Compatible with scan DFT design• Capable of exhaustive and/or pseudo
exhaustive testing• Low aliasing probability.
Page 12EL/CCUT T.-C. Huang May 2004
TCH
CCUTCharacteristic polynomial P(x)
Characteristic Polynomials of an LFSR
D1
C1
+
D2
C2
+
D3
C3
+
D4
C4
+
Dn-1
Cn-1
+
Dn
Cn=1
0
)(m
mm xaxG
Generating function
1a 2a 3a 4a 1 na naInitial State =
1ma 2ma 3ma 4ma 1 nma nma
11
m
n
iim aca
01
1
1 00 1
)]([)(m
mm
n
i im
mm
ii
i
n
m
imim
ii
m
n
i
mimi xaxaxcxaxcxacxG
n
i
ii
im
mm
n
i
iin
i im
mm
n
i
ii
ii
xc
xaxcxaxcxGxcxG
1
1
1
1
1
1 1)()(
)(
1
xP If IS=1 at Dn.
Page 13EL/CCUT T.-C. Huang May 2004
TCH
CCUT
Maximum Length Sequence
p
p
m
mm
j
pp
m
mm x
xaxxa
xP
1)(
1
1
0
0
1
0
Let p be the generating period, P(x) divides into 1-xp.
Reciprocal polynomial of P(x) is P*(x)=xnP(1/x).
If G(x) of an n-stage LFSR has period 2n-1, then it is called a maximum-length sequence (MLS) and the characteristic polynomial is called a primitive polynomial.
An irreducible polynomial P(x) is with odd number of terms and it’s primitive if min(k)=n for .]1[|)( )12(
k
xxP
Primitive (MLS)Polynomials
Irreduciblepolynomials
Page 14EL/CCUT T.-C. Huang May 2004
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CCUT
An Algorithm to Search ML-LFSR
1. For i=1, x+1 is a primitive polynomial;2. Put searched irreducible polynomials into a queue.3. Check a polynomial of order n with the irreducible
polynomial of order less than square-root of n.4. If it is irreducible, check if k is the smallest integer such that
it divides into 1+xk, where k=2n-1.
Page 15EL/CCUT T.-C. Huang May 2004
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CCUT
Examples of Primitive Polynomials
D1 D2
+
D3
1)(* 23 xxxPD1 D2 D3+
125 xx
1568 xxxx
123516 xxxx
1272832 xxxx
11136 xx
1)( 3 xxxPD1 D2
+
D3D1 D2 D3+
primitive
Note that P*(x) must not be primitive even if P(x) primitive.
Page 16EL/CCUT T.-C. Huang May 2004
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CCUT
Characteristics of MLS
1. The number of ones in an L-Sequence differs from the number of zeros by 1.
2. An L-Sequence produces an equal number of runs of 1s and 0s.
3. In every L-Sequence, one half the runs have length 1, one fourth have length 2, one eighth have length 3, and so forth.
4. The above properties of randomness make feasible the use of LFSRs as test sequence generators in BIST (Built-In Self-Test, introduced in next chapter) circuitry.
5. LFSRs used as counters are taken advantage of its speed (usually with only the exclusive gate for propagation time of the combinational circuits)
Page 17EL/CCUT T.-C. Huang May 2004
TCH
CCUT
Pseudo Randomness156 xxExample:
0
10
20
30
40
50
60
70
0 20 40 60 80 100 120 140
G%(2n-1)=G%63
0
1
2
3
4
5
6
7
8
0 20 40 60 80 100 120 140
G%2(n-1)=G%8
0
12
34
56
78
9
0 20 40 60 80 100 120 140
G%2(n-1)=G%9
0
1
2
3
4
5
6
7
0 20 40 60 80 100 120 140
G%2(n-1)=G%7
Page 18EL/CCUT T.-C. Huang May 2004
TCH
CCUT
LFSR with the All-Zero Pattern
D1
C1
+
D2
C2
+
D3
C3
+
D4
C4
+
Dn-1
Cn-1
+
Dn
Cn=1
Reset all FFs
Page 19EL/CCUT T.-C. Huang May 2004
TCH
CCUT
(Pseudo) Random Pattern Generator (RPG)
RPG
Typically, 32~128 bitsScan chain
Typically, length of 500~3000
CUTCUT CUTCUTCUT
SA
Typically, 32~128 bits
Page 20EL/CCUT T.-C. Huang May 2004
TCH
CCUT
Signature Analyzer (SA)
D1
C1
+
D2
C2
+
D3
C3
+
D4
C4
+
Dn-1
Cn-1
+
Dn
Cn=1
0
)(m
mm xaxG
orGenerating function
1a 2a 3a 4a 1 na naInitial State =
)(xS
Input Streamof length L
)(xQQuotient
)(xRRemainder
Characteristic polynomial P(x)
)(
)()()()(
xP
xRxSxQxG
• Signature Analysis is a compression technique based on the concept of cyclic redundancy checking (CRC).
• We use S(x) to denote the input stream (instead of G(x) that is confused in textbook).
Page 21EL/CCUT T.-C. Huang May 2004
TCH
CCUT
Signature Analyzer (SA)
RPG as a special case of SA: S(x)=0 and
1
1
)(im
mm
n
i
ii xaxcxR
There are 2L possible input stream, 2L-n streams produce a signature.
Aliasing rate (proportion of masking error streams is n
L
nL
212
12
SA with >1 non-0 coefficients detects all single-bit errors (e.g. x+1).
Page 22EL/CCUT T.-C. Huang May 2004
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CCUT
Two Different Application Examples
SA1 SA2
Encryption Decryption
Communication
X(t) X(t-d)????
PRPG SA
Testing
CUT
Page 23EL/CCUT T.-C. Huang May 2004
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CCUT
Multiple Input Signature Register (MISR)Only Type II (Internal) forms can be improved to be multiple-input.
D1 D2 D3 D4 Dn-1 Dn
Cn=1 Cn-1
+
Cn-2
+
Cn-3
+
Cn-4
+
C1
+
CUT
Can be RPG or Non-Random Patterns (e.g., Counter)
Page 24EL/CCUT T.-C. Huang May 2004
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CCUT
Multiple Inputs Used in Seed Loading
D1 D2 D3 D4 Dn-1 Dn
Cn=1 Cn-1
+
Cn-2
+
Cn-3
+
Cn-4
+
C1
+
Seed base ROM or Register
Page 25EL/CCUT T.-C. Huang May 2004
TCH
CCUT
Integrated RPG/MISR into Scan Cells
Combinational Circuit
Di
Si
Dn
Ci
Normal
MISR
RPG
Scan
Page 26EL/CCUT T.-C. Huang May 2004
TCH
CCUT
Syllabus & Chapter PrecedenceIntroduction
Modeling
Logic Simulation Fault Modeling
Fault Simulation
Testing for Single Stuck Faults
Test Compression
Built-In Self-Test
Design for Testability
( I )
Page 27EL/CCUT T.-C. Huang May 2004
TCH
CCUT
Built-In Self-Test (BIST)
1. To Reduce input/output pin signal traffic.2. Permit easy circuit initialization and observation.3. Eliminate as much test pattern generation as possible.4. Achieve fair fault coverage on general class of failure
mode.5. Reduce test time.6. Execute at-speed testing.7. Test circuit during burn-in.
Page 28EL/CCUT T.-C. Huang May 2004
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CCUT
Issues
1. Area overhead2. Performance degradation3. Fault coverage4. Ease of Implementation5. Capability for system test6. Diagnosis capability
Page 29EL/CCUT T.-C. Huang May 2004
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CCUT
Typical BIST Techniques
1. Stored Vector Based1. Microinstruction support2. Stored in ROM
2. Algorithmic Hardware Test Pattern Generators1. Counter2. Linear Feedback Shift Register3. Cellular Automata
Design with BIST
Test Good (or Not)