32-bit Embedded Core Peripheral

Parallel Input/Output 2 (PIO2)

Rev. 1725A–03/01

Features• Compatible with an Embedded 32-bit ARM7TDMI® Processor• Up to 32 Programmable I/O Lines• Two Peripherals per I/O Line• Peripheral Input Drivable by Output Peripheral (Loop Mode)• Interrupt Generation on Event• Glitch Filter• Fully Scan Testable (up to 98% Fault Coverage)• Can be Directly Connected to the Atmel Implementation

of the AMBA™ Peripheral Bus (APB) of the ARM7TDMI Microcontroller• Multi-driver (Open Drain) Option• Certain Options Parameterizable on Request:

– Number of Programmable Lines– Glitch Filter Option– Multi-driver (Open Drain) Option– Reset State of PIO Status and Glitch Filter Status

DescriptionThe Parallel Input/Output 2 (PIO2) 32-bit embedded core peripheral features 32 fully-programmable input/output lines, each of which may be dedicated as general-purposeI/O or be multiplexed with a signal generated by another embedded peripheral, inorder to optimize the use of available package pins in the overall system-on-chipdesign. The PIO2 controller provides a bit-maskable event-driven internal interruptsignal.

The PIO2 and other analog and digital modular embedded peripherals, together with achoice of microprocessor and DSP cores, on-chip RAM, ROM, EEPROM and Flashmemory, as well as special-purpose analog or digital user-developed blocks, allowrapid and cost-effective design and implementation of an optimized system-on-chip.The large range of functional blocks offers a realistic and efficient design pathway tosystem-level integration (SLI).

The PIO2 is bus-compatible with the ARM7TDMI 32-bit microcontroller core. It canalso be used with other 32-bit MCU or DSP cores.

The PIO2 is supplied with comprehensive test vector sets. Atmel’s proprietary foundryinterface tools ensure a smooth transition from design to fabrication.

1

Figure 1. PIO2 Terminal Connections

Note: 1. Depends on “on-request” parameters. For example, if 20 lines are requested, it will be [19:0].

p_d_in[31:0]

nreset

p_a[13:0]

p_write

p_stb

clock

p_sel_pio

scan_test_mode

pio_int

test_so[2:1]

p_d_out[31:0]

PIO

APB

APB

test_se

test_si[2:1] Scan Test

Scan Test

p_stb_rising

Pad d_from_pad[31*:0]

Chip-wide

Peripherald_from_periph[31*:0]

en_periph_n[31*:0]

Interrupt

d_to_pad[31*:0]

oen_to_pad[31*:0]

d_to_periph[31*:0]

Pad

Peripheral

*Depends on "on-request" parameters. For example, if 20 lines are requested, it will be [19:0].

2 PIO21725A–03/01

PIO2

Table 1. PIO2 Terminal Description

Name Function TypeActive Level Comments

Chip-wide

nreset System reset Input Low Resets all counters and signals Clocked on rising edge of clock

nreset_f System reset Input Low Resets all counters and signals Clocked on falling edge of clock

clock System clock Input – System clock

Atmel Peripheral Bus (APB)

p_a [13:0] Address bus Input – The address takes into account the 2 LSBs [1:0], but the PIO2 macrocell does not decode these bits

p_d_in [31:0] Input data bus Input – From host (bridge)

p_d_out [31:0] Output data bus Output – To host (bridge)

p_write Write enable Input High From host (bridge)

p_stb Peripheral strobe Input High From host (bridge)

p_stb_rising User interface clock signal Input – From host (bridge) – Clock for all DFFs controlling the configuration registers

p_sel_pio Selects the PIO2 block Input High From host (bridge)

Pad

d_from_pad [31(1):0] Pad input data Input – Data from an I/O pad

d_to_pad [31(1):0] Pad output data Output – Data to an I/O pad

oen_to_pad [31(1):0] Pad output enable Output Low Output enable for a bi-directional pad

in_pad_enable [31(1):0] Pad input enable Output High Pad input buffer enable/disable

Peripheral

d_from_periph_a [31(1):0] Peripheral data input Input – Data from an on-chip peripheral

d_from_periph_b[31(1):0] Peripheral data input Input – Data from an on-chip peripheral

d_to_periph_a[31(1):0] Peripheral data output Output – Data to an on-chip peripheral

d_to_periph_b[31(1):0] Peripheral data output Output – Data to an on-chip peripheral

en_periph_n_a [31(1):0] Peripheral data enable Input Low Enables data from an on-chip peripheral to a pad when a peripheral connection is enabled

en_periph_n_b [31(1):0] Peripheral data enable Input Low Enables data from an on-chip peripheral to a pad when a peripheral connection is enabled

Interrupt

pio_int PIO2 generated Interrupt Output High Any I/O line may be programmed to generate an event-driven interrupt

Test Scan

scan_test_mode Clock selection for test purposes Input High

31725A–03/01

Note: 1. Depends on “on-request” parameters. For example, if 20 lines are requested, it will be [19:0].

test_se Scan test enable Input High/Low Scan shift/scan capture

test_si[2:1] Scan test input Input High Entry of scan chain

test_so [2:1] Scan test output Output – Ouput of scan chain

Table 1. PIO2 Terminal Description (Continued)

Name Function TypeActive Level Comments

4 PIO21725A–03/01

PIO2

Figure 2. Interconnecting the PIO2 in an ARM®-based Microcontroller System-on-chip (Example)

32-bitProcessor

Core

Atmel Bridge

p_d_

in[3

1:0]

p_w

rite

p_d_

out[3

1:0]

p_st

b

p_a

[13:

0]

p_se

l_pi

o

Atmel Peripheral BusAPB

Advanced System BusASB

Parallel Input/OutputPIO0

nreset

nreset

clock

To Advanced Interrupt

Controller (AIC)

pio_int

USARTPeripheral

Pad

d_from_pad

d_to_pad

oen_to_pad

clockp_

stb_

risin

g

rxd

txd

en_clk_n

(ARM)

Chip-wide Signals

d_to_periph

d_from_periph

en_periph_n

51725A–03/01

Functional Description

The 32-bit PIO2 peripheral is fully compatible with an embedded ARM7TDMI processor.

The PIO2 peripheral features 32 fully-programmable I/O lines, each of which may be multi-plexed with an on-chip peripheral signal.

The device can also provide a bit-maskable event-driven on-chip interrupt signal.

The PIO2 peripheral is fully-controllable via 11 sets of three 32-bit registers; pin data and inter-rupt source conditions are available to user software via two 32-bit registers.

Figure 3 illustrates PIO2 functionality and the effect of register programming as described inthe following sections.

Figure 3. PIO2 Control and Status Register Architecture

Pad

PIO_OSR

1

0

1

0

PIO_PSR

PIO_ODSR

Event Detection

PIO_PDSR

PIO_ISR

PIO_IMR

PeripheralOutputEnable

PeripheralOutput

PeripheralInput

PIO_IRQ

Pad Output Enable

Pad Output

Pad Input

6 PIO21725A–03/01

PIO2

Scan Test Configuration

Fault coverage is maximized when all non-scan inputs can be controlled and when all non-scan outputs can be monitored. In order to achieve this, it is preferable that the ATPG vectorsbe generated on the entire circuit which includes the PIO2 embedded peripheral (top-level);alternatively, all of the inputs and outputs of the PIO2 should be made accessible so thatATPG vectors can be applied to all terminals.

Control Registers Each individual I/O channel is associated with a bit in the various 32-bit PIO2 user interfaceregisters (control and status registers) which are listed in Table 2. The inter-relationship offunctionality with the various status and control registers is also illustrated in Figure 3. If a par-allel I/O line is not defined, writing to the corresponding bits has no effect; reading the bit willreturn zero.

Functionality of the PIO2 is governed by four 32-bit read-only status registers and a read-onlyinterrupt mask register. These registers are each controlled by a pair of user software accessi-ble write-only control registers. Two further read-only 32-bit status registers allow pin data andinterrupt source conditions to be monitored by user software.

When writing to a Control Register, only a logic 1 affects the related bit: thus, the user soft-ware writes a 1 to the Enable Control Register to enable the desired function and it writes a 1to the associated Disable Control Register to disable the function. Writing a logic 0 to a ControlRegister has no effect. Any attempt at writing to a read-only register has no effect. Any attemptat reading a write-only control register returns undefined data.

Bi-directional Multiplexed I/O

After reset, all channels are connected to the PIO2 controller as I/O and are in input mode(unless the reset value of the related status registers is programmed otherwise during systemdesign; this may be the case if other on-chip peripherals are connected to the outside worldvia the PIO2).

I/O lines may be multiplexed with the input and output signals of another on-chip peripheral.The state of each bit of the PIO Status Register (PIO_PSR) determines whether the relatedchannel is connected to an on-chip peripheral or as processor-addressable Parallel I/O. ThePIO Status Register (PIO_PSR) is controlled by writing a logic 1 to the relevant bit of the PIOEnable (PIO_PER) or to the PIO Disable (PIO_PDR) Control Registers. Writing a 0 to a Con-trol Register has no effect.

When the PIO2 is selected, the peripheral input line is connected to zero.

If a pin is a general-purpose parallel I/O pin (not multiplexed with a peripheral), PIO_PER andPIO_PDR has no effect and reading PIO_PSR returns a logic 1 for the bits corresponding tothese pins.

Output Enabling Each channel is effectively bi-directional. A channel output may be disabled by suitably pro-gramming the Output Status Register (PIO_OSR) via the PIO_ODR (Output Disable) write-only Control Register. Conversely, the user can enable a channel as an output by writing alogic 1 to the relevant bit of the PIO_OER (Output Enable) Control Register. The status of thevarious channels is monitored by reading the Output Status Register (PIO_OSR).

Output enabling/disabling may only be controlled by user software when the channel has beenconfigured as parallel I/O (via PIO Status Register, PIO_PSR); when the channel is configuredas peripheral-driven, the pad output is enabled by a logic 0 state on the Peripheral DataEnable (EN_PERIPH_N) terminal. This signal originates from another on-chip peripheral.

71725A–03/01

Pin Signal Levels Each pin may be actively driven high or low, or its level may be determined by off-chip cir-cuitry. The actual logic level on the pin is governed by the following conditions:• If a channel is driven by the PIO2 controller and is defined as an output (see "Output

Enabling" above), its pin level is governed by the state of the Output Data Status Register (PIO_ODSR) which may be controlled by writing a logic 1 to the Set Output Data Control Register (PIO_SODR) or to the Clear Output Data Control Register (PIO_CODR). The programmed value may be read from the Output Data Status Register (PIO_ODSR).

• If a channel is driven by the PIO2 controller, but is not enabled as an output, the pin level will be determined by the external off-chip circuit, irrespective of the Output Data Status Register contents.

• If a channel is driven by an on-chip peripheral and the PIO Status Register (PIO_PSR) is programmed to enable the peripheral connection, its level will be defined by the peripheral.

In all cases, the actual level on a pin may be monitored by reading the corresponding bit of thePin Data Status Register (PIO_PDSR).

Interrupts Each I/O channel can be programmed to generate an interrupt when a voltage level changeoccurs on the related external pin.

Each individual channel may have its interrupt generation enabled or disabled according to thelogic condition of the related bit in the Interrupt Mask Register (PIO_IMR) which is controlledby writing a logic 1 to the relevant bit of the Interrupt Enable (PIO_IER) or to the Interrupt Dis-able (PIO_IDR) Control Register, in the same fashion as for the other Control Registersdescribed above.

When a change in level occurs, the corresponding bit in the Interrupt Status Register(PIO_ISR) register is set, whether the pin is used for a peripheral function or for processoraddressed PIO and whether the channel is working in input or in output mode. When the Inter-rupt Status Register (PIO_ISR) is read by user software, its contents are automaticallycleared.

If the corresponding interrupt is enabled in the Interrupt Mask Register (PIO_IMR), the rele-vant interrupt signal is generated. The interrupt signals from all 32 channels are gated togetherto generate a single PIO Interrupt signal (PIO_INT) that is available for routing to the systeminterrupt controller.

Glitch Filtering Optional glitch filtering is available for each channel. It is governed by the state of the Input Fil-ter Status Register (PIO_IFSR) which is controlled by writing a logic 1 to the relevant bit of theInput Filter Enable (PIO_IFER) or to the Input Filter Disable (PIO_IFDR) Control Registers, inthe same fashion as for the other control registers described above.

Input glitch filtering may be selected, whether the pin is used for a peripheral function or forprocessor addressed parallel input.

When the filter is activated, a glitch with a duration of less than 1/2 clock cycle is automaticallyrejected, while a pulse with a duration of 1 clock cycle or more is accepted. For pulse dura-tions between 1/2 clock cycle and 1 clock cycle the pulse may or may not be taken intoaccount, depending on the precise timing of its occurrence. Thus for a pulse to be visible itmust exceed 1 clock cycle, whereas for a glitch to be reliably filtered out, its duration must notexceed 1/2 clock cycle.

8 PIO21725A–03/01

PIO2

Multi-driver (Open Drain)

Each I/O can be programmed for multi-driver option. This means that the I/O is configured asopen drain (can only drive a low level) in order to support external drivers on the same pin. Anexternal pull-up is necessary to guarantee a logic level of one when the pin is not being driven.

Registers PIO_MDER (Multi-driver Enable) and PIO_MDDR (Multi-driver Disable) control thisoption. Multi-driver can be selected whether the I/O pin is controlled by the PIO controller orthe peripheral. PIO_MDSR (Multi-driver Status) indicates which pins are configured to supportexternal drivers.

Peripheral Select The active peripheral is selected by means of the PIO_ABSR register. It allows the reductionof I/O pads when peripherals are not used at the same time.

Peripheral to Peripheral Drives

When selected, this mode allows peripheral A/B to drive input through peripheral B/A outputusing the register PIO_ALSR and/or PIO_BLSR.

Disabling Pad Input Buffer

When gated input pad buffers are used, the PIO_PADDR and PIO_PADER registers can beused to drive the gated input and avoid static consumption when the output PIO line is in tri-state mode.

Direct Write Output Status Register

When the Write Output Status Register is activated, it is possible to write directly to thePIO_ODSR register without using registers PIO_SODR and PIO_CODR. The bits of the regis-ter are, therefore, in Read/Write mode instead of Read Only when the corresponding bits inPIO_WOSR are set.

91725A–03/01

PIO2 User Interface Register Descriptions

Table 2. PIO2 Controller Memory Map

Offset Control Registers Status Registers Name Access Reset State

0x000 PIO Enable Register PIO_PER Write-only –

0x004 PIO Disable Register PIO_PDR Write-only –

0x008 PIO Status Register PIO_PSR Read-onlyFFFFFFF (See Notes 1 and 4)

0x00C Reserved

0x010 Output Enable Register PIO_OER Write-only –

0x014 Output Disable Register PIO_ODR Write-only –

0x018 Output Status Register PIO_OSR Read-only 0

0x01C Reserved

0x020Glitch Input Filter Enable

Register PIO_IFER Write-only –

0x024Glitch Input Filter Disable

Register PIO_IFDR Write-only –

0x028Glitch Input Filter Status

Register PIO_IFSR Read-only (See Note 4)

0x02C Reserved

0x030 Set Output Data Register PIO_SODR Write-only –

0x034 Clear Output Data Register PIO_CODR Write-only –

0x038 Output Data Status Register PIO_ODSR Read-only 0 (see Note 5)

0x03C Pin Data Status Register PIO_PDSR Read-only (see Note 2)

0x040 Interrupt Enable Register PIO_IER Write-only –

0x044 Interrupt Disable Register PIO_IDR Write-only –

0x048 Interrupt Mask Register PIO_IMR Read-only 0

0x04C Interrupt Status Register PIO_ISR Read-only0

(see Note 3)

0x050 Multi-driver Enable Register PIO_MDER Write-only –

0x054 Multi-driver Disable Register PIO_MDDR Write-only –

0x058 Multi-driver Status Register PIO_MDSR Read-only (see Note 4)

0x05C Reserved

0x060 Pad Enable Register PIO_PADER Write-only –

0x064 Pad Disable Register PIO_PADDR Write-only –

0x068 Pad Status Register PIO_PADSR Read-only 0

0x06C Reserved

10 PIO21725A–03/01

PIO2

Notes: 1. Unless otherwise programmed during system-level design according to peripheral mapping and multiplexing.2. The value of this register will depend on the level of the external pins.3. This register is cleared on Reset. However, the first read of the register may give a non-zero value if any changes have

occurred on any of the external pins between Reset and when the register is read.4. The value of these registers can be customer-defined. The default value is 0.5. The value of this register is Read Only or Read/Write if PIO_OWSR is configured with ones.

Reset Configuration

The Reset state of the following PIO2 registers can be defined by the customer: PIO StatusFilter, Glitch Input Filter Status, Multi-driver.

User Interface Register Descriptions

All control and status registers are 32-bit: each bit of the User Interface Registers is associ-ated with the corresponding I/O channel, bit 0 with channel 0, bit 1 with channel 1, and so on.This mapping is shown diagrammatically in the table below.

0x070 Select B Register PIO_BSR Write-only –

0x074 Select A Register PIO_ASR Write-only –

0x078 AB Select Status Register PIO_ABSR Read-only 0 (A selected)

0x07C Reserved

0x080 Loop Enable Register A PIO_ALER Write-only –

0x084 Loop Disable Register A PIO_ALDR Write-only –

0x088 A Loop Status Register PIO_ALSR Read-only 0

0x08C Loop Enable Register B PIO_BLER Write-only –

0x090 Loop Disable Register B PIO_BLDR Write-only –

0x094 B Loop Status Register PIO_BLSR Read-only 0

0x098 Reserved

0x09C Reserved

0x0A0 Output Write Enable PIO_OWER Read-only –

0x0A4 Output Write Disable PIO_OWDR Read-only –

0x0A8 Output Write Status Register PIO_OWSR Write-only 0

Table 2. PIO2 Controller Memory Map (Continued)

Offset Control Registers Status Registers Name Access Reset State

31 30 29 28 27 26 25 24P31 P30 P29 P28 P27 P26 P25 P24

23 22 21 20 19 18 17 16P23 P22 P21 P20 P19 P18 P17 P16

15 14 13 12 11 10 9 8P15 P14 P13 P12 P11 P10 P9 P8

7 6 5 4 3 2 1 0P7 P6 P5 P4 P3 P2 P1 P0

111725A–03/01

PIO2/Peripheral MultiplexingFor the bit configuration of the register, see Table 2, “PIO2 Controller Memory Map,” on page 10.

PIO Enable RegisterRegister Name: PIO_PERAccess Type: Write-only This register is used to enable control of individual pins by the PIO controller rather than by an internally connected periph-eral. When the PIO is enabled, the Data to Peripheral (D_TO_PERIPH) signal is held at logic zero. The register isprogrammed as follows:

1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin).

0 = No effect.

PIO Disable RegisterRegister Name: PIO_PDRAccess Type: Write-only This register is used to disable control of individual pins by the PIO controller. When PIO control is disabled, the peripheralfunction (if any) connected to the I/O channel is enabled to control the corresponding pin. The register is programmed asfollows:

1 = Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin).

0 = No effect.

PIO Status RegisterRegister Name: PIO_PSRAccess Type: Read-onlyReset Value: FFFFFFF (Unless programmed otherwise in system-level design according to peripheral mappingand multiplexing)This register indicates which pins are enabled for PIO control. This register is updated when PIO lines are enabled or dis-abled. The register reads as follows:

1 = PIO is active on the corresponding line (peripheral is inactive).

0 = PIO is inactive on the corresponding line (peripheral is active).

12 PIO21725A–03/01

PIO2

PIO Output EnableFor the bit configuration of the register, see Table 2, “PIO2 Controller Memory Map,” on page 10.

PIO Output Enable Register Register Name: PIO_OERAccess Type: Write-only This register is used to enable PIO output drivers. If the pin is driven by an internally connected peripheral, PIO_OER hasno effect on the pin, but the information is stored. The register is programmed as follows:

1 = Enables the PIO output on the corresponding pin.

0 = No effect.

PIO Output Disable RegisterRegister Name: PIO_ODRAccess Type: Write-only This register is used to disable PIO output drivers. If the pin is driven by an internally connected peripheral, PIO_ODR hasno effect on the pin, but the information is stored. The register is programmed as follows:

1 = Disables the PIO output on the corresponding pin.

0 = No effect.

PIO Output Status RegisterRegister Name: PIO_OSRAccess Type: Read-onlyReset Value: 0 This register shows the PIO pin control (output enable) status which is programmed via PIO_OER and PIO_ODR. Thedefined value is effective only if the pin is controlled by the PIO. The register reads as follows:

1 = The corresponding PIO is output on this line.

0 = The corresponding PIO is input on this line.

131725A–03/01

Glitch FilteringFor the bit configuration of the register, see Table 2, “PIO2 Controller Memory Map,” on page 10.

PIO Input Filter Enable RegisterRegister Name: PIO_IFERAccess Type: Write-only This register is used to enable input glitch filters; it affects the data read from the pin whether or not the PIO is enabled. Theregister is programmed as follows:

1 = Enables the glitch filter on the corresponding pin.

0 = No effect.

PIO Input Filter Disable RegisterRegister Name: IO_IFDRAccess Type: Write-only This register is used to disable input glitch filters. It affects the data read from the pin whether or not the PIO is enabled.The register is programmed as follows:

1 = Disables the glitch filter on the corresponding pin.

0 = No effect.

PIO Input Filter Status RegisterRegister Name: PIO_IFSRAccess Type: Read-onlyReset Value: 0 This register indicates which pins have glitch filters selected, as programmed via PIO_IFER and PIO_IFDR. The registerreads as follows:

1 = Filter is selected on the corresponding input (peripheral and PIO).

0 = Filter is not selected on the corresponding input.

14 PIO21725A–03/01

PIO2

PIO Data OutputFor the bit configuration of the register, see Table 2, “PIO2 Controller Memory Map,” on page 10.

PIO Set Output Data RegisterRegister Name: PIO_SODRAccess Type: Write-only This register is used to set PIO data output to the corresponding pads. It affects the related pins only if the correspondingPIO outputs are enabled and if the pins are controlled by the PIO controller. Otherwise, the information is simply stored andis acted on if the PIO is later enabled. The register is programmed as follows:

1 = PIO output data on the corresponding pin is set (logic 1).

0 = No effect.

PIO Clear Output Data RegisterRegister Name: PIO_CODRAccess Type: Write-only This register is used to clear PIO data output to the corresponding pads. It affects the related pins only if the correspondingPIO outputs are enabled and if the pins are controlled by the PIO controller. Otherwise, the information is simply stored andis acted on if the PIO is later enabled. The register is programmed as follows:

1 = PIO output data on the corresponding pin is cleared (logic 0).

0 = No effect.

PIO Output Data Status RegisterRegister Name: PIO_ODSRAccess Type: Read-onlyReset Value: 0 This register shows the output data status which is programmed via PIO_SODR or PIO_CODR. The bit pattern is effectiveonly for those pins under the control of the PIO controller and only if the pins are enabled as outputs. Otherwise, the infor-mation is simply stored and is acted on if the PIO is later enabled. The register reads as follows:

1 = The output data for the corresponding pin is programmed to 1.

0 = The output data for the corresponding pin is programmed to 0.

151725A–03/01

Interrupt MaskingFor the bit configuration of the register, see Table 2, “PIO2 Controller Memory Map,” on page 10.

PIO Interrupt Enable RegisterRegister Name: PIO_IERAccess Type: Write-only This register is used to enable PIO interrupts generated by the corresponding pins; logic level changes are detected andstored in the Interrupt Status Register (PIO_ISR). Enabled interrupts will be generated whether the PIO is enabled or not.The register is programmed as follows:

1 = Enables an interrupt when a change of logic level is detected on the corresponding pin.

0 = No effect.

PIO Interrupt Disable RegisterRegister Name: PIO_IDRAccess Type: Write-only This register is used to disable PIO interrupts generated by the corresponding pins. Logic level changes are still detectedand stored in the Interrupt Status Register (PIO_ISR). Disabled interrupts will be inhibited whether the PIO is enabled ornot. The register is programmed as follows:

1 = Disables the interrupt generated by the corresponding pin.

0 = No effect.

PIO Interrupt Mask RegisterRegister Name: PIO_IMRAccess Type: Read-onlyReset Value: 0 This register shows which pins have interrupts enabled. It is updated when interrupts are enabled or disabled by writing toPIO_IER or PIO_IDR. The register reads as follows:

1 = Interrupt is enabled from the corresponding pin.

0 = Interrupt is disabled from the corresponding input pin.

16 PIO21725A–03/01

PIO2

Interrupt SourceFor the bit configuration of the register, see Table 2, “PIO2 Controller Memory Map,” on page 10.

PIO Interrupt Status RegisterRegister Name: PIO_ISRAccess Type: Read-onlyReset Value: 0 This register indicates, for each pin, when a logic level change has been detected (rising or falling edge). This is validwhether the PIO is selected for the pin or not and whether the pin is an input or output.The register is reset to zero following a read, as well as at reset. The register reads as follows:

1 = At least one change has been detected on the corresponding pin since the register was last read or since reset.

0 = No change has been detected on the corresponding pin since the register was last read or since reset.

Output Pin LevelFor the bit configuration of the register, see “PIO2 Controller Memory Map” on page 10.

PIO Pin Data Status RegisterRegister Name: PIO_PDSRAccess Type: Read-onlyReset Value: UndefinedThis register shows the logic level of the physical I/O pin. The pin logic levels are always valid, regardless of whether thepins are enabled as PIO, peripheral, input or output. The value of this register will depend on the level of the external pins. The register reads as follows:

1 = The corresponding pin is at logic 1.

0 = The corresponding pin is at logic 0.

171725A–03/01

Multi-drive OptionFor the bit configuration of the register, see Table 2, “PIO2 Controller Memory Map,” on page 10.

PIO Multi-drive Enable RegisterRegister Name: PIO_MDERAccess Type: Write-only This register is used to enable PIO output drivers to be configured as open drain to support external drivers on the samepin.

1 = Enables multi-drive option on the corresponding pin.

0 = No effect.

PIO Multi-drive Disable RegisterRegister Name: PIO_MDDRAccess Type: Write-only This register is used to disable the open drain configuration of the output buffer.

1 = Disables multi-drive option on the corresponding pin.

0 = No effect.

PIO Multi-drive Status RegisterRegister Name: PIO_MDSRAccess Type: Read-only This register indicates which pins are configured with open drain drivers.

1 = PIO is configured as an open drain.

0 = PIO is not configured as an open drain.

18 PIO21725A–03/01

PIO2

Pad Status RegisterFor the bit configuration of the register, see Table 2, “PIO2 Controller Memory Map,” on page 10.

PIO Pad Enable RegisterRegister Name: PIO_PADERAccess Type: Write-only

1 = No effect.

0 = Input pad buffer is enabled.

PIO Pad Disable RegisterRegister Name: PIO_PADDR

Access Type: Write-only

1 = No effect.

0 = Input pad buffer is disabled.

PIO Pad Status RegisterRegister Name: PIO_PADSR

Access Type: Read-onlyReset Value: 0

1 = Input pad buffer is disabled.

0 = Input pad buffer is enabled.

Select Status RegisterFor the bit configuration of the register, see Table 2, “PIO2 Controller Memory Map,” on page 10.

PIO Select B RegisterRegister Name: PIO_BSRAccess Type: Write-only

1 = Select peripheral B.

0 = No effect.

PIO Select A RegisterRegister Name: PIO_ASRAccess Type: Write-only

1 = Select peripheral A.

0 = No effect.

PIO AB Select RegisterRegister Name: PIO_ABSRAccess Type: Read-onlyReset Value: 0 (A selected)

1 = Peripheral B Selected.

0 = Peripheral A Selected.

191725A–03/01

A Loop Status RegisterFor the bit configuration of the register, see Table 2, “PIO2 Controller Memory Map,” on page 10.

PIO A Loop Enable RegisterRegister Name: PIO_ALERAccess Type: Write-only

1 = Enable loop.

0 = No effect.

PIO A Loop Disable RegisterRegister Name: PIO_ALDRAccess Type: Write-only

1 = Disable loop.

0 = No effect.

PIO A Loop Status RegisterRegister Name: PIO_ALSRAccess Type: Read-onlyReset Value: 0

1 = Loop enabled.

0 = Loop disabled.

B Loop Status RegisterFor the bit configuration of the register, see Table 2, “PIO2 Controller Memory Map,” on page 10.

PIO B Loop Enable RegisterRegister Name: PIO_BLERAccess Type: Write-only

1 = Enable loop.

0 = No effect.

PIO B Loop Disable RegisterRegister Name: PIO_BLDRAccess Type: Write-only

1 = Disable loop.

0 = No effect.

PIO B Loop Status RegisterRegister Name: PIO_BLSRAccess Type: Read-onlyReset Value: 0

1 = Loop enabled.

0 = Loop disabled.

20 PIO21725A–03/01

PIO2

Output Write StatusFor the bit configuration of the register, see Table 2, “PIO2 Controller Memory Map,” on page 10.

Output Write Enable RegisterRegister Name: PIO_OWERAccess Type: Read-only

1 = Enables the possibility to write directly to PIO_ODSR Register.

0 = No effect.

Output Write Disable RegisterRegister Name: PIO_OWDRAccess Type: Read-only

1 = Disables the possibility to write directly to PIO_ODSR Register.

0 = No effect.

Output Write Status RegisterRegister Name: PIO_OWSRAccess Type: Write-onlyReset Value: 0

1 = Direct write to PIO_ODSR is enabled.

0 = Direct write to PIO_ODSR is disabled.

211725A–03/01

Timing Diagrams

Figure 4. APB Signal Timing

Valid

p_stb

p_a[13:0]

p_d_in[31:0]

p_write

p_d_out[31:0]

tPD1

tSU_WRITE tHOLD_WRITE

tHOLD_DINtSU_DIN

p_stb_rising

tSU_A tHOLD_A

tPD2

22 PIO21725A–03/01

PIO2

Figure 5. PIO Signal Timing

clock

tPD_PIO_INT

pio_int

d_to_padd_to_periphoen_to_pad

tPD_D_TO_PAD

tHOLDt

SU

d_from_periphd_from_pad

tPD_D_TO_PERIPH

PD_OEN_TO_PADt

231725A–03/01

© Atmel Corporation 2001.Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warrantywhich is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errorswhich may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and doesnot make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are grantedby the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as criticalcomponents in life support devices or systems.

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