EE1411

Parameter VariationsParameter Variations

EE1412

VariationsVariations

VariationsVariations

Wafer to WaferWafer to Wafer InterInter--die die IntraIntra--diedie

EnvironmentalEnvironmental ProcessProcess

VVdddd

TemperatureTemperature

DeviceDevice

InterconnectInterconnect

EE1413

Process VariationsProcess Variations

333633141016472006

323430121012402005

273028101010352002

24332610108331999

22252510108321997

ρHWVtVddToxLeffYear

H=ILDH=ILD

WW

TT

SS

Ground planeGround plane

Source: IBM, ISSCC’00Source: IBM, ISSCC’00

% variation from mean value% variation from mean value

EE1414

Sources of Process VariationsSources of Process Variationsq Film thickness variations: Tox is critical but is relatively well

controlled. Vertical variations caused by Chemical-Mechanical Planarization (CMP); Inter-layer distances (dielectric thickness)

q Horizontal: Poly line-width & Leff variation comes from:- Mask, exposure and etch variations (photolithography)

EE1415

Statistical Description: Lumped StatisticsStatistical Description: Lumped Statistics

L0=µL is the sample mean of L, and σ2L is estimated as the

sample variance. The combined set of underlying deterministic and random contributions are lumped into a combined “random” statistical description.

It is important to remember the basis for the distribution beingdescribed, and to apply the distribution only to similar samples. For devices on one wafer, the distribution (mean and variance) for L can be different from devices within a single die.

LLL ∆+= 0

),0( 2LNL σµ ==∆

µµ=0=0

σσLL

EE1416

Separation of interSeparation of inter--die and intradie and intra--die variationsdie variations

Variation in ILD thickness across wafer Variation in ILD thickness across wafer –– across dieacross die

Sources of parametric variation are separated into: interdie and intradie variation.

Since the variation within the die - due to layout pattern dependencies – may be larger than variations across wafer, thus matching of devices is different on one chip vs. on one wafer.

P0 = nominal design value∆Pintradie = intradie variation (within a given chip)∆Pinterdie = interdie variation (from one chip to another)∆Pε = remaining “random” or unexplained variation

P indicates a structural or electrical parameters such as W, tox, device parameters, Vth, channel mobility, coupling capacitances, line resistances.

eintradieinterdie0 PPPPP ∆+∆+∆+=

EE1417

IntradieIntradie VariationVariationIt is the deviation occurring spatially within any one die. In contrast to interdie variation, intradievariation contributes to the loss of matched behavior between structures on the same chip.Two important sources for intradie variations are: (1) wafer level trends and (2) die pattern dependencies.

(1) Wafer scale variation can result in small trends that are reflected across the spatial range of the chip. For example, some deposition processes suffer from a gentle “bowl” or concentric ring pattern in thickness from the center of the wafer outwards. These can cause systematic trends across the die.

(2) Die-pattern dependencies can create variations that have become increasingly problematic in IC fabrication. Two interconnect lines that are designed identically in different regions of the die may result in lines of different width, due to photolithographic interactions, plasma etch micro-loading, ..etc. Distortion in lens and other elements of a lithographic system are also known to create systematic variations across the die.

Within any randomly selected die, wafer level variation can be approximated as a random bias function of the coordinates of the die within the wafer. Due to the small die area w.r.t. wafer, it is reasonable to assume that the wafer level variation can be modeled within the die as a linear function of position:

where ω denotes the coefficients ω0, ω x and ω y are random variables describing the plane (example: slanted plane)

yxyxWyxP yx ωωωω ++== 0intradie ),,(),(

EE1418

Supply Voltage VariationSupply Voltage Variation

Time (Time (msecmsec))

Sup

ply

volt

age

(V)

Sup

ply

volt

age

(V)

Reliability & power Reliability & power èè VVmaxmax

VVminmin èè frequencyfrequency

•• Activity changesActivity changes•• Current delivery RI and Current delivery RI and L(di/dtL(di/dt) drops, wire ) drops, wire

planningplanning•• WithinWithin--die variation die variation

S. S. BorkarBorkar, “Parameter Variations and Impact on Circuits and , “Parameter Variations and Impact on Circuits and MicroarchitectureMicroarchitecture,” DAC, pp. 338,” DAC, pp. 338--342, 2003 342, 2003

EE1419

VVdddd ProfileProfileIBM ChipIBM Chip0.130.13µµm CMOS Tech.m CMOS Tech.160K Macros160K Macros8mm X 8mm8mm X 8mmVVdddd=1.2V=1.2VPower = 48W, 20% leakagePower = 48W, 20% leakage

Variations in Variations in VVdddd = 3% to 15%= 3% to 15%Hot spots = High power density regions Hot spots = High power density regions

Hot SpotsHot Spots

H. Su et al., “Full Chip Leakage Estimation Considering Power SuH. Su et al., “Full Chip Leakage Estimation Considering Power Supply and Leakage Variations,” pply and Leakage Variations,” ISLPED, pp. 78ISLPED, pp. 78--83, 2003 83, 2003

EE14110

Temperature VariationTemperature Variation

Temp(oC)

CoreCore

CacheCache 7070ººCC

120120ººCC• Activity & ambient change• Within-die variation• Floorplan• power distributions

• Higher temperature results in slower transistors, higher interconnect resistance and exponentially higher subthreshold leakage

S. S. BorkarBorkar, “Parameter Variations and Impact on Circuits and , “Parameter Variations and Impact on Circuits and MicroarchitectureMicroarchitecture,” DAC, pp. 338,” DAC, pp. 338--342, 2003 342, 2003

EE14111

Thermal ProfileThermal ProfileIBM ChipIBM Chip0.130.13µµm CMOS Tech.m CMOS Tech.CPU Core of CPU Core of µµProcessorProcessor2.5mm X 4.7mm2.5mm X 4.7mmVVdddd=1.0V=1.0VPower = 5.6W, 20% leakagePower = 5.6W, 20% leakage

Variations in temperature = 0.8Variations in temperature = 0.8ooC to 30.3C to 30.3ooCCHot spots = High power density regionsHot spots = High power density regions

Hot SpotsHot Spots

H. Su et al., “Full Chip Leakage Estimation Considering Power SuH. Su et al., “Full Chip Leakage Estimation Considering Power Supply and Leakage Variations,” pply and Leakage Variations,” ISLPED, pp. 78ISLPED, pp. 78--83, 2003 83, 2003

EE14112

MotivationMotivationIncreasing uncertainty in Timing

– Technology-generated uncertainty

– Process variations are increasing with every new technology generation

– Coupling noise impact on timing – Power supply variations and its impact on timing– Inaccuracies in the delay calculator

Statistical timing analysis regarded as a key area in the industry and in technology roadmap (ITRS)

EE14113

Frequency & Frequency & SubthresholdSubthreshold LeakageLeakage

0.18 micron0.18 micron~1000 samples~1000 samples

20X20X30%30%

Low FreqLow FreqLow Low IsbIsb

High FreqHigh FreqMedium Medium IsbIsb

High FreqHigh FreqHigh High IsbIsb

0.90.9

1.01.0

1.11.1

1.21.2

1.31.3

1.41.4

00 55 1010 1515 2020Normalized Leakage (Normalized Leakage (IsbIsb))

Nor

mal

ized

Fre

quen

cyN

orm

aliz

ed F

requ

ency

Source: IntelSource: Intel

EE14114

~30mV~30mV

VVtt DistributionDistribution

0.18 micron~1000 samples

Low FreqLow FreqLow Low IsbIsb

High FreqHigh FreqMedium Medium IsbIsb

High FreqHigh FreqHigh High IsbIsb

002020404060608080

100100120120

--39.7139.71 --25.2725.27 --10.8310.83 3.613.61 18.0518.05 32.4932.49

∆∆VVtt(mv(mv))

# of

Chi

ps#

of C

hips

Source: IntelSource: Intel

EE14115

Leakage with Leakage with VVdddd and Temp. Variationsand Temp. VariationsLeakage considering environmental variationsLeakage considering environmental variations•• Accurate leakage model of actual Accurate leakage model of actual VVdddd and temperature profileand temperature profile

Hot SpotsHot Spots

Large leakage variations regions correspond to the Large leakage variations regions correspond to the hot spotshot spotsin the in the VVdddd and Temp. profiles and Temp. profiles

H. Su et al., “Full Chip Leakage Estimation Considering Power SuH. Su et al., “Full Chip Leakage Estimation Considering Power Supply and Leakage Variations,” pply and Leakage Variations,” ISLPED, pp. 78ISLPED, pp. 78--83, 2003 83, 2003

EE14116

Temperature DependenceTemperature Dependenceq Gate Leakage is unaffected by temperatureq Subthreshold Leakage has an super linear relationship to Temperature

- At room temperatures, gate leakage is dominant for future processes- At higher temperatures (where chips normally operate), subthreshold

leakage dominates- This situation may change in future with technology scaling (Igate scales

faster)q For a 50nm device with 1.5nm Tox

S. S. MukhopadhyayMukhopadhyay et al., “Gate Leakage reduction for scaled devices using transiet al., “Gate Leakage reduction for scaled devices using transistor stacking,” stor stacking,” IEEE Trans. VLSI Systems, pp. 716IEEE Trans. VLSI Systems, pp. 716--730, Aug. 2003.730, Aug. 2003.

EE14117

Leakage with Process VariationsLeakage with Process VariationsMonteMonte--Carlo AnalysisCarlo Analysis

NMOSNMOS-- TToxox and Length have greatest effectand Length have greatest effect-- The mean of length variations is not equal to nominalThe mean of length variations is not equal to nominal-- Larger mean and variance when all parameters are varyingLarger mean and variance when all parameters are varying

PMOSPMOS-- Much larger dependence on lengthMuch larger dependence on length

42.5 1.8 4.2%42.9 9.0 21.0%44.1 9.6 21.8%45.9 15.7 34.2%

NchToxLdrawnAll above

42.4None

Mean Leakage Standard(pA) Deviation SD/Mean

Parameter varied

26.5 1.0 3.8%27.0 6.2 23.0%32.0 22.0 68.8%33.6 27.8 82.7%

NchToxLdrawnAll above

26.4None

Mean Leakage Standard(pA) Deviation SD/Mean

Parameter varied

NMOSNMOS

PMOSPMOS

R. R. RaoRao et al., “Statistical et al., “Statistical Estimation of Leakage Current Estimation of Leakage Current Considering InterConsidering Inter-- and Intraand Intra--Die Die Process Variation,” ISLPED, pp. Process Variation,” ISLPED, pp. 8484--89, 200389, 2003

A. A. SrivastavaSrivastava et al., “Modeling et al., “Modeling and Analysis of Leakage Power and Analysis of Leakage Power Considering WithinConsidering Within--Die Process Die Process Variations,” ISLPED, pp. 64Variations,” ISLPED, pp. 64--67, 67, 20022002

EE14118

Impact on Circuits and Impact on Circuits and MicroMicro--architecturesarchitectures

EE14119

Delay PathsDelay Paths

Path DelayPath Delay

Path delay variability due to variations in Path delay variability due to variations in VVdddd, V, Vtt, and Temp, and Tempimpacts individual circuit performance and powerimpacts individual circuit performance and power

Objective: full chip performance, power, and yieldObjective: full chip performance, power, and yieldMultivariable optimization of individual circuitMultivariable optimization of individual circuit——VVdddd, , VVtt, size, size

Optimize each circuit for full chip objectives by guard-banding

Optimize each circuit for full chip objectives by guard-banding

DelayDelay

Pro

babi

lity

Pro

babi

lity

EE14120

Delay Paths: Problem of CorrelationsDelay Paths: Problem of Correlations

BB

CCAA

DD

I1I1

gate delay gate delay pdfspdfsArrival time Arrival time pdfpdf

Arrival time Arrival time pdfpdf

EE14121

Clock SkewClock Skewq Performance of high-speed

synchronous digital systems is reduced significantly by clock skew, even though the H-tree clock distribution network is used.

q When circuits run at giga-Hz, clock skew becomes a significant part of the clock period.

q Random and wafer level variation impact

q Interconnect sensitivity analysisq Statistical Interconnect Impact

B

SkewSkew

LLeffeff Variations:Variations:

•• Impact of PolyImpact of Poly--Silicon mask, lithography and etch at the chip levelSilicon mask, lithography and etch at the chip level•• Each buffer (total of 65) has a unique value of Each buffer (total of 65) has a unique value of LLeffeff

EE14122

Interconnect Sensitivity AnalysisInterconnect Sensitivity Analysisq Take derivative of delay with respect to variable of

interest

- Vt- Channel length - Gate oxide thickness- ILD thickness - Wire thickness- IR drop- Temperature gradients

EE14123

Control of Parameter VariationsControl of Parameter Variations

EE14124

Body Biasing TechniquesBody Biasing TechniquesForward Body Bias: Forward Body Bias: VVtt ModulationModulation

°

00

0.50.5

11

1.51.5

00 200200 400400 600600

Forward body bias (mV)Forward body bias (mV)

Nor

mal

ized

N

orm

aliz

ed o

pera

ting

freq

uenc

yop

erat

ing

freq

uenc

y

1.2V1.2V110110°CC

450mV450mV

250250

500500

750750

10001000

12501250

15001500

17501750

20002000

0.90.9 1.11.1 1.31.3 1.51.5 1.71.7

VVdddd (V)(V)FF m

axm

ax(M

Hz)

(MH

z)

Body bias chipBody bias chipwith 450 mV FBBwith 450 mV FBB

NBB chipNBB chip& body bias& body biaschip withchip withZBBZBB

S. S. NarendraNarendra et al., “1.1V 1GHz Communications Router with Onet al., “1.1V 1GHz Communications Router with On--Chip Body Bias in 150nm CMOS,” ISSCCChip Body Bias in 150nm CMOS,” ISSCCpp.270pp.270--271, 2002271, 2002

Intel’s 6.6M transistors communications router chipIntel’s 6.6M transistors communications router chip

EE14125

Body Biasing Techniques Body Biasing Techniques Reverse Body Bias: Leakage ReductionReverse Body Bias: Leakage Reduction

11

1010

100100

0.010.01 0.10.1 11 1010 100100 10001000

Target Target IIoffoff ((nAnA/mm)/mm)

110C110C0.5V RBB0.5V RBB

Lower Lower VVttHigher Higher VVtt

IntrinsicIntrinsicLeakageLeakageReductionReductionFactor (X)Factor (X)

Shorter LShorter L

RBB reduces subthreshold leakageLess effective with: shorter L, lower Vt, & scaling

RBB reduces RBB reduces subthresholdsubthreshold leakageleakageLess effective with: shorter L, lower Less effective with: shorter L, lower VVtt, & scaling, & scaling

1E1E--0909

1E1E--0808

1E1E--0707

1E1E--0606

1E1E--0505

00 0.50.5 11 1.51.5

Reverse VReverse VBSBS (V)(V)

II leak

gele

akge

(A)

(A)

150nm, 27150nm, 27ooCC

LLworstworst--casecase

LLnominalnominal

A. A. KeshavarziKeshavarzi et al., “Effectiveness of Reverse Body Bias for Leakage Controlet al., “Effectiveness of Reverse Body Bias for Leakage Control in Scaled Dual in Scaled Dual VtVtCMOS ICs,” ISLPED, pp.207CMOS ICs,” ISLPED, pp.207--210, 2001210, 2001

EE14126

Body Biasing Techniques Body Biasing Techniques Adaptive Body BiasAdaptive Body Bias

0%0%

20%20%

60%60%

100%100%

Acc

epte

d di

eA

ccep

ted

die

NBBNBB

100% yield100% yield

ABB

Higher FrequencyHigher Frequency à

97% highest bin97% highest bin

within die ABB

50% of dies with NBB fell, but are 50% of dies with NBB fell, but are recovered using ABBrecovered using ABBFor given Freq and Power densityFor given Freq and Power density•• 100% yield with ABB 100% yield with ABB •• 97% highest freq bin with ABB for 97% highest freq bin with ABB for

within die variability, compared to within die variability, compared to 30% for ABB 30% for ABB

ff ff

Num

ber

of d

ies

Num

ber

of d

ies

FrequencyFrequency

too too slow slow

fftargettarget

too too leakyleaky

fftargettarget

ABBABB

FBBFBB RBBRBB

J. J. TschanzTschanz et al., “Adaptive Body Bias for Reducing Impacts of Dieet al., “Adaptive Body Bias for Reducing Impacts of Die--toto--Die and WithinDie and Within--Die Parameter Die Parameter Variations on Microprocessor Frequency and Leakage,” ISSCC, pp.4Variations on Microprocessor Frequency and Leakage,” ISSCC, pp.42222--423, 2002423, 2002

EE14127

Supply Voltage ControlSupply Voltage Control

0%0%

20%20%

60%60%

100%100%

Num

ber

of d

ies

Num

ber

of d

ies

Fixed Fixed VVdddd

Adaptive Adaptive VVdddd

Bin1 Bin2 Bin3Bin1 Bin2 Bin3

Bin improvement by adaptive Vdd20% of dies are pushed from Bin1 to Bin2 +

recovered dies that fell below Bin 1

37%37%

15%15%

52%52%

74%74%

6%6% 10%10%

Higher FrequencyHigher Frequency à

S. S. BorkarBorkar et al., “Parameter Variations and Impact on Circuits and et al., “Parameter Variations and Impact on Circuits and MicroarchitecturesMicroarchitectures,” DAC, pp. ,” DAC, pp. 338338--342, 2003.342, 2003.

EE14128

Supply Voltage Control Supply Voltage Control VVdddd Variation ReductionVariation Reduction

On die decoupling capacitors reduce On die decoupling capacitors reduce ?? VVdddd•• Cost area, and gate oxide leakage concernsCost area, and gate oxide leakage concerns

With Die Caps

Without Die Caps

With Die Caps

Without Die Caps

T. T. RahalRahal--ArabiArabi et al., “Design and Validation of the Pentium III and Pentium 4et al., “Design and Validation of the Pentium III and Pentium 4 Processors Power Processors Power Delivery,” VLSI Delivery,” VLSI SympSymp. Circuits, pp. 220. Circuits, pp. 220--223, 2002223, 2002

EE14129

Temperature ControlTemperature Control

Tem

pera

ture

Tem

pera

ture

Time (Time (µµsec)sec)

ThrottleThrottle

TTmaxmax: frequency & power: frequency & powerWhen temperature exceeds When temperature exceeds the thresholdthe threshold

1.1. Lower frequency Lower frequency (activity)(activity)

2.2. Lower Lower VVdddd

This leads to a power consumption drop This leads to a power consumption drop followed by a drop in onfollowed by a drop in on--die temperaturedie temperature

S. S. BorkarBorkar et al., “Parameter Variations and Impact on Circuits and et al., “Parameter Variations and Impact on Circuits and MicroarchitecturesMicroarchitectures,” DAC, pp. ,” DAC, pp. 338338--342, 2003.342, 2003.