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slide 1 of 59University of Toronto© D.A. Johns, 1997
Partial Response andViterbi Detection
Prof. David JohnsUniversity of Toronto
([email protected])(www.eecg.toronto.edu/~johns)
slide 2 of 59University of Toronto© D.A. Johns, 1997
Partial-Response MotivationDisadvantage — Feed-Forward Equalizer
• An FFE boosts the noise in areas where received sig-nal power is low
• Example:
• Noise is boosted at high frequencies.
FFEHtc z( )
input data
output dataH1 z( )
Ak 1±=Ak 1±=
f
Htc H1×
Nyquist Pulsef
H1
f
Htc
slide 3 of 59University of Toronto© D.A. Johns, 1997
Partial-Response MotivationDisadvantage — Decision Feedback Equalizer
• A DFE does not make use of all the impulse response.
• Since , impulse response is • If single input, better to look for than
• Postcursor ISI may have significant signal power.
Htc z( )qk
input data
output data
H2 z( )
Htc z( ) 1 0.9z 1– 0.1z 2–+ +=
Ak 1±=Ak 1±=
H2 z( ) 0.9z 1– 0.1z 2–+=
–DFE
Ak Ak= δ k( )
1 0.9 0.1 0 0, , , ,1 0 0 0 0 0, , , , ,
slide 4 of 59University of Toronto© D.A. Johns, 1997
Partial-Response Motivation
• Rather than equalizing to a Nyquist pulse, equalize toa partial-response signal
• Equalize to in DFE example• Less noise boost• More of the impulse response used to determine
transmitted signal• Need to look at a string of received symbols rather
than symbol-by-symbol detection — MLSD
• Disadvantage — extra complexity and may notrecover full dynamic range loss
1 z 1–+
slide 5 of 59University of Toronto© D.A. Johns, 1997
Nyquist Criterion for Zero ISI
• Nyquist’s First Criterion for zero ISI
Transmitter Channel Σ Receiver DetectorkT
Data
in
Data
out
Noise
h t( )Impulse response
Filter Filter
h kT( )1 k 0=
0 k 0≠
=
H ω 2πnT
----------–
n∑ T=
slide 6 of 59University of Toronto© D.A. Johns, 1997
Minimum Bandwidth System with Zero ISI
• A brickwall low-pass spectrum with a cutoff frequency of (“sinc” impulse response)
• However — impulse response decays at a rate of due to the frequency discontinuity in .
• Excessive ISI if any timing perturbation occurs
H ω( ) T0
ω π T⁄≤elsewhere
=
1 2T( )⁄
H f( )
f12T------1
2T------– 0 0 T 2TT–
h t( )
t
1 t⁄H f( )
slide 7 of 59University of Toronto© D.A. Johns, 1997
Non-Minimum Bandwidth System
• One way to overcome jitter problem is to use more than the minimum bandwidth.
• A popular class of non-minimum bandwidth solutions are — Cosine Roll-Off Filters
• Can still transmit and receive only one of two sym-bols.
• But are minimum bandwidth systems practical? Yes. — use partial-response signaling.
slide 8 of 59University of Toronto© D.A. Johns, 1997
Partial-Response Signaling
• By relaxing the zero-ISI criterion of Nyquist, the maximum symbol rate of 2 symbols/hertz can be achieved.
• Allow a controlled amount of ISI by digitally FIR fil-tering the data — results in more signal levels.
• Three popular FIR filters:duobinary - class 1 zero at dicode zero at dcmodified duobinary - class 4 zeros at dc, (also called PR4 or PRIV)
1 z 1–+ fs 2⁄
1 z 1––1 z 2–– fs 2⁄
slide 9 of 59University of Toronto© D.A. Johns, 1997
Duobinary (1+z-1)
• Impulse response decays at a rate of since is continuous but its first derivative is not.
• However, it transmits signal power at dc.
z 1–
Equalized Channel Response
received signal
1 z 1–+
0 1 2, ,
0 1,
H f( )
f1
2T------1
2T------– 0 0 T 2TT–
h t( )
t
1 t2⁄ H f( )
slide 10 of 59University of Toronto© D.A. Johns, 1997
Dicode (1-z-1)
• Impulse response decays at a rate of due to the frequency discontinuity in .
• However, it does not transmit any signal power at dc.
z 1–
Equalized Channel Response
1± 0,received signal
–
1 z 1––
0 1,
H f( )
f1
2T------1
2T------– 0
0
T
2TT–
h t( )
t
1 t⁄H f( )
slide 11 of 59University of Toronto© D.A. Johns, 1997
Modified Duobinary (1-z-2) — class 4
• decays at a rate of since is continuous. • It does not transmit signal power at either dc or .
z 2–
Equalized Channel Response
1± 0,received signal
–
1 z 2–– 1 z 1––( ) 1 z 1–+( )=
0 1,
H f( )
f1
2T------1
2T------– 0
0 T 2TT–
h t( )
t
h t( ) 1 t2⁄ H f( )fs 2⁄
slide 12 of 59University of Toronto© D.A. Johns, 1997
Class-4 Partial Response Signaling Scheme • Spectral nulls at DC and
• Can be encoded/decoded by two interleaved dicode encoder/decoder each operating at half the rate.
• Thus, we need only decode a dicode and use two interleaved identical blocks to decode PRIV.
• If binary inputs, 3 level output — BPR4 or BPRIV • (If 4 level inputs, 9 level output — QPR4 or QPRIV)
fs 2⁄
Encoder/Decoder (fs/2)
Encoder/Decoder (fs/2)fs fs
1 z 1––
1 z 1––
slide 13 of 59University of Toronto© D.A. Johns, 1997
Magnetic Recording Similarities• At low densities, a magnetic read signal is inherently
1-D encoded (i.e. a dicode).
• At higher densities, high-frequency roll-off important(modelled as a Lorentzian pulse).
• If equalized to a 1-D channel, high-frequency noise isamplified.
• Find a good approximation to channel so that theboost required by equalizer is kept small.
0 1 0 0 1 0 1 1 0
+1 -1 0 +1 -1 +1 0 -1
slide 14 of 59University of Toronto© D.A. Johns, 1997
Magnetic Recording Similarities • Magnetic recording channel often modelled as
Lorentzian pulse
0 0.5 1 1.5 2 2.5 3 3.50
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
w
|H(w
)|Frequency Response of a Lorentzian Magnetic Read Channel
t/T=0
t/T=1
t/T=1.5
t/T=2
slide 15 of 59University of Toronto© D.A. Johns, 1997
Magnetic Recording Similarities • Similar to partial-response channel.1 z 1––( ) 1 z 1–+( )
n
0 0.5 1 1.5 2 2.5 3 3.50
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
w
|H(w
)|
Frequency Response of (1-D)(1+D) PRS Schemen
n=0
n=1
n=2
n=5
(dicode)
(PR4)
(EPR4)
slide 16 of 59University of Toronto© D.A. Johns, 1997
SNR Degradation for Dicode • Now 3 levels being sent rather than just two.
• Thus, a bit-by-bit detection results in SNR perfor-mance degradation (about 2-3 dB loss).
• However, the 3 levels have some redundancy included.
• SNR performance can be recovered in detection by employing Maximum-Likelihood Sequence Estimation (MLSE) detection schemes
• The Viterbi Algorithm is an efficient way of realizing MLSE detection
Uncoded binary signal “1-D” encoded ternary signal
∆
-11
slide 17 of 59University of Toronto© D.A. Johns, 1997
Trellis Introduction
state
Input
Outputz 1–0 1,
1± 0,–
0
1
0/0
1/0
1/+1 0/-1
State Diagram Trellis Diagram
0/0
1/0
1/+1
0/-1
0
1
time
state
k-1 k k+10/0
1/0
1/+1
0/-1
slide 18 of 59University of Toronto© D.A. Johns, 1997
Trellis Representation of Dicode (1-z-1)
• A trellis can be used to describe an encoder. • Example:
state
0/0
1/0
1/+1
0/-1
Encoder+1 0 -1 +1 -1 01 1 0 1 0 00
0
1
time
state
k-1 kData
Encoded Data
Trellis
Data Encoded Data
z 1–0 1,
1± 0,–
slide 19 of 59University of Toronto© D.A. Johns, 1997
Transmit Trellis for Dicode (1-z-1)
• Note that following a ‘+1’ output, there can be an arbitrary number of zeros followed by a ‘-1’.
• In other words, if two ‘+1’ symbols are detected with no ‘-1’ between them, an error occurred in transmis-sion.
• Similar for a ‘-1’ output.
0/0
1/0
1/+1
0/-1
0
1
k-1 k
slide 20 of 59University of Toronto© D.A. Johns, 1997
Conventional Bit-by-Bit Detection
• Note the error in bit 3 received.
• Error can be detected since a “-1” must be next non-zero symbol after a “+1”.
• Did the error most likely occur in symbol 2, 3 or 4? •
0.8 0.3 -0.4 0.9 -0.8 -0.1Channel y
y+1 0 0 +1 -1 0
Data1 1 0 1 0 0
Encoded Data+1 0 -1 +1 -1 0 Encoded Data Received
thresholds at 0.5±
noise corrupted received signals
slide 21 of 59University of Toronto© D.A. Johns, 1997
Viterbi Algorithm (VA) • VA is an iterative method for determining the most
likely sequence sent — maximum likelihood detector.
• Accomplished by creating a receive trellis having branch metrics proportional to the difference squared between received signal and each ideal sym-bol value.
• The most likely sequence is the shortest path through the receive trellis.
• State metrics and path memory also stored to reduce search time through trellis — they are the length of shortest path and path taken at each node.
slide 22 of 59University of Toronto© D.A. Johns, 1997
Viterbi Algorithm Example
Channel
Encoded Data
0.00
0.64 0.09 0.16 0.81 0.64
0.09 0.16 0.81 0.64
0.490.04 1.96 0.01 3.24
1.69 0.36 3.61 0.04
0.64
0.04
0.73
0.13
0.49
0.29
1.3
0.50
0.54
1.14
+1 0 -1 +1 -1 0
0.8 0.3 -0.4 0.9 -0.8 -0.1
0.01
0.01
1.21
0.89
0.55
1.15
0 +1 0 -1 +1 -1 0
Data1 1 0 1 0 0
1 1 0 1 0 0DataReceived
Encoded Data Received
0/0
1/0
1/+1
0/-1
large noise
0.00 0.64
3.24
slide 23 of 59University of Toronto© D.A. Johns, 1997
Viterbi Algorithm Example0.00 0.64
0.04
0.64
0.04
0.00 0.64
3.24
0.00 0.64 0.09
0.09
0.490.04
1.69
0.73
0.13
0.00 0.64
3.24
0
0
0
0
0
1
0.00 0.64 0.09 0.16
0.09 0.16
0.490.04 1.96
1.69 0.36
0.49
0.29
large noise
0.00 0.64
3.24
1
1
0
0
0
1
0.64
0.04
0.73
0.13
0.00 0.64 0.09 0.16 0.81
0.09 0.16 0.81
0.490.04 1.96 0.01
1.69 0.36 3.61
1.3
0.50
large noise
0.00 0.64
3.24
1
1
0
0
0
1
0
0
0.49
0.29
Timestep 1
Timestep 2
Timestep 3
Timestep 4
slide 24 of 59University of Toronto© D.A. Johns, 1997
Detailed Received Trellis Description (BPR4) • Transmitted signal — one of three values, • Received signal — .
• Equations:
a± 0,
yk
m0k 1–
m1k 1–
yk a+( )2
yk 0–( )2
yk 0–( )2
yk a–( )2
m0k
m1k
state metrics
state metrics
branch metrics
m0k min m0k 1– yk2+( ) , m1k 1– yk a+( )2+( ) =
m1k min m1k 1– yk2+( ) , m0k 1– yk a–( )2+( ) =
slide 25 of 59University of Toronto© D.A. Johns, 1997
Simplifications to Remove Multiplications • Remove terms since it occurs in both terms and
we are only interested in finding the minimum path (don’t need the absolute length of the path).
• State-metrics can now be either positive or negative.
yk2
m0k 1–
m1k 1–
2ayk a2+( ) 2ayk– a2+( )
m0k
m1k
m0k 1–
m1k 1–
0
0
m0k
m1k
yk2–
yk a+( )2
yk 0–( )2
yk 0–( )2
yk a–( )2
slide 26 of 59University of Toronto© D.A. Johns, 1997
Simplifications to Remove Multiplications • Divide all branches by (assume )
• Simply scales state metrics.
• Equations:
2a a 0>
m0k 1–
m1k 1–
2ayk a2+( )
0
0
2ayk– a2+( )
m0k
m1k
m0k 1–
m1k 1–
yka2---+
0
0
yk– a2---+
m0k
m1k
2a÷
m0k min m0k 1– , m1k 1– yk a++( ) =m1k min m1k 1– , m0k 1– yk– a+( ) =
slide 27 of 59University of Toronto© D.A. Johns, 1997
Difference Metric Algorithm• [Wood and Peterson, Trans. on Comm., May 1986]
• We are not interested in absolute state-metric values— only which state-metric is smaller.
• Store only the difference in the state-metrics,
• We shall see that while absolute state-metric valuesincrease in time, their difference does not.
• This “difference metric algorithm” results in less com-plex realizations for both digital and analog realiza-tions in cases where there are only two state-metrics.
∆mk
∆mk m0k m1k–≡
slide 28 of 59University of Toronto© D.A. Johns, 1997
Difference Metric Algorithm • Subtract off from input state-metrics and add it
into each branch metric instead.
• Now, can be subtracted off branch metrics since it is the same in all branches.
m1k 1–
m1k 1–
m0k 1–
m1k 1–
yka2---+
0
0
yk– a2---+
m0k
m1k
∆mk 1–
0
yka2---+
0
0
yk– a2---+
m0k
m1k
eliminatingm1k 1–
slide 29 of 59University of Toronto© D.A. Johns, 1997
Difference Metric Algorithm • Different path choices.
∆mk 1–
0
yka2---+
0
0
yk– a2---+
m0k
m1k
Condition
Result
∆mk 1– yka2---+<
and ∆mk 1– yka2---–<
∆mk yka2---–=
∆mk 1–
0
yka2---+
0
0
yk– a2---+
m0k
m1k
Condition
Result
∆mk 1– yka2---+>
and ∆mk 1– yka2---–>
∆mk yka2---+=
slide 30 of 59University of Toronto© D.A. Johns, 1997
Difference Metric Algorithm • Different path choices.
∆mk 1–
0
yka2---+
0
0
yk– a2---+
m0k
m1k
Condition
Result
∆mk 1– yka2---+<
and ∆mk 1– yka2---–>
∆mk ∆mk 1–=
∆mk 1–
0
yka2---+
0
0
yk– a2---+
m0k
m1k
Condition
Result
∆mk 1– yka2---+>
and ∆mk 1– yka2---–<
IMPOSSIBLE
do nothing
slide 31 of 59University of Toronto© D.A. Johns, 1997
Difference Metric Algorithm
• Equations:
• These equations describe an adjustable threshold device.
• Used in digital PR4 implementations.
• They are also simple to implement in analog.
∆mk
yka2--- ∆mk 1– yk
a2---+>+
∆mk 1– yka2---– ∆mk 1– yk
a2---+< <
yka2--- ∆mk 1– yk
a2---–<–
=
slide 32 of 59University of Toronto© D.A. Johns, 1997
Typical Digital Implementation
• 6-bit flash A/D requires 63 comparators + decoding logic.
• A/D converter might consume around 300mW (ormore)
• FIR equalizer might be 1mW/MHz/tap— 8-tap at 100MHz = 800mW
6-bitA/D
digitalequalizer
digitaldifferencealgorithm
evenoutput
digitalpath
memory
digitaldifferencealgorithm
digitalpath
memory
oddoutput
fromchannel
evensamples
oddsamples
fs fs/2
slide 33 of 59University of Toronto© D.A. Johns, 1997
Typical Digital Implementation
• Digital equalizer requires multi-bit multiplies in feed-forward equalizer (power hungry)
• If decision feedback is used, it will need to use early estimates of output (cannot wait for MLSE to finish).
• Digital difference algorithm requires some minor adders and digital comparators.
• Digital path memory logic consists of about 16 serial/parallel shift registers.
slide 34 of 59University of Toronto© D.A. Johns, 1997
Typical Analog Implementation
• Analog equalizer needed (less power than digital butmore challenging)
• Digital path memory is the same as in fully digital realization.
analogequalizer
fromchannel
analogdifferencealgorithm
evenoutput
digitalpath
memory
analogdifferencealgorithm
digitalpath
memory
oddoutput
evensamples
oddsamples
fs/2
slide 35 of 59University of Toronto© D.A. Johns, 1997
Typical Analog Implementation
• Analog difference algorithm is very small (about thesize of 2 comparators)
• Thus, power is saved and speed can be increasedover 6-bit A/D converter.
• Note that dynamic range in analog parts need only bearound 6 bits (i.e. 40dB)
slide 36 of 59University of Toronto© D.A. Johns, 1997
Analog Implementation
• Path memory consists of two serial/parallel in/out shift registers.
S/HDC
level
shifterS/H
+
-
+
-
S
S
R
R
Q
Q
CLK
to path
yk-a/2
yk+a/2
y(t)memory
Mux ∆mk-1∆mk-10
+a/2
-a/2
∆mk-1+a/2
∆mk-1-a/2
Threshold Device Viterbi Detector
...0
1 ...
State “0”
State “1”
slide 37 of 59University of Toronto© D.A. Johns, 1997
Some Practical Limitations
• In a digital implementation, performance is degraded by limiting the number of bits used in A/D conversion
• Typically use about 6-bit A/D converters (easily achievable in an all analog implementation).
• Truncating the trace-back length (path memory) also degrades the performance.
• Typically use length of 16 for little loss in perfor-mance.
slide 38 of 59University of Toronto© D.A. Johns, 1997
Why an Analog Implementation? • Avoids using a pre-stage A/D converter. • Combines the A/D and VA into one stage with a com-
plexity near to a 2-bit A/D (Special-purpose A/D con-verter).
• Consumes less power. • Operates faster. • 6-bit accuracy is enough (Moderate Precision Cir-
cuitry). • Low-dynamic range requirement (Low-Voltage Oper-
ation). • The difference algorithm updates only one sampled
data without using previous samples (no accumula-tive analog errors)
slide 39 of 59University of Toronto© D.A. Johns, 1997
Simulation and Experimental Results
• Simulation and experimental (discrete prototype) results confirm validity of the analog approach and its robustness against imperfections.
0 5 10 1510
-6
10-5
10-4
10-3
10-2
10-1
100
Signal to Noise Ratio, SNR
Bit
Err
or R
ate,
BE
R
Viterbi Bound--- Threshold Device+ 10%x 5%o 2%
0 5 10 1510
-6
10-5
10-4
10-3
10-2
10-1
100
Signal to Noise Ratio, SNR
Bit
Err
or R
ate,
BE
R
Viterbi Bound--- Threshold Device+ 10%x 5%o 2%
DC Offset or Absolute Gain Error Gain Mismatch
Offsets and mismatches are described in percentage of a
0 5 10 1510
-6
10-5
10-4
10-3
10-2
10-1
100
Signal to Noise Ratio, SNR
Bit
Err
or R
ate,
BE
R
Viterbi Bound--- Threshold Deviceo Measurment
Measured BER Performance of the Detector (Path Memory = 17)
slide 40 of 59University of Toronto© D.A. Johns, 1997
Input-Interleaved Algorithm
• The implementation above updates ∆mk once thecomparator outputs are known.
• Thus, critical speed path is 2 sample-and-holds.(Sample input and compare, then, perhaps, update∆mk with another sample-and-hold).
• The input-interleaved algorithm reduces the criticalspeed path to a single sample-and-hold (i.e. canoperate at twice the speed).
• It uses two sample-and-holds at the input andswitches which one the input goes to if ∆mk needs tobe updated.
slide 41 of 59University of Toronto© D.A. Johns, 1997
Input Interleaved Algorithm
• According to the update mechanism, ∆mk-1 is a DC-shifted version of a previously-sampled input signal
• We can use the previously held input signal plusappropriate sign of DC shift for ∆mk.
• When ∆mk needs to be updated, switch input on toother sample-and-hold capacitor and use the justsampled input and a sign-bit for new ∆mk
∆mk 1– yk j– 0.5±=
slide 42 of 59University of Toronto© D.A. Johns, 1997
Input-Interleaved Algorithm• Toggle between two S/Hs which store yk and yk-j• Use a flip-flop to properly switch the DC signal
• Speed improvement, as no additional S/H is required(yk-j has already been stored)
T
T
S
S
TF-F
SRF-F
+
-
+
-
PolaritySwitch
PolaritySwitch
PolaritySwitch
Vref
Σ
y(t)
φ1.T
φ1.T
To the PathMemory
S
S
T and T
yk-yk-j-Vref0
yk-yk-j+Vref
0
+
- -
+
-+
Σ
slide 43 of 59University of Toronto© D.A. Johns, 1997
BiCMOS Integrated-Circuit Implementation
Switch V/I
V/I V/I
V/I V/I
Latch
Latch
+
-
+
-
-
+
+
-
+
-
-
+
+
-
+
-
+
-
+
-
-
+
Bias
Bias
+ -- +
+ -- +
+ -- +
+ -- +
+
-
+
-L
L+ L-
φ2 φ3
φ1.T
DL
φ1.T
+
-
+
-
L+ L-
L DL
φ3φ2
φ1.T φ1.T
+
-VDC
+
-y(t)
φ1.T
φ1.T
SW
SW
SW
SW
S
S
SW
SW
T
T
A1
B1
B1
A1
A0
B0
B0
A0
Switch Switch
T
SS
A0A1
A0A1
φ1
φ1.T φ1.TT T
slide 44 of 59University of Toronto© D.A. Johns, 1997
BiCMOS Integrated-Circuit Implementation
out- out+
in+ in-
bias1
bias2
bias3
in+ in-
SW SW
out- out- out+
bias3
in+
in-
LL+
DLL-
out-out+
Switch
V/I
Latch
out+
slide 45 of 59University of Toronto© D.A. Johns, 1997
BiCMOS Integrated-Circuit Implementation• Path memory consists of 2x12 multiplexed-input D
flip-flops
• Clock phases
...“0”
“1” ...
State “0”
State “1”
D
D
D
D
D
D
φ4
φ5
B1/B0 B1/B0
A1/A0A1/A0
in0/in1
in1/in0
out0/out1
CLK
φ1 φ2 φ3 φ4 φ5
slide 46 of 59University of Toronto© D.A. Johns, 1997
BiCMOS Integrated-Circuit Implementation• Compared to other analog implementations
[Matthews and Spencer, JSSC, Dec. 93]
• Less complex (Individual state metrics are not calculated)
• Less prone to imperfections (Feedback signals are only digital)
• Fully differential• Faster (Master-slave S/Hs are not used)
[Yamasaki, ISSCC, 1994]
• No details given
slide 47 of 59University of Toronto© D.A. Johns, 1997
Integrated-Circuit Implementation
Analog
Digital
ControlLogic
SecondDicode
0.1mm
slide 48 of 59University of Toronto© D.A. Johns, 1997
Experimental Results
• Process: 0.8 µm BiCMOS• Area (dicode): ~0.25 mm2
• Analog: ~0.06 mm2
• Digital: ~0.1 mm2
• Bypass capacitors, ...• Power consumption (dicode):
• 3.3V power supply• ~12mW at 50MHz• ~15mW at 100MHz
slide 49 of 59University of Toronto© D.A. Johns, 1997
Experimental Results• Setup
• Measured Bit-Error-Rate (BER) performance
CLK
PseudoRandom
GeneratorEncoder
WhiteNoise
Generator
Σ ChipUnderTest
PhaseAdjust
LevelTranslatorCompare
ErrorCounter
Delay
Σ
4 6 8 10 12 14 16 1810
−8
10−7
10−6
10−5
10−4
10−3
10−2
10−1
100
Signal−to−Noise Ratio (SNR), dB
Bit−
Err
or R
ate
(BE
R)
o Measured at 50MHz/Dicodex Measured at 100MHz/Dicode
Threshold Device
slide 50 of 59University of Toronto© D.A. Johns, 1997
A General Implementation Approach
• Analog implementations are useful if the precedingsignal processing is simple
• Magnetic recording• Data transmission over unshielded cables
• Simplifications are only possible in some specialcases (i.e. PR4)
• This general approach can be used in• More general PRS schemes (i.e. EPR4, EEPR4)• Convolutional codes• Multi-level digital communication• Irregular trellises
slide 51 of 59University of Toronto© D.A. Johns, 1997
A General Implementation Approach• This approach takes full advantage of the ability of
simple analog circuits in realizing the ACS function
• Branch metrics, eij, are usually expressed in terms oflinear combinations of the received samples and DCsignals
mi k( ) Maxj
mj k 1–( ) eji k( )– i 1 2 … N, , ,=j 1 2 … M, , ,=
=
... mi(k)
m1(k-1)
m2(k-1)
mM(k-1)
e1ie2i
eMi
slide 52 of 59University of Toronto© D.A. Johns, 1997
Circuit Realization
• A generalized differential cell is employed to realizethe ACS function
• Using degenerated differential pairs in V/I conversionsmakes the linear combinations simple to realize
. . .. . .+-
+-
+-
m1(k-1) m2(k-1) mM(k-1)
mi(k)
e1i e2i eMi
αe1i αe2i αeMi
. . .
m1(k-1) m2(k-1) mM(k-1)
R R RVin1 VinMVin2
Vout Maxj
Vin j vBE–= mi k( ) Maxj
mj k 1–( ) eji k( )– vBE–= mi k( ) Maxj
mj k 1–( ) αReji k( )– –=
mi(k)Vout
slide 53 of 59University of Toronto© D.A. Johns, 1997
• Optional DC currents added to the error signalsreduce the unnecessary DC voltage drops across theresistors
slide 54 of 59University of Toronto© D.A. Johns, 1997
Circuit Realization• Branch currents in the differential cells are compari-
son results• To achieve high speeds, ping-pong S/Hs are preferred
to master-slave S/Hs in feeding the state metrics back
• Algorithmic growth of state metrics is overcome by afast Common-Mode FeedBack (CMFB) circuit
• Fast CMFB minimizes the signal swings of the statemetrics — this approach is usually not practical in dig-ital realizations
Master-Slave S/H Ping-Pong S/H
slide 55 of 59University of Toronto© D.A. Johns, 1997
Design Example: Binary Dicode
bias1
bias2
bias3
bias1
bias2
bias3
refφ1
φ2
φ1
φ2
φ1
φ2
φ1
φ2
- 0.5 + +0.5 -+ y(t) -
bias3
slide 56 of 59University of Toronto© D.A. Johns, 1997
Integrated Circuit Implementation
• A chip containing Viterbi decoders for a binary dicodeand an Extended PR4 (EPR4, (1-D)(1+D)2) has beenfabricated in a 0.8µm BiCMOS process
• Based on simulations, fast speed (>100 MHz) can beachieved with ~15mW/state (Excluding path memory)
• The area is ~0.03mm2/state (Excluding path memory)• In a CMOS implementation, lower gm causes some
degradation in:• Obtaining simple low-impedance nodes• ACS performance due to the high dependency of
vGS to the drain current
slide 57 of 59University of Toronto© D.A. Johns, 1997
Integrated Circuit Implementation
0.1mm
Dicode
DicodeTest
EPR4
ClockGenerator
50 ΩDrivers
50 ΩDriversClock
Generator
slide 58 of 59University of Toronto© D.A. Johns, 1997
Preliminary Experimental Results
• Results on dicode
• High-frequency tests have been conducted up to 80MHz (Off-chip path memory)
8 9 10 11 12 13 1410
−6
10−5
10−4
10−3
10−2
10−1
Signal−to−Noise Ratio (SNR), dB
Bit−
Err
or R
ate
(BE
R)
o Measured at 1 MHz__ Viterbi Bound
slide 59 of 59University of Toronto© D.A. Johns, 1997
Summary• The use of partial-response signals allows one to
send closer to the maximum rate of 2 symbols/hertz.
• Making use of partial-response signalling reduces the need for large equalization boost.
• The difference algorithm is efficient for PR4 signals• Analog realizations of the difference algorithm save
silicon and power over digital realizations (however, an analog equalizer is needed)
• Input-interleaved algorithm increases the speed for an analog implementation
• A general analog Viterbi approach was discussed. (However, it makes use of bipolar transistors).