Sherry Xiaoxia Wu*, Ravi Varadarajan†, Navneet Mohindru†, Durodami Lisk*, Riko Radojcic*

*Qualcomm Inc.†Atrenta Inc.

PathFinding Methodology for Interposer and 3D Die StackingPathFinding Methodology for Interposer and 3D Die Stacking

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OutlineOutline

Motivation of PathFinding Methodology

PathFinding Methodology Flow

Demonstrations using an Example

Conclusion

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Typical 3D Design OptionsTypical 3D Design Options

Courtesy: Si2

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Motivation of PathFinding MethodologyMotivation of PathFinding Methodology

Navigating many choices …. Cost, power, performance…

Co-optimize process & design

Need a structured design exploration methodology Past experience not applicable

to disruptive technologies Not tie to legacy design Quick and flexible High fidelity/low accuracy

AssemblyChoices

AssemblyChoices

FillChoices

FillChoices

PackageChoices

PackageChoices

PackageChoices

PD Choices

PD ChoicesTech

Choices

???Form Factor, Yield, Power, Performance

ConceptArchitecture

ConceptTechnology

u-ArchChoicesu-Arch

Choicesu-Arch

Choices

PartitioningChoices

PartitioningChoices

PartitioningChoices

TSVChoicesTSV

Choices

OrientationChoices

OrientationChoices

AssemblyChoices

FillChoices

TSVChoices

OrientationChoices

Need methodology to make the selections PathFinding

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PathFinding MethodologyPathFinding Methodology

Many more challenges in 3D:

- IP/tier assignment

- Intra/inter die floorplan

- Power & thermal

- Timing across dies

- TSV & stack configuration

- TSV/bump alignment

Design ArchitectureRTL, Blackbox, Netlist,

Top level SDC/DEF/IO Constr,

Interfaces, Tier/die config.

Early Design

Planning

Physical Units Handoff 1

Logical, Physical, Timing

BackendImplementation 1

Tier/Die 1

…

…

Physical Units Handoff N

Logical, Physical, Timing

BackendImplementation N

Tier/Die N

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PathFinding MethodologyPathFinding MethodologyCreate logical partitions for each die

Are interconnectivity and TSV reports for all dies

acceptable?

3D stack XML file

N

Commit logical partitions in to 3D physical partitions

Y

Y

Physical prototyping on each die partition

Modify partitions

N

Modify TSV cluster/locations

Backside RDL/ Interposer routing

N

Modify number of RDL layers/bump locations

Are all diesphysically feasible?

Is BacksideRDL routing/Interposer

feasible?

1. Handoff 3D stack XML file with partitions2. Handoff DEF file for every partition

Y

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3D Format - XML 3D Format - XML

Two Dies on a Passive Interposer

Two Stacked Dies

XML: Ongoing Standardization Interposer and 3D die stacking

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Logic PartitionLogic Partition

Block in bottom die

Block in top dieTSV

Bottom die front-side

net

Bottom die backside

net

Bottom die backside ubump

Top die frontside ubump

Top die frontside

net

Dummy

net

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Floorplan Constraints and An Example Floorplan Constraints and An Example

TSV/ubmp size, XML

Create/mark TSV/ubump clusters

Assign TSVs/ubump to clusters

Set cluster utilization/aspect ratio

FP constraints: guide/region

Floorplan constraints Blackbox locations Die utilization: block area/die area Number of TSV clusters: 2, 4, 8 TSV size/pitch/location ubump size/pitch/location

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Floorplan Options for a LoL CaseFloorplan Options for a LoL Case

TSV

Number of TSV clusters

TSV cluster guide

TSV cluster aspect ratio

TSV pitch

2 TSV clusters 4 TSV clusters 8 TSV clusters

TSV cluster guide TSV aspect ratio

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Frontside Routing AnalysisFrontside Routing Analysis

Vary bottom and top routing layer

Vary macro routing layer

Vary routing porosity in a window for PDN/DFT consideration

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Backside Routing AnalysisBackside Routing Analysis Explore BRDL options when TSV and ubumps are not aligned

Vary number of BRDL layers and pitch

ubump group 2

Foundry OSAT

Above 2 BRDL layers, more complicated and expensive process

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2.5D Interposer2.5D Interposer

Interposer Floorplan, Interposer Routing and Congestion

2 interposer routing layers, pitch = 5um

2 interposer routing layers, pitch = 2um

2 interposer routing layers, pitch = 1um

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ConclusionConclusion

A physical PathFinding methodology for interposer and 3D die stacking is presented

The results show that with this methodology, users are able to explore different process and design options for early estimation of their designs to reduce expensive backend iterations

This methodology is a general flow, it also works for mixed interposer and 3D die stacking