PCB Design Guidelines for 0.5mm Package-On-Package · PDF fileApplication Report SPRABB3– June 2010 PCB Design Guidelines for 0.5mm Package-on-Package Applications Processor, Part

Application ReportSPRABB3–June 2010

PCB Design Guidelines for 0.5mm Package-on-PackageApplications Processor, Part I

K. Gutierrez, Keven Coates ................................................................................................................

ABSTRACT

Ball grid array (BGA) packages having 0.5mm ball pitch require careful attention to printed circuit board(PCB) design parameters to successfully yield reliable and robust assemblies. PCBs withpackage-on-package (PoP) technology have additional assembly requirements and options that need tobe considered when designing the PCB.

Fine-pitch PCB design is a team effort and may require more than a common list of design rules. Closecoordination and communication between component supplier, PCB designer, PCB fabricator, and PCBassembly vendor is mandatory.

The following factors have a major effect on the quality and reliability of PCB assembly: pad design,via-in-pad (VIP) guidelines, via finishing, stencil design, solder paste requirements, solder pastedeposition, and reflow profile. This application report provides a starting point for estblishing a set ofdesign guidelines. It is strongly recommended that you perform actual studies in conjunction with yourPCB assembly vendor and PCB fabricator to optimize the process.

Figure 1. Applications Processor (bottom device) and PoP Memory (top device) Stack Up on PCB

Contents1 Introduction .................................................................................................................. 32 Scope of These Guidelines ................................................................................................ 43 Design For Manufacturability .............................................................................................. 44 Teamwork .................................................................................................................... 55 Be Wary of Quotes ......................................................................................................... 56 Do Not Forget Your CAD Tools ........................................................................................... 67 Metric Vs English ........................................................................................................... 68 PCB Fabrication Limits ..................................................................................................... 69 Routing and Layer Stackup ................................................................................................ 710 Applications Processor Package .......................................................................................... 811 Applications Processor Power/Ground ................................................................................... 912 Pad Type ..................................................................................................................... 913 PCB Dimensions for 0.5mm Pitch with Routing Track ............................................................... 1014 PCB Dimensions for 0.5mm Pitch with Via ............................................................................ 1115 Line Widths and Clearances ............................................................................................. 1216 Teardrop and Snowman Pads ........................................................................................... 1317 Multiple BGA Packages .................................................................................................. 1318 BGA Routing ............................................................................................................... 1419 Etch Traps and Heat Sinks ............................................................................................... 1420 VIAS ......................................................................................................................... 15

1SPRABB3–June 2010 PCB Design Guidelines for 0.5mm Package-on-Package Applications Processor,Part I

Copyright © 2010, Texas Instruments Incorporated

www.ti.com

21 Know Your Tools .......................................................................................................... 2022 Example PCB Design ..................................................................................................... 2023 PCB Finishes for HDI ..................................................................................................... 2524 Solder Paste Stencil Design ............................................................................................. 2625 Real World Second Opinion ............................................................................................. 2826 Acknowledgments ......................................................................................................... 3027 References ................................................................................................................. 30

List of Figures

1 Applications Processor (bottom device) and PoP Memory (top device) Stack Up on PCB....................... 1

2 Part 1 - Focus for Part I - PCB Design................................................................................... 3

3 Focus for Part II - PoP Assembly ......................................................................................... 4

4 Teamwork Needs for PCB Design........................................................................................ 5

5 Applications Processor CBC Package Specification Details .......................................................... 8

6 Applications Processor CBC Package Drawing ........................................................................ 8

7 Solder-Mask-Defined (SMD) and Non-Solder-Mask-Defined (NSMD) Pads........................................ 9

8 PCB Pad Dimensions for 0.5mm Pitch Packages - Top Layer...................................................... 11

9 PCB Via Dimensions for 0.5mm Pitch Packages - Top Layer....................................................... 12

10 Line Width Figure.......................................................................................................... 12

11 Teardrop and Snowman Pads ........................................................................................... 13

12 Multiple BGA Components Should Be Off-Set ........................................................................ 13

13 Multiple BGA Components Should not Be Overlapped .............................................................. 13

14 BGA Routing ............................................................................................................... 14

15 Etch Trap Routing Guidelines............................................................................................ 14

16 Heat Sink Routing Guidelines............................................................................................ 15

17 Vias.......................................................................................................................... 15

18 Effect of an Uncapped Via ............................................................................................... 16

19 Offset VIP................................................................................................................... 17

20 Adjacent Via................................................................................................................ 17

21 Tented Vias................................................................................................................. 18

22 Plugged Via ................................................................................................................ 19

23 Filled Via .................................................................................................................... 19

24 Filled and Capped Via .................................................................................................... 19

25 OMAP25x EVM PCB Layout............................................................................................. 20

26 Layer 1 – Signal - Top Copper – Area Around The OMAP25x...................................................... 21

27 Layer 1 – Signal - Top Copper – Teardrop Trace..................................................................... 21

28 Layer 1 – Top Copper – Close Up View and Measurements........................................................ 22

29 Layer 2 - Signal ............................................................................................................ 22

30 Layer 3 - Ground .......................................................................................................... 23

31 Layer 4 - Power............................................................................................................ 23

32 Layer5 - Signal............................................................................................................. 24

33 Layer 6 - Signal – Bottom Copper – Bottom Component Outlines ................................................. 24

34 Bottom Side of the OMAP EVM25x PCB .............................................................................. 25

35 Desired & Poor Wetting................................................................................................... 28

36 First Pass DFM of the OMAP35x EVM ................................................................................. 29

List of Tables

1 2003 SMTA Paper Summary of Attributes of Each PCB Finish..................................................... 25

2 PCB Design Guidelines for 0.5mm Package-on-Package Applications Processor, SPRABB3–June 2010Part I


Memory

Applications Processor

Main PCB

Part – IPCB Design

0.5mm pitch

0.65mm pitch

Focus for

Part I

www.ti.com Introduction

1 Introduction

This application report focuses on PCB design guidelines specific to the CBC package, with 0.5mm pitch,using PoP technology. Experience has shown that PCB design is the most crucial aspect of a design thatcontains PoP technology due to the extremely small pad pitches. Also, not all assembly vendors can buildsuch small pitch assemblies or properly mount the memory on top of the applications processor.

Figure 2 shows a 0.5mm pitch processor and its matching memory at 0.65mm pitch.

Figure 2. Part 1 - Focus for Part I - PCB Design

Guidelines for the assembly of PCBs that use PoP technology are covered in the companion article to thisdocument, PCB Assembly Guidelines for 0.5mm Package-on-Package Applications Processor Part II(SPRABA8), which is referred to as Part II throughout the remainder of this document. Included areassembly options and suggestions to use when qualifying and working with your assembly vendors.



http://www.ti.com/lit/pdf/SPRABA8

0.5mm pitch

0.65mm pitch

Focus for

Part II

Memory

Applications Processor

Main PCB

Part – IIPCB Design

Scope of These Guidelines www.ti.com

Figure 3. Focus for Part II - PoP Assembly

2 Scope of These Guidelines

This document discusses the BGA package and the main PCB immediately below the BGA. Theguidelines do not cover all aspects of PCB design.

Since this is a rapidly evolving technology, spend some time reading recently published articles, papers,and company presentations on all aspects of fine-pitch PCB design.

A common theme emerged as this paper was developed – long standing “rules” for PCB design are nolonger applicable at these small geometries.

The emergence of the theme came about as a result of many meetings among the different suppliers anddesigners. The meetings included representatives from four major team players of high yielding PoPdesign: PCB designers, PCB fabricators, component suppliers, and assembly vendors. Also, an extensiveliterature review was conducted and appropriate references are included at the end of this paper.

You should plan on performing your own experimental layouts and prototype runs before committing tovolume production. Based on your findings, you’ll discover that your suppliers can handle the device oryou may have to change PCB fabricators and/or find assembly vendors with better equipment.

3 Design For Manufacturability

The increasing focus on Design For Manufacturability (DFM) has resulted in expanding the scope oftraditional design activities in order to identify and eliminate manufacturing problems during the designstage. DFM is as much a system as it is a task.

Although PCB design incurs only a small fraction of the total product cost, the decisions made during thePCB design phase determines the cost of the product over its life-cycle and can be crucial to the successor failure of the finished assembly.

In DFM all of the design goals and manufacturing constraints are considered simultaneously andanalyzed. Such analysis can identify design elements that pose problems for manufacturing and suggestchanges in the design to address these problems.

There are many ways to design a good PCB and the ideas presented here must be considered only asrecommendations.



Successful PCB Design Requires Teamwork

PCB

Design

PCB

Fabrication

PCB

Assembly

Component

Suppliers

Failure to include the fabrication and assembly team members can prove costly since choicesmade early in the design will adversely impact the final cost and reliability of the assembled PCB.

www.ti.com Teamwork

4 Teamwork

Everyone involved in the design, fabrication, and assembly of complex, fine-pitch PCBs must worktogether as a team to achieve low-cost and reliable products. The days of tossing circuit diagrams overthe cubical wall to the PCB designer who then tosses them to the assembly vendor are gone. Most PCBdesigns being done today require a team approach and the entire process, from component selection toassembly, requires careful coordination.

The typical team is composed of members from four sub-teams that represent the four major steps inproduct fabrication: the component supplier (semiconductors, passives, mechanical, etc.), the PCBdesigner, the PCB fabricator, and the PCB assembly vendor. In some cases there may be additionalmembers or some members may do more than one job.

Each of the team members brings their own experiences and design guidelines to bear on the task. As aresult, it is not uncommon to find conflicting guidelines. These conflicts must be resolved prior to the startof work. Unresolved conflicts will result in poor assembly yields at best or 100% failure at worst. Constantand frequent communication is the key to resolving conflicts and everyone must be in the loop.

Get to know your team members and be sure to have frequent meetings as the project proceeds fromdesign through production. It will be money and time well spent.

A good relationship with the other members of your team assures that your company does not have to bethe expert in all of these areas. Calling on the expertise of the rest of your team assures the bestpossibility of a manufacturable design.

Figure 4. Teamwork Needs for PCB Design

5 Be Wary of Quotes

PCB fabrication cost estimates vary widely. One of the largest contributors to unit price is the quantity ofPCBs being built in the production run.



Do Not Forget Your CAD Tools www.ti.com

Several PCB design and layout options may be provided on the quote with various pricing options thatoffer a lower price. However, the lower price assumes a relatively large number of PCBs are beingfabricated. For smaller volumes, or for prototyping, the cost may be the same or even higher for some ofthese options.

Obtain several quotes and be wary of quick quotes that seem out of line. When this occurs, the PCBfabricator providing an out of line quote may classify your PCB design as advanced technology by theirstandards causing a relatively high quote compared to other PCB fabricators that classify your PCBdesign as standard technology. Press them hard for ways to lower the cost. Also be careful of quotes thatare much lower than others. This may occur when a PCB fabricator does not understand the complexity ofyour PCB design.

6 Do Not Forget Your CAD Tools

Review the microvia capabilities of your CAD system. Blind microvias open up routing channels on theinner layers. Therefore, your CAD system must be capable of handling blind and buried microvias as wellas through-hole vias. Your system’s features and setup dictates the difficulty or ease with which the PCBwill route. Some of the setup parameters include via size, span, and a whole slew of clearance rules. MostCAD vendors offer specialized training on high-density interconnects and fine-pitch BGA PCBs. Talk tothem – they are also part of your design team.

Your CAD tool may have capabilities to automatically check your design for common DFM parameters;take advantage of these capabilities. Each CAD platform is different and has different capabilities. Forexample, the Altium PCB design rules checking section spans more than 119 pages. Your particular CADplatform will have various checks and tests that can be performed on the finished PCB design. Learn whatthese checks and tests do, and use them to verify your PCB design.

7 Metric Vs English

Using the metric system is one of the most common complaints about fine-pitch PCB design. Mostdesigners dislike this simply because all of their familiar rule-of-thumb guidelines are in the Englishsystem. It is strongly suggested that you set the grid in your CAD system to micrometers (mm) and doaway with the four decimal places of accuracy needed to represent small features in the English system.This will also aid in layout for metric footprints when using the “copy” style commands. Otherwise the lackof accuracy in translation can cause design rule check (DRC) violations.

8 PCB Fabrication Limits

Most PCB fabricators publish a table that indicates their limitations for various parameters like drill size,trace width, aspect ratio, etc. In many cases, these parameters may have more restrictive limitations whenyou consider other dependencies which result from one or two dominate characteristics of the PCBdesign. What this means is that there are tradeoffs and options for the PCB designer to consider. Alwaysconsult with your PCB fabricator for their limits and capabilities and remember that as you approach thelimit of their equipment, yields go down and costs go up. As an example, we will describe a fabricator'stechnology and capabilities:

Standard Technology— Usually means this is the middle of the fabricator’s capability and pricing. Thetechnology does not push the limits of the fabricator’s equipment. Our example fabricator may list aminimum trace width and clearance of 3 mils with 4 mil vias and 10 mil pads for standardtechnology.

High Yield Technology— Loosens up the specifications to provide more clearance and wider tracesresulting in lower cost per unit PCB and higher yields. Our example fabricator may list a minimumtrace width and minimum clearance of 4 mils with 4 mil vias and 10 mil pads for high yieldtechnology. However, a PCB built using high yield technology may be larger and require morelayers.

Engineering Development Technology— Really pushes the fabricator’s capabilities to the limits of theirequipment. Our example fabricator may list a minimum trace width and minimum clearance of 2.5mils with 3 mil vias and 9 mil pads for engineering development technology. Do not make themistake of thinking these limits can be used for production. The cost will be high and the yield maynot be good.



www.ti.com Routing and Layer Stackup

9 Routing and Layer Stackup

One huge benefit of PoP is the elimination of the high-speed, balanced transmission lines between theprocessor and memory. The external memory’s data and control lines no longer have to be routed outfrom under the processor. This is a huge savings in both time and the number of layers. For thesereasons, OEMs have quickly adopted PoP as their applications processor package of choice. This alsoimpacts your pad and layer stackup decisions.

A customer does not need to worry about PCB design requirements for external high-speed DDR memorywhen using PoP because this interconnect is not part of the main PCB design.

It is possible to use a 6-layer PCB and route all of the connections without requiring via in pad technology.There are several suitable layer stackups.

Layer 1 Signal (Top Copper)Layer 2 SignalLayer 3 GroundLayer 4 PowerLayer 5 SignalLayer 6 Signal (Bottom Copper)

If the stackup above is used, great care must be taken to minimize cross talk between the outside 2 layerson both the top and the bottom. Also, signals must still adhere to the impedance recommended in therespective component data sheet (45-65 ohms in most cases), so care must be taken to allow the tracesto have a reference plane for impedance control.

Another popular stackup, shown below, allows for sensitive clock signals or relatively high speed lines tobe routed between power planes.

Layer 1 Signal (Top Copper)Layer 2 GroundLayer 3 Signal - high speedLayer 4 Signal - high speedLayer 5 PowerLayer 6 Signal (Bottom Copper)

Another recommended stackup.

Layer 1 Ground with pad cutoutsLayer 1 Signal – high speedLayer 3 Signal - high speedLayer 4 PowerLayer 5 GroundLayer 6 Signal (Bottom Copper)

At first it would seem that using ground as the top layer would not be efficient. Once the designer realizesthat this reduces vias by ~30% (because of the number of pins connected directly to ground) andtherefore promotes great routing efficiency on the second layer, the advantage is seen. Several highdensity interconnect (HDI) experts have used ground as the top layer and recommend this practice. Thisstackup also provides reduced EMI.

In addition to layer stackups, package footprints and pad stacks are the next important item to consider.Proper definitions and strict adherence to clearance will play a key role in the development of high yieldPoP designs



Solder ball chemistry

Package size

Package designator

A Ball pitch (bottom)

B Ball diameter

C PAD pitch (top)

D PAD diameter

LF35

14x14 mm

CBC

500um

250um min to 350um max

650um

300um

[ 98.25Sn, 1.2Ag, 0.5Cu, 0.05Ni ]

Applications Processor Package www.ti.com

10 Applications Processor Package

Familiarity with the basic dimensions of the applications processor package is helpful. This sectiondiscusses the key parameters of the CBC package.

Figure 5. Applications Processor CBC Package Specification Details

Figure 6. Applications Processor CBC Package Drawing



www.ti.com Applications Processor Power/Ground

11 Applications Processor Power/Ground

There are a lot of power and ground pins on the applications processor. Decoupling capacitors arerequired and must be placed as close as possible to the ball connection. When selecting a power and aground, choose the ground closest to the power pin for each decoupling capacitor. A single decouplingcapacitor can serve up to 3 balls if placed closely to them.

Review the applications processor datasheet for power assignments and recommended decouplingcapacitor values.

This paper will show the location of the decoupling capacitors for an example EVM module later.

12 Pad Type

Before getting into the specific details, it is important to understand the pros, cons, and unknownsconcerning the two most common types of solder pads, solder-mask-defined (SMD) andnon-solder-mask-defined (NSMD) pads.

Industry reliability studies have revealed that NSMD-type pads are highly recommended for most 0.5mmpitch PCB designs. They have the advantage of tighter copper dimensions, compared to solder maskdimensions, and the uniform coverage is better at the solder melting temperature. The pads are alsosmaller, allowing for improved routing. Another advantage of the NSMD pad is reduced stressconcentrated on the solder joint, which increases solder joint reliability especially if paste overprinting isused. This concept will be covered later in a section that discusses solder stencil design.

Figure 7. Solder-Mask-Defined (SMD) and Non-Solder-Mask-Defined (NSMD) Pads



PCB Dimensions for 0.5mm Pitch with Routing Track www.ti.com

However, there are some companies that swear by SMD pads claiming that the greater copper area (ofthe pad) and the solder-mask overlap create better adhesion strength to the fiber/glass laminate. Theyclaim that flexing and bending during accelerated thermal cycling testing causes a weak link where thepad attaches to the PCB and could be the main failure location, as opposed to the typical solder fracturewhich dominates the NSMD pad.

Be sure and talk to your PCB fabricator and your PCB assembly vendor and discuss their experiencesand preferences before deciding which type of pad will be used on your PCB design.

13 PCB Dimensions for 0.5mm Pitch with Routing Track

Through several meetings with both PCB fabricators and PCB assembly vendors, the followingrecommendation has been created for the PCB BGA footprint of the applications processor having 0.5mmor 500 mm, pitch solder balls. The pattern shown in Figure 8 assumes there will be traces between solderpads on the top layer.

Non-solder-mask defined (NSMD) pad designs perform better than solder mask defined pads due to lowerstresses in the solder near the top of pad according to several industry studies. In addition, there isadditional “grip” area around pad edge as previously described.

According to IPC (an industry association for PCB manufacturing) standards IPC-7351A, the most reliabledesign is a NSMD pad which has a diameter that is slightly smaller than the solder ball. For a ball size of0.3mm, the IPC 7351A standard recommends a .25mm pad (~10 mils).

This will allow the use of a 82um (3.2mil) trace between pads, yet preserve 82um (3.2 mil) clearancebetween pads and traces. Some vendors suggest a 3.0mil trace (75um) with a 3.3mil (83um) clearance.

Finally, the suggested clearance around the pad for the solder mask opening is about 50um (2mil).

Pad Type NSMDPad Pitch A 500mm (~20mils)Pad Size B 250mm (~10mils)Mask Shape RoundMask Opening C 50mm around pad (350mm antipad for the 250mm pad)Mask Web D 150 mmTrace Allowed Between Yes 3.2mil trace maximumTrace Width E 82 mm (~3.2mil)Pad to Trace Clearance E 82 mm (~3.2mil)



D

EE

E

A

C

B

www.ti.com PCB Dimensions for 0.5mm Pitch with Via

Figure 8. PCB Pad Dimensions for 0.5mm Pitch Packages - Top Layer

14 PCB Dimensions for 0.5mm Pitch with Via

When you want to use vias to drop down to lower layers, the following technique is commonly used. At the0.5mm pitch, there is sufficient space between pads to allow for a via that has the same dimension as thepackage ball pad. The pad and via are connected with a 200um wide trace. The pattern shown in Figure 9shows how vias are used to connect solder pads on the top layer to subsequent layers.

For this size via, PCB fabricators will use a laser drill. Be sure and verify that your facility can maintain thetight tolerances required to ensure adequate clearances between vias and pads.

This type of via is referred to as an “offset via” and is very robust. Note that the via is completely coveredby the solder mask. This prevents short circuits during paste application, allows for paste overprinting(discussed later) and prevents etch entrapment.

Pad Type NSMDPad Pitch A 500mmPad Size B 250mm (~10mils)Via pad size B 254mmVia drill size F 127mm (5mil)Pad to Via clearance G 72mmPad to Via Trace H 82mm wide (~3.2mil)Length of Connecting I 354mm pad center to pad centerTrace



B

F

I

GH

82um (3.2mil) Trace

82um (3.2mil)

Pad to Trace

Clearance

82um (3.2mil)

Pad to Trace

Clearance

250um

(10mil)

Pad

250um

(10mil)

Pad

250um

(10mil)

Pad

250um

(10mil)

Pad

0.5mm Pad Pitch

0.5mm Pad Pitch

82um (3.2mil)

Pad to Trace

Clearance

82um (3.2mil)

Pad to Trace

Clearance

250um

(10mil)

Pad

250um

(10mil)

Pad

250um

(10mil)

Pad

250um

(10mil)

Pad

0.5mm Pad Pitch

0.5mm Pad Pitch

Line Widths and Clearances www.ti.com

Figure 9. PCB Via Dimensions for 0.5mm Pitch Packages - Top Layer

15 Line Widths and Clearances

Top layer routing between 0.5mm pitch solder balls, can be accomplished if the pad size is no larger than250um (10mils). This will allow a single trace, 82um (3.2mils) wide, with 82um (3.2mils) clearancebetween pad and trace. These are generic guidelines and should be used for the layer on which the0.5mm BGA package is mounted. Most high quality PCB fabricators should have no problem if 82um(3.2mils) is used as the minimum clearance between pads, traces and combinations of both.

Figure 10. Line Width Figure



www.ti.com Teardrop and Snowman Pads

16 Teardrop and Snowman Pads

Teardrops should be used when traces exit the pad whether it is a solid pad or a pad with a via. One wayof creating teardrops is to add secondary pads at the junction of an existing (primary) pad and the trace,sometimes called a “snowman.” These secondary pads are sized 0.05mm smaller than the primary pads,and the center is placed 0.075mm away from the center of the primary pad.

This technique is designed to provide additional metal at the critical junction of a pad and a trace. Itbecomes especially important during the process of registration and via drilling. This will reduce solderjoint stresses, reduces risk of cracking, improves resistance to thermal shock and improves resistance toimpact shearing. Use of teardrops, in conjunction with NSMD pads, provides additional ball-to-land contactarea, making them more mechanically robust.

Check the latest IPC standards and discuss them with your PCB fabricator and PCB designer. In somecases, this feature is simply a check box on your CAD system or something that your PCB designer willdo for you.

Figure 11. Teardrop and Snowman Pads

17 Multiple BGA Packages

When BGA components are placed on both sides of the PCB, do not place one BGA component directlyopposite another BGA component. The temperature cycle board-level-reliability (BLR) degrades if the PCBis designed with an overlap of BGA components.

Figure 12. Multiple BGA Components Should Be Off-Set

Several studies, including the one referenced here, show that temperature cycle (BLR) performancedegrades if there is an overlap of package footprints. A small BGA opposite a large BGA or QFP, with itsfootprint within the unpopulated IO shadow of the larger package, has temperature cycle performancesimilar to that of a single-sided PCB assembly.

Figure 13. Multiple BGA Components Should not Be Overlapped

For additional information on this concept, please see section 5.4, Single-Sided Soldering andDouble-Sided Soldering, of NEC’s, Semiconductor Device Mount Manual,http://www.necel.com/pkg/en/mount/.



http://www.necel.com/pkg/en/mount/

BGA Routing www.ti.com

18 BGA Routing

One trace can be routed between two solder pads of a 0.5mm pitch PGA. This allows the outer two rowsof solder pads to be routed on the top layer. Therefore, each solder pad on the remaining rows will need avia to connect to another routing layer if all top layer routing tracks are used to route the second row ofsolder pads.

The inner rows of solder pads will connect to another routing layer for routing outside of the BGA area.VIP technology is not required if you consider the following routing strategy. The left portion of Figure 14shows how a via can be placed between solder pads and connected to one of the adjacent solder pads onthe top layer. This signal trace is routing outside of the BGA area using another layer in the PCB. Thisstrategy can used for routing all of the inner solder pads. Since there is only enough space to route onetrace between vias, this strategy requires an additional routing layer for every inner row of solder padsafter the fourth row. The right portion of Figure 14 shows a cross-section side view of the via connections.

Figure 14. BGA Routing

19 Etch Traps and Heat Sinks

Be careful not to create etch traps when routing circuit traces. Figure 15 shows examples of etch traprouting guidelines. Another challenge with fine pitch PCB design is to ensure traces and vias do not pullheat away from the solder pad.

Figure 15. Etch Trap Routing Guidelines

Small BGA pads do not have much solder and depend on uniform heating for a good joint. Here are sometips to ensure that traces and vias do not serve as heatsinks.

• Keep the trace smaller than the pad or via.• Do not gang up pads with a copper pour such as around a ground plane without thermal reliefs.• Use individual traces to interconnect the pads.

TI applications processors are relatively low-power devices so the smaller traces are appropriate.



www.ti.com VIAS

Figure 16. Heat Sink Routing Guidelines

20 VIAS

The applications processor will need vias to make connections to other components. Fortunately, the useof PoP removes the cost, difficulty and challenge of routing high speed memory signals from under theapplications processor to the memory. Instead, the memory sits on top of the processor and theconnections are automatically made during PCB assembly.

The remaining connections from the applications processor can be accomplished using standard routingtechniques. Exotic and expensive stacked vias or VIP technology will not be required for most PCBdesigns.

The 0.5mm pitch CBC package can be routed using an offset via with a 10mil diameter and a 5 mil hole.Although these vias might be called microvias, they are still constructed in the same fashion. It is commonto classify a via that is 6mil or smaller as a microvia. There is nothing unique about them and can bedrilled with either mechanical or laser drills.

The one key point to know is that vias with hole sizes over 0.4mm (15mil) cannot be tented because thesolder mask falls into the holes and makes a mess.

Vias that pass through the entire PCB, from top to bottom, are through-hole vias. Vias that are visible ononly one side are blind vias. And a via that is not exposed to the outside layers is called a buried via.

The formation of blind and buried vias may be accomplished through different processes. In some cases,they may be mechanically drilled and use standard equipment for making multilayer PCBs. The maindifference is their smaller diameter, which requires greater care in the drilling process. The PCB fabricatorneeds to make certain the wall of the blind or buried via is clean and all debris is removed in order toensure proper plating on the wall surfaces. Always talk to your PCB fabricator to discuss their limitationsand recommendations.

Figure 17. Vias



Void Caused byTrapped Air

Solder Ball

Unfilled Pad with Via

VIAS www.ti.com

20.1 Laser Blind Vias

A laser blind via should range from 5mils for standard vias to 2mils for advanced technology vias. Thehole aspect ratio should be kept at a maximum of 0.75:1. Ratios can be as high as 1:1. Some holes usedin modules can go to 1.5:1, but this should not be used for standard PCBs.

Laser vias are typically drilled through reinforced FR-4 material that is 0.002” thick or less. There isstandard FR-4 or laser-drillable FR-4 that uses a more uniform glass weave. The LD glass has a costadder to it, but produces a smoother hole wall surface which makes filling and capping easier. Thesedecisions are best made by working with the PCB fabricator to see what has worked best in the past.

The minimum average copper plating thickness for a laser blind via hole should be specified as 0.0005” orshould be specified as “In accordance with IPC-6012A, class 2.”

20.2 Via-In-Pad, Microvias, Stacked Vias, Filled Vias Introduction

Although not generally needed for 0.5mm pitch, you may be considering VIP technology for the smallerpitch devices. The VIP methodology places the via directly under the solder pad. However, this will requireanother step to seal the via. Usually this is done with either conductive or non-conductive filling of the vias.

For a 10mil solder pad, TI recommends the use of 4mil microvias that are laser drilled. After drilling, anddepending on the PCB fabricator preferences, the vias are copper plated, then filled with a polymerconsisting of a blend of copper and epoxy for a non-conductive option or copper, silver, and epoxy for aconductive option. It is important to ensure that the PCB vendor utilizes a via fill material with a copperparticle size below 1 mil to ensure a complete penetration of the via by the fill material.

Once the vias are filled, cured, and planarized, the remainder of the plated holes are processed. Thisyields a flat copper plated cap over the vias which facilitates component attachment. The Via-in-Padtechnology provides two primary benefits: higher component density and improved routing.

For most PCB fabricators, blind, stacked vias should be limited to only one or two layers, with three beingthe max. You must validate your PCB fabricator’s capability to reliably build with this class of technology.

All vias must be capped or filled to prevent voids and out gassing. The images in Figure 18 show theeffect of an uncapped via. The voids and damage occurs during reflow. The right picture is a failurecaused by the excessive package movement during reflow, caused by out gassing

Again, these decisions are best made by working closely with the PCB fabricator.

Figure 18. Effect of an Uncapped Via

20.3 Offset VIP

Offset VIP is a VIP with a hole that have been shifted from the center, towards one side of the solder pad.Studies have shown that the offset VIP will experience less voiding problems than a standard VIP with acentered hole. Sometimes these are called dogbones and depending on the distance from the pad center,they may be called snowman vias.

There are two generic configurations: the drilled hole is located between the center of the solder pad andthe edge of the solder pad; or the drilled hole is located on a overlapping, or adjacent pad, where the holeis offset from the mounting pad center by up to RPAD + RVIA PAD – 0.002”. This is the equivalent of anoverlapping adjacent pad.



www.ti.com VIAS

Plated though hole vias must be filled with either conductive or non-conductive material and plated over.This will eliminate solder wicking down the via end eliminate trapped air in the via from moving up into thesolder joint.

BGA pads with a pitch of 0.5mm to 0.8mm which utilize blind vias should have a drilled via diameter≤0.004” and have an aspect ratio ≤ 0.75:1. These will not require any via fill or over plating. These vias willnot significantly increase solder joint void formation versus pads with no vias.

The PCB assembler should be consulted prior to using a offset VIP configuration to establish theirmanufacturing requirements

Figure 19. Offset VIP

20.4 Adjacent Via

If space permits, this old fashioned dog-bone style via is best. It suffers from none of the voiding issues ofthe other techniques since the hole is not capped by the ball. However, it is still recommended that the viabe covered up or plugged from the side that the component is mounted.

The trace length “L” connecting the via pad to the solder pad should be at least 0.005” long. This willeliminate solder flow from the pad into the via and allow for a soldermask dam to be placed across thetrace. If the connecting trace is less than 0.003” the vias cannot be covered with solder mask. This is dueto the high probability of getting solder mask on the solder pad.

Blind vias do not require any via fill or over plating. These vias will not significantly increase solder jointvoid formation versus pads with no vias.

Figure 20. Adjacent Via

20.5 Via Covering

TI strongly recommends that all vias be tented, filled and/or capped, especially under BGA packages. ThePCB fabricator should be consulted prior to specifying via fill to establish their manufacturingrequirements. Also, make sure your CAD system provides the required design files and the neededdocumentation. In some cases, additional files may be required.

Tom Hausherr, from PCLibraries, www.pclibraries.com , has a very good presentation covering varioustypes of vias and via coverings. His presentation, “Metric Pitch BGA and Micro BGA Routing Solutions,”can be found on their website. They show seven different versions, each with different pros and cons.Please read this material since this paper will only highlight the three most commonly used types.

20.5.1 Tented Vias

A tented via is defined as a via that is completely covered by the solder mask. Tented vias are verypopular because they have the lowest cost. Tenting can be used on a blind-via or a thru-hole via.



VIAS www.ti.com

Vias under components are often tented to prevent the paste flux from running into the holes and onto theopposite side of the card, and to allow vacuum hold down on test equipment.

Tenting is normally done with a dry film solder mask rather than a liquid photo-imagable solder mask.However, a single-pass LPI mask cannot guarantee 100% coverage of the vias. Obtaining the bestpossible via coverage with screen printing is a compromise between hole size, surface tension of theliquid mask and PCB thickness. Thru-hole vias can be tented on both ends to reduce chances of chemicalentrapment during surface precleaning. However, be aware that trapped gas will expand inside the hollowvia during reflow and might present reliability problems.

A tented via which is open on one end may have another issue. This type of via can be subject to the"micro-etch" process. This is caused by a small amount of residual etchant trapped inside a tented via.This material will crystallize rapidly, creating copper sulfate crystals. Over time, these crystals can causelong term reliability issues. In the case of a electroless nickel immersion gold (ENIG) finish, the gold andsmall area of exposed copper near the tent could form a galvanic cell, accelerating the etch process.

Although tenting is inexpensive, other methods provide a more robust PCB design that does not sufferfrom the downsides of trapped gases or micro-etching. These factors must be carefully evaluated againstthe added processing cost of plugged vias which are much more reliable. Always discuss these optionsand considerations with your PCB fabricator before selecting any of these methods.

Figure 21. Tented Vias

20.5.2 Plugged Vias

A plugged via is defined as a via that is partially filled with mask or other non conductive media. Nosurface finish is applied to via barrel. No surface finish is applied to the via.

Although sometimes confused with “filled vias,” a plugged via may not be completely filled. The materialmay be applied on either one side or both sides.

During solder mask application, the via is flooded with mask. And since it is only partially filled, chemicalentrapment is a major concern.



www.ti.com VIAS

Figure 22. Plugged Via

20.5.3 Filled Vias

Filled vias are 100% filled, usually with a non-conductive material. This process uses additional processsteps. This is done to ensure 100% of the vias are covered.

There are several variations of the filled via.

A filled and covered via has a secondary covering of material (liquid or dry film solder mask) applied overthe via. It may be applied from either one side or both sides.

Figure 23. Filled Via

20.5.4 Filled and Capped Vias

This is the ultimate via and is commonly called Via-In-Pad (VIP). Vias are filled with a conductive ornon-conductive media, planarized and then plated over. This process allows the use of via capture padsas SMD pads.

VIP has become very common in BGA PCB designs to reduce routing issues and lower inductanceassociated with high speed connections. However, it does drive up the overall PCB cost. If at all possible,consider other alternatives and use VIP only as a last resort.

Figure 24. Filled and Capped Via



Know Your Tools www.ti.com

21 Know Your Tools

Your CAD program must be setup correctly to define the appropriate pad and via stacks to supportdifferent types of vias. The additional process steps may require additional gerber files.

Your CAD manual and PCB fabricator will be your best friends as your tools are set up, so plan to learnand use all available supporting documentation as well as your extended team members.

NOTE: It is strongly recommended that all vias be covered, especially under BGA packages. Inaddition, the PCB fabricator should be consulted prior to specifying via fill to establish theirmanufacturing requirements, required design files, and the needed documentation.

22 Example PCB Design

The OMAP25x EVM is used as an example PCB design that required similar design guidelines as thosediscussed in this document. The OMAP25x component is not packaged in the same CBC packagediscussed, but it is similar enough to demonstrate good examples of PCB design guidelines presented inthis document. Figure 25 from the layout of the OMAP25x EVM PCB, shows an example of the use of thediscussed design guidelines. While the OMAP25x does not use exactly the same package as theOMAP35x, it is very similar and this PCB design shows some good examples of earlier discussions.

This example PCB design uses the previously discussed design guidelines and a six layer PCB. Eachlayer will be shown along with important notes about the PCB design.

These images of the OMAP25x EVM are from the Allegro viewer with the appropriate pins, vias and etchturned on for each layer. Figure 25 provides an overall PCB image, while Figure 26 through Figure 33show various enlarged areas underneath the BGA package.

The color code is simple: green is etch, blue are vias, and gray is SMT pads for the components.

Figure 25. OMAP25x EVM PCB Layout



www.ti.com Example PCB Design

Figure 26. Layer 1 – Signal - Top Copper – Area Around The OMAP25x

Note that this viewer shows the individual traces used to approximate the teardrop trace exit from the padsand vias.

Figure 27. Layer 1 – Signal - Top Copper – Teardrop Trace



Large Via 20 mil diameterand 10 mil drill

10 mil BGA pad

10 mil microviaand 4 mil drill

3 mil trace between BGApads

8 mil power trace

Example PCB Design www.ti.com

Figure 28. Layer 1 – Top Copper – Close Up View and Measurements

The microvia only goes between layer one and layer two on this design. There are no stacked vias.

The small vias are from layer two to layer one. The large vias are through vias from top to bottom.

Figure 29. Layer 2 - Signal



www.ti.com Example PCB Design

Figure 30. Layer 3 - Ground

Figure 31. Layer 4 - Power



Example PCB Design www.ti.com

Figure 32. Layer5 - Signal

Figure 33. Layer 6 - Signal – Bottom Copper – Bottom Component Outlines

The majority of the components within the U1 outline (which is not physically present on the bottomsilkscreen) are bypass capacitors.

Figure 34 shows the bottom side of the OMAP 25x EVM PCB showing the traces, vias and bypasscapacitors. The outline of the OMAP processor is shown as a black dotted line. This illustrates how thebypass capacitors are literally as close as possible to the appropriate supply pins of the processor. Mostare connected through vias to the top side of the PCB. Appropriate connections are also made to thepower and ground layers.



www.ti.com PCB Finishes for HDI

Figure 34. Bottom Side of the OMAP EVM25x PCB

23 PCB Finishes for HDI

A surface finish provides a coating over the outer layer copper that prevents oxidation and provides anelectrically conductive surface. This surface has two generic functional requirements: to provide asolderable surface for connecting components with solder and to attach a component without soldering,such as a wire bond or press-fit connector.

Organic Solderability Preservative (OSP)— This process coats a very thin coating of an organicmaterial that inhibits copper oxidation. It is so thin that it is nearly impossible to see and measure.The organic material is removed by the solder flux used during PCB assembly. PCBs that havebeen OSP coated will have bright copper pad coloration. The most prevalent OSP is ENTEKCU-106A. This coating is used for PCB assemblies that will go through multiple assemblyoperations. PCB’s that have multiple surface finishes can also use the CU-106A(X) finish.

Immersion Tin (ImSn)— This process coats a thin layer of tin directly on top of the copper surface. Thetin produces an extremely flat surface for mounting of surface mount components with ultrafine-pitch components. This coating also provides a thicker, uniform surface that provideslubrication for press-fit pins.

Immersion Silver (ImAg)— This process plates a thin layer of silver directly on top of the copper surface.As with the other immersion surface finishes, the finished product produces a very flat surface; it isideal for fine pitch components. This surface finish has the ability to maintain high solderability aftermultiple heat cycles. This can also be used as an aluminum wire bondable surface. It is compatiblewith no-clean assembly processes. This is becoming popular as a hot air solder leveling (HASL)replacement for lead-free soldering applications. This surface finish yields a dull tarnished lookingsurface. There is significant industry data showing that the dullness does not affect solderability orreliability.

Other Finishes— Other finishes include hot-air solder leveling and immersion nickel-gold (ImNiAu).Table 1, from a 2003 Surface Mount Technology Association (SMTA) paper, summarizes theattributes of each PCB finish.

Table 1. 2003 SMTA Paper Summary of Attributes of Each PCB Finish

Parameter HASL OSP ENIG ImAg ImSn

Standard solder joints are P P P P Ppredictable

BGA solder joints are predictable P P M P P

Solderability shelf life is one year P M P M M



Solder Paste Stencil Design www.ti.com

Table 1. 2003 SMTA Paper Summary of Attributes of Each PCB Finish (continued)

Parameter HASL OSP ENIG ImAg ImSn

Soldermask compatibility P P M P M

Via plugging is safe and reliable P M P M M

Improves overall via reliability M --–- P --–- --–-

Flat surface benefits assembly M P P P P

Conductive contact surface P M P P P

Solderable over four heating P P M P Pcycles

Thickness variation is minimal M P P P P

Coating is environment friendly M P P P P

Tin whiskers are not a problem P P P P M

P = plus, M = minus, N = neutral 8P 8P 9P 9P 7P

September 2003 SMTA International

24 Solder Paste Stencil Design

Stencil design has several critical factors that affect solder paste deposition. For this discussion, therecommendations apply only to round pads for fine pitch, BGA packages with 0.5mm spacing. Theserecommendations can be considered as a starting point for building design rules that fit yourmanufacturing requirements and capabilities. These recommendations assume a lead-free process isused. In all cases, you must carefully monitor assembly startup so as to ensure the desired results arebeing achieved.

24.1 Area Ratio

The relationship between the surface of the aperture and the inside surface of the aperture walls in thestencil is referred to as the Area Ratio (AR). The area ratio is much more suitable for shapes such ascircles than the aspect ratio. For fine pitch BGA pads, a round aperture is recommended.

An area ratio of ≥ 0.66 has been shown to provide the best transfer efficiency and repeatability ofdeposited solder paste. Values from 0.66 to 0.8 ensure a good paste release from the stencil.

The biggest impact on area ratio is the stencil thickness. The equation is

AR = Ap / Aw ≥ 0.66

where Ap is the aperture opening area and Aw is the wall area

pr2 / 2prT ≥ 0.66



aperture aperture stencil stencil

opening (mils) radius (mils) thickness (um) thickness (mils) AR

10 5.0 100 3.94 0.64 100um stencil

11 5.5 100 3.94 0.70

12 6.0 100 3.94 0.76

13 6.5 100 3.94 0.83

14 7.0 100 3.94 0.89

15 7.5 100 3.94 0.95

16 8.0 100 3.94 1.02

10 5.0 125 4.92 0.51 125um stencil

11 5.5 125 4.92 0.56

12 6.0 125 4.92 0.61

13 6.5 125 4.92 0.66

14 7.0 125 4.92 0.71

15 7.5 125 4.92 0.76

16 8.0 125 4.92 0.81

10 5.0 127 5.00 0.50 5 mil stencil

11 5.5 127 5.00 0.55

12 6.0 127 5.00 0.60

13 6.5 127 5.00 0.65

14 7.0 127 5.00 0.70

15 7.5 127 5.00 0.75

16 8.0 127 5.00 0.80

10 5.0 152.4 6.00 0.42 6 mil stencil

11 5.5 152.4 6.00 0.46

12 6.0 152.4 6.00 0.50

13 6.5 152.4 6.00 0.54

14 7.0 152.4 6.00 0.58

15 7.5 152.4 6.00 0.63

16 8.0 152.4 6.00 0.67

Overprinting for BGA @ 0.5mm

Copper Pad radius overprint amount Aperture Opening

10 5 3 16

10 5 2 14

10 5 1 12

www.ti.com Solder Paste Stencil Design

Where r is the aperture opening radius and T is the stencil thickness. This table shows the various valuesof AR for different aperture openings and stencil thicknesses.

24.2 Aperture Size and Overprinting

When depositing solder paste, overprinting of the pad is desirable to get additional solder on the pad for amore robust joint. This also helps to minimize coplanarity issues. In addition, there is sufficient solder tocover the sides of the NSMD pad, which helps distribute stress to a larger area.

When overprinting, it is mandatory that all traces and vias be plugged and covered with soldermask.

Based on studies by Avant of Austin, Texas, it is recommended to overprint a 0.5mm BGA’s 10 mil padfrom 1 to 3 mils around the pad’s circumference. Thus a 10 mil copper pad will have a stencil aperturefrom 12 to 16 mils in diameter using a 6 mil thick stencil. While this may seem excessive, the solder pastewill quickly wick back to the pad leaving a good solid foundation of solder and a very robust joint.

The table below summarizes the various overprint amounts and the resulting aperture opening. Use thisvalue to confirm the correct AR value for the stencil thickness to be used.

24.3 Aperture Shape

A round aperture shape is recommended for BGA pads. This allows for an equal amount of overprintingon a round pad. Square corners can result in unequal amounts of paste being deposited and should beavoided.



Desired Poor

Real World Second Opinion www.ti.com

24.4 Stencil Material and Finishing

The solder stencil should be made from stainless steel, chromium or Cobalt Nickel. The apertures shouldbe laser cut. The finish should be eletropolished to provide mirror smooth walls. The mirror smoothaperture walls ensure good paste release.

During assembly, the wider side of the aperture should be against the PCB.

The best solder joint for BGA packages, is created using a NSMD pad along with the recommendedstencil design. In the figure below, the red arrows show the stress points for two types of pad and pastedepositions. These stress points have been found to have the highest stress during thermal cycling.

When the paste is allowed to wet the side walls of the pad, a much more robust joint is formed.

With poor wetting of solder pad edges, the stress induced during thermal cycling will be more focused atthe interface between solder and the copper pad. Furthermore, the poor wetting will cause a reduction ofthe solder fillet diameter at the level of the pad surface, which also will contribute to the significantlyreduced fatigue life.

Figure 35. Desired & Poor Wetting

With proper stencil design, proper paste deposition, proper paste formulation and correct reflowtemperatures, the solder will wet the solder ball and adhere to the edges of the copper pad resulting in avery strong and robust joint that can withstand the rigors of today’s consumer products.

25 Real World Second Opinion

The first OMAP EVM PCB was designed prior to the release of these guidelines and was submitted to anassembly vendor where they performed a DFM analysis on the gerber files. Their comments related to theoriginal PCB design are listed below and the locations being discussed are shown in Figure 36.

This demonstrates an example of valuable communications between members of the design team. If theoriginal PCB design had gone into production, the yield would have been very poor. Our thanks to Elcoteqin Richardson, TX for their analysis of the PCB design.



www.ti.com Real World Second Opinion

Figure 36. First Pass DFM of the OMAP35x EVM

• At location A, seven BGA Pads are ganged together. This acts as a large heatsink during reflow.• The traces between D and the BGA pad should be narrower. A trace entering a pad should never be

larger than the diameter of the pad.• In some cases the BGA to ground plane is done like D and the other is done like A. Neither are good

techniques.• In C, the trace width exiting the BGA pad is much too large. In this case the trace acts as a heatsink

during reflow.• As in details A,B,C and D, the heat transfer from the ground planes is passing through a large via

through a large trace and fanned out across 7 BGA pads ganged together.• Do not gang BGA pads together with a copper plane as this increases the heat sink effect.



Acknowledgments www.ti.com

26 Acknowledgments• Clint Cooley and Franklin Troung, CircuitCo, 675 N. Glenville #195, Richardson, TX 75081,

214-466-6690, www.circuitco.com• Elcoteq, Sinimaentie 8B, P.O. Box 8, FI-02631 Espoo, Finland• Micron Technology, Inc., 8000 South Federal Way, Post Office Box 6, Boise, ID 83707-0006• Ron Weindorf, Process Engineer, for his review and critique of this paper. His contributions and

suggestions are gratefully acknowledged, received and incorporated. Avant Technology, 9715A BurnetRoad, Austin, TX 78758

27 References

Sanmina PCB_Fabrication_Volume_DFM_Guidelines_Rev_D.pdf

“PCB Design and SMT Assembly/Rework Guidelines for MCM-L Packages” © 2001–2006, SkyworksSolutions, Inc. All Rights Reserved.

“PC-Board Layout Techniques for ML67Q4060/4061 ARM 7 W-CSP Packaged Devices” October 5, 2005,Rev 1.0, OKI Semiconductor

“PCB Pad Pattern Design and Surface-Mount Considerations,” XAPP439 (v1.0) April 11, 2005, Xilinix

“Eliminating Microvoid Risk Via An Optimized Surface Finish Process,” Donald Cullen, Witold Paw, JohnSwanson, Lenora Toscano, MacDermid, Inc. Waterbury, CT USA

“Effect Of Printed Wiring Board Warpage On Ball Grid Arrays Over Temperature,” Kyra Ewer and JeffreySeekatz Raytheon Dallas, TX. 2004

“Design Method for High Reliable Flip Chip BGA Package,” Naoto Saito, Hitachi Ltd. 2001

“How to Control Voiding in Reflow Soldering,” Dr. Ning-Cheng Lee, Indium, 2006

“Reflow Soldering Processing and Troubleshooting SMT, BGA, CSP, and Flip-Chip Technologies,”Newnes, pp. 288, 2001

“Voiding of Lead-Free Soldering at Microvia,” Dr. Ning-Cheng Lee, Indium, 2001

“The Effect Of Via-In-Pad Via-Fill On Solder Joint Void Formation,” Adam Singer, Cookson ElectronicsFoxboro, MA, 2002

“Impact Of Microvia-In-Pad Design On Void Formation,” Frank Grano, Sanmina-Sci, 2001

“Voids in Solder Joints,” Raiyo Aspandiar, Intel, 2005

“Package on Package (PoP) Stacking and Board Level Reliability, Results of Joint Industry Study,” LeeSmith - Amkor Technology, 2005

“Surface Mount Requirements for Land Grid Array (LGA) Packages,” Amkor Technology, Inc 2002

“A Study on Package Stacking Process for Package-on-Package (PoP),” Akito Yoshida, et. al, Sharp,Senju, Panasonic, Amkor

“0.4mm BGA Fabrication Result Based Design Requirements,” Shrikant Patel, Eagle Circuits 2006

Package-on-Package JEDEC Standard No. 21-C, release 16

NAND Flash and Mobile DDR SDRAM, 1Gb NAND Flash and 512Mb Mobile DDR SDRAM CombinationMemory Part-on-Part (PoP), Micron Datasheet

“Flip Chip CSP Packages,” Application Note Onsemiconductor, 2003

“Surface Mounting Technology BGA Assembly Guidelines,” AN-3011 Fairchild, 2001

“Stencil Design Guidelines,” www.alphametals.com/products/stencils

PCB Layout Recommendations for BGA Packages,” TN1074, Lattice Semiconductor, 2006

“Stacked Package on Package (PoP) Design Guidelines,” Moody Dreiza, Amkor, 2004

“NanoStar_ & NanoFree_ 300_m Solder Bump Wafer Chip-Scale Package Application,” SBVA017Rosson, TI, 2004



http://www.circuitco.com

www.ti.com References

“Solder Stencil Design Guidelines,” Cookson Electronics at www.alphametals.com 2006

“Design for Manufacturability of Rigid Multi-Layer Boards,” Hausherr, PCB Libraries 2006

“Stencil Design Guidelines,” Coleman Photo Stencil, 2000

“Board Routability Guidelines with Xilinx Fine-Pitch BGA Packages,” Maheshwari, XAPP157, 2002

“MicroStar BGA_ Packaging Reference Guide,” SSYZ015B, TI 2000

“Substrate Topics,” Rob Rowland, RadiSys Corporation, SMTA International 2003

EMI Resources and References

Ott, H. W., Noise Reduction Techniques in Electronic Systems, Second Edition, Wiley Interscience, 1988.

Johnson, H. W. & Graham, M., High-Speed Digital Design, Prentice-Hall, 1993.

Montrose, M. I., Printed Circuit Board Design Techniques for EMC Compliance, IEEE Press, 1996.

Fitts, M., The Truth About Microvias, Printed Circuit Design, February 2000.

Edwards, T. C., Foundations of Microstrip Circuit Design, Second Edition, John Wiley & Sons, 1992.

IPC-D-317A, Design Guidelines for Electronic Packaging Utilizing High Speed Techniques, 1995.

Wadell, B. C., Transmission Line Design Handbook, Artech House, 1991

Johnson, H., Why Digital Engineers Don’t Believe in EMC, IEEE EMC Society Newsletter, Spring, 1998

Lau, J. H., Ball Grid Array Technology, McGraw-Hill, 1995. ! IEEE EMC Society web page atwww.emcs.org.

Henry Ott Consultants <www.hottconsultants.com>

Other Useful PCB Design Guidelines

“Design for Manufacturability of Rigid Multi-Layer Boards,” Tom Hausherr; PCB Libraries, Inc. , DesPlaines, IL; www.pcblibraries.com;

IPC-7351A Land Pattern Calculator (Freeware)

http://landpatterns.ipc.org/files/PCBM_LP_Calculator_V2009-0831.zip



IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the latest relevant information before placing orders and should verify that such information is current and complete. All products aresold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standardwarranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except wheremandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products andapplications using TI components. To minimize the risks associated with customer products and applications, customers should provideadequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Informationpublished by TI regarding third-party products or services does not constitute a license from TI to use such products or services or awarranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectualproperty of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompaniedby all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptivebusiness practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additionalrestrictions.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids allexpress and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is notresponsible or liable for any such statements.

TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonablybe expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governingsuch use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, andacknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their productsand any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may beprovided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products insuch safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products arespecifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet militaryspecifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely atthe Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products aredesignated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designatedproducts in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products Applications

Amplifiers amplifier.ti.com Audio www.ti.com/audio

Data Converters dataconverter.ti.com Automotive www.ti.com/automotive

DLP® Products www.dlp.com Communications and www.ti.com/communicationsTelecom

DSP dsp.ti.com Computers and www.ti.com/computersPeripherals

Clocks and Timers www.ti.com/clocks Consumer Electronics www.ti.com/consumer-apps

Interface interface.ti.com Energy www.ti.com/energy

Logic logic.ti.com Industrial www.ti.com/industrial

Power Mgmt power.ti.com Medical www.ti.com/medical

Microcontrollers microcontroller.ti.com Security www.ti.com/security

RFID www.ti-rfid.com Space, Avionics & www.ti.com/space-avionics-defenseDefense

RF/IF and ZigBee® Solutions www.ti.com/lprf Video and Imaging www.ti.com/video

Wireless www.ti.com/wireless-apps

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2010, Texas Instruments Incorporated

http://amplifier.ti.com

http://www.ti.com/audio

http://dataconverter.ti.com

http://www.ti.com/automotive

http://www.dlp.com

http://www.ti.com/communications

http://dsp.ti.com

http://www.ti.com/computers

http://www.ti.com/clocks

http://www.ti.com/consumer-apps

http://interface.ti.com

http://www.ti.com/energy

http://logic.ti.com

http://www.ti.com/industrial

http://power.ti.com

http://www.ti.com/medical

http://microcontroller.ti.com

http://www.ti.com/security

http://www.ti-rfid.com

http://www.ti.com/space-avionics-defense

http://www.ti.com/lprf

http://www.ti.com/video

http://www.ti.com/wireless-apps

Documents

PCB Design Guidelines for 0.5mm Package-On-Package · PDF fileApplication Report SPRABB3– June 2010 PCB Design Guidelines for 0.5mm Package-on-Package Applications Processor, Part