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PCB Layout Consideration

PCB Basics :

PCB methodologies originated in the United States PCB Units of Measurement

Units of measurement are therefore typically in Imperial units, not SI/metric units.

B d di i l d i i hzBoard dimensions are commonly measured in inches.zDielectric thickness & conductor length and width typically

measured in inches and mils.1 mil = 0.001 inches1 mil = .0254 mmzConductor thickness measured in ounces (oz)zConductor thickness measured in ounces (oz).The weigh of conductor metal in a square foot(ft2) of material.Typical thicknessz 0.5oz = 17.5mz 1.0oz = 35.0mz 2.0oz = 70.0m

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z 3.0oz = 105.0m

PCB Anatomy : PCB Conductors : Traces

LLL

Source: http://circuitcalculator.com/wordpress/wp-content/uploads/2007/04/pcb-trace-geometry-1.png

WLRs

WhL

ALR =

== Cu resistivity: =1.7E10-8m

Copper (Cu) is the most commonly used conductor in PCBs.z Traces and/or connectors may be plated in nickel followed by gold to provide a corrosion-

resistant electrically conductive. Trace Width (W) and Length (L) controlled by PCB layout engineer Trace Width (W) and Length (L) controlled by PCB layout engineerz Width and spacing between traces typically 5 mil in common fabrication processes

Trace Thickness (h) variable of fabrication processz Typically 0.5oz 3oz z Trend towards 0.25oz

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Signal Integrity Tip: All of the above affect the resistance, capacitance and impedance of the trace and must be well understood for high-speed design.

PCB Basics : PCB Conductors : Power Planes

Prepreg

Copper FoilSignal trace Prepreg

CorePrepregCore

Power plane

PrepregCorePrepreg

Power Planesz A solid layer of copper used to provide power or ground.z Typically use thicker copper layer than signal layers to reduce resistancez Typically use thicker copper layer than signal layers to reduce resistance.

Why are they needed?z Provide a stable, low-impedance path for power and ground signals to all

devices on the PCBz Shield signals between layers to minimize cross-talk

Signal Integrity Tip: By placing power and ground on opposite sides of thin core material, we can maximize the intra-plane

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pcapacitance. Also, this minimizes PCB warping.

PCB Layout Parasiticsy

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Calculation of Sheet resistance

R =X

ZY

Calculation of Sheet resistance (For Standard Copper PCB)

R

= RESISTIVITYX Y

X

Z

YX

SHEET RESISTANCE CALCULATION FOR1 OZ. COPPER CONDUCTOR:1 OZ. COPPER CONDUCTOR:

= 1.724 X 106 cm, Y = 0.0036cmR = 0 48 m ZR = 0.48 m

= NUMBER OF SQUARESXZ

XZ

8

R = SHEET RESISTANCE OF 1 SQUARE (Z=X)= 0.48m /SQUARE

Long Track Resistance Impact on ADC

16-BIT ADC,SIGNAL

5cmLong Track Resistance Impact on ADC

16 BIT ADC,RIN = 5k

SIGNALSOURCE

0 25 (10 il ) id0.25mm (10 mils) wide,1 oz. copper PCB trace

Assume ground pathresistance negligible

OHM L di t >1 LSB f d t d i PCB d t OHMs Law predicts >1 LSB of error due to drop in PCB conductor.z Consider a 16-bit ADC with a 5k input resistance,

z PCB track is 5cm of 0.25mm wide 1 oz. z The track resistance of nearly 0.1.

z The resulting voltage drop is a gain error of 0.1/5k (~0.0019%), z Over 1LSB (0.0015% for 16 bits).

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Trace/Pad CapacitanceTrace/Pad Capacitance

Example: Pad of SOIC

dA

L = 0.2cm W = 0.063cm

K= 4.7A

A = 0.126cm2

d = 0.073cm

dkAC311

= C = 0.072pFd3.11

K = relative dielectric constantA i 2

Reduce CapacitanceA = area in cm2

d = spacing between plates in cm

p1) Increase board thickness 2) Reduce trace/pad area 3) Remove ground plane

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3) Remove ground plane

Approximate Trace InductanceApproximate Trace Inductance

All dimensions are in mm

Example

L= 2.54cm =25.4mmMinimize Inductance

1) Use Ground planeW = .25mm

H = .035mm (1oz copper)

1) Use Ground plane 2) Keep length short: Halving

the length reduces i d b 44%

( )

Strip Inductance = 28.8nH

At 10MHz ZL = 1.86 a 3.6% error

inductance by 44%3) Doubling width only reduces

inductance by 11%

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At 10MHz ZL 1.86 a 3.6% error in a 50 system

Via ParasiticsVia Parasitics

Via Inductance Via Capacitance

+

= 14ln2dhhL

12

155.0DDTDC r=

D2 = diameter of clearance hole in the

nH

L = inductance of the via, nHH = length of via, cm

D = diameter of via cm

D2 diameter of clearance hole in the ground plane, cm

D1 = diameter of pad surrounding via, cmT = thickness of printed circuit board, cm

= relative electric permeability of circuitD = diameter of via, cmConsider a power supply pin of an op

amp that goes through a via to the power plane of an 0.157 cm thick board, the

= relative electric permeability of circuit board material

C = parasitic via capacitance, pF

r

p ,diameter of the via is 0.041 cm

)1570(4

Consider a signal coming from the back of the board to the top of the

board through a via. Board thickness = 0 157cm

+

= 1041.0

)157.0(4ln)157.0(2L

L = 1.2nh

thickness = 0.157cm, D1=0.071cm D2 = 0.127

C = 0 51pf

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C = 0.51pf

Op-Amp SchematicOp-Amp SchematicLow Frequency versus High Frequency

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Is My Design Low Speed?Is My Design Low Speed?

Im measuring low frequency signals, why should I care about the speed?zSome low speed circuits, actually have very fast switching edgesSome low speed circuits, actually have very fast switching edgeszE.g. ADCs, auto-zero amplifiers

Period is long 10us

but edge is fast ~ 5ns

Current is moving at 200MHz!

Design low inductive current return paths

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Design low inductive current return paths

How to start with good layout g y

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SchematicSchematic

A strong and reliable structure (including PCBs) requires a solid foundation, the SCHEMATIC is the PCBs foundation!

A good layout starts with a good Schematic!A good layout starts with a good Schematic!Schematic flow and content are essential Include as much information as you canWhat should you include?

Good foundation

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Items to Include on a SchematicItems to Include on a Schematic

N tNotesComponent tolerances and case sizesPart numbers (internal/external/alternative) ( )Test informationPower dissipationControlled impedance and line matchingControlled impedance and line matchingComponent de-rating Thermal requirementsqKeep outsMechanical considerationsCritical component placementCritical component placementBoard stack up

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Schematic C10 1uF+5V Put C4 and C7 on Place this cap right at pin 14 to digital groundSchematic40 MHz

0.1uF

U1

+5V

R6301

S1C4

2.2uF

C5

40 MHz OSC Out

Must be right at op amp supply

pins

back of board right under the

power supply pin.

Run 40MHz traces on bottom of the board ensure signal

+

R3562 ADA4860-

1

-

+

R4210

C50.01uF

R5562 C6

0.01uF

U2

VIN

VOUT

R750

of the board ensure signal trace is the same length

40 MHz OSC Out

R11K

-5V

C2SAT

C3SAT C72.2uF

Must be right at op amp supply

pins

R250+5V

FREQUENCY ADJUST1.0 C2=C3, use these 2 capacitors to adjust the -3dB BW

+

AD590

ADP667

Linear Regulator

Temperature Sensor+12V +5

V+ +

U3

U4D11N4148

C810uFC

C1210uFCase

+5V

+5V

1K

Derating Table

R1

R2R3

VALUE123

62mW 10mWITEM REF DES ACTUALRATING

See critical component placement drawing for location

AD590 VOUT

Linear Regulator

-12V -5V

++

U5

D21N4148

Case size 1210

C90.01uF

C110.1uF

Case size1210

C1310ufCase

C1610uF

Case size

-5V R81K

C1C2C3U1

U2

45678

Case size1210 C14

0.1uFC15

0.1uF

Case size1210

2.0 All Resistors in ohms unless noted otherwise.3.0 All capacitors in pF unless noted otherwise. Signal 1 Analog Ground 1

Power plane

BOARD STACK UP1.0 All resistors and capacitors are 0603 case size unless noted otherwise.

4.0 Run analog traces on Signal 1 layer, run digital traces on Signal 2 layer

NOTES:

5 0 Remove ground plane on all layers under the mounting pins of U2

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6.0 U1 SOIC-14, U2 SOT-23-6, U3, SOIC-8, U4 SOIC-80.062"Digital Ground

Analog Ground 2 Signal 2

5.0 Remove ground plane on all layers under the mounting pins of U2

Location! Location! Location!

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Location, Location, Location, ,Critical Component Placement and Routing

Signal

Power

TempTemp Sensor

2020Not optimal placement

Location, Location, Location, ,Critical Component Placement and Routing

Temp Sensor

Signal

Power

2121Improved placement

Current Return Path

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AC + DC Current Return PathAC + DC Current Return Path

DC C R P h l i

iAC Current Return Path ~ least impedance(inductance)

DC Current Return Path ~ least resistance

i

23

Ground PlaneGround Plane

I

II

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Ground Plane and Trace RoutingGround Plane and Trace Routing

DigitalAnalog

R

e

s

i

s

t

o

r

ClockWrong Way CircuitryCircuitryCircuitryWrong Way

Sensitive Analog Circuitry Disrupted by Digital Supply Noise

IDIA INCORRECT

ANALOGCIRCUITS

DIGITALCIRCUITSVD VA

+ +

VIN

INCORRECT

25IDIA + IDGNDREF

Ground Plane and Trace RoutingGround Plane and Trace Routing

AnalogCircuitry

R

e

s

i

s

t

o

r

Right Way DigitalCircuitry

ClockSensitive Analog

Circuitry Safe from

Right Way

CircuitryCircuitry Safe from Digital Supply Noise

ID

ANALOG DIGITAL+ +

IDIA CORRECT

ANALOGCIRCUITS

DIGITALCIRCUITSVD VA VIN

GND

26ID

IAGNDREF

Example 1: Know where the current returnsExample 1: Know where the current returns

+5V+5V

ibib

2 ib

V ib

2 ib

ibAD8226(in-amp)

ib

ib

V AD8226(in-amp)

ib

ib

ADR3612.5V

PNP Input Transistors Current In = Current Out

Saturates amplifier! ADR3612.5V2 ib

PNP Input TransistorsSmall bias current

Current In = Current Out

Nowhere for current to go!

Example 2: Know where the current returnsExample 2: Know where the current returns

100k100

AD8610

1kV i1 i2

0.01 0.01parasiticresistancein trace

If i1 = 10 mAV = 100uVOutput Error = 100mVOutput Error = 100mV

Example 2: Be aware of currents during Example 2: Be aware of currents during PCB LayoutFor Low Frequency Signals

100k

100k100

connector

From source

AD86101-IN2+IN3

+VSOUT

8

7

6

100

0.1uFAD8610

1k

P d L d GND

Signal GNDconnector +IN3

-VS4OUT 6

5 1k

0.1uF

1k

star ground

Power from power planeOnly top microstrip and Ground shown

Power and Load GNDg

Disturbance through parasiticGround is separated under

resistance is common to both inputs

Ground is separated undersensitive input areaLarge output current goes to power groundI t d ti d t d t i tInput area ground tied to power ground at one point

Grounding Consideration

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Grounding the Mixed Signal ICGrounding the Mixed Signal IC

Which One is Better?VA VD VA VD

ANALOGCIRCUITS

DIGITALCIRCUITS

AGND DGND

MIXEDSIGNALDEVICE

VA VD

ANALOGCIRCUITS

DIGITALCIRCUITS

AGND DGND

MIXEDSIGNALDEVICE

ONEGROUNDPLANE WITH

VA VD

A A D D

AGND DGNDSTAR

GROUND

AGND DGNDWITHGOOD

LOCATIONS

ANALOGGROUND PLANE

DIGITALGROUND PLANE

DADA

DIGITALSUPPLY

ANALOGSUPPLY

DA

DIGITALSUPPLY

ANALOGSUPPLY

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Another Split Ground Plane IdeapWhy every power pin need decoupling Caps?

VAFERRITE BEAD

VD

VDA D

VA

FERRITE BEAD

L L

CSTRAY

DATA

LP LP

RP RP

ANALOGCIRCUITS

DIGITALCIRCUITS

BUFFERGATE OR

REGISTER

R

AIN/

DATABUS

DATA REGISTERA B

CSTRAY

OUTCIN 10pF

RP RP

AGND DGND

LP LPIA ID

32A A DVNOISE

A = ANALOG GROUND PLANE D = DIGITAL GROUND PLANE

SHORTCONNECTIONS

Power Supply Bypassingpp y yp g

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Power Supply BypassingPower Supply Bypassing

Bypassing is essential to high speed circuit performance

Capacitors right at power supply pinszCapacitors provide low

impedance AC return pzProvide local charge storage

for fast rising/falling edgesKeep trace lengths short

VDDint

Keep trace lengths shortPut Smaller Values Capacitor

Closer to the PinCl t l d t

CGATE

PMOS

NMOS

Close to load returnzHelps minimize transient

currents in the ground planeVDD

VDDGND High to low

t iti

3434

VDD

GND

transition

Bypassing Capacitor Layoutyp g p y

C CVCC C CorrectVCCGND

VCC

Via

C W

LQFPLFCSP

VCC

VCCC WrongLFCSP

GND

WrongCVCCGNDGND

No long trace under ICz Short trace then to bottom by via

Short trace to GND or Power under ICCorrectWrong

Short trace to GND or Power under IC. Short trace to decouple Capacitors

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Capacitor ChoicesCapacitor Choices

0603 0612

3636

Power Supply BypassingPower Supply Bypassing

ESR (Equivalent SeriesESR (Equivalent Series Resistance)z RsC itCapacitancezXC = 1/2fC

ESL (Equivalent Series ( qInductance)zXL=2fL

Effective Impedance

At Series resonance zXL=XC

3737

zXL XCzZ = R

Multiple Parallel Capacitors Multiple Parallel Capacitors

1F330F 0.1F 0.01F

1 x 330F T520, 1 x 1.0F 0603, 2 x 0.1F 0603, and 6 x 0.01F 0603

*

3838 *Courtesy of Lee Ritchey

2 x (1 x 330F T520, 1 x 1.0F 0603, 2 x 0.1F 0603, and 6 x 0.01F 0603)

Power Supply BypassingPower Supply BypassingFerrite Beads

Ferrite BeadszProvide no DC drop

I i d ith L1

+VS

Without Ferrite BeadzIncrease impedance with increasing frequency

U1AD8138AR

C110nF

L1

-35dB@50MHz

Without Ferrite Bead50mVpp@50MHz =890V14-bit system with 2V FS

1LSB = 120V

With Ferrite BeadAt 50MHz Ferrite bead Z = 60

B Z 0 32 How much noise is

present at the output of a VOCM8

2

5 OUT3

AD8138AR 10nF1LSB = 120VNoise is equivalent to 7 LSBs

Bypass cap Z = 0.32 Bead and bypass cap provideAdditional 45dB of attenuation

AD8138 differential amplifier, with 50mVpp@50MHz the

1 4 OUT+

650mVpp@50MHz =5V

Noise is well below 1 LSB50mVpp@50MHz the supply linezWithout a ferrite bead?

C110nFL2

39

zWith a ferrite bead?VS

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IC Package and PCB Layout Issues

for Thermal Performance

40

Thermal Performance for Different PackagesThermal Performance for Different Packages

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Thermal Performance for Different LayoutsThermal Performance for Different Layouts

LQFP LFCSP42

Thermal Design Technique Layout ExampleThermal Design Technique Layout Example

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