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Low Power TestingLow Power Testing

SantanuSantanu ChattopadhyayChattopadhyay

Dept. of Electronics & Elec. Comm.Dept. of Electronics & Elec. Comm. EnggEngg..

Indian Institute of Technology,Indian Institute of Technology, KharagpurKharagpur

EE--mail:mail: [email protected]@ece.iitkgp.ernet.in

IntroductionIntroduction

SystemSystem--onon--aa--chip (chip (SoCSoC) revolution challenges) revolution challengesboth design and test engineers.both design and test engineers.

A circuit or system consumes more power inA circuit or system consumes more power intest mode than in normal mode.test mode than in normal mode.

Can give rise to severe hazard in circuitCan give rise to severe hazard in circuitreliability, or instant circuit damage.reliability, or instant circuit damage.

Increases product cost, difficulty in performanceIncreases product cost, difficulty in performanceverification, reduced autonomy of portableverification, reduced autonomy of portablesystems, and decrease in overall yield.systems, and decrease in overall yield.

Test challengesTest challenges

Escalating transistor counts, increasing chipsEscalating transistor counts, increasing chipscomplexity, while maintaining its size.complexity, while maintaining its size.

Testing is one of the most expensive and problematicTesting is one of the most expensive and problematicaspects in a circuit design cycle.aspects in a circuit design cycle.

Traditionally test engineers evaluated test techniquesTraditionally test engineers evaluated test techniquesaccording to area, fault coverage, test application timeaccording to area, fault coverage, test application timeetc.etc.

The new class of low power systems make powerThe new class of low power systems make power

management a critical parameter that cannot be ignoredmanagement a critical parameter that cannot be ignoredin test development.in test development.

Why test power is higherWhy test power is higher

Test efficiency correlates with toggle rate.Test efficiency correlates with toggle rate.

In test mode, switching activity of all nodes is often several tIn test mode, switching activity of all nodes is often several timesimeshigher than during normal operation.higher than during normal operation.

Often parallel testing is used inOften parallel testing is used in SoCsSoCs to reduce test applicationto reduce test applicationtime, which might result in excessive energy and powertime, which might result in excessive energy and powerdissipation.dissipation.

DFT circuitry designed to reduce test complexity is often idleDFT circuitry designed to reduce test complexity is often idleduring normal operation, but might be intensively used in testduring normal operation, but might be intensively used in testmode.mode.

Correlation between successive functional inputs may beCorrelation between successive functional inputs may be

significant, however, for test patterns it is generally kept lowsignificant, however, for test patterns it is generally kept low..

Ad hoc industrial solutionAd hoc industrial solution -- II

OversizingOversizingpower supply, package, and coolingpower supply, package, and coolingto withstand increased current.to withstand increased current.

Insert breaks into the test process to avoid hotInsert breaks into the test process to avoid hot

spots.spots.

Increases both hardware costs and time.Increases both hardware costs and time.

Ad hoc industrial solutionAd hoc industrial solution -- IIII

Testing with reduced operating frequency.Testing with reduced operating frequency. Reduces hardware.Reduces hardware.

Increases test time and might lead to aIncreases test time and might lead to a

loss of defect coverage due to masking ofloss of defect coverage due to masking of

dynamic faults.dynamic faults.

Lengthens test time, so does not reduceLengthens test time, so does not reduce

the total energy consumed during test.the total energy consumed during test.


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Ad hoc industrial solutionAd hoc industrial solution -- IIIIII

SystemSystem--underunder--test partitioning.test partitioning.

Appropriate test planning.Appropriate test planning.

Increases hardware costs and test time.Increases hardware costs and test time.

TerminologiesTerminologies

Energy:Energy:The total switching activity during testThe total switching activity during testapplication. Affects battery lifetime.application. Affects battery lifetime.

Average power:Average power:Total distribution of powerTotal distribution of powerover a time period. Equals the ratio of Energy toover a time period. Equals the ratio of Energy to

TestTest--time.time.

Instantaneous power:Instantaneous power: Power consumed at anyPower consumed at anygiven instant.given instant.

Peak power:Peak power: Highest power value at any givenHighest power value at any giveninstant.instant.

Terminologies (contd.)Terminologies (contd.)

LetLetEEvkvk be the energy consumed by the circuitbe the energy consumed by the circuit

after application of successive input vectorsafter application of successive input vectors VVkk--11andand VVkk..

Instantaneous power,Instantaneous power, PPinstinst(V(Vkk) =) =EEvkvk / T,/ T,where,where,

TTis the clock period.is the clock period.

Peak powerPeak power PPpeakpeak == maxmaxkk[[PPinstinst ((VVkk))]] ==

maxmaxkk(E(Evkvk)/T)/T..

Average power,Average power, PPaveave ==EEtotaltotal/ [(/ [(LengthLengthtesttest)T)T],],wherewhere

EEtotaltotalis the total energy consumed duringis the total energy consumed during

application of complete test sequence.application of complete test sequence.

Problems induced by excessive testProblems induced by excessive test

powerpower

A nondestructive test must satisfy all the powerA nondestructive test must satisfy all the powerconstraints defined in the design phase.constraints defined in the design phase.

Cost constraints typically require plasticCost constraints typically require plasticpackages.packages.

Excessive switching leads to increased current flowExcessive switching leads to increased current flowin the CUT , requiring expensive packages for thein the CUT , requiring expensive packages for theremoval of excessive heat.removal of excessive heat.

ElectromigrationElectromigration (due to temperature and current(due to temperature and current

density) causes erosion of conductors anddensity) causes erosion of conductors andsubsequently leads to circuit failure.subsequently leads to circuit failure.


power (contd.)power (contd.)

Autonomy of batteryAutonomy of battery--powered remote and portablepowered remote and portable

systems suffers from increased activity.systems suffers from increased activity. Remote system operation occurs mostly in standRemote system operation occurs mostly in stand--by modeby mode

with almost no power consumption, interrupted by periodicwith almost no power consumption, interrupted by periodicselfself--tests.tests.

Power saving during test mode directly prolong batteryPower saving during test mode directly prolong batterylifetime.lifetime.

Aggressive timing makes it essential for tests to identifyAggressive timing makes it essential for tests to identifyslow chips through delay testing.slow chips through delay testing.

During functional testing of a die just after waferDuring functional testing of a die just after waferetching, the unpackaged bare die has very littleetching, the unpackaged bare die has very littleprovision for power or heat dissipation.provision for power or heat dissipation.



Memory testing using wafer probes.Memory testing using wafer probes.

Wafer probing with poor powerWafer probing with poor power--supply connections results insupply connections results in

significant, high power and ground noise caused by highsignificant, high power and ground noise caused by high

switching activity during testing.switching activity during testing.

This excessive noise can erroneously change the logic state ofThis excessive noise can erroneously change the logic state of

circuit lines causing some good die to fail.circuit lines causing some good die to fail.

BIST using LFSRBIST using LFSR--generated test patterns takes longergenerated test patterns takes longer

to reach acceptable level of fault coverage. Thisto reach acceptable level of fault coverage. This

increases total power consumption.increases total power consumption.


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ScanScan--based selfbased self--test architectures are populartest architectures are popular

because of their low impact on performance andbecause of their low impact on performance and

area.area.

Expensive, since each test pattern requires a powerExpensive, since each test pattern requires a power--

consuming shift operation to provide test patternsconsuming shift operation to provide test patterns

and evaluate response.and evaluate response.

It is thus important to reduce power dissipationIt is thus important to reduce power dissipation

during scan shifting.during scan shifting.

Low power external testingLow power external testing

techniquestechniques

Low power ATPG algorithmsLow power ATPG algorithms

Ordering techniquesOrdering techniques

Input controlInput control

Vector compaction and data compressionVector compaction and data compression

Scan chain transformationScan chain transformation

Clock scheme modificationClock scheme modification

Low power ATPG algorithmsLow power ATPG algorithms

Exploiting dont cares:Exploiting dont cares:

Modify ATPG algorithm (for example, pathModify ATPG algorithm (for example, path--orientedoriented

decisiondecision--making (making (PodemPodem)) where assignment of)) where assignment ofdont caredont carebitsbits

minimizes the number of transitions occurring in the CUTminimizes the number of transitions occurring in the CUT

between two consecutive test vectors.between two consecutive test vectors.

Exploiting redundancy:Exploiting redundancy:

Modify faultModify fault--dropping principle. A fault is dropped only if itdropping principle. A fault is dropped only if it

has been covered by at leasthas been covered by at least MMpatterns.patterns.

Select patterns from the redundant set to maximize faultSelect patterns from the redundant set to maximize faultcoverage and minimize switching.coverage and minimize switching.

Ordering techniquesOrdering techniques Test vector reordering:Test vector reordering:

Modify the order in which test vectors are appliedModify the order in which test vectors are applied

to the CUT. Applying test vectors {110111, 0000000,to the CUT. Applying test vectors {110111, 0000000,

0010010, 0111111, 1100010} needs 372 transitions,0010010, 0111111, 1100010} needs 372 transitions,

however, {110111, 0010010, 1100010, 0111111,however, {110111, 0010010, 1100010, 0111111,

0000000} require 352 transitions.0000000} require 352 transitions.

Ordering techniques (contd.)Ordering techniques (contd.)

ScanScan--latch ordering:latch ordering:Scan flipScan flip--flops are ordered to reduce transitions.flops are ordered to reduce transitions.

Ordering scan flipOrdering scan flip--flops like {S0,S2,S1}, number offlops like {S0,S2,S1}, number of

transitions is 328. However, with cell order {S2, S1,transitions is 328. However, with cell order {S2, S1,

S0}, number of transitions is 296.S0}, number of transitions is 296.

Input controlInput control

Identify an input control pattern for a fullIdentify an input control pattern for a full--scanscancircuit.circuit.

The pattern is applied to the circuits primaryThe pattern is applied to the circuits primary

inputs during scan.inputs during scan.

This minimizes or eliminates switching activityThis minimizes or eliminates switching activity

in the combinational part of the circuit.in the combinational part of the circuit.

Can be used in conjunction with vectorCan be used in conjunction with vector-- and/orand/or

scanscan-- reordering.reordering.


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Vector compaction and DataVector compaction and Data

compressioncompression

Serves dual purpose of test time and scan powerServes dual purpose of test time and scan power

reduction.reduction.

Special codes, likeSpecial codes, like GolombGolomb codes, Huffmancodes, Huffman

codes etc. are used to compress the test vectors.codes etc. are used to compress the test vectors.

The coding strategy often fills up the dont caresThe coding strategy often fills up the dont cares

in the patterns in such a way that the scanin the patterns in such a way that the scan

transitions are minimized.transitions are minimized.

Reduces both peak and average power.Reduces both peak and average power.

Scan chain transformationScan chain transformation

Multiple scan chains instead of a single one canMultiple scan chains instead of a single one can

be used.be used.

It reduces transitions by upto 76%.It reduces transitions by upto 76%.

Both Q and Q lines can be utilized.Both Q and Q lines can be utilized.

Different types of flipDifferent types of flip--flop combinations can beflop combinations can be

tried out.tried out.

All these schemes can be coupled with testAll these schemes can be coupled with test

vector reordering, scan chain ordering etc.vector reordering, scan chain ordering etc.

Clock scheme modificationClock scheme modification

Test powers major contributor is the clock tree.Test powers major contributor is the clock tree.

Generate and order test sets so that some scanGenerate and order test sets so that some scanchains can have their clocks disabled forchains can have their clocks disabled forportions of the test set. This preventsportions of the test set. This prevents flipflopsflipflopsfrom transitioning and the reduces test power.from transitioning and the reduces test power.

Gated clockGated clock for scan path and the clock treefor scan path and the clock treefeeding the scan path. Lowers transitions andfeeding the scan path. Lowers transitions and

thus minimizes average and peak power, andthus minimizes average and peak power, andenergy consumption.energy consumption.

Low power BIST techniquesLow power BIST techniques

BuiltBuilt--InIn--SelfSelf--TestTest schemes are popular for their abilityschemes are popular for their abilityto run independently.to run independently.

Low power approaches for BIST are,Low power approaches for BIST are,

Test scheduling algorithmsTest scheduling algorithms

Low power BIST pattern generatorsLow power BIST pattern generators

Toggle suppressionToggle suppression

LFSR tuningLFSR tuning

Vector filtering BISTVector filtering BIST

Circuit partitioningCircuit partitioning

Test scheduling algorithmsTest scheduling algorithms

A distributed BIST control scheme can be used thatA distributed BIST control scheme can be used that

can schedule the execution of each BIST element tocan schedule the execution of each BIST element to

keep power dissipation under specified limit.keep power dissipation under specified limit.

Reduces average power, however, increases test time.Reduces average power, however, increases test time.

SeveralSeveral SoCSoC test scheduling algorithms have beentest scheduling algorithms have been

proposed based on test bus partitioning, rectangleproposed based on test bus partitioning, rectangle

packing, simulated annealing, genetic algorithm etc.packing, simulated annealing, genetic algorithm etc.

The schemes take care of power and precedence asThe schemes take care of power and precedence as

constraints.constraints.


Dual speed LFSR:Dual speed LFSR:

Based upon two different speedBased upon two different speed LFSRsLFSRs..

CUT inputs with elevated transition densities areCUT inputs with elevated transition densities areconnected to slowconnected to slow--speed LFSRspeed LFSR

Significantly reduces average power and energySignificantly reduces average power and energyconsumption, without decreasing fault coverage.consumption, without decreasing fault coverage.

Hybrid Cellular Automata:Hybrid Cellular Automata:

Uses both linear and nonUses both linear and non--linear rules to come uplinear rules to come upwith CA structure to reduce test power in the CUT,with CA structure to reduce test power in the CUT,while attaining high fault coverage.while attaining high fault coverage.


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(contd.)(contd.)

Clock gating:Clock gating:

Uses a modified LFSR based approach.Uses a modified LFSR based approach.

Gated clock scheme is used for the test pattern generator andGated clock scheme is used for the test pattern generator andthe clock tree feeding it.the clock tree feeding it.

Weighted pseudorandom vectors:Weighted pseudorandom vectors:

LFSR structure can be modified by adding weight sets to tuneLFSR structure can be modified by adding weight sets to tune

the pseudorandom vectors signal probabilities.the pseudorandom vectors signal probabilities.

Scan chain architecture can be modified to increaseScan chain architecture can be modified to increase

correlation betweencorrelation between neighbouringneighbouringbits in the scan chain,bits in the scan chain,

though the patterns generated by the LFSR arethough the patterns generated by the LFSR are equiprobableequiprobable..

Toggle suppressionToggle suppression

Modifies the scanModifies the scan--path structures scan cells.path structures scan cells.

The CUT inputs remain unchanged during aThe CUT inputs remain unchanged during a

shift operation.shift operation.

This allows for 70This allows for 70--90% energy saving over a90% energy saving over a

standard scanstandard scan--based BIST architecture.based BIST architecture.

Increases area overhead and may lead toIncreases area overhead and may lead to

performance degradation.performance degradation.

LFSR tuningLFSR tuning

LFSR pattern generation capability dependsLFSR pattern generation capability dependsupon the characteristic polynomial and the initialupon the characteristic polynomial and the initialseed.seed.

It has been found that polynomial selection doesIt has been found that polynomial selection doesnot influence energy consumption, seednot influence energy consumption, seedselection is a more important parameter.selection is a more important parameter.

Simulated annealing based strategies have beenSimulated annealing based strategies have been

proposed in the literature to select anproposed in the literature to select an LFSRsLFSRsseed to provide lowest energy consumption.seed to provide lowest energy consumption.

Vector filtering BISTVector filtering BIST

LFSRsLFSRs generate a good number of unnecessarygenerate a good number of unnecessary

patterns. These do not detect further faults.patterns. These do not detect further faults.

Such patterns can be filtered out.Such patterns can be filtered out.

Use a decoding logic to store first and last vectors ofUse a decoding logic to store first and last vectors of

thethe nonnon--detectingdetectingsequences. A Dsequences. A D--type fliptype flip--flopflop

switches the enable/disable mode of the LFSRswitches the enable/disable mode of the LFSR

outputs.outputs.

Vector filtering with toggle suppression reduces testVector filtering with toggle suppression reduces testpower by several orders of magnitude.power by several orders of magnitude.

Circuit partitioningCircuit partitioning

Partition the original circuit into two structural subPartition the original circuit into two structural sub--

circuits so that two different BIST sessions cancircuits so that two different BIST sessions cansuccessively test each subsuccessively test each sub--circuit.circuit.

DFT engineers partition the circuit and plan the testDFT engineers partition the circuit and plan the testsession to minimize the average and peak powersession to minimize the average and peak powerconsumption.consumption.

Reduces total energy consumed during BIST since theReduces total energy consumed during BIST since thetest length for the two subtest length for the two sub--circuits is not much morecircuits is not much morethan that of the original circuit.than that of the original circuit.

Area overhead is very low and there is almost noArea overhead is very low and there is almost nopenalty on circuit performance.penalty on circuit performance.

Low power RAM testingLow power RAM testing

Reordering of read and write accesses canReordering of read and write accesses cansignificantly reduce energy consumption.significantly reduce energy consumption.

Test time remains same.Test time remains same.

Average power is thus minimized.Average power is thus minimized.


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Selecting effective low power testingSelecting effective low power testing

strategystrategy

Implementation context:Implementation context:Whether the technique isWhether the technique isfor external testing, scan, scan BIST etc.for external testing, scan, scan BIST etc.

Way to address test power minimization:Way to address test power minimization:Act onAct ontest sequence or on the test architecture.test sequence or on the test architecture.

Relax classical test constraints:Relax classical test constraints: Fault coverage, test time must remain unaltered.Fault coverage, test time must remain unaltered.

Area overhead from hardware modification must beArea overhead from hardware modification must beacceptably low.acceptably low.

Must maintain circuit performance.Must maintain circuit performance.

Effect on the design flow, and hence on the design time mustEffect on the design flow, and hence on the design time mustbe small enough for the solution to be acceptable.be small enough for the solution to be acceptable.

Designers must make the clock tree as small as possible orDesigners must make the clock tree as small as possible ordisable clock signals as often as possible.disable clock signals as often as possible.

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