1 © 2013 The MathWorks, Inc.

Per Knopfdruck vom Modell zum Code

mit automatischer Generierung von

Seriencode

Model to Code via Push-Button Production Code Generation

Michael Fröstl

Pilot Engineering, Production Code Generation

MathWorks

http://www.mathworks.de/embedded-code-generation/

2

switch(braindump)

{

3

case ‘Applications’:

4 http://www.mathworks.com/company/user_stories

5

case ‘Programming’:

6

ASCII MATLAB

C

C++

ASM

IEC 61131-3

7

case ‘Hardware’:

8

MCU /

DSP

ARM®

Analog Devices®

Atmel®

Freescale™

Infineon®

Intel®

Microchip®

NXP™ Renesas®

STMicroelectronics®

Texas Instruments™

Xilinx®

9

case ‘Operating Systems’:

10

OS

Green Hills® Integrity RTOS

Embedded Linux®

Texas Instruments™ DSP/BIOS™

Wind River® VxWorks®

OSEK-OS

Microsoft® Windows Embedded

QNX® Neutrino® RTOS

Android™

11

case ‘Standards’:

12

NORM

AUTOSAR MISRA C

ISO 26262

IEC 61508

EN 50128

DO-178B/C

13

default :

printf(“Need a break?”);

}

14

MBD_Overview();

15

INTEGRATION

IMPLEMENTATION

PLC MCU DSP FPGA ASIC

Structured

Text VHDL, Verilog C, C++

DESIGN

Environment Models

Physical Components

Algorithms

RESEARCH REQUIREMENTS

TE

ST

& V

ER

IFIC

AT

ION

TEST

SYSTEM

16

INTEGRATION

IMPLEMENTATION

DESIGN

TE

ST

& V

ER

IFIC

AT

ION

RESEARCH REQUIREMENTS

Environment Models

Mechanical

Control Algorithms

Electrical

Supervisory Logic

Structured

Text VHDL, Verilog C, C++

TEST

SYSTEM

MCU DSP FPGA ASIC PLC

17

switch(topics)

{

18

case ‘Fixed-Point’:

19

void diffEq( void ) { /* Implements a fixed point first order difference equation */ int Prod; long Accum; static short lastVal=0; short a=0x7eb8; /* 0.99 in s16,15 */ short oneminusa=0x0148; /* .01 in s16,15 */ short temp; Prod = gAlg_in1 * gAlg_in1; temp = Prod >> 15; Accum = a*lastVal + oneminusa*temp; gAlg_out1 = (short)(Accum >> 15); lastVal = gAlg_out1; }

Keep track of binary point location

No saturation or rounding

Convert variables to integer types

Need lots of comments

to understand code

20

21

Fixed-Point Design Workflow

Proof of Concept

Design and simulate floating-point algorithms

Iterate on algorithm trade-offs

Verifying Fixed-Point Algorithms

Verify fixed-point results against floating-point reference

Verify results against original requirements

Model Hardware Constraints

Convert algorithm to fixed-point and simulate

Iterate on implementation trade-offs

22

case ‘Code Generation’:

23

24

25

Algorithm Export (MAAB Model, MISRA C )

A B C

M

I N P U T

B L U E G R E E N R E D

P O W E R

RGBSplit-4BLACK BOX

V R C S

Input

Drivers

Output

Drivers

Special

Device

Drivers

Comm

Drivers

Scheduler/Operating System

and Support Utilities

Communication

Interfaces

Sensors

Actuators

Special

Interfaces

Tuning

Generated

Algorithm

Code

Included

Legacy

Code

Controller

Model

1MathWorks Automotive Advisory Board Style Guidelines, v3.0 2MISRA AC AGC: Guidelines for the Application of MISRA-C:2004 in the Context of Automatic Code Generation

1 2

26

27

28

29

30

31

A B C

M

I N P U T

B L U E G R E E N R E D

P O W E R

RGBSplit-4BLACK BOX

V R C S

Generated

Algorithm

Code

Input

Drivers

Output

Drivers

Special

Device

Drivers

Comm

Drivers

Scheduler/Operating System

and Support Utilities

Communication

Interfaces

Sensors

Actuators

Special

Interfaces

Tuning

Included

Target

Optimized

Code

Controller

Model

Algorithm Export (MAAB Model, Target Code)

32

33

34

A B C

M

I N P U T

B L U E G R E E N R E D

P O W E R

RGBSplit-4BLACK BOX

V R C S

Generated

Algorithm

Code

Input

Drivers

Output

Drivers

Special

Device

Drivers

Comm

Drivers

Scheduler/Operating System

and Support Utilities

Communication

Interfaces

Sensors

Actuators

Special

Interfaces

Tuning

Optional

Target

Optimized

Code

Controller Model

w/Driver Blocks

Full Executable (Target Model, Target Code)

35

36

37

case ‘Targets’:

38 http://www.mathworks.de/hardware-support/home.html

41 http://www.mathworks.de/services/consulting/areas/developing-embedded-targets.html

42

case ‘Getting ARMed’:

43

INTEGRATION

IMPLEMENTATION

DESIGN

TE

ST

& V

ER

IFIC

AT

ION

RESEARCH REQUIREMENTS

Environment Models

Mechanical

Control Algorithms

Electrical

Supervisory Logic

Structured

Text VHDL, Verilog C, C++

TEST

SYSTEM

MCU DSP FPGA ASIC PLC

44

Create Model

45

Stateflow

Simulink

46

Simulate and Test (on Host)

47

49

Generate ARM Optimized Code

50

Embedded

Coder

51

Processor-in-the-Loop

Execution Profiling

52 STM32F

Cable

Host Target

53

Add I/O Blocks, Generate Code, and

Deploy!

54

STM32F4xx

Blockset

55

default :

printf(“Time for a

break!”);

}

56

INTEGRATION

IMPLEMENTATION

DESIGN

TE

ST

& V

ER

IFIC

AT

ION

RESEARCH REQUIREMENTS

Environment Models

Mechanical

Control Algorithms

Electrical

Supervisory Logic

Structured

Text VHDL, Verilog C, C++

TEST

SYSTEM

MCU DSP FPGA ASIC PLC