Performed by: Yulia Okunev

Instructor: Yossi Hipsh

High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

הטכניון - מכון טכנולוגי לישראל

הפקולטה להנדסת חשמל

Technion - Israel institute of technologydepartment of Electrical Engineering

דו”ח סיכום פרויקט -סופי

Developing fast clock source with deterministic jitter

2015חורף 1

AbstractHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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Designing fast clock source with deterministic jitter for high speed phenomena experiment.

Part A:Studying the theory and performing simulation

Part B: Building an engineering models and designing the PCB

System descriptionHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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• Engineering model to function as a 4 times faster clock source with deterministic jitter for Jitter phenomena experiment

• Engineering model to function as “delays array bank”, which divides the clock source into four routes, which feed 4 consumers with clock signals. This clock signals arrive within predetermined skew intervals. This unit will be used for skew phenomena experiment.

• Printed circuit board which will be used to create 8 times faster clock source

SpecificationHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

• Hardware:Power Divider - ZN4PD1-50-S+ mini-CircuitsPower Combiner - ZN4PD1-50-S+ mini-CircuitsCoaxial cables

• Software : Simulation- SigXplorerSchematic – Orcad (Cadence)Layout – PCB designer (Cadence)

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System Block DiagramHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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