PG Diploma in Integrated VLSI and Embedded System Design (DIVESD)- Modules

7/26/2019 PG Diploma in Integrated VLSI and Embedded System Design (DIVESD)- Modules

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PG Diploma in Integrated VLSI and Embedded System Design (DIVESD)- Modules

Programming Concepts, Object Oriented Programming with C++ AND Data Structure For Language Processing 110 Hours

SOFTWARE ENGINEERING CONCEPTS Introduction to SE The software process SDLC Describe and compare different SDLC models Project management Software implementation and maintenance Structured programming, language standards Software testing SQA, ISO, CMM Configuration management Software process and project metrics

Design conceptsPROGRAMMING WITH C++ & DS Difference between C and C+ Linux C++ Debugging Class and Objects Constructors and Destructors Inheritance Multiple Inheritances Friend functions and Classes Polymorphism Overloading functions Copy Constructors

Run Time Polymorphism Virtual Functions Class and Function Templates Exception Handling NamespacesIntroduction to Data Structures Algorithms and Abstract data types, Complexity of Algorithms Linked lists types, implementation and applications Stacks Implementation and applications Queues types, implementation and applications Various Searching and Sorting Algorithms

Treestypes, implementation and applications Graphs implementation and applications

Advance Microcontroller Programming with 8 Bit Microcontroller, ARM Processor and their Techniques 130 Hours

8-BIT MICROCONTROLLERS AND INTERFACING Processor Architecture (Princeton and Harvard) RISC & CISC Microcontrollers Features & Memories Internal Architecture Addressing Modes Overview Instruction Set Data Movement Instructions Memory Instructions Arithmetic & Bit Operation Instructions Hardware Features Reset & System Clock /Oscillators Timers, Input Captur

e & Output Compare Modes ,Watchdog Timer, Timer/Counter Application Design Power, Oscillator & Reset Circuitry I/O Ports Interfacing LEDs, Switches & LCD Parallel Interface


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Interfacing Hardware to Microcontroller Types of ADC and DAC Example Interfacing of ADC & DAC to Microcontroller Serial Interface through RS232 ,I2C SPI Communication CAN Interface & USB Interfacing16/32 BIT ARM CONTROLLER

Introduction to 16/32-bit Processors The ARM Architecture, Overview of ARM, Register Set and Modes ARM Processor Core ARM7TDMI & ARM 9TDMI, Data Path and Instruction Decoding ARM Instruction Set Introduction to Exceptions Conditional Execution, Branch, Branch Link and Branch Exchange ARM Development Environment Assembler and Compilers Linkers and Debuggers Software Interrupts Data Processing Instructions Multiple Register Transfer Instruction Thumb Instruction Set Mixing ARM & Thumb Instructions Architectural Support for High Level Language Data Types

Floating Point Data Types Expressions, Conditional Statements and Loops Memory Hierarchy Memory Interfacing Memory Size & Speed Cache Architectural Support for Operating System ARM System Control Coprocessor CP15 Protection Unit Registers ARM MMU Architecture Synchronization Context Switching Enhanced DSP Extension

RTOS Concepts and Programming in Real Time with RT LINUX, with Device Driver andperl Script 150 Hours

OPERATING SYSTEM CONCEPTS System Components/Services Introduction to Process Management

Multiprogramming, threading, tasking and processing CPU Scheduling Basic concept Scheduling criteria Scheduling Algorithm Multi-Process Scheduling Real Time Scheduling System Components/Services Process Synchronization Semaphores Critical Region Monitors Deadlocks Deadlock Characterization Method for handling deadlocks Deadlock prevention Deadlock Avoidance Introduction to memory management Logical Address Physical Address Swapping Memory Management Contiguous Allocation Paging Segmentation Segmentation with paging

Virtual Memory Pages Demand Paging Page Replacement


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Page-Replacement Algorithme Thrashing File-System Interface Pages (337-360) Direct Memory Access Pages (406-420) Application I/O Interface Kernel I/O Subsystem Secondary Storage Structure Pages (431-444)

Disk Structure Disk Scheduling Disk Management Swap-Space Management Disk Reliability Network Structure Motivation Topology Network Type Distributed Operating System Pages Comparison of different operating system(window NT/Linux/Unix)

Perl Scripting Introduction to PERLWhy PERL ScriptPerl files extensionAdvantage of PerlSystem command to use PerlComment entryPrint stuff on screen Language Variable Used in PerlScalar variablesList variablesPush,pop,shift,unshift,reverseHashes,keys,values,each

Read from terminal, command line argumentsRead and write to filesPush,pop,shift,Unshift,reverse operator Control StatementWhile / until statementsFor statementsForeach statementsLast , next , redo statements&& And || as control structuresFunction declarationCalling a functionPassing parametersLocal variablesReturning values Regular ExpressionSplit and joinMatching & replacingSelecting a different target$&,$', And $`Parenthesis as memoryUsing different delimiterOthersPROGRAMMING WITH LINUX INTERNALS File System Management File concepts, Allocation and protection

Mechanisms I/O and Secondary Storage Management Linux Architecture and System Call interface


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Processes & Signal API and POSIX thread API IPC Mechanisms (Pipes, FIFOs, Semaphores, Shared Memory) IPC Mechanisms (Message Queues and Sockets) Memory Management in Linux, Interrupts and Timers Disk Cache and Disk I/O Management

RTOS FUNDAMENTALS and PROGRAMMING

Introduction to Real time systems and Real Time Operating Systems Real Time OS Concepts Installation of RTLinux RTLinux / ( Architecture, Module Concept, Linking a module with the kernel) Introduction to basic kernel API Real Time FIFO, Inter Process Communication between RT Task and Linux Process IPC using shared memory, Mail boxes, Hard & Soft Interrupts, Interrupt Handling .DEVICE DRIVER PROGRAMMINGLinux Kernel configuration and compilation

Introduction to Linux Device ModelTypes of device driversBuilding and running moduleDebugging techniques in the kernelIntroduction to Character DriversInterrupt HandlingPCI Bus Architecture and SpecificationsIntroduction to USB Device Driver

Digital Electronics 20 Hours

Introduction of Digital electronics Number System

Boolean algebra Combinational logic design, standard representation for logic functions K- map representations and simplification for logic functions Quine-Maclinsy Method Basic Building Block Arithmetic Operations Mux D- Mux Decoder Encoder Adder Sub tractor Sequential logic design Flip-Flops Application of Flip-Flops Synchronous and asynchronous counterLFSRSynchronizersBasics of State Machine MOORE and MEALY FSMState Reduction methodologies Problems on State MachinesTiming analysis of digital CircuitVHDL 70 Hours

History Capabilities Overview


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Features of VHDL Language abstractions Entity Declaration Concurrent VHDL Signal assignment Transport and inertial delays Concurrency

Concurrent control statements Behavior and data flow modeling Data Types and synthesizable data type Advanced data types Subtypes Multi dimensional array Relational and arithmetic operators Vector assignment Bit string and literal Slice of array Sequential VHDL Concurrent and sequential data processing

Processes Sequential Control statements Clocked sequential processes Synchronous and asynchronous process Postponed process Assert and Loop Statements Exit and Next Statements Generate Statements Libraries Packages Subprograms Functions Procedures

Side effects Resolution Function Structural VHDL Components declaration and specification Generic components Configurations State Machine Moore machine Mealy machine State Machine Coding Style State machine with clocked output Different level of test benches

Verilog & System Verilog 90 Hours

Introduction and overview of VERILOG History and major capabilities Development flow and Verilog modules Description of different modeling Gate Level Modeling Structural design Data flow Modeling Behavioral Modeling Simulation of the design. Language element, identifiers, comments, format,

System task Compiler directives Data types: Net, Wire, wor and trior nets, wand and triand nets, Reg,


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vector and scalar nets Operators: Arithmetic and logical, signed and unsigned operators, conditional operator, shift operator, concatenation operator, bit wise operator, Logical operator, Equality Operater,Relational operator, Reduction Operator Gate level modeling Multiple input output gates Tri state gates

Array of instance and implicit nets Structural statement Module instantiation, unconnected ports, external ports and other examples Data flow modeling, continuous assignment Net declaration assignment Delays and net delays Behavioral modeling Procedural construct Initial statement Always statement Timing control

Delay control Event control Sequential statement Parallel block statement Conditional statement Blocking and Non-Blocking Statements Loops in verilog Switch level Modeling Task and Function Introduction to User defined primitives (UDPs) Combinational UDPs Sequential UDPs Level triggered UDPs

Edge triggered UDPsSpecify blockand exampledefparamand its example FSM Modeling Mealy and Moore ModelPLI overviewSYSTEM VERILOG An Introduction to verification Types of verification Code Coverage, Functional coverage Introduction to System Verilog Data Types, Operators, Arrays Oops concepts in system verilog Task and Function in System verilog System Verilog Assertions

CMOS 15 Hours

Introduction of MOS device N- Mos P-Mos CMOS Structure of MOS cells Threshold Voltage CMOS Inverter DC Characteristics

Device sizing Ratioed Logic Non ratioed logic


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Latch Up effect Body Effect Channel Length Modulation CMOS as a switch Noise Margin Capacitance Estimation Rise and fall times

Power dissipation Design of complex circuit Fabrication steps

HDL Synthesis AND System Architecture 45 Hours

HDL FLOWSynthesis FlowLibrariesIP CoresSynchronous Vs Asynchronous DesignsClock and Reset Designs

Synthesis basic Logic Synthesis Design constraints Translation Optimization Logic Duplication

Technology mapping Design Partitioning Resource sharing Pipelining Synthesis of sequential and Concurrent Statements Difference between synthesis and simulation result If-else Vs Case

State Machine encoding Timing Fundamental Timing analysis Timing issues Critical path Slack Problems of Timing Clock skew Types of skew Design format

Reporting files Introduction to PLDS Introduction to PAL, Introduction to PLA

FPGA architecture Comparison Of available FPGA Architecture

Memory ArchitectureFPGA and logic synthesis

ASIC Design 50 Hours

Introduction of ASIC Design Flow Diagram Specifications and Schematic cell Design.

Design Rule Checks, Micron Rules Lambda rules of the design


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Fabrication methods of circuit elements Layout design of different cells Diff. Library cell designing, NAND, NOR, NOT, X-OR etc Circuit Extraction Electrical rule check LVS Post-layout Simulation

Parasitic extraction Antenna effect Electro migration effect Body effect Inductive and capacitive cross talk Drain punch through, etc. Design format Timing analysis Back notation Post layout simulation Spice simulation Analysis of analog and digital circuits, circuit elements, AC and DC analysis.

Transfer Characteristics, Transient responses, Noise analysis of currentand voltage DFT Guideline Test Pattern BIST

Business Communication 60 HoursAptitude 40 HoursProject 120 Hours

Documents

PG Diploma in Integrated VLSI and Embedded System Design (DIVESD)- Modules