PHENIX DAQ RATES

RHIC Data Rates at Design Luminosity

•PHENIX Max <rate> = 25 kHz•Every FEM must send in 40 us.•Since we multiplex 2, that limit is 12 kHz and 80 us.•For Au-Au, Level-1 rate is ~1400 Hz - we sample every event in the level-2.•For p-p, the interaction rate is 10MHz - need very good level-1 rejection.

Au-Au: L = 2 x 1026 cm-2 s-1

p-p: L = 2 x 1032 cm-2 s-1

Design Luminosities

• Assumptions:– A total period of 25 weeks for beam availability– RHIC duty factor = 50%– PHENIX duty factor = 50%– Collision region rms = 20 cm.– All running at

• Au-Au segment of 17 weeks:– First 7 weeks:

• RHIC: commissioning from ~10% to 100% of design luminosity• PHENIX: Commissioning, calibrating, start of data-taking

– Last 10 weeks:• Running at ~100% of design luminosity (2 x 1026 cm-2 s-1)

– 300 b-1 (possibly 600) of integrated luminosity recorded

• p-p segment of 8 weeks– 2 weeks to commission collisions– 1 week to commission polarization (> ~50%)– 5 weeks of polarized running at 5 x 1030 cm-2 s-1

– 3.5 pb-1 of integrated luminosity recorded:

Run Segments (“borrowed” from Bill’s RBUP)

GeV200sNN

Data Volumeshttp://www.nevis.columbia.edu/~nagle/Trigger/phenix_data_volume2.htm

UnSuppressed 2.93 x 10^6

Au-Au Central 4.02 x 10^510% occ

Au-Au mbias 1.61 x 10^52.5% occ

Au-Au mbias 1.26 x 10^52.5% occ,min fem header

p-p mbias 4.30 x 10^40% occupancymin fem header

Data Type Size (bytes)Overhead

Packet > 22 x 10^3Header

FEM Header 53.2 x 10^3

Minimal FEM 18.1 x 10^3Header (clk, evt,summary)

Data Type Size (bytes)

•Is the minimal FEM header really “the” mininal?•Packet and FEM headers can be dropped from empty packets, but not from non-empty ones•We are currently running with all headers and packets...

PHENIX Hardware ThroughputSpews out data

at 25 kHz*

Must be able to make L1 decision in 40 beam crossings (GL1 + LL1)

*EMC needs short format FPGA, TOF needs extra controllers to get < 40us output time.

FEM

fiber

40 MHz DC, TEC20 MHz all else.(ie, 160 or 80 MB/s)

LEVEL-1

Reads in FEM data, 0-suppress Process

Data

JoinsData, further

processing

High Speed Transfer to

SEB

DSPs 1-4

DSP 5 (1 per DCB)

20 MB/sLink Port

JoinsData, further

processing

JoinsData, further

processing

160 MB/s

(40 MHz)Token Passing Bus

PARTITIONERLVDS

CABLE to

Event

Builder

DCMFPGA

PHENIX Hardware Throughput

Dual Buffer Storage in RAID Arrays running

on Linux Box (one writes to HPSS, one reads from ATPs)

28? x 100Mbitethernet

10 Gbit/saggregate,5 each way

155 Mbit/s NIC

30-40? MB/s RAID

LVDS

CABLE

(from PAR)

Buffer Data from DCM’s

JSEB Input Card (PCI, 132 MB/s)

26? SEBs (NT 4)

Assemble Events, Run

Level 2 Trigger

28? ATPs (NT 4)

Event Builder

Buffer Boxes

HPSS20 MB/s

•Each SEB can write out at 155 Mbit/s, so max rate is (155Mbit/s - overhead)/event size•20 MB/s sustained max overall output rate set by HPSS•30-40 into the buffer boxes isinstantaneous rate.

155 Mbit/s NIC

Fore ASX-1000ATM Switch

Current Status, 2001-08-18

Event Size = 120 kBytes

Event Rate ~ 600 Hz

MVD Largest Granule

Some Personal Thoughts...•For the Au-Au running, we want to be at 1400 Hz, and it would be even better to get to 2100 Hz if we want the coherent peripheralprogram to succeed. •We are currently somewhere around 600 Hz, but we’re still working on it.•Given the limit of 155 MBits/s per SEB due to the ATM NIC, the Level 1 limit is set by the DC - at 2.5% occ, event size is 26.3 kB, so 15 MB/26.3 kB => max rate of 1140 Hz.•If we go to minimal FEM headers, the DC size goes down to 21.8kB, or a max rate of ~1400 Hz.•If we want coherent peripheral, we’d need to split the DC granules.•Still a lot of work to do for p-p running, and none of it seems certain: minimize headers, drop packets, level-1 b•oards…