PHYS 162 - Chapter 8 Field Effect Transistor CHAPTER 8 ... · PDF fileCHAPTER 8 FIELD EFFECT TRANSISTOR (FETs) INTRODUCTION ... DSS (Drain to Source current gate Shorted). - I DSS

PHYS 162 - Chapter 8 Field Effect Transistor

Prepared By: Syed Muhammad Asad – Semester 102 Page 1

CHAPTER 8 FIELD EFFECT TRANSISTOR (FETs)

INTRODUCTION - FETs are voltage controlled devices as opposed to BJT which are current controlled.

- There are two types of FETs.

o Junction FET (JFET)

o Metal Oxide Semiconductor FET (MOSFET)

- The basic difference between the two is in terms of their construction.

- Both have the advantage of high input resistance and low output resistance as compared to BJT.

- Both have an advantage of high power output.

8-1 THE JFET - JFET operate with a reverse biased pn junction to control the current in a channel.

- Depending upon the construction, JFETs fall in either of two categories,

o n-channel

o p-channel

- The basic representation of the both is given in Figure 1.

- Wires are connected to each end of the n-channel (Figure 1a).

- Upper end is the Drain while the lower end is the Source.

- Two p-types regions are diffused in the n-channel to form a channel.

- Both p-regions are connected to the Gate.

8.1.1 Basic Operation

- The basic operation of the JFET is illustrated in Figure 2 which shows a biased n-channel JFET.

- VDD is the drain-to-source voltage and provides the drain current ID.

- VGG sets the reverse bias between the gate and the source.

- JFET is always operated with the gate-source pn junction reverse biased.

- The reverse bias produces a depletion region along the pn junction and increases the resistance of the

channel which controls the current.

Figure 1 Basic structure of JFET



- Therefore, VGS, the gate-source voltage can be changed to control the amount of drain current ID flowing in the channel.

Figure 3 Effect of VGS on channel width, resistance and drain current

8.1.2 JFET Symbols

- The schematic symbols for n-channel and p-channel JFETs are shown in Figure 4.

- The “in” arrow on the gate indicates an n-channel JFET while the “out” arrow indicates p-channel.

8.2 JFET CHARACTERISTICS AND PARAMETERS - JFET is a voltage-controlled, constant-current device.

- The controlling voltage for JFET is VGS.

- Following is an explanation to understand the characteristics and parameters of JFET (Figure 5a):

o Consider the case when gate-to-source voltage 𝑉𝐺𝑆 = 0𝑉.

o As VDD and thus VDS is increased, ID will increase. This is highlighted in the graph of Figure 5b

between points A and B.

o This region is called the Ohmic Region and in this region channel resistance is constant.

o At point B, the curve of Figure 5b levels and enters the active region.

o In this region, ID is constant.

o As voltage VDS is increased, the drain current ID remains constant between points B and C.

Figure 2 Biased n-channel JFET

Figure 4 JFET schematic symbols



8.2.1 Pinch Off

- At 𝑉𝐺𝑆 = 0𝑉, the value of VDS where ID becomes constant (Point B on Figure 5b) is called Pinch-Off

voltage, Vp.

- A given JFET has fixed value of Vp given in datasheets.

- At 𝑉𝐺𝑆 = 0𝑉, the value of the constant drain current is called IDSS (Drain to Source current gate

Shorted).

- IDSS is given in datasheets.

- IDSS is the maximum current a JFET can produce.

8.2.2 Breakdown

- Breakdown occurs at point C when ID increases very rapidly.

- Breakdown can damage the transistor.

- JFETs should be operated below breakdown in the active region (between point B and C).

8.2.3 VGS controls ID

- Connect a bias voltage VGG from gate to source as shown in Figure 6a.

- As VGS becomes more negative (𝑉𝐺𝑆 < 0𝑉), the resistance of the n-channel increases with the

increase in the depletion region.

- As we keep on decreasing VGS, a family of drain characteristic curves is produced as shown in Figure

6b.

- Drain current ID decreases with more negative VGS.

- This behavior illustrates that the drain current is controlled by VGS.

8.2.4 Cutoff Voltage

- The value of VGS that makes ID approximately zero is the cutoff voltage VGS(off).

- A JFET must be operated between 𝑉𝐺𝑆 = 0𝑉 and VGS(off).

8.2.5 Comparison of Pinch-Off Voltage and Cutoff Voltage

- VGS(off) and Vp are always equal in magnitude but opposite in sign.

- So 𝑉𝐺𝑆 𝑜𝑓𝑓 = −𝑉𝑝 .

- Anyone one of the two parameters is mentioned in the datasheet but not both.

Figure 5 Drain characteristic curve of a JFET for VGS=0V



NOTE: REFER EXAMPLE 8-1 PAGE 375

8.2.6 JFET Universal Transfer Characteristic

- We now know that VGS controls ID.

- Therefore the relationship between VGS and ID is very important.

- Figure 7 shows a general characteristic curve that graphically shows how VGS and ID are related.

- This graph is known as a transconductance curve.

- Following points need to be noticed about the graph:

o 𝐼𝐷 = 0𝐴 when 𝑉𝐺𝑆 = 𝑉𝐺𝑆 𝑜𝑓𝑓

o 𝐼𝐷 =𝐼𝐷𝑆𝑆

4 when 𝑉𝐺𝑆 = 0.5𝑉𝐺𝑆 𝑜𝑓𝑓

o 𝐼𝐷 =𝐼𝐷𝑆𝑆

2 when 𝑉𝐺𝑆 = 0.3𝑉𝐺𝑆 𝑜𝑓𝑓

o 𝐼𝐷 = 𝐼𝐷𝑆𝑆 when 𝑉𝐺𝑆 = 0𝑉

- The mathematical relation between the drain current ID and VGS can be given approximately as

Figure 6 VGS controls ID

Figure 7 JFET universal transfer characteristic curve



Figure 8 gm varies depending on VGS

𝐼𝐷 ≈ 𝐼𝐷𝑆𝑆 1 −𝑉𝐺𝑆

𝑉𝐺𝑆 𝑜𝑓𝑓

2

- The above equation can determine ID for any given value of VGS if IDSS and VGS(off) are known.

- IDSS and VGS(off) are given in the datasheets.


8.2.7 JFET Forward Transconductance

- Transconductance can be roughly defined as the inverse of resistance.

- The forward transconductance of the JFET is given by symbol gm.

- It is the change in the drain current (Δ𝐼𝐷) for a given change in the gate-to-source voltage (Δ𝑉𝐺𝑆) with

constant VDS.

- It is expressed as a ratio and has a unit of Siemens (S) or mho.

𝑔𝑚 =Δ𝐼𝐷Δ𝑉𝐺𝑆

- As the JFET transfer curve is nonlinear, gm varies in value on different location of the curve.

- gm is greater at the top (near 𝑉𝐺𝑆 = 0𝑉) of the curve as compared to the bottom (near 𝑉𝐺𝑆 𝑜𝑓𝑓 ) as

shown in Figure 8.

- The datasheet normally gives values of gm at 𝑉𝐺𝑆 = 0𝑉 (gm0).

- Given gm0, we can calculate gm at any point on the curve using the following formula:



𝑔𝑚 = 𝑔𝑚0 1 −𝑉𝐺𝑆


- If gm0 is not available, we can use the following formula to calculate it:

𝑔𝑚0 =2𝐼𝐷𝑆𝑆



8.2.8 Input Resistance

- The input resistance of JFETs is extremely high as compared to BJTs.

- This is due to the reverse bias at the gate-to-source junction which increases the depletion region at

the junction and thus increases the resistance.

- The input resistance can be determined by the following formula:

𝑅𝐼𝑁 = 𝑉𝐺𝑆𝐼𝐺𝑆𝑆

8.3 JFET Biasing - The main purpose of DC biasing is to select the proper DC gate-to-source voltage VGS to establish a

desired value of drain current ID which is the Q-point of the circuit.

- There are 3 types of bias circuit used with JFETs.

o Self Bias

o Voltage Divider Bias

o Current Source Bias

8.3.1 Self-Bias

- Self-bias is the most common type of bias circuit for JFET.

- Figure 9 shows the self-bias circuit for n-channel (Figure 9a) and p-channel (Figure 9b) JFETs.

- The gate terminal being grounded through RG results in 𝑉𝐺 = 0𝑉.

- This setup achieves the reverse bias condition of the gate required for proper biasing of JFET.


Figure 9 Self-bias JFET



8.3.2 Setting the Q-Point of a Self Biased JFET

- For setting a Q-point, first either find ID for some VGS or vice versa.

- Then calculate the required RS by the following relation:

𝑅𝑆 = 𝑉𝐺𝑆𝐼𝐷

- For a desired value of VGS, ID can be determined in two ways.

o Graphical using the transfer curve.

o Using Equation of 𝐼𝐷 ≈ 𝐼𝐷𝑆𝑆 1 −𝑉𝐺𝑆


2

where IDSS and VGS(off) are given.


8.3.2.1 Midpoint Bias

- It is good to bias a JFET near the midpoint of the transfer curve.

- At the midpoint

𝐼𝐷 =𝐼𝐷𝑆𝑆

2

𝑉𝐺𝑆 =𝑉𝐺𝑆 𝑜𝑓𝑓

3.4

𝑉𝐷 =𝑉𝐷𝐷

2

- Select a value of RD to get the required VD.

- Choose RG large enough (mega ohm range).


8.3.3 Graphical Analysis of a Self-Biased JFET

- The transfer characteristic curve of a JFET can be used to find the Q-point (ID and VGS) of a self biased

circuit.

- If the curve is not given then it can be plotted using the equation of ID and using the datasheet values

of IDSS and VGS(off).

- To determine the Q-point of the circuit, a DC load line must be drawn.

- The DC load line is established as follows (illustrated in Figure 10):

o At 𝐼𝐷 = 0𝐴 find 𝑉𝐺𝑆 = −𝐼𝐷𝑅𝑆 = 0𝑉. This gives us the first point of the load line.

o At 𝐼𝐷 = 𝐼𝐷𝑆𝑆 find 𝑉𝐺𝑆 = −𝐼𝐷𝑅𝑆 = −𝐼𝐷𝑆𝑆𝑅𝑆. This gives the second point. Connecting these two

points establishes the load line.

o The point where the load line intersects the transfer curve is the Q-point.

o Note the corresponding values of ID and VGS at the Q-point.



Figure 10 Self-bias DC load line


8.3.4 Voltage-Divider Bias

- An n-channel JFET with voltage-divide bias is shown in Figure 11.

- For proper biasing, the voltage at the source must be more positive than the

voltage at the gate.

- This ensures that the gate-source junction is reverse biased.


8.3.5 Graphical Analysis of a JFET with Voltage-Divider Bias

- A similar approach as JFET self-biased circuit can be used to find the Q-point

graphically.

- The DC load line is established as follows (illustrated in Figure 12):

o At 𝐼𝐷 = 0𝐴 find 𝑉𝐺𝑆 = 𝑉𝐺. This gives us the first point of the load line.

o At 𝑉𝐺𝑆 = 0𝑉 find 𝐼𝐷 =𝑉𝐺

𝑅𝑆. This gives the second point. Connecting these

two points establishes the load line.

o Extending the load line to intersect the transfer curve gives us the Q-point.

o Note the corresponding values of ID and VGS at the Q-point.

Figure 11 JFET voltage-divider bias



Figure 12 DC load line for JFET voltage-divider bias


8.3.6 Q-Point Stability

- The transfer characteristic curve differs from one JFET to the other of the same type.

- This behavior is not suitable for circuit parameter stability.

- This difference in curve may cause the Q-point to change significantly.

- Figure 13 shows a typical transfer curve of two JFETs 2N5459.

- Figure 13a is for self-biased while Figure 13b is for the voltage-divider biased.

- As can be seen, both have different transfer curves.

- Changing one with the other changes the Q-point dramatically.

- It is worth noting that in terms of Q-point stability, voltage-divider bias is better then the self-bias

circuit.

- This can be seen by the amount of change in the drain current for both the circuits.



Figure 13 Variation in transfer curve and Q-point of self-biased and voltage-divider biased JFET of the same type

- The change in the drain current value for self-bias is more then the change for the same in voltage-

divider.

- The reason for this is that the slope of the load line for voltage-divider is much gradual then the slope

of the load line for self-biased and thus the change in y-axis is small.

8.3.4 Current-Source Bias

- Current-source bias is a method for increasing the Q-point stability of a self-biased JFET.

- This is done by making drain current independent of VGS.

- This is accomplished by using a constant current source in series with JFET source as shown in Figure

14.

- In this circuit, the BJT acts as a constant current source so the emitter current is constant.

- This makes the drain current constant because 𝐼𝐸 ≈ 𝐼𝐷 ≈𝑉𝐸𝐸

𝑅𝐸.

- As can be seen from the transfer characteristic curve of 2 different JFET, the drain current remains

constant thus providing highly stable Q-point.



Figure 15 Ohmic region in shaded area

Figure 14 Current-source bias

8.4 THE OHMIC REGION - Ohmic region is the part of the FET characteristic curve where Ohm’s law can be applied.

- A proper biased JFET exhibits property of variable resistance in this region.

- Ohmic region extends from the point where 𝑉𝐺𝑆 = 0𝑉 to the point where ID becomes constant.

- The slope of the characteristic curve can be taken to be constant for small values of ID.

- The slope of the curve is the DC drain-to-source conductance given by

𝑆𝑙𝑜𝑝𝑒 = 𝐺𝐷𝑆 =𝐼𝐷𝑉𝐷𝑆

- As resistance is inverse of conductance, the DC drain-to-source resistance is given by

𝑅𝐷𝑆 =1

𝐺𝐷𝑆=𝑉𝐷𝑆𝐼𝐷



8.4.1 JFET as a Variable Resistance

- A JFET is biased in the Ohmic region to be used a voltage-controlled variable resistor.

- The controlling voltage is VGS which determines the resistance by changing the Q-point.

- To bias the JFET in the Ohmic region, the load line must intersect the curves inside the Ohmic region

as shown in Figure 16.

- This is done by setting the DC saturation current ID(sat) much less than IDSS.

- Figure 16 shows 3 Q-points in the Ohmic region.

- As you move along the load line or change the Q-point, the resistance RDS changes as the slope at each

Q-point are different.

- If the Q-point is moved from 𝑉𝐺𝑆 = 0𝑉 to 𝑉𝐺𝑆 = −2𝑉, the slope at each point is less then the previous

one.

- This means less ID and more VDS which results in increase in RDS.


8.5 THE MOSFET - Metal Oxide Semiconductor FET is another type of FET.

- It is different from JFET as it does not contain a pn junction instead the gate is insulated from the

channel by a silicon dioxide (SiO2) layer.

- There are two types of MOSFET

o Enhancement (E) MOSFET – most commonly used.

o Depletion (D) MOSFET

8.5.1 Enhancement MOSFET (E-MOSFET)

- Enhancement MOSFET only operates in the enhancement mode and there is no depletion mode.

- Figure 17 shows the structure of an n-channel E-MOSFET.

- It does not contain any n-channel.

Figure 16 Load line intersect the curves inside the Ohmic region



- Instead the channel is induced by a positive threshold voltage at the gate that pulls the electrons to

make the channel.

- This structure makes it possible to have more conduction by pulling more electrons in the channel.

- Figure 18 shows the schematic symbols of n-channel and p-channel E-MOSFETs.

8.5.2 Depletion MOSFET (D-MOSFET)

- Another type of MOSFET is the Depletion MOSFET (D-MOSFET).

- The basic structure of n-channel and p-channel D-MOSFET is shown in Figure 19.

- Unlike the E-MOSFET, there is a small channel in the D-MOSFET.

- This channel enables it work in both the enhancement mode as well as the depletion mode.

- It operates in depletion mode when 𝑉𝐺𝑆 < 0𝑉 and operates in enhancement mode when

𝑉𝐺𝑆 > 0𝑉.

8.5.2.1 Depletion Mode

- Applying negative VGS at the gate terminal of a D-MOSFET repels the electrons in the n-channel and

replaces it by hole.

- This depletes the channel of any electrons and when 𝑉𝐺𝑆 = 𝑉𝐺𝑆 𝑜𝑓𝑓 , the channel is totally depleted

and drain current ID becomes zero.

8.5.2.2 Enhancement Mode

- Applying positive VGS at the gate terminal of a D-MOSFET attracts more electrons in the n-channel.

Figure 18 E-MOSFET structure

Figure 17 E-MOSFET schematic symbols

Figure 19 D-MOSFET structure



- This increases or enhances the channel conductivity.

- Figure 20 shows the schematic symbols of n-channel and p-

channel D-MOSFET.

8.5 MOSFET CHARACTERISTICS AND PARAMETERS - Most of the concepts of JFET characteristics and

parameters apply equally to MOSFETs.

- We shall discuss the characteristics of both the MOSFETs

separately.

8.5.1 E-MOSFET Transfer Characteristics

- The E-MOSFET only operates in the enhancement mode.

- So an n-channel device requires positive VGS and p-channel requires negative VGS.

- Figure 21 shows the transfer characteristic curve of n-channel and p-channel E-MOSFET.

- 𝐼𝐷 = 0𝐴 at 𝑉𝐺𝑆 = 0𝑉 so there is no IDSS in E-MOSFETs.

- Ideally there is no drain current until VGS reaches a specific value called the threshold voltage, VGS(th).

- The equation for the drain current in E-MOSFET differs from JFET and is given by

𝐼𝐷 = 𝐾 𝑉𝐺𝑆 − 𝑉𝐺𝑆 𝑡𝑕 2

𝑎𝑛𝑑 𝐾 =𝐼𝐷 𝑜𝑛

𝑉𝐺𝑆 − 𝑉𝐺𝑆 𝑡𝑕 2

Where values of ID(on) is specified in the datasheets at a given VGS.


8.5.2 D-MOSFET Transfer Characteristics

- D-MOSFET can operate in both enhancement as well as the depletion mode.

- It means it can work with both positive and negative VGS.

- Figure 22 shows the transfer curve for n-channel and p-channel D-MOSFETs.

- The point on the curve where 𝑉𝐺𝑆 = 0𝑉 corresponds to IDSS.

- The point where 𝐼𝐷 = 0 correponds to VGS(off).

Figure 20 D-MOSFET schematic symbols

Figure 21 E-MOSFET transfer curve



- The curve shows that with positive VGS (n-channel) or negative VGS (p-channel) the channel conduction

increases allowing more current through the drain as than IDSS.

- The same equation of ID as in JFET also applies to D-MOSFET.


Figure 22 D-MOSFET transfer curve

8.6 MOSFET BIASING - MOSFET can be biased in three ways.

o Voltage-divider bias (For E-MOSFET and D-MOSFET)

o Drain-feedback bias (For E-MOSFET and D-MOSFET)

o Zero-bias (only for D-MOSFET)

8.6.1 E-MOSFET Bias

- The purpose of biasing an E-MOSFET is to make

VGS greater than the VGS(th).

- Figure 23 shows the circuit arrangement for the

voltage-divider and drain-feedback bias for an n-

channel E-MOSFET.

- Equation for the voltage-divider bias are

𝑉𝐺𝑆 = 𝑅2

𝑅1 + 𝑅2 𝑉𝐷𝐷

𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷𝑅𝐷

- Equation for drain-feedback bias is

𝑉𝐺𝑆 = 𝑉𝐷𝑆

NOTE: REFER EXAMPLE 8-18 & 8-19 PAGE 405 & 406

8.6.2 D-MOSFET Bias

- The simplest bias method for D-MOSFET is to set 𝑉𝐺𝑆 = 0𝑉.

- This enables the AC voltage source to vary above and below this 0V bias point.

- Equations for the zero-bias are

𝑉𝐺𝑆 = 0𝑉 then 𝐼𝐷 = 𝐼𝐷𝑆𝑆

𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷𝑆𝑆𝑅𝐷

Figure 23 E-MOSFET bias arrangement



- Figure 24 shows an n-channel zero-biased D-MOSFET.


Table 1 JFET Formula Sheet

Pinch-Off Voltage 𝑉𝑝 = −𝑉𝐺𝑆 𝑜𝑓𝑓

Drain Current 𝐼𝐷 ≈ 𝐼𝐷𝑆𝑆 1 −𝑉𝐺𝑆


JFET Forward Transconductance

𝑔𝑚 = 𝑔𝑚0 1 −𝑉𝐺𝑆


𝑔𝑚0 =2𝐼𝐷𝑆𝑆


Input Resistance 𝑅𝐼𝑁 = 𝑉𝐺𝑆𝐼𝐺𝑆

Self-Bias

𝑉𝐺𝑆 = 𝑉𝐺 − 𝑉𝑆 = −𝐼𝐷𝑅𝑆 𝑉𝐷 = 𝑉𝐷𝐷 − 𝐼𝐷𝑅𝐷

𝑉𝐷𝑆 = 𝑉𝐷 − 𝑉𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 + 𝑅𝑠 RS at Q-point is given by

𝑅𝑆 =𝑉𝐺𝑆𝐼𝐷

Midpoint Bias is given by

𝐼𝐷 =𝐼𝐷𝑆𝑆

2

𝑉𝐺𝑆 =𝑉𝐺𝑆 𝑜𝑓𝑓

3.414

𝑉𝐷 =𝑉𝐷𝐷

2

Voltage-Divider Bias

𝑉𝑆 = 𝐼𝐷𝑅𝑆

𝑉𝐺 = 𝑅2


𝑉𝐺𝑆 = 𝑉𝐺 − 𝑉𝑆 𝑉𝑆 = 𝑉𝐺 − 𝑉𝐺𝑆

𝐼𝐷 =𝑉𝑆𝑅𝑆

=𝑉𝐺 − 𝑉𝐺𝑆

𝑅𝑆

Figure 24 Zero-biased D-MOSFET



Ohmic Region

𝑆𝑙𝑜𝑝𝑒 = 𝐺𝐷𝑆 ≈𝐼𝐷𝑉𝐷𝑆

𝑅𝐷𝑆 =1

𝐺𝐷𝑆=𝑉𝐷𝑆𝐼𝐷

𝐼𝐷 𝑠𝑎𝑡 =𝑉𝐷𝐷𝑅𝐷

Table 2 MOSFET Formula Sheet

E-MOSFET Drain Current

𝐼𝐷 = 𝐾 𝑉𝐺𝑆 − 𝑉𝐺𝑆 𝑡𝑕 2

𝐾 =𝐼𝐷 𝑜𝑛

𝑉𝐺𝑆 − 𝑉𝐺𝑆 𝑡𝑕 2

D-MOSFET Drain Current 𝐼𝐷 ≈ 𝐼𝐷𝑆𝑆 1 −𝑉𝐺𝑆


E-MOSFET Bias

Voltage Divider Bias

𝑉𝐺𝑆 = 𝑅2


𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷𝑅𝐷 Drain Feedback Bias

𝑉𝐺𝑆 = 𝑉𝐷𝑆 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷𝑅𝐷

D-MOSFET Bias

Zero-Bias 𝑉𝐺𝑆 = 0𝑉 𝐼𝐷 = 𝐼𝐷𝑆𝑆

𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷𝑆𝑆𝑅𝐷

Documents

PHYS 162 - Chapter 8 Field Effect Transistor CHAPTER 8 ... · PDF fileCHAPTER 8 FIELD EFFECT TRANSISTOR (FETs) INTRODUCTION ... DSS (Drain to Source current gate Shorted). - I DSS