PHYSICAL DESIGN

ANANTHARAMAN.KRA151200801001

M.TECH., VLSI DESIGN

WHAT IS VLSI?

■VLSI is the current level of computer microchip miniaturization and refers to microchips containing in the hundreds of thousands of transistors.

■It was for the first time in mid -1980’s that a CPU was fabricated on a single integrated circuit, to create a microprocessor.

■In 1986, with the introduction of first one megabit ram chips, more than one million transistors were integrated.

STEPS FOR MANUFACTURING CHIP:

SOURCE : INTERNET

PHYSICAL DESIGN:

■Physical design is a step in the standard design cycle which follows after the circuit design.

■Circuit representations of the components (devices and interconnects) of the design are converted into geometric representations of shapes which, when manufactured in the corresponding layers of materials, will ensure the required functioning of the components.

SOURCE :INTERNET

PARTITIONING:

■Partitioning is a process of dividing the chip into small blocks.

■This is done mainly to separate different functional blocks and also to make placement and routing easier. 

■These modules are linked together in the main module called the top level module.

SOURCE : UDEMY

SOURCE : UDEMY

FLOORPLANNING:

■ Floorplanning is the process of identifying structures that should be placed close together, and allocating space for them .

■Floorplanning decides the io structure, aspect ratio of the design.

■Data-path sections benefit most from floorplanning.`

■Data paths are typically the areas of your design where multiple bits are processed in parallel with each bit being modified the same way with maybe some influence from adjacent bits

■Example structures that make up data paths are adders, subtractors, counters, registers, and muxes.

SOURCE : UDEMY

PLACEMENT:■The portion of the physical design flow that assigns exact

locations for various circuit components within the chip’s core area.

■This phase is very crucial in overall physical design cycle.■These occur at 3 different levels

– System– Board– Chip

SOURCE : UDEMY

CLOCK TREE SYNTHESIS:

■The goal of clock tree synthesis (cts) is to minimize skew and insertion delay.

■In clock tree optimization (cto) clock can be shielded so that noise is not coupled to other signals.

■Most common technique used is h-tree algorithm.

SOURCE : UDEMY

SOURCE : UDEMY

ROUTING:

■The objective is to complete the interconnection between blocks according to specified netlist.

■The goal is to complete all circuit connections using shortest possible wire length

■It can be done using channel and swith boxes.

■It can be done in two ways– Global routing– Detailed routing.

■Global routing generates a loose route for each net.■Detailed routing finds actual geometric layout of each

net within assigned routing routes.

SOURCE : UDEMY

SOURCE : UDEMY

PHYSICAL VERIFICATION:

■Physical verification checks the correctness of the generated layout design.

■This includes verifying that the layout by– Design rule checking (DRC)– Layout vs. Schematic (LVS)– Antenna rule checking– Electrical rule checking (ERC)

PARASITIC EXTRACTION (SPEF FORMAT):

SOURCE : UDEMY

SOURCE : UDEMY

SOURCE : INTERNET

SOURCE : INTERNET

JOBS:ASIC frontend designerFPGA frontend designerASIC physical design engineerAMS (Analog Mixed Signal) designerLibrary developerIP design engineer Verification EngineersFront-end verification engineerFPGA Back-end verification engineerPhysical design verification engineerAMS verification engineerEDA tool validation engineerIP verification engineerBoard validation engineerEDA/CAD EngineersSoftware Development EngineerSoftware Test EngineerRegression and Automation Engineer Build and Release Engineer Application EngineersField Application Engineer (FAE)Corporate Application Engineer (CAE)Application Engineer Technical SupportTech Support EngineerProduct Application Engineer (PAE)Reliability Engineer Fab/Foundry Engineer 

■ Major Recruiters:The major recruiters in this

fields are 1.Texas Instruments, 2.PMC Sierra, 3.Infineon, 4.Alliance Semiconductor,5. Analog Devices, 6.Cadence, Synopsys, 7. Mentor Graphics,8. Celox Networks, 9.Cisco, 10.Control Net, 11.Cypress, 12.DSPG,

13.HCL,14. Intel, 15.Lucent,16. Micron Tech,17. National Semiconductor, 18.Motorola, 19.Philips Semiconductor,20. Qualcomm,21. Sasken,22. C2C,  23.Atrenta, 24.Conexant,25. Moschip,26. Cradle  Tech,27. Synplicity, 28.STM,29. Paxonet, 30.Wipro, 31.TCS, 32.eInfochips,33. Ishoni Networks and34. CGCoreEL.