Physical Mechanisms and SPICE Modeling of Resistive Random … · 2 Motivation • Various next-generation NVMs ¾PCM, RRAM (resistive switching) • SPICE Models to facilitate memory

電阻式記憶體之物理機制與SPICE模型建立

Physical Mechanisms and SPICE Modeling of Resistive Random

Access Memory

Student: Huan-Lin Chang (張環麟)Advisor: Prof. Chee Wee Liu (劉致為博士)

2011/7/20

Graduate Institute of Electronics Engineering,National Taiwan University (NTU), Taiwan, R.O.C.

1

Outline• Motivation• SPICE Modeling of Phase Change

Random Access Memory (PCM)Subcircuit method (Eldo)Compact model (Verilog-A)

• SPICE Modeling of Resistive Random Access Memory (RRAM)

Physical MechanismsSubcircuit method (HSPICE)Compact model (Verilog-A)

• Conclusions• Appendixes

2

Motivation• Various next-generation NVMs

PCM, RRAM (resistive switching)• SPICE Models to facilitate memory

circuit design• Two ways of creating SPICE models

Subcircuit method (macromodel) (e.g., inductor, RFMOS)Compact model (e.g., BSIM: C, PSP: Veriog-A)

• Compact Model EnvironmentVerilog-A compiler in HSPICE

3

Verilog-AMS (Verilog-A)

• Verilog-AMS is an extension to Verilog-HDL.• Compatible to HSPICE, Eldo, flexible in coding. • No need to use tran/DC mode. More Secure.

4






5

Phase Change Memory• Resistance Switching Nonvolatile Memory

(NVM) Family• Advantages:

– Good Scalability (Simple structure)– Low Power (V = 1.5V, I = 1mA)– Fast speed (~ 100 ns)

6

Bit Storage• Bits are stored by Resistance Difference

– Bit Alterable (No need to do Erase!)– Promising Multilevel (ML) Operation

Bit alterable

Increase memory density immediately!

7

Phase Change• Phase change of chalcogenide Ge2Sb2Te5 (GST)

is temperature-driven.

A. Pirovano et al., IEEE Tran. Electron Devices, pp. 452-459, Mar. 2004

Multilevel by crystallization fraction

8

PROGRAM and READ• PROGRAM by Current Pulses

• READ by Small VAPP ~ 0.2 V

RESET

SETCurrent Waveform Temperature Resistance

9

I-V Characteristic

Measurement Setup

VSNAP

Convergence

• Snapback phenomenon is observed.

• I-V Convergence at high voltage.

Measured I-V Curve

Test Waveform

10

R-I Characteristic

Measurement Setup

• To design Programming Pulses.

Measured R-I Curve

Test Waveform

LRS

HRS

11

Model Architecture

System Input

System Output

12

Decision Circuit

From Logic Circuit

To Phase Change Circuit

Inspired from I-V Curve

R1

R2

R3

R4

Model Architecture

* Marked in Red: I-V Convergence (R4)

For I-V Continuity

13

Phase Change Circuit

Model Architecture

* Marked in Blue: Falling Edge Correction Circuit

* Marked in Red: Crystallization Time Calibration

From Decision Circuit

Device Temperature

To Logic Circuit

Cx Fraction

Cx Time

Power Dissipation

Absorbed Power

14

Falling Edge Problem

Problem:

Segment S1 and S3 cannotbe differentiated.

VXP

Correct Waveform!

TR

S3: AmorphousS1: Crystalline

XOR

AND

15

Crystallization Time Calibration

VPD = VXP － CEN CT = CTP － CPD

CTP

Problem: Cx time (CTP) do not return to zero during RESET (amorphous).

16

Logic Circuit

Binary (1-bit) PCM Multilevel (2-bit) PCM

Model Architecture

17

Model Verification

I-V Curve R-I Curve

Symbol: Measured DataLine: Model Simulation

• I-V and R-I Curves are accurately modeled.

18

Crystallization Fraction

(1) Device Temperature TR(2) Crystallization Fraction CTX

Simulation Results

From the phase change circuit, we have

19






20

Goal• Develop a compact PCM SPICE model to bridge

process fabrication and IC design community

Intel and Numonyx’s phase change memory and switch

(PCMS), Oct. 2009.

SPICE Model

Phase change memory array using MOS as the

select device.

21

Tools and Environment• Development Tools

Language: Verilog-A (VA)VA Compilers in HSPICESimulators: HSPICEViewers: Waveview

• Test EnvironmentsPC: Windows 7WS: Solaris, RedHat

22

ImplementationI/O Ports

Auxiliary Ports

Step 3 (Crystal Fraction)

Note:C. F. is proportional to crystal time and temperature.

Step 2 (Temperature)

Step 1 (I-V)

Note:Current 1:1 mapping to voltage, but not otherwise.

Consider C.F.:

23

SPICE Parameters• 16 SPICE parameters

HSPICE model card “pcram.l”

• Model Card interface (same as foundry).

24

Simulation Results (I)• A Binary (1-bit) example

HRS: 500kohmLRS: 1kohmSET: 300nsRESET: 100ns

• Temperature and Crystal Fraction are simulated for verification.

READ

25

Simulation Results (II)• A MLC (2-bit) example using various SET Pulse Time

HRS: 500kohmLRS: 1kohmSET: 80, 160, 320nsRESET: 100ns

• SET Pulse Time causes different C.F. to realize MLC.

READ

26

Simulation Results (III)• A MLC (2-bit) example using SET Pulse Amplitude


• SET Pulse Amplitude causes different temperature and C.F.to realize MLC. More efficient than using SET pulse time.

READ

27

Simulation Results (IV)• C. F. is temperature-dependent


tau as T

28

Simulation Results (V)• C. F. is accumulative before RESET.


• Accumulative C.F. is another way to realize MLC.

READ

29

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Simulation Measured Data

Cur

rent

(mA

)

Voltage (V)

From HRS to LRS (40 nm T-shaped PCM from ITRI)

I-V Curve

300.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

1k

10k

100k

TM

TGT Pulse width: 500 ns

Res

ista

nce

(Ω)

Programming Current (mA)

Measured Data Simulation

0

150

300

450

600

750

900

Tem

pera

ture

(oC

)

• Intrinsic temperature is shown for reference

R-I Curve (Fundamental)

31

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.01k

10k

100k Measured Data Simulation

Res

ista

nce

(Ω)

Programming Current (mA)

Pulse width: 500 ns

R-I Curve (Advanced)• For accurate resistance switching

32






33

HfO2-Based Bipolar RRAM

RRAM with a 10 nm-thick HfO2 layer

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.51E-7

1E-6

1E-5

1E-4

1E-3

CC = 0.1 mA

Cur

rent

(A)

Voltage (V)

10 nm HfO2

RRAM stack Bipolar RRAM I-V

34

FormingViewed as: Injection of oxygen vacancies

Two types of oxygen vacancies:

OVtotal=

OV1 (Vo2+)+

OV2 (Hf4+)

35

Filament GrowthElectrochemical Redox Process

Hf (neutral) filament grows from cathode to anode.

OV2OV1

Electric Fieldas

Catalyst

36

RESETReverse Redox: Rupture of filament near anode

(Filament breaks at the weakest part)

Vo2+

Vo2+

Vo2+Vo2+

Vo2+Vo2+

Vo2+

Vo2+

Vo2+

Vo2+

37

HRS-LRS Switching

Switching speed of 0.3 ns has been reported in IEDM 2010.

Vo2+ Vo2+

Vo2+

Vo2+

Vo2+

Vo2+Vo2+

Switching: Rupture/Reformation of filament

SET (LRS):RESET (HRS):

The speed can be very fast because switching occurs only a few nm (< 3 nm) near anode.

38

LRS ConductionQuasi-ballistic theory might apply.

Current density (temperature) is too high to sustain.

None or a few scattering occurs during carrier transport in filament. Scattering mostly occurs at metal electrodes.

1D filament @ 0 K

Ω⋅⎟⎠⎞

⎜⎝⎛≈ k

MR D

131

∫ −=2

1

))(()(2 21f

f

E

EdEffEMET

hqI

1mA: T > 2233 oC (melting point of Hf)

39

HRS Conduction

tunneling 300 350 400 450 500100k

1M

10M

V = - 0.2V

HR

S (Ω

)

Temperature (K)

- 1.14 %/K

-1.5 -1.2 -0.9 -0.6 -0.3 0.010k

100k

1M

HR

S (Ω

)

Voltage (V)

Not Sensitive to T+

Exponential V Dependence=

Tunneling Transport

)exp(dHRS ∝

40

MLC: VST vs. HRS

-1.5 -1.2 -0.9 -0.6 -0.3 0.0 0.3 0.6 0.91E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

VST = - 0.8 V VST = - 1.1 V VST = -1.4 V

Cur

rent

(A)

Voltage (V)

MLC of HRS: Variation of tunnel gap

)exp(dVHRS ST ∝∝

More O2- driven out of Ti layer to break the filament deeper with larger VST.

41

1001k

10k

LRS

(Ω)

Current Compliance (μA)

MLC: CC vs. LRS

QmHf ⋅×=−41062.4

(g/mol) 49.178=HfM

⎟⎟⎠

⎞⎜⎜⎝

⎛⋅⎟

⎠⎞

⎜⎝⎛=

Hf

HfHf z

MFQm

Hf4eHf 4 →+ −+

)in and in ( gmCQ

Faraday’s laws of electrolysis

Faraday’s constant:Molar mass of Hf:Electrons transferred per ions:

HfmQCC1 11 LRS ∝∝∝

Thick filament

Thin filament

MLC of LRS: Variation of thickness of filament

(C/mol) 96485=F

4=Hfz

Filament growth:

42

Resistance Fluctuation

10 100 1k 10k 100k 1M 10M0

5k

10k

15k

20k

25k

30k CC = 45 μA CC = 90 μA CC = 220 μA

Res

ista

nce

(Ω)

Number of Cycling

VRESET = -1.4V

CCRR 1)Avg( ∝∝Δ

Redistribution of mobile Frenkel-Poole defects

Total number of OV’s are fixed during forming process (OVtotal = OV1 + OV2)

43

Scaling Trend

Size Cell1HRS ∝

LRS independent of cell size down to 0.1 um2

(Under same VSET, VRESET)

Constant LRS because cell size is much larger than filament cross-section.

HRS trend due to O2- diffusion from isolation oxide (Hf-O > Si-O)

Large Cell Size:

Small Cell Size:

44






45Typical measured I-V curve of the bipolar RRAM.

Typical I-V and 1T1R

46

SPICE macromodel for binary RRAM

Switch network

Macromodel

47

MM S

List of SPICE parameters in the model

SPICE Parameters

48

A two-segment SCLC model for LRS

Schottky emission-like model for HRS

I-V Mechanisms (Fitting)

49

Add-on circuit to realize three LRS levels

I-V simulation vs. measured data for three

LRS levels

Multilevel LRS

50

Test of the forming behavior of the 1T1R cell

Test of initial resistance setting of the 1T1R cell

Circuit Verification

51

Architecture of the READ circuit with four RRAM cells

Simulation results of the READ architecture with

four RRAM cells

Simulation With Peripheral Circuits

Layout of the 1 kbit RRAM chip

52






53

Detect/Decide Switching

53

• VA has a parallel input nature. Hard to detect pulse width directly.

SWIVS: Switch time from HRS to LRS

@(cross(…)) function is suitable for RRAM model.

SWIVR: Switch time from LRS to HRS

54

1ns 3ns 5ns

VAPP

RHRS LRS

VS = 0.8V

SWIVS = 5ns

Simulation of the two-level switching of SWIVS = 5ns

Concept Validation

55

The 1T1R testing array (2x2) used for verification of the Verilog-A model

Operation voltages for word line (WL), bit line (BL), and source line (SL)

Memory Array (2x2) Setting

56Simulation waveform of the 2x2 memory array.

Memory Array (2x2) Simulation

R1, R2, R3, R4 RESET to HRS (logic 1) consecutively.

57

Block diagram of the 1k bit RRAM array with peripheral circuits.

Simulation results showing all successful switching in V_out.

1 kbit Simulation with Peripherals

58TYPICAL corner selector: “.lib 'C:\....\rram.l' TYPICAL”

RRAM sweeping I-V curves showing VSET and VRESETvariation.

Values of the TYPICAL, BEST, WORST corners of four SPICE parameters VS, VR, LRS, HRS.

Corner Models

59

Sub-Modelcards

Sublibraries realization of corner models

60

Three RESET voltages using corner models

Three SET voltages using corner models

Simulation Results

61






62

ConclusionsPCM SPICE Modeling

•PCM SPICE model is developed by macromodel (Eldo) and Verilog-A with matched I-V and R-Icurves.•Crystallization fraction and temperature can be extracted to further design multilevel PCM.•Peripheral memory circuits need to be tested for convergence issue.•The physics of gradual SET should be studied for R-I curve fitting improvement.

63

ConclusionsRRAM Physical Mechanisms

•RRAM optimization can be performed by:Fine-tune the thickness of Ti layer for control of oxygen vacanciesUse Si3N4 (no O) instead of SiO2 for RRAM isolation

Keep HRS scaling flatAvoid large HRS fluctuation

•Further simulation or measured evidences needed.

64

ConclusionsRRAM SPICE Modeling

•RRAM SPICE model is developed by macromodel (HSPICE) and Verilog-A with matched I-V curves and transient behavior.•The proposed physical mechanisms need to be integrated into advanced SPICE model for accurate RRAM behavior.•Multilevel RRAM and memristor idea (R = f(Q)) should be studied further.

65

Appendix A

Reduction of Crosstalk Between Dual Power Amplifiers Using

Laser Treatment

66

Performance of single PA, where P1dB is 25.3 dBm, linear gain is 18.6 dB, and PAE at P1dB is 16.7 %. The gain expansion is shown less than 1 dB (dashed lines).

Single PA Characteristic

67

PCB layout and coupling signal flow from port 1 to port 4 in the four-port S-parameter measurement.

Seq = |S4′1′| − |S2′1′|= (|S41|−|S1′1|−|S44′|) −(|S21|−|S1′1|−|S22′|) = |S41| − |S21|

Dual PAs Coupling

68

Simulation of three rows of L.T.-induced holes (10 nm hole spacing).

The Req is three times larger than that without L.T.

Laser Treatment Simulation

SEM image showing the impact of one L.T. implementation.

The inset shows entire L.T. area (1470 μm × 150 μm) after one and two L.T. implementations.

69

The equivalent coupling Seq shows a 4.55 dB reduction at 2.45 GHz after two L.T.s (power density ~ 5.0

μW/μm2).

Coupling Reduction by L.T.

70

Pout at 3 % EVM (linearity) shows a maximum 6.1 dB improvement under 0 dB interference.

Linearity Improvement

71

Appendix B

Effects of Extreme Ultraviolet Radiation on SiGe Heterojunction

Bipolar Transistors

72

SiGe HBT cross-section (not scaled)

Dashed circles indicate possible EUV damage regions

DUT layout showing that 57.8 % of active region not covered by Al layer, and thus susceptible to the EUV radiation

Device Structure and Layout

73

Forward Gummel plot of the DUT before and after an EUV dose of 7.9 nJ/μm2 (30-minute exposure) at 300 K.

Reverse Gummel plot of the DUT.

Forward/Reverse Gummel Plots

74

The forward and reverse current gain degradation is < 3X and < 2X within JC from 10-3 to 105 A/cm2, respectively.

Current Gain Degradation

75

Using the E-B junction as an example.

The surface traps are efficient recombination centers in the E-B depletion region, causing extrinsic Ib to increase due to more hole recombination, which leads to current gain degradation.

EUV-induced Surface Traps

Verilog-AMS (Verilog-A)Phase Change MemoryBit StoragePhase ChangePROGRAM and READI-V CharacteristicR-I CharacteristicModel ArchitectureDecision CircuitPhase Change CircuitFalling Edge ProblemCrystallization Time CalibrationLogic CircuitModel VerificationCrystallization FractionGoalTools and EnvironmentImplementationSPICE ParametersSimulation Results (I)Simulation Results (II)Simulation Results (III)Simulation Results (IV)Simulation Results (V)Detect/Decide SwitchingConclusionsConclusionsConclusions

Documents

Physical Mechanisms and SPICE Modeling of Resistive Random … · 2 Motivation • Various next-generation NVMs ¾PCM, RRAM (resistive switching) • SPICE Models to facilitate memory