PIC16(L)F153XX Product Brief - tme.eu filePIC16(L)F153XX DS40001835A-page 2 Advance Information 2016 Microchip Technology Inc. • Communication: - Up to two EUSART, RS-232, RS-485,

PIC16(L)F153XXCost-Effective 8 to 48 Pins Microcontroller Product Brief

Description

PIC16(L)F153XX microcontrollers feature Intelligent Analog, Core Independent Peripherals (CIPs) and communicationperipherals combined with eXtreme Low-Power (XLP) for a wide range of general purpose and low-power applications.The family features PWMs, multiple communication, temperature sensor and memory features like Memory AccessPartition (MAP) and Device Information Area (DIA). The products are offered in a broad range of pin counts from 8 to48 pins, to support customers in various applications.

Core Features

• C Compiler Optimized RISC Architecture• Only 49 Instructions• Operating Speed:

- DC – 32 MHz clock input- 125 ns minimum instruction cycle

• Interrupt Capability• 16-Level Deep Hardware Stack• Timers:

- 8-bit (TMR2) with Hardware Limit Timer (HLT) Extension

- 16-bit (TMR0/1)• Low-Current Power-on Reset (POR)• Configurable Power-up Timer (PWRTE)• Brown-out Reset (BOR) with Fast Recovery• Low-Power BOR (LPBOR) Option• Windowed Watchdog Timer (WWDT):

- Variable prescaler selection- Variable window size selection- All sources configurable in hardware or software

• Programmable Code Protection

Memory

• Up to 28 KB Flash Program Memory• Up to 2 KB Data SRAM Memory• Direct, Indirect and Relative Addressing modes• Memory Access Partition (MAP):

- Write protect- Customizable Partition

• Device Information Area (DIA)

Operating Characteristics

• Operating Voltage Range:- 1.8V to 3.6V (PIC16LF153XX)- 2.3V to 5.5V (PIC16F153XX)

• Temperature Range:- Industrial: -40°C to 85°C- Extended: -40°C to 125°C

Power-Saving Functionality

• Doze mode: - Ability to run CPU core slower than the

system clock• Idle mode:

- Ability to halt CPU core while internal peripherals continue operating

• Sleep mode: - Lowest power consumption

• Peripheral Module Disable (PMD): - Ability to disable hardware module to minimize

power consumption of unused peripherals

eXtreme Low-Power (XLP) Features

• Sleep mode: 50 nA @ 1.8V, typical • Watchdog Timer: 500 nA @ 1.8V, typical • Secondary Oscillator: 500 nA @ 32 kHz • Operating Current:

- 8 uA @ 32 kHz, 1.8V, typical - 32 uA/MHz @ 1.8V, typical

Digital Peripherals

• Four Configurable Logic Cells (CLCs): - Integrated combinational and sequential logic

• Complementary Waveform Generator (CWG):- Rising and Falling edge dead-band control- Full-bridge, half-bridge, 1-channel drive- Multiple signal sources

• Two Capture/Compare/PWM (CCP) modules• Four 10-bit PWMs• Numerically Controlled Oscillator (NCO):

- Generates true linear frequency control and increased frequency resolution

- Input Clock: 0 Hz < fNCO < 32 MHz- Resolution: fNCO/220

• Peripheral Pin Select (PPS): - Enables pin mapping of digital I/O

2016 Microchip Technology Inc. Advance Information DS40001835A-page 1

PIC16(L)F153XX

• Communication: - Up to two EUSART, RS-232, RS-485, LIN

compatible- Up to two SPI - Two I2C, SMBus, PMBus™ compatible

• Up to 44 I/O Pins- Individually programmable pull-ups slew rate

control Interrupt-on-Change with edge-select

Analog Peripherals

• Analog-to-Digital Converter (ADC):- 10-bit with up to 43 external channels- Conversion available during Sleep

• Two Comparator:- Low-Power/High-Speed mode - Fixed Voltage Reference at (non)inverting

input(s) - Comparator outputs externally accessible

• 5-Bit Digital-to-Analog Converter (DAC):- 5-bit resolution, rail-to-rail- Positive Reference Selection - Unbuffered I/O pin output- Internal connections to ADCs and comparators

• Voltage Reference:- Fixed Voltage Reference with 1.024V, 2.048V

and 4.096V output level

Flexible Oscillator Structure

• High-Precision Internal Oscillator:- Selectable frequency range up to 32 MHz- ±1% at calibration (nominal)

• x2/x4 PLL with Internal and External Sources• Low-Power Internal 32 kHz Oscillator (LFINTOSC)• External 32 kHz Crystal Oscillator (SOCS)• External Oscillator Block with:

- Three crystal/resonator modes up to 20 MHz- Three external clock modes up to 20 MHz- Fail-Safe Clock Monitor- Allows for safe shutdown if peripherals

clock stops - Oscillator Start-up Timer (OST)- Ensures stability of crystal oscillator sources

DS40001835A-page 2 Advance Information 2016 Microchip Technology Inc.

PIC16(L)F153XX

Deb

ug

(1

)

TABLE 1: PIC16(L)F153XX FAMILY TYPES

DeviceD

ata

Sh

eet

Ind

ex

Pro

gra

m F

las

h M

emo

ry (

KW

)

Pro

gra

m F

lash

Mem

ory

(K

B)

Sto

rag

e A

rea

Fla

sh

(B

)

Da

ta S

RA

M(b

ytes

)

I/O P

ins

10-B

it A

DC

5-B

it D

AC

Co

mp

ara

tor

8-B

it/ (

wit

h H

LT)

Tim

er

16-B

it T

ime

r

Win

do

w W

atc

hd

og

Tim

er

CC

P/1

0-B

it P

WM

CW

G

NC

O

CL

C

Ze

ro C

ross

De

tec

t

Tem

per

atu

re S

enso

r

Me

mo

ry A

cces

s P

arti

tio

n

De

vic

e In

form

atio

n A

rea

EU

SA

RT

/ I2 C

/SP

I

Pe

rip

her

al P

in S

ele

ct

Per

iph

eral

Mo

du

le D

isab

le

PIC16F15313 (C) 2 3.5 224 256 6 5 1 1 1 2 Y 2/4 1 1 4 Y Y Y Y 1/1 Y Y I

PIC16F15323 (C) 2 3.5 224 256 12 11 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 1/1 Y Y I

PIC16F15324 (D) 4 7 224 512 12 11 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/1 Y Y I

PIC16F15325 (B) 8 14 224 1024 12 11 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/1 Y Y I

PIC16F15344 (D) 4 7 224 512 18 17 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/1 Y Y I

PIC16F15345 (B) 8 14 224 1024 18 17 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/1 Y Y I

PIC16F15354 (A) 4 7 224 512 25 24 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I

PIC16F15355 (A) 8 14 224 1024 25 24 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I

PIC16F15356 (E) 16 28 224 2048 25 24 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I

PIC16F15375 (F) 8 14 224 1024 36 35 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I

PIC16F15376 (E) 16 28 224 2048 36 35 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I

PIC16F15385 (F) 8 14 224 1024 44 43 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I

PIC16F15386 (E) 16 28 224 2048 44 43 1 2 1 2 Y 2/4 1 1 4 Y Y Y Y 2/2 Y Y I

Note 1: I - Debugging integrated on chip.

Data Sheet Index:

A: Future Release PIC16(L)F15354/5 Data Sheet, 28-Pin

B: Future Release PIC16(L)F15325/45 Data Sheet, 14/20-Pin

C: Future Release PIC16(L)F15313/23 Data Sheet, 8/14-Pin

D: Future Release PIC16(L)F15324/44 Data Sheet, 14/20-Pin

E: Future Release PIC16(L)F15356/76/86 Data Sheet, 28/40/48-Pin

F: Future Release PIC16(L)F15375/85 Data Sheet, 40/48-Pin

Note: For other small form-factor package availability and marking information, visit www.microchip.com/packag-ing or contact your local sales office.


http://www.microchip.com/PIC16F15313










http://www.microchip.com/pagehandler/en-us/designsupport/quality/packaging.html

PIC16(L)F153XX

TABLE 2: PACKAGES

Device (S)PDIP SOIC SSOP TSSOP(U)DFN

(3x3)QFN (4x4)

QFN (6x6)

UQFN (4x4)

TQFPQFN (8x8)

UQFN (5x5)

UQFN (6x6)

PIC16(L)F15313 X X — — X — — — — — — —

PIC16(L)F15323 X X — X — X — X — — — —

PIC16(L)F15324 X X — X — X — X — — — —

PIC16(L)F15325 X X — X — X — X — — — —

PIC16(L)F15344 X X X — — X — X — — — —

PIC16(L)F15345 X X X — — X — X — — — —

PIC16(L)F15354 X X X — — — X X — — — —

PIC16(L)F15355 X X X — — — X X — — — —

PIC16(L)F15356 X X X — — — X X — — — —

PIC16(L)F15375 X — — — — — — — X X X —

PIC16(L)F15376 X — — — — — — — X X X —

PIC16(L)F15385 — — — — — — — — X — — X

PIC16(L)F15386 — — — — — — — — X — — X

Note: Pin details are subject to change.


PIC16(L)F153XX

PIN DIAGRAMS

FIGURE 1: 8-PIN PDIP, SOIC, MSOP, FOR PIC16(L)F15313

FIGURE 2: 14-PIN PDIP, SOIC, TSSOP FOR PIC16(L)F15323

FIGURE 3: 14-PIN PDIP, TSSOP FOR PIC16(L)F15324 AND PIC16(L)F15325

FIGURE 4: 20-PIN PDIP, SOIC, SSOP FOR PIC16(L)F15344, PIC16(L)F15345

1234

VDD

RA5RA4

VPP/MCLR/RA3

RA0/ICSPDATRA1/ICSPCLK

RA2

VSS8765

PIC

16(L

)F15

313

Note: See Table 3 for location of all peripheral functions.

1234567

VDD

RA5

RA4

VPP/MCLR/RA3RC5RC4RC3

RA0/ICSPDAT

RA1/ICSPCLK

RA2

RC0RC1RC2

14

13121110

9

8

VSS

PIC

16

(L)F

15

32

3Note: See Table 4 for location of all peripheral functions.

1234567

VDD

RA5

RA4

VPP/MCLR/RA3RC5RC4RC3

RA0/ICSPDAT

RA1/ICSPCLK

RA2

RC0RC1RC2

14

13121110

9

8

VSS

PIC

16

(L)F

15

32

4

PIC

16

(L)F

15

32

5


PIC

16

(L)F

15

34

4P

IC1

6(L

)F1

53

45

1

2

3

4

20

19

18

17

5

6

7

16

15

14

VDD

RA5

RA4

MCLR/VPP/RA3

RC5

RC4

RC3

VSS

RA0/ICSPDAT

RA1/ICSPCLK

RA2

RC0

RC1

RC2

8

9

10

13

12

11

RC6

RC7

RB7

RB4

RB5

RB6



PIC16(L)F153XX

FIGURE 5: 28-PIN PDIP, SOIC, SSOP FOR PIC16(L)F15354, PIC16(L)F15355, PIC16(L)F15356

FIGURE 6: 40-PIN PDIP FOR PIC16(L)F15375, PIC16(L)F15376

PIC

16

(L)F

15

35

4P

IC1

6(L

)F1

53

55

PIC

16

(L)F

15

35

6

1

2

3

4

5

6

7

8

9

10

VPP/MCLR/RE3

RA0

RA1

RA2

RA3

RA4

RA5

RB6/ICSPCLK

RB5

RB4

RB3

RB2

RB1

RB0

VDD

VSS

11

12

13

14 15

16

17

18

19

20

28

27

26

25

24

23

22

21VSS

RA7

RA6

RC0

RC1

RC2

RC3

RC5

RC4

RC7

RC6

RB7/ICSPDAT


2

3

4

5

6

7

8

9

10

VPP/MCLR/RE3

RA0

RA1

RA2

RA3

RA4

RA5

RE0

RE1

RE2

RB6/ICSPCLK

RB5

RB4

RB0

VDD

VSS

RD2

11

12

13

14

15

16

17

18

19

20

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

VDD

VSS

RA7

RA6

RC0

RC1

RC2

RC3

RD0

RD1

RC5

RC4

RD3

RD4

RC7

RC6

RD7

RD6

RD5

RB7/ICSPDAT1

RB3

RB2

RB1

PIC

16

(L)F

15

37

5P

IC1

6(L

)F1

53

76



PIC16(L)F153XX

FIGURE 7: 16-PIN QFN/UQFN (4X4) FOR PIC16(L)F15323, PIC16(L)F15324, PIC16(L)F15325

FIGURE 8: 20-PIN QFN/UQFN (4x4) FOR PIC16(L)F15344 AND PIC16(L)F15345

7 8

23

1 12

13

9

5

1011

141516

6

4

RA5RA4

MCLR/VPP/RA3RC5

RA2RA1/ICSPCLKRA0/ICSPDAT

Vss

VD

D

RC0

RC

4R

C3

RC

2R

C1

NC

NC

PIC16(L)F15323

PIC16(L)F15324

PIC16(L)F15325

Note 1: See Table 4 for location of all peripheral functions.

2: It is recommended that the exposed bottom pad be connected to VSS.

-

8 9

23

11415

16

10

11

6

1213

17181920

7

54

PIC16

(L)F

1534

4

PIC16

(L)F

1534

5RA3/MCLR/VPP

RC5RC4RC3RC6

RC

7R

B7

RB

4R

B5

RB

6

RC1RC0RA2RA1/ICSPCLK

RA

0/IC

SP

DA

TV

ssV

DD

RA

4R

A5

RC2


2: It is recommended that the exposed bottom pad be connected to VSS.


PIC16(L)F153XX

FIGURE 9: 28-PIN UQFN (4X4) FOR PIC16(L)F15354, PIC16(L)F15355, PIC16(L)F15356

FIGURE 10: 28-PIN QFN (6X6) FOR PIC16(L)F15354, PIC16(L)F15355, PIC16(L)F15356

Note: See Table 5 or the pin allocation tables.

23

6

1

18192021

1571617

RC

0

54

RB

7/IC

SP

DA

TR

B6/

ICS

PC

LKR

B5

RB

4

RB0VDD

VSS

RC7

RC

6R

C5

RC

4

RE

3/M

CLR

/VP

P

RA

0R

A1

RA2RA3RA4RA5VSS

RA7RA6

RC

1R

C2

RC

3

9 10

13

8 14

12

11

27

26

23

28

22

24

25

RB3RB2RB1PIC16(L)F15354

PIC16(L)F15355PIC16(L)F15356

Note: See Table 5 or the pin allocation tables.

23

6

1

18192021

1571617

RC

0

54

RB

7/IC

SP

DA

TR

B6/

ICS

PC

LKR

B5

RB

4

RB0VDD

VSS

RC7

RC

6R

C5

RC

4

RE

3/M

CLR

/VP

P

RA

0R

A1

RA2RA3RA4RA5VSS

RA7RA6

RC

1R

C2

RC

3

9 10

13

8 14

12

11

27

26

23

28

22

24

25

RB3RB2RB1PIC16(L)F15354

PIC16(L)F15355PIC16(L)F15356


PIC16(L)F153XX

FIGURE 11: 40-PIN UQFN (5X5) FOR PIC16(L)F15375, PIC16(L)F15376

FIGURE 12: 44-PIN TQFP (10X10) FOR PIC16(L)F15375, PIC16(L)F15376

Note: See Table 6 for the pin allocation tables.

10

11

2

3

4

5

6

1

18 19 20

21

22

12 13 14 15

38

8

7

40

39

16 17

29

30

313233

23

24

25

26

27

28

36 34

35

9

37

RA

1R

A0

VP

P/M

CLR

/RE

3

RB

3

ICS

PD

AT

/RB

7IC

SP

CLK

/RB

6R

B5

RB

4R

C6

RC

5R

C4

RD

3R

D2

RD

1R

D0

RC

3R

C2

RC

1

RC0RA6RA7VSS

VDD

RE2RE1RE0RA5RA4

RC7RD4RD5RD6RD7VSS

VDD

RB0RB1RB2

PIC16(L)F15375PIC16(L)F15376

RA

3R

A2


2: All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to floatmay result in degraded electrical performance or non-functionality.

10

11

23

6

1

18

19

20

21

2212

13

14

15

38

87

44

43 42 41

40

39

16

17

29

30313233

2324252627

28

36

34

35

9

37

5

4

PIC16(L)F15375PIC16(L)F15376

RC

6

RC

5

RC

4

RD

3

RD

2

RD

1

RD

0

RC

3R

C2

RC

1

RC0

RA

1A

N0

/RA

0V

PP/M

CL

R/R

E3

RB3

ICS

PD

AT

/RB

7IC

SP

CL

K/R

B6

RB

5R

B4

NC

RA

3

RA

2

RC7RD4

RD5

RD6RD7VSS

VDD

RB0

RB1RB2

RA6RA7VSS

NC

VDD

RE2

RE1RE0RA5RA4

NC

NC


PIC16(L)F153XX

FIGURE 13: 44-PIN QFN (8X8X0.9) FOR PIC16(L)F15375, PIC16(L)F15376

FIGURE 14: 48-PIN UQFN (6X6) FOR PIC16(L)F15385, PIC16(L)F15386

Note 1: See Table 6 for location of all peripheral functions.2: All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to float

may result in degraded electrical performance or non-functionality.

3: The bottom pad of the QFN/UQFN package should be connected to VSS at the circuit board level.

4: No internal connection; reserved for backwards compatibility with previous 44-pin devices (VSS connection).

5: No internal connection; reserved for backwards compatibility with previous 44-pin devices (VDD connection).

1011

23456

1

18

19

20

21 22

12

13

14

15

38

87

44

43

42

41

40

39

16

17

2930313233

232425262728

36

34

35

9

37

RA

0V

PP/M

CL

R/R

E3

RB

3

ICS

PD

AT

/RB

7IC

SP

CL

K/R

B6

RB

5R

B4

NC

RC

6R

C5

RC

4R

D3

RD

2R

D1

RD

0R

C3

RC

2R

C1

RC

0

RA6RA7NCVSSNCVDDRE2RE1RE0RA5RA4

RC7RD4RD5RD6RD7VSSVDDNC

RB0RB1RB2

PIC16(L)F15375PIC16(L)F15376

RA

3R

A2

RA

1


48 47 46 45 43 42 41 40 39 38

13 14 15 16 17 18 19 21 22 23

3

33

31

30

29

28

27

26

25

4

5

7

9

10

11

12

1

2 35

34

6

24

36

37

RA4

RA5

RE0

RE1

RE2

VDD

VSS

RA6

RC0

RC1

RF0

RC

6

RC

5

RC

4

RD

3

RD

1

RD

0

RC

3

RC

2

RF

3

RF

2

RF

1

RF4

RB3

RB2

RB1

VDD

VSS

RD7

RD6

RD5

RD4

RC7

RF

5

RF

6

RF

7

RB

4

RB

5

ICS

PC

LK/R

B6

ICS

PD

AT

/RB

7

RA

0

RA

1

RA

2

RA

3

8RB0

20

VP

P/M

CLR

/RE

3

32 RA7

44

RD

2

PIC16(L)F15385PIC16(L)F15386


PIC16(L)F153XX

FIGURE 15: 48-PIN TQFP (7X7) FOR PIC16(L)F15385, PIC16(L)F15386

10

11

23

6

1

20

21

22

23

24

16

17

42

87

48

47 46 45

44

43

18

19

31

32333435

2526272829

30

40

39

9

41

5

4

RC

6

RC

5

RC

4

RD

3R

D2

RD

1

RD

0

RC

3R

C2

RF

3

RC0

RA

1

RA

0V

PP/M

CL

R/R

E3

RB3

ICS

PD

AT

/RB

7IC

SP

CL

K/R

B6

RB

5R

B4

RA

3

RA

2

RC7RD4

RD5

RD6RD7VSS

VDD

RB0

RB1RB2

RA6RA7VSS

RC1

VDD

RE2

RE1RE0RA5RA412RF4

13

14

15

RF

5

RF

7

RF

6

36 RF0

37

38

RF

2R

F1


PIC16(L)F15385

PIC16(L)F15386


PIC

16(L)F

153XX

DS

40

00

18

35

A-p

ag

e 1

2A

dv

anc

e In

form

atio

n

20

16

Micro

chip

Te

chn

olo

gy In

c.

EU

SA

RT

CL

C

CL

KR

Inte

rru

pt

Pu

ll-u

p

Ba

sic

/CK(1) CLCIN3(1) ― IOCA0 Y ICDDAT/ ICSPDAT

/DT(1) CLCIN2(1) ― IOCA1 Y ICDCLK/ ICSPCLK

― ― ― INT(1) IOCA2

Y ―

― CLCIN0(1) ― IOCA3 Y MCLR VPP

― ― ― IOCA4 Y CLKOUT OSC2

― CLCIN1(1) ― IOCA5 Y CLKIN OSC1 EIN

― ― ― ― ― VDD

― ― ― ― ― VSS

T1(3) CLC1OUT CLKR ― ― ―

K1 CLC2OUT ― ― ― ―

X1 CLC3OUT ― ― ― ―

― CLC4OUT ― ― ― ―

s.tions.S output registers.

as selected by the INLVL register, instead of the I2C

PIN ALLOCATION TABLESTABLE 3: 8-PIN ALLOCATION TABLE (PIC16(L)F15313)

I/O(2

)

8-P

in P

DIP

/SO

IC/

MS

OP

AD

C

Re

fere

nce

Co

mp

arat

or

NC

O

DA

C

Tim

ers

CC

P

PW

M

CW

G

MS

SP

ZC

D

RA0 7 ANA0 ― C1IN0+ ― DAC1OUT ― ― ― ― ― ― TX

RA1 6 ANA1 VREF+ C1IN0- ― DA1REF+ T0CKI(1) ― ― ― SSP1CLK(1),(4)

SSP1DAT(1),(4)― RX

RA2 5 ANA2 VREF- ― ― DAC1REF- ― ― ― CWG1(1) SSP1CLK(1),(4)

SSP1DAT(1),(4)ZCD1

RA3 4 ― ― ― ― ― ― ― ― ― SSP1SS(1) ―

RA4 3 ANA4 ― C1IN1- ― ― T1G(1)

SOSCO― ― ― ― ―

RA5 2 ANA5 ADACT(1)

― ― ― ― T1CKI(1)

T2IN(1) SOSCIN SOSCI

CCP1(1) CCP2(1)

― ― ― ―

VDD 1 ― ― ― ― ― ― ― ― ― ― ―

VSS 8 ― ― ― ― ― ― ― ― ― ― ―

OUT(2)

― ― ― C1OUT NCO1OUT ― TMR0 CCP1 PWM3 CWG1A SDO1 ― D

― ― ― C2OUT ― ― ― CCP2 PWM4 CWG1B SCK1 ― C

― ― ― ― ― ― ― ― PWM5 CWG1C SCL1(3),(4) ― T

― ― ― ― ― ― ― ― PWM6 CWG1D SDA1(3),(4) ―

Note 1: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pin2: All digital output signals shown in this row are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin op3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PP4: These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST

specific or SMBUS input buffer thresholds.

2

01

6 M

icroch

ip T

ech

no

log

y Inc.

Ad

van

ce

Info

rma

tion

DS

40

00

18

35

A-p

ag

e 1

3

PIC

16(L)F

153XX

TA 6(L)F15344, PIC16(L)F15345)

EU

SA

RT

CL

C

CL

KR

Inte

rru

pt

Pu

ll-u

p

Bas

ic

RA ― ― IOCA0 Y ICDDAT/ ICSPDAT

RA ― ― IOCA1 Y ICDCLK/ ICSPCLK

RA CLCIN0(1),(6) ― INT(1) IOCA2

Y ―

RA ― ― IOCA3 Y MCLR VPP

RA ― ― IOCA4 Y CLKOUT OSC2

RA CLCIN3(1),(5) ― IOCA5 Y CLKIN OSC1 EIN

RC ― ― IOCC0 Y ―

RC CLCIN2(1),(5) ― IOCC1 Y ―


RC CLCIN1(1),(6)

CLCIN0(1),(5)― IOCC3 Y ―

RC K1(5) CLCIN1(1),(5) ― IOCC4 Y ―

RC T1(5) ― ― IOCC5 Y ―



RB CLCIN2(1),(6) ― IOCB4 ― ―

RB T1(6) CLCIN3(1),(6) ― IOCB5 ― ―

BLE 4: 14/16/20-PIN ALLOCATION TABLE (PIC16(L)F15323, PIC16(L)F15324, PIC16(L)F15325, PIC1

I/O(2

)

14-P

in P

DIP

/SO

IC/T

SS

OP

16-

Pin

QF

N/U

QF

N

20-P

in P

DIP

/SO

IC/S

SO

P

20-P

in Q

FN

AD

C

Re

fere

nc

e

Co

mp

ara

tor

NC

O

DA

C

Tim

ers

CC

P

PW

M

CW

G

MS

SP

ZC

D

0 13 12 19 16 ANA0 ― C1IN0+ ― DAC1OUT ― ― ― ― ― ― ―

1 12 11 18 15 ANA1 VREF+ C1IN0- ― DA1REF+ T0CKI(1) ― ― ― ― ― ―

2 11 10 17 14 ANA2 VREF- ― ― DAC1REF- ― ― ― CWG1(1) ― ZCD1 ―

3 4 3 4 1 ― ― ― ― ― ― ― ― ― ― ― ―

4 3 2 3 20 ANA4 ― C1IN1- ― ― T1G(1)

SOSCO― ― ― ― ― ―

5 2 1 2 19 ANA5 ― ― ― ― T1CKI(1) T2IN SOSCIN SOSCI

― ― ― ― ―

0 10 9 16 13 ANC0 ― C2IN0+ ― ― ― ― ― ― SSP1CLK(1),(5)

SSP1DAT(1),(5)― ―

1 9 8 15 12 ANC1 ― C1IN1- C2IN1-

― ― ― ― ― ― SSP1CLK(1),(5)

SSP1DAT(1),(5)― ―

2 8 7 14 11 ANC2 ― C1IN2- C2IN2-

― ― ― ― ― ― ― ― ―

3 7 6 7 4 ANC3 ― C1IN3- C2IN3-

― ― ― CCP2 ― ― SSP1SS(5) ― ―

4 6 5 6 3 ANC4 ― ― ― ― ― ― ― ― SSP2CLK(1),(5)

SSP2DAT(1),(5)― TX1/C

5 5 4 5 2 ANC5 ― ― ― ― ― CCP1 ― ― SSP1CLK(1),(5)

SSP1DAT(1),(5)― RX1/D

6 ― ― 8 5 ANC6 ― ― ― ― ― ― ― ― SSP1SS1(6) ― ―

7 ― ― 9 6 ANC7 ― ― ― ― ― ― ― ― ― ― ―

4 ― ― 13 10 ANB4 ADACT(1)

― ― ― ― ― ― ― ― SSP1CLK(1),(6)

SSP1DAT(1),(6)― ―

5 ― ― 12 9 ANB5 ― ― ― ― ― ― ― ― SSP2CLK(1),(6)

SSP2DAT(1),(6)― RX1/D

PIC

16(L)F

153XX

DS

40

00

18

35

A-p

ag

e 1

4A

dv

anc

e In

form

atio

n

20

16

Micro

chip

Te

chn

olo

gy In

c.

― ― ― IOCB6 Y ―

TX1/CK1(6) ― ― IOCB7 Y ―

― ― ― ― ― VDD

― ― ― ― ― VSS

DT1(3) CLC1OUT CLKR ― ― ―

CK1 CLC2OUT ― ― ― ―

TX1 CLC3OUT ― ― ― ―

― CLC4OUT ― ― ― ―

s.tions.S output registers.s selected by the INLVL register, instead of the I2C specific or

IC16(L)F15344, PIC16(L)F15345)

EU

SA

RT

CL

C

CL

KR

Inte

rru

pt

Pu

ll-u

p

Bas

ic

RB6 ― ― 11 8 ANB6 ― ― ― ― ― ― ― ― SSP1CLK(1),(6)

SSP1DAT(1),(6)―

RB7 ― ― 10 7 ANB7 ― ― ― ― ― ― ― ― SSP2CLK(1),(6)

SSP2DAT(1),(6)―

VDD 1 16 1 18 ― ― ― ― ― ― ― ― ― ― ―

VSS 14 13 20 17 ― ― ― ― ― ― ― ― ― ― ―

OUT(2)

― ― ― ― ― ― C1OUT NCO1OUT ― TMR0 CCP1 PWM3 CWG1A SDO1SDO2

―

― ― ― ― ― ― C2OUT ― ― ― CCP2 PWM4 CWG1B SCK1SCK2

―

― ― ― ― ― ― ― ― ― ― ― PWM5 CWG1C SCL1(3),(4)

SCL2(3),(4)―

― ― ― ― ― ― ― ― ― ― ― PWM6 CWG1D SDA1(3),(4)

SDA2(3),(4) ―

Note 1: This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pin2: All digital output signals shown in this row are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin op3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PP4: These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST a

SMBUS input buffer thresholds.5: For 14 and 16-pin package only.6: For 20-pin package only.

TABLE 4: 14/16/20-PIN ALLOCATION TABLE (PIC16(L)F15323, PIC16(L)F15324, PIC16(L)F15325, PI/O

(2)

14-P

in P

DIP

/SO

IC/T

SS

OP

16-

Pin

QF

N/U

QF

N

20-P

in P

DIP

/SO

IC/S

SO

P

20-P

in Q

FN

AD

C

Re

fere

nc

e

Co

mp

ara

tor

NC

O

DA

C

Tim

ers

CC

P

PW

M

CW

G

MS

SP

ZC

D

2

01

6 M

icroch

ip T

ech

no

log

y Inc.

Ad

van

ce

Info

rma

tion

DS

40

00

18

35

A-p

ag

e 1

5

PIC

16(L)F

153XX

TA

CL

C

CL

KR

Inte

rru

pt

Pu

ll―u

p

Bas

ic

RA LCIN0(1) ― IOCA0 Y ―

RA LCIN1(1) ― IOCA1 Y ―

RA ― IOCA2 Y ―

RA ― IOCA3 Y ―

RA ― IOCA4 Y ―

RA ― IOCA5 Y ―

RA ― IOCA6 Y CLKOUT

RA ― IOCA7 Y CLKIN

RB ― INT(1)

IOCB0Y ―

RB ― IOCB1 Y ―

RB ― IOCB2 Y ―

RB ― IOCB3 Y ―

RB ― IOCB4 Y ―

RB ― IOCB5 Y ―

RB LCIN2(1) ― IOCB6 Y ICDCLK ICSPCLK

RB LCIN3(1) ― IOCB7 Y ICDDAT ICSPDAT

RC ― IOCC0 Y ―

RC ― IOCC1 Y ―

RC ― IOCC2 Y ―

RC ― IOCC3 Y ―

RC ― IOCC4 Y ―

BLE 5: 28-PIN ALLOCATION TABLE (PIC16(L)F15354, PIC16(L)F15355, PIC16(L)F15356)

I/O

(2)

28-P

in P

DIP

/SO

IC/S

SO

P

28-

Pin

(U

)QF

N

AD

C

Ref

eren

ce

Co

mp

arat

or

NC

O

DA

C

Tim

ers

CC

P

PW

M

CW

G

MS

SP

ZC

D

EU

SA

RT

0 2 27 ANA0 ― C1IN0- C2IN0-

― ― ― ― ― ― ― ― ― C

1 3 28 ANA1 ― C1IN1- C2IN1-

― ― ― ― ― ― ― ― ― C

2 4 1 ANA2 ― C1IN0+ C2IN0+

― ― ― ― ― ― ― ― ― ―

3 5 2 ANA3 VREF+ C1IN1+ ― DACREF+ ― ― ― ― ― ― ― ―

4 6 3 ANA4 ― ― ― ― T0CKI ― ― ― ― ― ― ―

5 7 4 ANA5 ― ― ― ― T1G(1) ― ― ― SSP1SS(1) ― ― ―

6 10 7 ANA6 ― ― ― ― ― ― ― ― ― ― ― ―

7 9 6 ANA7 ― ― ― ― ― ― ― ― ― ― ― ―

0 21 18 ANB0 ― C2IN1+ ― ― ― ― ― CWG1(1) SSP2SS(1) ZCD1 ― ―

1 22 19 ANB1 ― C1IN3- C2IN3-

― ― ― ― ― ― SSP1CLK(1)

SSP1DAT(1)― ― ―

2 23 20 ANB2 ― ― ― ― ― ― ― ― SSP1CLK(1) SSP1DAT(1)

― ― ―

3 24 21 ANB3 ― C1IN2- C2IN2-

― ― ― ― ― ― ― ― ― ―

4 25 22 ANB4ADACT(1)

― ― ― ― ― ― ― ― ― ― ― ―

5 26 23 ANB5 ― ― ― ― ― ― ― ― ― ― ― ―

6 27 24 ANB6 ― ― ― ― ― ― ― ― ― ― TX2 CK2(1)

C

7 28 25 ANB7 ― ― ― DAC1OUT2 ― ― ― ― ― ― RX2 DT2(1)

C

0 11 8 ANC0 ― ― ― ― SOSCO T1CKI

― ― ― ― ― ― ―

1 12 9 ANC1 ― ― ― ― SOSCI CCP2(1) ― ― ― ― ― ―

2 13 10 ANC2 ― ― ― ― ― CCP1(1) ― ― ― ― ― ―

3 14 11 ANC3 ― ― ― ― T2IN(1) ― ― ― SSP1CLK(1)


4 15 12 ANC4 ― ― ― ― ― ― ― ― SSP1CLK(1)


PIC

16(L)F

153XX

DS

40

00

18

35

A-p

ag

e 1

6A

dv

anc

e In

form

atio

n

20

16

Micro

chip

Te

chn

olo

gy In

c.

― ― IOCC5 Y ―

)― ― IOCC6 Y ―

)― ― IOCC7 Y ―

― ― IOCE3 Y MCLR VPP

― ― ― ― VDD

― ― ― ― VSS

― ― ― ― VSS

― ― ― ― ―

CLC1OUT CLKR ― ― ―

CLC2OUT ― ― ― ―





INUED)

CL

C

CL

KR

Inte

rru

pt

Pu

ll―

up

Ba

sic

RC5 16 13 ANC5 ― ― ― ― ― ― ― ― ― ― ―

RC6 17 14 ANC6 ― ― ― ― ― ― ― ― ― ― TX1 CK1(1

RC7 18 15 ANC7 ― ― ― ― ― ― ― ― ― ― RX1 DT1(1

RE3 1 26 ANE3 ― ― ― ― ― ― ― ― ― ― ―

VDD 20 17 ― ― ― ― ― ― ― ― ― ― ― ―

VSS 8 16 ― ― ― ― ― ― ― ― ― ― ― ―

VSS 19 5 ― ― ― ― ― ― ― ― ― ― ― ―

VSEL0 19 17 ― ― ― ― ― ― ― ― ― ― ― ―

OUT(2)

― ― ― ― C1OUT NCO1OUT ― TMR0 CCP1 PWM3 CWG1A CWG2A

SDO ― DT(3)

― ― ― ― C2OUT ― ― ― CCP2 PWM4 CWG1B CWG2B

SCK ― CK

― ― ― ― ― ― ― ― ― PWM5 CWG1C CWG2C

SCL(3),(4) ― TX

― ― ― ― ― ― ― ― ― PWM6 CWG1D CWG2D

SDA(3),(4) ― ―

Note 1: This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pin2: All digital output signals shown in this row are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin op3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PP4: These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST


TABLE 5: 28-PIN ALLOCATION TABLE (PIC16(L)F15354, PIC16(L)F15355, PIC16(L)F15356) (CONTI/O

(2)

28-

Pin

PD

IP/S

OIC

/SS

OP

28-P

in (

U)Q

FN

AD

C

Re

fere

nce

Co

mp

ara

tor

NC

O

DA

C

Tim

ers

CC

P

PW

M

CW

G

MS

SP

ZC

D

EU

SA

RT

2

01

6 M

icroch

ip T

ech

no

log

y Inc.

Ad

van

ce

Info

rma

tion

DS

40

00

18

35

A-p

ag

e 1

7

PIC

16(L)F

153XX

TA

EU

SA

RT

CL

C

CL

KR

Inte

rru

pt

Pu

ll-u

p

Ba

sic

RA CLCIN0(1) ― IOCA0 Y ―

RA CLCIN1(1) ― IOCA1 Y ―

RA ― ― IOCA2 Y ―




RA ― ― IOCA6 Y CLKOUT

RA ― ― IOCA7 Y CLKIN

RB ― ― INT(1)

IOCB0Y ―

RB ― ― IOCB1 Y ―





RB (1)

CLCIN2(1) ― IOCB6 Y ICDCLK ICSPCLK

RB (1)

CLCIN3(1) ― IOCB7 Y ICDDAT ICSPDAT






BLE 6: 40/44-PIN ALLOCATION TABLE (PIC16(L)F15375, PIC16(L)F15376)

I/O

(2)

40-P

in P

DIP

40-P

in U

QF

N

44-

Pin

QF

N

44

-Pin

TQ

FP

AD

C

Re

fere

nce

Co

mp

arat

or

NC

O

DA

C

Tim

ers

CC

P

PW

M

CW

G

MS

SP

ZC

D

0 2 17 19 19 ANA0 ― C1IN0- C2IN0-

― ― ― ― ― ― ― ― ―

1 3 18 20 20 ANA1 ― C1IN1- C2IN1-

― ― ― ― ― ― ― ― ―

2 4 19 21 21 ANA2 ― C1IN0+ C2IN0+

― ― ― ― ― ― ― ― ―

3 5 20 22 22 ANA3 VREF+ C1IN1+ ― DACREF+ ― ― ― ― ― ― ―

4 6 21 23 23 ANA4 ― ― ― ― T0CKI(1) ― ― ― ― ― ―

5 7 22 24 24 ANA5 ― ― ― ― T1G(1) ― ― ― SSP1SS(1) ― ―

6 14 29 33 31 ANA6 ― ― ― ― ― ― ― ― ― ― ―

7 13 28 32 30 ANA7 ― ― ― ― ― ― ― ― ― ― ―

0 33 8 9 8 ANB0 ― C2IN1+ ― ― ― ― ― CWG1(1) SSP2SS(1) ZCD1 ―

1 34 9 10 9 ANB1 ― C1IN3- C2IN3-

― ― ― ― ― ― SSP1CLK(1)

SSP1DAT(1)― ―

2 34 10 11 10 ANB2 ― ― ― ― ― ― ― ― SSP1CLK(1)

SSP1DAT(1)― ―

3 36 11 12 11 ANB3 ― C1IN2- C2IN2-

― ― ― ― ― ― ― ― ―

4 37 12 14 14 ANB4 ADACT(1)

― ― ― ― ― ― ― ― ― ― ―

5 38 13 15 15 ANB5 ― ― ― ― ― ― ― ― ― ― ―

6 39 14 16 16 ANB6 ― ― ― ― ― ― ― ― ― ― TX2CK2

7 40 15 17 17 ANB7 ― ― ― DAC1OUT2 ― ― ― ― ― ― RX2DT2

0 15 30 34 32 ANC0 ― ― ― ― SOSCO T1CKI(1)

― ― ― ― ― ―

1 16 31 35 35 ANC1 ― ― ― ― SOSCI CCP2(1) ― ― ― ― ―

2 17 32 36 36 ANC2 ― ― ― ― ― CCP1(1) ― ― ― ― ―

3 18 33 37 37 ANC3 ― ― ― ― T2IN(1) ― ― ― SSP1CLK(1)

SSP1DAT(1)― ―

4 23 38 42 42 ANC4 ― ― ― ― ― ― ― ― SSP1CLK(1)

SSP1DAT(1)― ―

PIC

16(L)F

153XX

DS

40

00

18

35

A-p

ag

e 1

8A

dv

anc

e In

form

atio

n

20

16

Micro

chip

Te

chn

olo

gy In

c.

― ― ― IOCC5 Y ―

TX1 CK1(1)

― ― IOCC6 Y ―

RX1 DT1(1)

― ― IOCC7 Y ―

― ― ― ― ― ―

― ― ― ― ― ―

― ― ― ― ― ―

― ― ― ― ― ―

― ― ― ― ― ―

― ― ― ― ― ―

― ― ― ― ― ―

― ― ― ― ― ―

― ― ― ― ― ―

― ― ― ― ― ―

― ― ― ― ― ―

― ― ― IOCE3 Y MCLR VPP

― ― ― ― ― VDD

― ― ― ― ― VDD

― ― ― ― ― VSS

― ― ― ― ― VSS

― ― ― ― ― ―

EU

SA

RT

CL

C

CL

KR

Inte

rru

pt

Pu

ll-u

p

Ba

sic

RC5 24 39 43 43 ANC5 ― ― ― ― ― ― ― ― ― ―

RC6 25 40 44 44 ANC6 ― ― ― ― ― ― ― ― ― ―

RC7 26 1 1 1 ANC7 ― ― ― ― ― ― ― ― ― ―

RD0 19 34 38 38 AND0 ― ― ― ― ― ― ― ― SSP2CLK(1)

SSP2DAT(1)―

RD1 20 35 39 39 AND1 ― ― ― ― ― ― ― ― SSP2CLK(1)

SSP2DAT(1)―

RD2 21 36 40 40 AND2 ― ― ― ― ― ― ― ― ― ―

RD3 22 37 41 41 AND3 ― ― ― ― ― ― ― ― ― ―

RD4 27 2 2 2 AND4 ― ― ― ― ― ― ― ― ― ―

RD5 28 3 3 3 AND5 ― ― ― ― ― ― ― ― ― ―

RD6 29 4 4 4 AND6 ― ― ― ― ― ― ― ― ― ―

RD7 30 5 5 5 AND7 ― ― ― ― ― ― ― ― ― ―

RE0 8 23 25 25 ANE0 ― ― ― ― ― ― ― ― ― ―

RE1 9 24 26 26 ANE1 ― ― ― ― ― ― ― ― ― ―

RE2 10 25 27 27 ANE2 ― ― ― ― ― ― ― ― ― ―

RE3 1 16 18 18 ANE3 ― ― ― ― ― ― ― ― ― ―

VDD 11 26 7 7 ― ― ― ― ― ― ― ― ― ― ―

VDD 32 7 28 28 ― ― ― ― ― ― ― ― ― ― ―

VSS 12 27 6 6 ― ― ― ― ― ― ― ― ― ― ―

VSS 31 6 30 29 ― ― ― ― ― ― ― ― ― ― ―

VSEL0 31 6 6 6 ― ― ― ― ― ― ― ― ― ― ―

TABLE 6: 40/44-PIN ALLOCATION TABLE (PIC16(L)F15375, PIC16(L)F15376) (CONTINUED)I/O

(2)

40-P

in P

DIP

40-P

in U

QF

N

44-P

in Q

FN

44-P

in T

QF

P

AD

C

Re

fere

nc

e

Co

mp

ara

tor

NC

O

DA

C

Tim

ers

CC

P

PW

M

CW

G

MS

SP

ZC

D

2

01

6 M

icroch

ip T

ech

no

log

y Inc.

Ad

van

ce

Info

rma

tion

DS

40

00

18

35

A-p

ag

e 1

9

PIC

16(L)F

153XX

OU

3) CLC1OUT CLKR ― ― ―




No

tput registers.cted by the INLVL register, instead of the I2C specific

TA

EU

SA

RT

CL

C

CL

KR

Inte

rru

pt

Pu

ll-u

p

Ba

sic

T(2)

― ― ― ― ― ― C1OUT NCO1OUT ― TMR0 CCP1 PWM3 CWG1A CWG2A

SDO1 SDO2

― DT(

― ― ― ― ― ― C2OUT ― ― ― CCP2 PWM4 CWG1B CWG2B

SCK1 SCK2

― CK1CK2

― ― ― ― ― ― ― ― ― ― ― PWM5 CWG1C CWG2C

SCK1(3),(4)

SCL2(3),(4)― TX1

TX2

― ― ― ― ― ― ― ― ― ― ― PWM6 CWG1D CWG2D

SDA1(3),(4) SDA2(3),(4)

― ―

te 1: This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. 2: All digital output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options.3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS ou4: These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as sele

or SMBUS input buffer thresholds.

BLE 6: 40/44-PIN ALLOCATION TABLE (PIC16(L)F15375, PIC16(L)F15376) (CONTINUED)I/O

(2)

40-P

in P

DIP

40-P

in U

QF

N

44-P

in Q

FN

44-P

in T

QF

P

AD

C

Re

fere

nc

e

Co

mp

ara

tor

NC

O

DA

C

Tim

ers

CC

P

PW

M

CW

G

MS

SP

ZC

D

PIC

16(L)F

153XX

DS

40

00

18

35

A-p

ag

e 2

0A

dv

anc

e In

form

atio

n

20

16

Micro

chip

Te

chn

olo

gy In

c.

EU

SA

RT

CL

C

CL

KR

Inte

rru

pt

Pu

ll-u

p

Bas

ic

CLCIN0(1) ― IOCA0 Y ―

CLCIN1(1) ― IOCA1 Y ―

― ― IOCA2 Y ―

― ― IOCA3 Y ―

― ― IOCA4 Y ―

― ― IOCA5 Y ―

― ― IOCA6 Y CLKOUT

― ― IOCA7 Y CLKIN

― ― INT(1) IOCB0

Y ―

― ― IOCB1 Y ―

― ― IOCB2 Y ―

― ― IOCB3 Y ―

― ― IOCB4 Y ―

― ― IOCB5 Y ―

CLCIN2(1) ― IOCB6 Y ICDCLK ICSPCLK

CLCIN3(1) ― IOCB7 Y ICDDAT ICSPDAT

― ― IOCC0 Y ―

― ― IOCC1 Y ―

― ― IOCC2 Y ―

― ― IOCC3 Y ―

TABLE 7: 48-PIN ALLOCATION TABLE (PIC16(L)F15385, PIC16(L)F15386)I/O

(2)

48-P

in U

QF

N/T

QF

P

AD

C

Re

fere

nc

e

Co

mp

ara

tor

NC

O

DA

C

Tim

ers

CC

P

PW

M

CW

G

MS

SP

ZC

D

RA0 21 ANA0 ― C1IN0- C2IN0-

― ― ― ― ― ― ― ― ―

RA1 22 ANA1 ― C1IN1- C2IN1-

― ― ― ― ― ― ― ― ―

RA2 23 ANA2 ― C1IN0+ C2IN0+

― ― ― ― ― ― ― ― ―

RA3 24 ANA3 VREF+ C1IN1+ ― DACREF+ ― ― ― ― ― ― ―

RA4 25 ANA4 ― C1IN1- ― ― T0CKI(1) ― ― ― ― ― ―

RA5 26 ANA5 ADACT

― ― ― ― T1G(1) ― ― ― SSP1SS(1) ― ―

RA6 33 ANA6 ― ― ― ― ― ― ― ― ― ― ―

RA7 32 ANA7 ― ― ― ― ― ― ― ― ― ― ―

RB0 8 ANB0 ― C2IN1+ ― ― ― ― ― CWG1(1) SSP2SS(1) ZCD1 ―

RB1 9 ANB1 ― C1IN3- C2IN3-

― ― ― ― ― ― SSP1CLK(1)

SSP1DAT(1)― ―

RB2 10 ANB2 ― ― ― ― ― ― ― ― SSP1CLK(1)

SSP1DAT(1)― ―

RB3 11 ANB3 ― C1IN3- C2IN3-

― ― ― ― ― ― ― ― ―

RB4 16 ANB4 ADACT(1)

― ― ― ― ― ― ― ― ― ― ―

RB5 17 ANB5 ― ― ― ― ― ― ― ― ― ― ―

RB6 18 ANB6 ― ― ― ― ― ― ― ― ― ― TX2 CK2(1)

RB7 19 ANB7 ― ― ― DAC1OUT2 ― ― ― ― ― ― RX2 DT2(1)

RC0 34 ANC0 ― ― ― ― SOSCO T1CKI(1)

― ― ― ― ― ―

RC1 35 ANC1 ― ― ― ― SOSCI CCP2(1) ― ― ― ― ―

RC2 40 ANC2 ― ― ― ― ― CCP1(1) ― ― ― ― ―

RC3 41 ANC3 ― ― ― ― T2IN(1) ― ― ― SSP1CLK(1)

SSP1DAT(1)― ―

2

01

6 M

icroch

ip T

ech

no

log

y Inc.

Ad

van

ce

Info

rma

tion

DS

40

00

18

35

A-p

ag

e 2

1

PIC

16(L)F

153XX





RD ― ― ― Y ―

RD ― ― ― Y ―

RD ― ― ― Y ―

RD ― ― ― Y ―

RD ― ― ― Y ―

RD ― ― ― Y ―

RD ― ― ― Y ―

RD ― ― ― Y ―

RE ― ― ― Y ―

RE ― ― ― Y ―

RE ― ― ― Y ―

RE ― ― IOCE3 Y MCLR VPP

RF ― ― ― Y ―

RF ― ― ― Y ―

RF ― ― ― Y ―

RF ― ― ― Y ―

RF ― ― ― Y ―

RF ― ― ― Y ―

RF ― ― ― Y ―

RF ― ― ― Y ―

VD ― ― ― Y VDD

VD ― ― ― ― VDD

TA

CL

C

CL

KR

Inte

rru

pt

Pu

ll-u

p

Ba

sic

4 46 ANC4 ― ― ― ― ― ― ― ― SSP1CLK(1)

SSP1DAT(1)― ―

5 47 ANC5 ― ― ― ― ― ― ― ― ― ― ―

6 48 ANC6 ― ― ― ― ― ― ― ― ― ― TX1CK1(1)

7 1 ANC7 ― ― ― ― ― ― ― ― ― ― RX1DT1(1)

0 42 AND0 ― ― ― ― ― ― ― ― SSP2CLK(1)

SSP2DAT(1)― ―

1 43 AND1 ― ― ― ― ― ― ― ― SSP2CLK(1)

SSP2DAT(1)― ―

2 44 AND2 ― ― ― ― ― ― ― ― ― ― ―

3 45 AND3 ― ― ― ― ― ― ― ― ― ― ―

4 2 AND4 ― ― ― ― ― ― ― ― ― ― ―

5 3 AND5 ― ― ― ― ― ― ― ― ― ― ―

6 4 AND6 ― ― ― ― ― ― ― ― ― ― ―

7 5 AND7 ― ― ― ― ― ― ― ― ― ― ―

0 27 ANE0 ― ― ― ― ― ― ― ― ― ― ―

1 28 ANE1 ― ― ― ― ― ― ― ― ― ― ―

2 29 ANE2 ― ― ― ― ― ― ― ― ― ― ―

3 20 ANE3 ― ― ― ― ― ― ― ― ― ― ―

0 36 ANF0 ― ― ― ― ― ― ― ― ― ― ―

1 37 ANF1 ― ― ― ― ― ― ― ― ― ― ―

2 38 ANF2 ― ― ― ― ― ― ― ― ― ― ―

3 39 ANF3 ― ― ― ― ― ― ― ― ― ― ―

4 12 ANF4 ― ― ― ― ― ― ― ― ― ― ―

5 13 ANF5 ― ― ― ― ― ― ― ― ― ― ―

6 14 ANF6 ― ― ― ― ― ― ― ― ― ― ―

7 15 ANF7 ― ― ― ― ― ― ― ― ― ― ―

D 30 ― ― ― ― ― ― ― ― ― ― ― ―

D 7 ― ― ― ― ― ― ― ― ― ― ― ―

BLE 7: 48-PIN ALLOCATION TABLE (PIC16(L)F15385, PIC16(L)F15386) (CONTINUED)I/

O(2

)

48-P

in U

QF

N/T

QF

P

AD

C

Ref

ere

nce

Co

mp

ara

tor

NC

O

DA

C

Tim

ers

CC

P

PW

M

CW

G

MS

SP

ZC

D

EU

SA

RT

PIC

16(L)F

153XX

DS

40

00

18

35

A-p

ag

e 2

2A

dv

anc

e In

form

atio

n

20

16

Micro

chip

Te

chn

olo

gy In

c.

― ― ― ― VSS

― ― ― ― VSS

― ― ― ― ―

CLC1OUT CLKR ― ― ―






EU

SA

RT

CL

C

CL

KR

Inte

rru

pt

Pu

ll-u

p

Ba

sic

VSS 6 ― ― ― ― ― ― ― ― ― ― ― ―

VSS 31 ― ― ― ― ― ― ― ― ― ― ― ―

VSEL0 ― ― ― ― ― ― ― ― ― ― ― ― ―

OUT(2)

― ― ― C1OUT NCO1OUT ― TMR0 CCP1 PWM3 CWG1A CWG2A

SDO1 SDO2

― DT(3)

― ― ― C2OUT ― ― ― CCP2 PWM4 CWG1B CWG2B

SCK1 SCK2

― CK1 CK2

― ― ― ― ― ― ― ― PWM5 CWG1C CWG2C

SCK1(3),(4)

SCL2(3),(4)― TX1

TX2

― ― ― ― ― ― ― ― PWM6 CWG1D CWG2D

SDA1(3),(4) SDA2(3),(4)

― ―

Note 1: This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pin2: All digital output signals shown in this row are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin op3: This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PP4: These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST


TABLE 7: 48-PIN ALLOCATION TABLE (PIC16(L)F15385, PIC16(L)F15386) (CONTINUED)I/

O(2

)

48-P

in U

QF

N/T

QF

P

AD

C

Ref

ere

nce

Co

mp

ara

tor

NC

O

DA

C

Tim

ers

CC

P

PW

M

CW

G

MS

SP

ZC

D

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights unless otherwise stated.

2016 Microchip Technology Inc. Advance Info

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV

== ISO/TS 16949 ==

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.

All other trademarks mentioned herein are property of their respective companies.

© 2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

ISBN: 978-1-5224-0407-1

rmation DS40001835A-page 23


AMERICASCorporate Office2355 West Chandler Blvd.Chandler, AZ 85224-6199Tel: 480-792-7200 Fax: 480-792-7277Technical Support: http://www.microchip.com/supportWeb Address: www.microchip.com

AtlantaDuluth, GA Tel: 678-957-9614 Fax: 678-957-1455

Austin, TXTel: 512-257-3370

BostonWestborough, MA Tel: 774-760-0087 Fax: 774-760-0088

ChicagoItasca, IL Tel: 630-285-0071 Fax: 630-285-0075

ClevelandIndependence, OH Tel: 216-447-0464 Fax: 216-447-0643

DallasAddison, TX Tel: 972-818-7423 Fax: 972-818-2924

DetroitNovi, MI Tel: 248-848-4000

Houston, TX Tel: 281-894-5983

IndianapolisNoblesville, IN Tel: 317-773-8323Fax: 317-773-5453

Los AngelesMission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608

New York, NY Tel: 631-435-6000

San Jose, CA Tel: 408-735-9110

Canada - TorontoTel: 905-673-0699 Fax: 905-673-6509

ASIA/PACIFICAsia Pacific OfficeSuites 3707-14, 37th FloorTower 6, The GatewayHarbour City, Kowloon

Hong KongTel: 852-2943-5100Fax: 852-2401-3431

Australia - SydneyTel: 61-2-9868-6733Fax: 61-2-9868-6755

China - BeijingTel: 86-10-8569-7000 Fax: 86-10-8528-2104

China - ChengduTel: 86-28-8665-5511Fax: 86-28-8665-7889

China - ChongqingTel: 86-23-8980-9588Fax: 86-23-8980-9500

China - DongguanTel: 86-769-8702-9880

China - HangzhouTel: 86-571-8792-8115 Fax: 86-571-8792-8116

China - Hong Kong SARTel: 852-2943-5100 Fax: 852-2401-3431

China - NanjingTel: 86-25-8473-2460Fax: 86-25-8473-2470

China - QingdaoTel: 86-532-8502-7355Fax: 86-532-8502-7205

China - ShanghaiTel: 86-21-5407-5533 Fax: 86-21-5407-5066

China - ShenyangTel: 86-24-2334-2829Fax: 86-24-2334-2393

China - ShenzhenTel: 86-755-8864-2200 Fax: 86-755-8203-1760

China - WuhanTel: 86-27-5980-5300Fax: 86-27-5980-5118

China - XianTel: 86-29-8833-7252Fax: 86-29-8833-7256

ASIA/PACIFICChina - XiamenTel: 86-592-2388138 Fax: 86-592-2388130

China - ZhuhaiTel: 86-756-3210040 Fax: 86-756-3210049

India - BangaloreTel: 91-80-3090-4444 Fax: 91-80-3090-4123

India - New DelhiTel: 91-11-4160-8631Fax: 91-11-4160-8632

India - PuneTel: 91-20-3019-1500

Japan - OsakaTel: 81-6-6152-7160 Fax: 81-6-6152-9310

Japan - TokyoTel: 81-3-6880- 3770 Fax: 81-3-6880-3771

Korea - DaeguTel: 82-53-744-4301Fax: 82-53-744-4302

Korea - SeoulTel: 82-2-554-7200Fax: 82-2-558-5932 or 82-2-558-5934

Malaysia - Kuala LumpurTel: 60-3-6201-9857Fax: 60-3-6201-9859

Malaysia - PenangTel: 60-4-227-8870Fax: 60-4-227-4068

Philippines - ManilaTel: 63-2-634-9065Fax: 63-2-634-9069

SingaporeTel: 65-6334-8870Fax: 65-6334-8850

Taiwan - Hsin ChuTel: 886-3-5778-366Fax: 886-3-5770-955

Taiwan - KaohsiungTel: 886-7-213-7828

Taiwan - TaipeiTel: 886-2-2508-8600 Fax: 886-2-2508-0102

Thailand - BangkokTel: 66-2-694-1351Fax: 66-2-694-1350

EUROPEAustria - WelsTel: 43-7242-2244-39Fax: 43-7242-2244-393

Denmark - CopenhagenTel: 45-4450-2828 Fax: 45-4485-2829

France - ParisTel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79

Germany - DusseldorfTel: 49-2129-3766400

Germany - KarlsruheTel: 49-721-625370

Germany - MunichTel: 49-89-627-144-0 Fax: 49-89-627-144-44

Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781

Italy - VeniceTel: 39-049-7625286

Netherlands - DrunenTel: 31-416-690399 Fax: 31-416-690340

Poland - WarsawTel: 48-22-3325737

Spain - MadridTel: 34-91-708-08-90Fax: 34-91-708-08-91

Sweden - StockholmTel: 46-8-5090-4654

UK - WokinghamTel: 44-118-921-5800Fax: 44-118-921-5820

Worldwide Sales and Service

07/14/15

http://support.microchip.com

http://www.microchip.com

Documents

PIC16(L)F153XX Product Brief - tme.eu filePIC16(L)F153XX DS40001835A-page 2 Advance Information 2016 Microchip Technology Inc. • Communication: - Up to two EUSART, RS-232, RS-485,