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2007 Microchip Technology Inc. Preliminary DS39625C

PIC18F2585/2680/4585/4680Data Sheet

28/40/44-PinEnhanced Flash Microcontrollers

with ECAN Technology, 10-Bit A/Dand nanoWatt Technology

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DS39625C-page ii Preliminary 2007 Microchip Technology Inc.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE . Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyers risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,dsPIC, K EE LOQ , KEE LOQ logo, micro ID , MPLAB, PIC,PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, andSmartShunt are registered trademarks of MicrochipTechnology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, MigratableMemory, MXDEV, MXLAB, PS logo, SEEVAL, Smar tSensorand The Embedded Control Solutions Company areregistered trademarks of Microchip Technology Incorporatedin the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,rfPICDEM, Select Mode, Smart Serial, SmartTel, TotalEndurance, UNI/O, WiperLock and ZENA are trademarks ofMicrochip Technology Incorporated in the U.S.A. and othercountries.

SQTP is a service mark of Microchip Technology Incorporatedin the U.S.A.

All other trademarks mentioned herein are property of theirrespective companies.

2007, Microchip Technology Incorporated, Printed in theU.S.A., All Rights Reserved.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

Microchip products meet the specification contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in theintended manner and under normal conditions.

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to ourknowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips DataSheets. Most likely, the person doing so is engaged in theft of intellectual property.

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does notmean that we are guaranteeing the product as unbreakable.

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Companys quality system processes and procedures are for its PIC MCUs and dsPIC DSCs, K EE LOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchips quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

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2007 Microchip Technology Inc. Preliminary DS39625C-page 1

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Power Managed Modes: Run: CPU on, peripherals on Idle: CPU off, peripherals on Sleep: CPU off, peripherals off Idle mode currents down to 5.8 A typical Sleep mode currents down to 0.1 A typical Timer1 Oscillator: 1.1 A, 32 kHz, 2V Watchdog Timer: 2.1 A Two-Speed Oscillator Start-up

Flexible Oscillator Structure:

Four Crystal modes, up to 40 MHz 4x Phase Lock Loop (PLL) available for crystaland internal oscillators

Two External RC modes, up to 4 MHz Two External Clock modes, up to 40 MHz Internal oscillator block:

- 8 user selectable frequencies, from 31 kHz to 8 MHz- Provides a complete range of clock speeds,

from 31 kHz to 32 MHz when used with PLL- User tunable to compensate for frequency drift

Secondary oscillator using Timer1 @ 32 kHz Fail-Safe Clock Monitor

- Allows for safe shutdown if peripheral clock stops

Special Microcontroller Features: C compiler optimized architecture with optionalextended instruction set

100,000 erase/write cycle Enhanced Flashprogram memory typical

1,000,000 erase/write cycle Data EEPROMmemory typical

Flash/Data EEPROM Retention: > 40 years Self-programmable under software control Priority levels for interrupts 8 x 8 Single Cycle Hardware Multiplier Extended Watchdog Timer (WDT):

- Programmable period from 41 ms to 131s Single-Supply 5V In-Circuit Serial

Programming (ICSP) via two pins In-Circuit Debug (ICD) via two pins Wide operating voltage range: 2.0V to 5.5V

Peripheral Highlights: High current sink/source 25 mA/25 mA Three external interrupts One Capture/Compare/PWM (CCP1) module Enhanced Capture/Compare/PWM (ECCP1) module

(40/44-pin devices only):- One, two or four PWM outputs- Selectable polarity- Programmable dead time- Auto-Shutdown and Auto-Restart

Master Synchronous Serial Port (MSSP) module

supporting 3-wire SPI (all 4 modes) and I2

CMaster and Slave modes Enhanced Addressable USART module:

- Supports RS-485, RS-232 and LIN 1.3- RS-232 operation using internal oscillator

block (no external crystal required)- Auto-Wake-up on Start bit- Auto-Baud Detect

10-bit, up to 11-channel Analog-to-DigitalConverter module (A/D), up to 100 Ksps- Auto-acquisition capability- Conversion available during Sleep

Dual analog comparators with input multiplexing

ECAN Module Features: Message bit rates up to 1 Mbps Conforms to CAN 2.0B ACTIVE Specification Fully backward compatible with PIC18XXX8 CAN

modules Three modes of operation:

- Legacy, Enhanced Legacy, FIFO Three dedicated transmit buffers with prioritization Two dedicated receive buffers Six programmable receive/transmit buffers Three full 29-bit acceptance masks 16 full 29-bit acceptance filters w/ dynamic association DeviceNet data byte filter support Automatic remote frame handling

Advanced error management features

DeviceProgram Memory Data Memory

I/O 10-BitA/D (ch)

CCP1/ ECCP1(PWM)

MSSP

E U S A R T

Comp. Timers8/16-bitFlash(bytes)

# Single-WordInstructions

SRAM(bytes)

EEPROM(bytes) SPI

MasterI2C

PIC18F2585 48K 24576 3328 1024 28 8 1/0 Y Y 1 0 1/3PIC18F2680 64K 32768 3328 1024 28 8 1/0 Y Y 1 0 1/3PIC18F4585 48K 24576 3328 1024 44 11 1/1 Y Y 1 2 1/3PIC18F4680 64K 32768 3328 1024 40/44 11 1/1 Y Y 1 2 1/3

28/40/44-Pin Enhanced Flash Microcontrollers with

ECAN Technology, 10-Bit A/D and nanoWatt Technology

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DS39625C-page 2 Preliminary 2007 Microchip Technology Inc.

Pin Diagrams

RB7/KBI3/PGDRB6/KBI2/PGCRB5/KBI1/PGMRB4/KBI0/AN9RB3/CANRXRB2/INT2/CANTXRB1/INT1/AN8RB0/INT0/FLT0/AN10

VDDVSSRD7/PSP7/P1DRD6/PSP6/P1CRD5/PSP5/P1BRD4/PSP4/ECCP1/P1ARC7/RX/DTRC6/TX/CKRC5/SDORC4/SDI/SDARD3/PSP3/C2IN-RD2/PSP2/C2IN+

MCLR/V PP /RE3RA0/AN0/CV REF

RA1/AN1RA2/AN2/V REF -RA3/AN3/V REF +

RA4/T0CKIRA5/AN4/SS/HLVDIN

RE0/RD/AN5

RE1/WR/AN6/C1OUTRE2/CS/AN7/C2OUT

VDDVSS

OSC1/CLKI/RA7OSC2/CLKO/RA6

RC0/T1OSO/T13CKIRC1/T1OSIRC2/CCP1

RC3/SCK/SCLRD0/PSP0/C1IN+RD1/PSP1/C1IN-

12345678

91011121314151617181920

4039383736353433323130292827262524232221

P I C 1 8 F 4 5 8 5

40-Pin PDIP

P I C 1 8 F 4 6 8 0

P I C 1 8 F 2 5 8 5

1011

23456

1

87

9

121314 15

1617181920

2324252627

28

2221

MCLR/VPP /RE3

RA0/AN0RA1/AN1

RA2/AN2/V REF -RA3/AN3/V REF +


VSSOSC1/CLKI/RA7

OSC2/CLKO/RA6RC0/T1OSO/T13CKI

RC1/T1OSIRC2/CCP1

RC3/SCK/SCL

RB7/KBI3/PGD

RB6/KBI2/PGCRB5/KBI1/PGMRB4/KBI0/AN9RB3/CANRXRB2/INT2/CANTXRB1/INT1/AN8RB0/INT0/AN10VDDVSSRC7/RX/DTRC6/TX/CKRC5/SDORC4/SDI/SDA

28-Pin PDIP, SOIC

P I C 1 8 F 2 6 8 0

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Pin Diagrams (Continued)

1011

23

6

1

1 8 1 9 2 0 2 1 2 2 1 2 1 3 1 4 1 5

3 8

87

4 4 4 3 4 2 4 1 4 0 3 9

1 6 1 7

2930313233

232425262728

3 6 3 4 3 5

9

PIC18F4585

3 7

R A 3 / A N 3 / V R E F +

R A 2 / A N 2 / V R E F -

R A 1 / A N 1

R A 0 / A N 0 / C V R E F

M C L R / V P P / R E 3

N C

R B 7 / K B I 3 / P G D

R B 6 / K B I 2 / P G C

R B 5 / K B I 1 / P G M

R B 4 / K B I 0 / A N 9

N C

R C 6 / T X / C K

R C 5 / S D O

R C 4 / S D I / S D A

R D 3 / P S P 3 / C 2 I N -

R D 2 / P S P 2 / C 2 I N +

R D 1 / P S P 1 / C 1 I N -

R D 0 / P S P 0 / C 1 I N +

R C 3 / S C K / S C L

R C 2 / C C P 1

R C 1 / T 1 O S I

N C

NCRC0/T1OSO/T13CKIOSC2/CLKO/RA6OSC1/CLKI/RA7VSSVDDRE2/CS/AN7/C2OUTRE1/WR/AN6/C1OUTRE0/RD/AN5RA5/AN4/SS/HLVDINRA4/T0CKI

RC7/RX/DTRD4/PSP4/ECCP1/P1A

RD5/PSP5/P1BRD6/PSP6/P1C

VSSVDD

RB0/INT0/FLT0/AN10RB1/INT1/AN8

RB2/INT2/CANTXRB3/CANRX

44-Pin TQFP

RD7/PSP7/P1D 54

44-Pin QFN

1011

23

6

1

1 8 1 9 2 0 2 1 2 2 1 2 1 3 1 4 1 5

3 8

87

4 4 4 3 4 2 4 1 4 0 3 9

1 6 1 7

2930313233

232425262728

3 6 3 4 3 5

9

PIC18F4585

3 7

R A 3 / A N 3 / V R E F +

R A 2 / A N 2 / V R E F -

R A 1 / A N 1

R A 0 / A N 0 / C V R E F

M C L R / V P P / R E 3

R B 7 / K B I 3 / P G D

R B 6 / K B I 2 / P G C

R B 5 / K B I 1 / P G M

R B 4 / K B I 0 / A N 9

N C

R C 6 / T X / C K

R C 5 / S D O

R C 4 / S D I / S D A

R D 3 / P S P 3 / C 2 I N -

R D 2 / P S P 2 / C 2 I N +

R D 1 / P S P 1 / C 1 I N -

R D 0 / P S P 0 / C 1 I N +

R C 3 / S C K / S C L

R C 2 / C C P 1

R C 1 / T 1 O S I

R C 0 / T 1 O S O / T 1 3 C K I

OSC2/CLKO/RA6OSC1/CLKI/RA7VSS

AVDDRE2/CS/AN7/C2OUTRE1/WR/AN6/C1OUT

RE0/RD/AN5RA5/AN4/SS/HLVDINRA4/T0CKI

RC7/RX/DT

RD5/PSP5/P1BRD6/PSP6/P1C

VSS

VDDRB0/INT0/FLT0/AN10

RB1/INT1/AN8RB2/INT2/CANTX

R B 3 / C A N R X

RD7/PSP7/P1D 54 AVSS

VDD

AVDD

PIC18F4680

PIC18F4680

RD4/PSP4/ECCP1/P1A

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Table of Contents1.0 Device Overview .......................................................................................................................................................................... 72.0 Oscillator Configurations ............................................................................................................................................................ 233.0 Power Managed Modes ............................................................................................................................................................. 334.0 Reset .......................................................................................................................................................................................... 415.0 Memory Organization................................................................................................................................................................. 616.0 Flash Program Memory.............................................................................................................................................................. 95

7.0 Data EEPROM Memory ........................................................................................................................................................... 1058.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 1119.0 Interrupts .................................................................................................................................................................................. 11310.0 I/O Ports ................................................................................................................................................................................... 12911.0 Timer0 Module ......................................................................................................................................................................... 14712.0 Timer1 Module ......................................................................................................................................................................... 15113.0 Timer2 Module ......................................................................................................................................................................... 15714.0 Timer3 Module ......................................................................................................................................................................... 15915.0 Capture/Compare/PWM (CCP1) Modules ............................................................................................................................... 16316.0 Enhanced Capture/Compare/PWM (ECCP1) Module.............................................................................................................. 17317.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 18718.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART)....................................................................................... 22719.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 24720.0 Comparator Module.................................................................................................................................................................. 25721.0 Comparator Voltage Reference Module................................................................................................................................... 26322.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 26723.0 ECAN Technology ................................................................................................................................................................ 27324.0 Special Features of the CPU.................................................................................................................................................... 34325.0 Instruction Set Summary .......................................................................................................................................................... 36126.0 Development Support............................................................................................................................................................... 41127.0 Electrical Characteristics .......................................................................................................................................................... 41528.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 45129.0 Packaging Information.............................................................................................................................................................. 453Appendix A: Revision History............................................................................................................................................................. 461Appendix B: Device Differences......................................................................................................................................................... 461Appendix C: Conversion Considerations ........................................................................................................................................... 462Appendix D: Migration From Baseline to Enhanced Devices............................................................................................................. 462Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 463Appendix F: Migration from High-End to Enhanced Devices............................................................................................................. 463Index .................................................................................................................................................................................................. 465The Microchip Web Site..................................................................................................................................................................... 477Customer Change Notification Service .............................................................................................................................................. 477Customer Support .............................................................................................................................................................................. 477Reader Response .............................................................................................................................................................................. 478PIC18F2585/2680/4585/4680 Product Identification System ............................................................................................................ 479
http://devtool_110306.pdf/http://devtool_110306.pdf/

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TO OUR VALUED CUSTOMERSIt is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchipproducts. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined andenhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

E-mail at [email protected] or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. Wewelcome your feedback.

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ErrataAn errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for currentdevices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revisionof silicon and revision of document to which it applies.To determine if an errata sheet exists for a particular device, please check with one of the following:

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NOTES:

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1.0 DEVICE OVERVIEWThis document contains device specific information forthe following devices:

PIC18F2585 PIC18F2680 PIC18F4585 PIC18F4680

This family of devices offers the advantages of all PIC18microcontrollers namely, high computationalperformance at an economical price with the additionof high-endurance, Enhanced Flash program memory.In addition to these features, thePIC18F2585/2680/4585/4680 family introduces designenhancements that make these microcontrollers alogical choice for many high-performance, powersensitive applications.

1.1 New Core Features

1.1.1 nanoWatt TECHNOLOGYAll of the devices in the PIC18F2585/2680/4585/4680family incorporate a range of features that can signifi-cantly reduce power consumption during operation.Key items include:

Alternate Run Modes: By clocking the controllerfrom the Timer1 source or the internal oscillatorblock, power consumption during code executioncan be reduced by as much as 90%.

Multiple Idle Modes: The controller can also runwith its CPU core disabled but the peripherals stillactive. In these states, power consumption can bereduced even further, to as little as 4% of normaloperation requirements.

On-the-fly Mode Switching: The powermanaged modes are invoked by user code duringoperation, allowing the user to incorporatepower-saving ideas into their applicationssoftware design.

Lower Consumption in Key Modules: Thepower requirements for both Timer1 and theWatchdog Timer have been reduced by up to80%, with typical values of 1.1 and 2.1 A,respectively.

Extended Instruction Set: In addition to thestandard 75 instructions of the PIC18 instruction

set, PIC18F2585/2680/4585/4680 devices alsoprovide an optional extension to the core CPUfunctionality. The added features include eightadditional instructions that augment indirect andindexed addressing operations and theimplementation of Indexed Literal OffsetAddressing mode for many of the standard PIC18instructions.

1.1.2 MULTIPLE OSCILLATOR OPTIONSAND FEATURES

All of the devices in the PIC18F2585/2680/4585/4680family offer ten different oscillator options, allowingusers a wide range of choices in developing applicationhardware. These include:

Four Crystal modes, using crystals or ceramicresonators Two External Clock modes, offering the option of

using two pins (oscillator input and a divide-by-4clock output) or one pin (oscillator input, with thesecond pin reassigned as general I/O)

Two External RC Oscillator modes with the samepin options as the External Clock modes

An internal oscillator block which provides an8 MHz clock (2% accuracy) and an INTRCsource (approximately 31 kHz, stable overtemperature and V DD), as well as a range of6 user selectable clock frequencies, between125 kHz to 4 MHz, for a total of 8 clockfrequencies. This option frees the two oscillatorpins for use as additional general purpose I/O.

A Phase Lock Loop (PLL) frequency multiplier,available to both the high-speed crystal andinternal oscillator modes, which allows clockspeeds of up to 40 MHz. Used with the internaloscillator, the PLL gives users a completeselection of clock speeds, from 31 kHz to32 MHz all without using an external crystal orclock circuit.

Besides its availability as a clock source, the internaloscillator block provides a stable reference source thatgives the family additional features for robustoperation: Fail-Safe Clock Monitor: This option constantly

monitors the main clock source against a refer-ence signal provided by the internal oscillator. If aclock failure occurs, the controller is switched tothe internal oscillator block, allowing for continuedlow-speed operation or a safe applicationshutdown.

Two-Speed Start-up: This option allows theinternal oscillator to serve as the clock sourcefrom Power-on Reset, or wake-up from Sleepmode, until the primary clock source is available.

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1.2 Other Special Features

Memory Endurance: The Enhanced Flash cellsfor both program memory and data EEPROM arerated to last for many thousands of erase/writecycles up to 100,000 for program memory and1,000,000 for EEPROM. Data retention without

refresh is conservatively estimated to be greaterthan 40 years. Self-programmability: These devices can write

to their own program memory spaces under inter-nal software control. By using a bootloader rou-tine located in the protected Boot Block at the topof program memory, it becomes possible to createan application that can update itself in the field.

Extended Instruction Set: ThePIC18F2585/2680/4585/4680 family introducesan optional extension to the PIC18 instruction set,which adds 8 new instructions and an IndexedAddressing mode. This extension, enabled as adevice configuration option, has been specificallydesigned to optimize re-entrant application codeoriginally developed in high-level languages, suchas C.

Enhanced CCP1 module: In PWM mode, thismodule provides 1, 2 or 4 modulated outputs forcontrolling half-bridge and full-bridge drivers.Other features include Auto-Shutdown, fordisabling PWM outputs on interrupt or other selectconditions and Auto-Restart, to reactivate outputsonce the condition has cleared.

Enhanced Addressable USART: This serialcommunication module is capable of standardRS-232 operation and provides support for the LIN

bus protocol. Other enhancements includeautomatic baud rate detection and a 16-bit BaudRate Generator for improved resolution. When themicrocontroller is using the internal oscillatorblock, the EUSART provides stable operation forapplications that talk to the outside world withoutusing an external crystal (or its accompanyingpower requirement).

10-bit A/D Converter: This module incorporatesprogrammable acquisition time, allowing for achannel to be selected and a conversion to beinitiated without waiting for a sampling period andthus, reduce code overhead.

Extended Watchdog Timer (WDT): Thisenhanced version incorporates a 16-bit prescaler,allowing a time-out range from 4 ms to over131 seconds, that is stable across operatingvoltage and temperature.

1.3 Details on Individual FamilyMembers

Devices in the PIC18F2585/2680/4585/4680 family areavailable in 28-pin (PIC18F2X8X) and 40/44-pin(PIC18F4X8X) packages. Block diagrams for the twogroups are shown in Figure 1-1 and Figure 1-2 .

The devices are differentiated from each other in sixways:

1. Flash program memory (48 Kbytes forPIC18FX585 devices, 64 Kbytes forPIC18FX680).

2. A/D channels (8 for PIC18F2X8X devices, 11 forPIC18F4X8X devices).

3. I/O ports (3 bidirectional ports and 1 input onlyport on PIC18F2X8X devices, 5 bidirectionalports on PIC18F4X8X devices).

4. CCP1 and Enhanced CCP1 implementation(PIC18F2X8X devices have 1 standard CCP1module, PIC18F4X8X devices have onestandard CCP1 module and one ECCP1module).

5. Parallel Slave Port (present only onPIC18F4X8X devices).

6. PIC18F4X8X devices provide two comparators.

All other features for devices in this family are identical.These are summarized in Table 1-1 .

The pinouts for all devices are listed in Table 1-2 andTable 1-3 .

Like all Microchip PIC18 devices, members of thePIC18F2585/2680/4585/4680 family are available asboth standard and low-voltage devices. Standard

devices with Enhanced Flash memory, designated withan F in the part number (such as PIC18 F2585),accommodate an operating V DD range of 4.2V to 5.5V.Low-voltage parts, designated by LF (such asPIC18 LF2585), function over an extended V DD rangeof 2.0V to 5.5V.

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TABLE 1-1: DEVICE FEATURES

Features PIC18F2585 PIC18F2680 PIC18F4585 PIC18F4680

Operating Frequency DC 40 MHz DC 40 MHz DC 40 MHz DC 40 MHz

Program Memory (Bytes) 49152 65536 49152 65536

Program Memory (Instructions) 24576 32768 24576 32768

Data Memory (Bytes) 3328 3328 3328 3328Data EEPROM Memory (Bytes) 1024 1024 1024 1024

Interrupt Sources 19 19 20 20

I/O Ports Ports A, B, C, (E) Ports A, B, C, (E) Ports A, B, C, D, E Ports A, B, C, D, E

Timers 4 4 4 4

Capture/Compare/PWM Modules 1 1 1 1

Enhanced Capture/ Compare/PWM Modules

0 0 1 1

ECAN Module 1 1 1 1

Serial Communications MSSP,Enhanced USART

MSSP,Enhanced USART

MSSP,Enhanced USART

MSSP,Enhanced USART

Parallel Communications (PSP) No No Yes Yes

10-bit Analog-to-Digital Module 8 Input Channels 8 Input Channels 11 Input Channels 11 Input Channels

Comparators 0 0 2 2

Resets (and Delays) POR, BOR,RESET Instruction,

Stack Full,Stack Underflow(PWRT, OST),

MCLR (optional),WDT

POR, BOR,RESET Instruction,


MCLR (optional),WDT



MCLR (optional),WDT



MCLR (optional),WDT

Programmable High/Low-VoltageDetect

Yes Yes Yes Yes

Programmable Brown-out Reset Yes Yes Yes Yes

Instruction Set 75 Instructions;83 with Extended

Instruction Setenabled

75 Instructions;83 with Extended






Packages 28-pin PDIP28-pin SOIC

28-pin PDIP28-pin SOIC

40-pin PDIP44-pin QFN

44-pin TQFP

40-pin PDIP44-pin QFN

44-pin TQFP

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FIGURE 1-1: PIC18F2585/2680 (28-PIN) BLOCK DIAGRAM

InstructionDecode &

Control

PORTA

PORTB

PORTC


RB0/INT0/AN10

RC0/T1OSO/T13CKIRC1/T1OSIRC2/CCP1RC3/SCK/SCLRC4/SDI/SDARC5/SDORC6/TX/CKRC7/RX/DT

RA3/AN3/V REF +

RA2/AN2/V REF -RA1/AN1RA0/AN0

RB1/INT1/AN8

Data Latch

Data Memory(3.9Kbytes)

Address Latch

Data Address12

AccessBSR4 4

PCH PCL

PCLATH

8

31 Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

8

88

ALU

Address Latch

Program Memory(48/64Kbytes)

Data Latch

20

8

8

Table Pointer

inc/dec logic

21

8

Data Bus

Table Latch8

IR

12

3

ROM Latch

RB2/INT2/CANTXRB3/CANRX

PCLATU

PCU

PORTE

MCLR/V PP /RE3 (1)

OSC2/CLKO/RA6

Note 1: RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.

2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins ar e not being used as digital I/O.Refer to Section 2.0 Oscillator Configurations for additional information.

RB4/KBI0/AN9RB5/KBI1/PGM

RB6/KBI2/PGCRB7/KBI3/PGD

EUSARTComparator MSSP 10-bit ADC

Timer2Timer1 Timer3Timer0

ECCP1

HLVD

CCP1

BOR DataEEPROM

W

Instruction Bus

STKPTR Bank

8

State MachineControl Signals

8

8Power-up

Timer

OscillatorStart-up Timer

Power-onReset

WatchdogTimer

OSC1 (2)

OSC2 (2)

VDD,

Brown-outReset

InternalOscillator

Fail-SafeClock Monitor

ReferenceBand Gap

VSS

MCLR(1)

Block

INTRCOscillator

8 MHzOscillator

Single-SupplyProgramming

In-CircuitDebugger

T1OSI

T1OSO

OSC1/CLKI/RA7

ECAN

BITOP

FSR0FSR1FSR2

inc/dec

Address

12

Decode

logic

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TABLE 1-2: PIC18F2585/2680 PINOUT I/O DESCRIPTIONS

Pin Name

PinNumber Pin

TypeBufferType DescriptionPDIP,

SOIC

MCLR/VPP /RE3MCLR

VPPRE3

1I

PI

ST

ST

Master Clear (input) or programming voltage (input).Master Clear (Reset) input. This pin is an active-lowReset to the device.Programming voltage input.Digital input.

OSC1/CLKI/RA7OSC1

CLKI

RA7

9I

I

I/O

ST

CMOS

TTL

Oscillator crystal or external clock input.Oscillator crystal input or external clock source input.ST buffer when configured in RC mode; CMOS otherwise.External clock source input. Always associated with pinfunction OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.)General purpose I/O pin.

OSC2/CLKO/RA6OSC2

CLKO

RA6

10O

O

I/O

TTL

Oscillator crystal or clock output.Oscillator crystal output. Connects to crystal or resonator inCrystal Oscillator mode.In RC mode, OSC2 pin outputs CLKO which has 1/4 thefrequency of OSC1 and denotes the instruction cycle rate.General purpose I/O pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or outputST = Schmitt Trigger input with CMOS levels I = InputO = Output P = Power

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PORTA is a bidirectional I/O port.

RA0/AN0RA0AN0

2I/O

ITTL

AnalogDigital I/O.Analog input 0.

RA1/AN1RA1AN1

3I/O

ITTL


RA2/AN2/V REF -RA2AN2VREF -

4I/O

II

TTLAnalogAnalog

Digital I/O.Analog input 2.A/D reference voltage (low) input.

RA3/AN3/V REF +RA3AN3

VREF +

5I/O

I

I

TTLAnalog

Analog

Digital I/O.Analog input 3.

A/D reference voltage (high) input.RA4/T0CKI

RA4T0CKI

6I/O

ITTLST

Digital I/O.Timer0 external clock input.

RA5/AN4/SS/HLVDINRA5AN4SSHLVDIN

7I/O

III

TTLAnalog

TTLAnalog

Digital I/O.Analog input 4.SPI slave select input.High/Low-Voltage Detect input.

RA6 See the OSC2/CLKO/RA6 pin.

RA7 See the OSC1/CLKI/RA7 pin.

TABLE 1-2: PIC18F2585/2680 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

PinNumber Pin


SOIC

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I = InputO = Output P = Power

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PORTB is a bidirectional I/O port. PORTB can be software

programmed for internal weak pull-ups on all inputs.RB0/INT0/AN10

RB0INT0AN10

21I/O

II

TTLST

Analog

Digital I/O.External interrupt 0.Analog input 10.

RB1/INT1/AN8RB1INT1AN8

22I/O

II

TTLST

Analog


RB2/INT2/CANTXRB2INT2CANTX

23I/O

IO

TTLST

TTL

Digital I/O.External interrupt 2.CAN bus TX.

RB3/CANRXRB3CANRX

24I/O

ITTLTTL

Digital I/O.CAN bus RX.

RB4/KBI0/AN9RB4KBI0AN9

25I/O

II

TTLTTL

Analog

Digital I/O.Interrupt-on-change pin.Analog input 9.

RB5/KBI1/PGMRB5KBI1PGM

26I/O

II/O

TTLTTLST

Digital I/O.Interrupt-on-change pin.Low-Voltage ICSP Programming enable pin.

RB6/KBI2/PGCRB6

KBI2PGC

27I/O

II/O

TTL

TTLST

Digital I/O.

Interrupt-on-change pin.In-Circuit Debugger and ICSP programming clock pin.

RB7/KBI3/PGDRB7KBI3PGD

28I/O

II/O

TTLTTLST

Digital I/O.Interrupt-on-change pin.In-Circuit Debugger and ICSP programming data pin.


Pin Name

PinNumber Pin


SOIC


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PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKIRC0T1OSOT13CKI

11I/OOI

STST

Digital I/O.Timer1 oscillator output.Timer1/Timer3 external clock input.

RC1/T1OSIRC1T1OSI

12I/O

IST

CMOSDigital I/O.Timer1 oscillator input.

RC2/CCP1RC2CCP1

13I/OI/O

STST

Digital I/O.Capture1 input/Compare1 output/PWM1 output.

RC3/SCK/SCLRC3SCK

SCL

14I/OI/O

I/O

STST

ST

Digital I/O.Synchronous serial clock input/output for SPI mode.

Synchronous serial clock input/output for I 2C mode.RC4/SDI/SDA

RC4SDISDA

15I/O

II/O

STSTST

Digital I/O.SPI data in.I2C data I/O.

RC5/SDORC5SDO

16I/OO

ST

Digital I/O.SPI data out.

RC6/TX/CKRC6TXCK

17I/OO

I/O

STST

Digital I/O.EUSART asynchronous transmit.EUSART synchronous clock (see related RX/DT).

RC7/RX/DTRC7RXDT

18I/O

II/O

STSTST

Digital I/O.EUSART asynchronous receive.EUSART synchronous data (see related TX/CK).

RE3 See MCLR/V PP /RE3 pin.

VSS 8, 19 P Ground reference for logic and I/O pins.

VDD 20 P Positive supply for logic and I/O pins.


Pin Name

PinNumber Pin


SOIC


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TABLE 1-3: PIC18F4585/4680 PINOUT I/O DESCRIPTIONS

Pin NamePin Number Pin

TypeBufferType DescriptionPDIP QFN TQFP

MCLR/VPP /RE3MCLR

VPPRE3

1 18 18I

PI

ST

ST

Master Clear (input) or programming voltage (input).Master Clear (Reset) input. This pin is anactive-low Reset to the device.

Programming voltage input.Digital input.

OSC1/CLKI/RA7OSC1

CLKI

RA7

13 32 30I

I

I/O

ST

CMOS

TTL

Oscillator crystal or external clock input.Oscillator crystal input or external clock source input.ST buffer when configured in RC mode;CMOS otherwise.External clock source input. Always associated withpin function OSC1. (See related OSC1/CLKI,OSC2/CLKO pins.)General purpose I/O pin.

OSC2/CLKO/RA6OSC2

CLKO

RA6

14 33 31O

O

I/O

TTL

Oscillator crystal or clock output.Oscillator crystal output. Connects to crystal orresonator in Crystal Oscillator mode.

In RC mode, OSC2 pin outputs CLKO which has 1/4the frequency of OSC1 and denotes the instructioncycle rate.General purpose I/O pin.


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PORTA is a bidirectional I/O port.

RA0/AN0/CV REFRA0AN0CVREF

2 19 19I/O

IO

TTLAnalogAnalog

Digital I/O.Analog input 0.Analog comparator reference output.

RA1/AN1RA1AN1

3 20 20I/O

ITTL


RA2/AN2/V REF -RA2AN2VREF -

4 21 21I/O

II

TTLAnalogAnalog

Digital I/O.Analog input 2.A/D reference voltage (low) input.

RA3/AN3/V REF +RA3AN3VREF +

5 22 22I/O

II

TTLAnalogAnalog

Digital I/O.Analog input 3.A/D reference voltage (high) input.

RA4/T0CKIRA4T0CKI

6 23 23I/O

ITTLST

Digital I/O.Timer0 external clock input.

RA5/AN4/SS/HLVDINRA5AN4SSHLVDIN

7 24 24I/O

III

TTLAnalog

TTLAnalog

Digital I/O.Analog input 4.SPI slave select input.High/Low-Voltage Detect input.

RA6 See the OSC2/CLKO/RA6 pin.

RA7 See the OSC1/CLKI/RA7 pin.




Legend: TTL = TTL compatible input CMOS = CMOS compatible input or outputST = Schmitt Trigger input with CMOS levels I = Input

O = Output P = Power

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PORTB is a bidirectional I/O port. PORTB can besoftware programmed for internal weak pull-ups on allinputs.

RB0/INT0/FLT0/AN10RB0INT0FLT0AN10

33 9 8I/O

III

TTLSTST

Analog

Digital I/O.External interrupt 0.Enhanced PWM Fault input (ECCP1 module).Analog input 10.

RB1/INT1/AN8RB1INT1AN8

34 10 9I/O

II

TTLST

Analog


RB2/INT2/CANTXRB2INT2CANTX

35 11 10I/O

IO

TTLST

TTL

Digital I/O.External interrupt 2.CAN bus TX.

RB3/CANRXRB3CANRX

36 12 11I/O

ITTLTTL

Digital I/O.CAN bus RX.

RB4/KBI0/AN9RB4KBI0AN9

37 14 14I/O

II

TTLTTL

Analog

Digital I/O.Interrupt-on-change pin.Analog input 9.

RB5/KBI1/PGMRB5KBI1PGM

38 15 15I/O

II/O

TTLTTLST

Digital I/O.Interrupt-on-change pin.Low-Voltage ICSP Programming enable pin.

RB6/KBI2/PGCRB6

KBI2PGC

39 16 16I/O

II/O

TTL

TTLST

Digital I/O.

Interrupt-on-change pin.In-Circuit Debugger and ICSP programmingclock pin.

RB7/KBI3/PGDRB7KBI3PGD

40 17 17I/O

II/O

TTLTTLST

Digital I/O.Interrupt-on-change pin.In-Circuit Debugger and ICSP programmingdata pin.





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PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKIRC0T1OSOT13CKI

15 34 32I/OOI

STST

Digital I/O.Timer1 oscillator output.Timer1/Timer3 external clock input.

RC1/T1OSIRC1T1OSI

16 35 35I/O

IST

CMOSDigital I/O.Timer1 oscillator input.

RC2/CCP1RC2CCP1

17 36 36I/OI/O

STST

Digital I/O.Capture1 input/Compare1 output/PWM1 output.

RC3/SCK/SCLRC3SCK

SCL

18 37 37I/OI/O

I/O

STST

ST

Digital I/O.Synchronous serial clock input/output forSPI mode.Synchronous serial clock input/output for

I2C mode.RC4/SDI/SDA

RC4SDISDA

23 42 42I/O

II/O

STSTST

Digital I/O.SPI data in.I2C data I/O.

RC5/SDORC5SDO

24 43 43I/OO

ST

Digital I/O.SPI data out.

RC6/TX/CKRC6TXCK

25 44 44I/OO

I/O

STST

Digital I/O.EUSART asynchronous transmit.EUSART synchronous clock (see related RX/DT).

RC7/RX/DTRC7RXDT

26 1 1I/O

II/O

STSTST

Digital I/O.EUSART asynchronous receive.EUSART synchronous data (see related TX/CK).





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PORTD is a bidirectional I/O port or a Parallel SlavePort (PSP) for interfacing to a microprocessor port.These pins have TTL input buffers when PSP module

is enabled.RD0/PSP0/C1IN+

RD0PSP0C1IN+

19 38 38I/OI/O

I

STTTL

Analog

Digital I/O.Parallel Slave Port data.Comparator 1 input (+).

RD1/PSP1/C1IN-RD1PSP1C1IN-

20 39 39I/OI/O

I

STTTL

Analog

Digital I/O.Parallel Slave Port data.Comparator 1 input (-)

RD2/PSP2/C2IN+RD2PSP2C2IN+

21 40 40I/OI/O

I

STTTL

Analog

Digital I/O.Parallel Slave Port data.Comparator 2 input (+).

RD3/PSP3/C2IN-RD3PSP3C2IN-

22 41 41I/OI/O

I

STTTL

Analog

Digital I/O.Parallel Slave Port data.Comparator 2 input (-).

RD4/PSP4/ECCP1/ P1A

RD4PSP4ECCP1P1A

27 2 2

I/OI/OI/OO

STTTLST

TTL

Digital I/O.Parallel Slave Port data.Capture2 input/Compare2 output/PWM2 output.ECCP1 PWM output A.

RD5/PSP5/P1BRD5PSP5

P1B

28 3 3I/OI/O

O

STTTL

TTL

Digital I/O.Parallel Slave Port data.

ECCP1 PWM output B.RD6/PSP6/P1C

RD6PSP6P1C

29 4 4I/OI/OO

STTTLTTL

Digital I/O.Parallel Slave Port data.ECCP1 PWM output C.

RD7/PSP7/P1DRD7PSP7P1D

30 5 5I/OI/OO

STTTLTTL

Digital I/O.Parallel Slave Port data.ECCP1 PWM output D.





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2.0 OSCILLATORCONFIGURATIONS

2.1 Oscillator Types

PIC18F2585/2680/4585/4680 devices can be operatedin ten different oscillator modes. The user can programthe Configuration bits, FOSC3:FOSC0, in ConfigurationRegister 1H to select one of these ten modes:

1. LP Low-Power Crystal2. XT Crystal/Resonator3. HS High-Speed Crystal/Resonator4. HSPLL High-Speed Crystal/Resonator

with PLL enabled5. RC External Resistor/Capacitor with

FOSC /4 output on RA66. RCIO External Resistor/Capacitor with I/O

on RA67. INTIO1 Internal Oscillator with F OSC /4 output

on RA6 and I/O on RA78. INTIO2 Internal Oscillator with I/O on RA6

and RA79. EC External Clock with F OSC /4 output10. ECIO External Clock with I/O on RA6

2.2 Crystal Oscillator/CeramicResonators

In XT, LP, HS or HSPLL Oscillator modes, a crystal orceramic resonator is connected to the OSC1 andOSC2 pins to establish oscillation. Figure 2-1 showsthe pin connections.

The oscillator design requires the use of a parallel cutcrystal.

FIGURE 2-1: CRYSTAL/CERAMICRESONATOR OPERATION(XT, LP, HS OR HSPLLCONFIGURATION)

TABLE 2-1: CAPACITOR SELECTION FORCERAMIC RESONATORS

Note: Use of a series cut crystal may give afrequency out of the crystal manufacturersspecifications.

Typical Capacitor Values Used:

Mode Freq OSC1 OSC2

XT 455 kHz2.0 MHz4.0 MHz

56 pF47 pF33 pF

56 pF47 pF33 pF

HS 8.0 MHz16.0 MHz

27 pF22 pF

27 pF22 pF

Capacitor values are for design guidance only.

These capacitors were tested with the resonatorslisted below for basic start-up and operation. Thesevalues are not optimized .Different capacitor values may be required to produceacceptable oscillator operation. The user should testthe performance of the oscillator over the expectedVDD and temperature range for the application.

See the notes on page 24 for additional information.

Resonators Used:

455 kHz 4.0 MHz

2.0 MHz 8.0 MHz

16.0 MHz

Note: When using resonators with frequenciesabove 3.5 MHz, the use of HS mode,rather than XT mode, is recommended.HS mode may be used at any V DD forwhich the controller is rated. If HS isselected, it is possible that the gain of theoscillator will overdrive the resonator.Therefore, a series resistor should beplaced between the OSC2 pin and theresonator. As a good starting point, therecommended value of R S is 330 .

Note 1: See Table 2-1 and Table 2-2 for initial values ofC1 and C2.

2: A series resistor (R S ) may be required for ATstrip cut crystals.

3: RF varies with the oscillator mode chosen.

C1 (1)

C2 (1)

XTAL

OSC2

OSC1

RF(3)

Sleep

To

Logic

PIC18FXXXXRS (2)

Internal

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TABLE 2-2: CAPACITOR SELECTION FORCRYSTAL OSCILLATOR

An external clock source may also be connected to theOSC1 pin in the HS mode, as shown in Figure 2-2 .

FIGURE 2-2: EXTERNAL CLOCKINPUT OPERATION(HS OSCILLATORCONFIGURATION)

2.3 External Clock Input

The EC and ECIO Oscillator modes require an externalclock source to be connected to the OSC1 pin. There isno oscillator start-up time required after a Power-onReset or after an exit from Sleep mode.

In the EC Oscillator mode, the oscillator frequencydivided by 4 is available on the OSC2 pin. This signalmay be used for test purposes or to synchronize otherlogic. Figure 2-3 shows the pin connections for the ECOscillator mode.

FIGURE 2-3: EXTERNAL CLOCKINPUT OPERATION(EC CONFIGURATION)

The ECIO Oscillator mode functions like the EC mode,except that the OSC2 pin becomes an additionalgeneral purpose I/O pin. The I/O pin becomes bit 6 ofPORTA (RA6). Figure 2-4 shows the pin connectionsfor the ECIO Oscillator mode.

FIGURE 2-4: EXTERNAL CLOCKINPUT OPERATION(ECIO CONFIGURATION)

Osc Type CrystalFreq

Typical Capacitor ValuesTested:

C1 C2

LP 32 kHz 33 pF 33 pF200 kHz 15 pF 15 pF

XT 1 MHz 33 pF 33 pF

4 MHz 27 pF 27 pF

HS 4 MHz 27 pF 27 pF

8 MHz 22 pF 22 pF

20 MHz 15 pF 15 pF

Capacitor values are for design guidance only.

These capacitors were tested with the crystals listedbelow for basic start-up and operation. These valuesare not optimized.

Different capacitor values may be required to produceacceptable oscillator operation. The user should testthe performance of the oscillator over the expectedVDD and temperature range for the application.

See the notes following this table for additionalinformation.

Crystals Used:

32 kHz 4 MHz

200 kHz 8 MHz

1 MHz 20 MHz

Note 1: Higher capacitance increases the stabilityof the oscillator but also increases thestart-up time.

2: When operating below 3V V DD, or whenusing certain ceramic resonators at anyvoltage, it may be necessary to use theHS mode or switch to a crystal oscillator.

3: Since each resonator/crystal has its owncharacteristics, the user should consultthe resonator/crystal manufacturer forappropriate values of externalcomponents.

4: Rs may be required to avoid overdriving

crystals with low drive level specification.5: Always verify oscillator performance over

the V DD and temperature range that isexpected for the application.

OSC1

OSC2Open

Clock fromExt. System PIC18FXXXX

(HS Mode)

OSC1/CLKI

OSC2/CLKOFOSC /4


OSC1/CLKI

I/O (OSC2)RA6


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2.6 Internal Oscillator Block

The PIC18F2585/2680/4585/4680 devices include aninternal oscillator block which generates two differentclock signals; either can be used as the microcontroller sclock source. This may eliminate the need for externaloscillator circuits on the OSC1 and/or OSC2 pins.

The main output (INTOSC) is an 8 MHz clock source,which can be used to directly drive the device clock. Italso drives a postscaler, which can provide a range ofclock frequencies from 31 kHz to 4 MHz. The INTOSCoutput is enabled when a clock frequency from 125 kHzto 8 MHz is selected.

The other clock source is the internal RC oscillator(INTRC), which provides a nominal 31 kHz output.INTRC is enabled if it is selected as the device clocksource; it is also enabled automatically when any of thefollowing are enabled:

Power-up Timer Fail-Safe Clock Monitor

Watchdog Timer Two-Speed Start-up

These features are discussed in greater detail inSection 24.0 Special Features of the CPU .

The clock source frequency (INTOSC direct, INTRCdirect or INTOSC postscaler) is selected by configuringthe IRCF bits of the OSCCON register ( Register 2-2 ).

2.6.1 INTIO MODESUsing the internal oscillator as the clock sourceeliminates the need for up to two external oscillatorpins, which can then be used for digital I/O. Two distinctconfigurations are available:

In INTIO1 mode, the OSC2 pin outputs F OSC /4,while OSC1 functions as RA7 for digital input andoutput.

In INTIO2 mode, OSC1 functions as RA7 andOSC2 functions as RA6, both for digital input andoutput.

2.6.2 INTOSC OUTPUT FREQUENCYThe internal oscillator block is calibrated at the factoryto produce an INTOSC output frequency of 8.0 MHz.

The INTRC oscillator operates independently of theINTOSC source. Any changes in INTOSC across

voltage and temperature are not necessarily reflectedby changes in INTRC and vice versa.

2.6.3 OSCTUNE REGISTERThe internal oscillators output has been calibrated atthe factory but can be adjusted in the users applica-tion. This is done by writing to the OSCTUNE register(Register 2-1 ). The tuning sensitivity is constantthroughout the tuning range.

When the OSCTUNE register is modified, the INTOSCand INTRC frequencies will begin shifting to the newfrequency. The INTRC clock will reach the newfrequency within 8 clock cycles (approximately8 * 3 2 s = 256 s). The INTOSC clock will stabilizewithin 1 ms. Code execution continues during this shift.There is no indication that the shift has occurred.

The OSCTUNE register also implements the INTSRCand PLLEN bits, which control certain features of theinternal oscillator block. The INTSRC bit allows usersto select which internal oscillator provides the clocksource when the 31 kHz frequency option is selected.This is covered in greater detail in Section 2.7.1Oscillator Control Register .

The PLLEN bit controls the operation of the frequencymultiplier, PLL, in internal oscillator modes.

2.6.4 PLL IN INTOSC MODESThe 4x frequency multiplier can be used with the inter-nal oscillator block to produce faster device clock

speeds than are normally possible with an internaloscillator. When enabled, the PLL produces a clockspeed of up to 32 MHz.

Unlike HSPLL mode, the PLL is controlled through soft-ware. The control bit, PLLEN (OSCTUNE), is usedto enable or disable its operation.

The PLL is available when the device is configured touse the internal oscillator block as its primary clocksource (FOSC3:FOSC0 = 1001 or 1000 ). Additionally,the PLL will only function when the selected output fre-quency is either 4 MHz or 8 MHz (OSCCON = 111or 110 ). If both of these conditions are not met, the PLLis disabled.

The PLLEN control bit is only functional in those internaloscillator modes where the PLL is available. In all othermodes, it is forced to 0 and is effectively unavailable.

2.6.5 INTOSC FREQUENCY DRIFTThe factory calibrates the internal oscillator blockoutput (INTOSC) for 8 MHz. However, this frequencymay drift as V DD or temperature changes, which canaffect the controller operation in a variety of ways. It ispossible to adjust the INTOSC frequency by modifyingthe value in the OSCTUNE register. This has no effecton the INTRC clock source frequency.

Tuning the INTOSC source requires knowing when to

make the adjustment, in which direction it should bemade and in some cases, how large a change isneeded. Three compensation techniques arediscussed in Section 2.6.5.1 Compensating withthe EUSART , Section 2.6.5.2 Compensating withthe Timers and Section 2.6.5.3 Compensatingwith the CCP1 Module in Capture Mode , but othertechniques may be used.

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REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER

2.6.5.1 Compensating with the EUSARTAn adjustment may be required when the EUSARTbegins to generate framing errors or receives data witherrors while in Asynchronous mode. Framing errorsindicate that the device clock frequency is too high. Toadjust for this, decrement the value in OSCTUNE toreduce the clock frequency. On the other hand, errorsin data may suggest that the clock speed is too low. Tocompensate, increment OSCTUNE to increase theclock frequency.

2.6.5.2 Compensating with the TimersThis technique compares device clock speed to somereference clock. Two timers may be used; one timer isclocked by the peripheral clock, while the other isclocked by a fixed reference source, such as theTimer1 oscillator.

Both timers are cleared, but the timer clocked by thereference generates interrupts. When an interruptoccurs, the internally clocked timer is read and bothtimers are cleared. If the internally clocked timer valueis greater than expected, then the internal oscillatorblock is running too fast. To adjust for this, decrementthe OSCTUNE register.

2.6.5.3 Compensating with the CCP1Module in Capture ModeThe CCP1 module can use free running Timer1 (orTimer3), clocked by the internal oscillator block and anexternal event with a known period (i.e., AC powerfrequency). The time of the first event is captured in theCCPRxH:CCPRxL registers and is recorded for uselater. When the second event causes a capture, thetime of the first event is subtracted from the time of thesecond event. Since the period of the external event isknown, the time difference between events can becalculated.

If the measured time is much greater than the

calculated time, the internal oscillator block is runningtoo fast. To compensate, decrement the OSCTUNEregister. If the measured time is much less than thecalculated time, the internal oscillator block is runningtoo slow. To compensate, increment the OSCTUNEregister.

R/W-0 R/W-0 (1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

INTSRC PLLEN (1) TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)0 = 31 kHz device clock derived directly from INTRC internal oscillator

bit 6 PLLEN: Frequency Multiplier PLL for INTOSC Enable bit (1)

1 = PLL enabled for INTOSC (4 MHz and 8 MHz only)0 = PLL disabled

Note 1: Available only in certain oscillator configurations; otherwise, this bit is unavailableand reads as 0. See text for details.

bit 5 Unimplemented: Read as 0bit 4-0 TUN4:TUN0: Frequency Tuning bits

01111 = Maximum frequency 00001 00000 = Center frequency. Oscillator module is running at the calibrated frequency.11111 10000 = Minimum frequency

Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as 0-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown

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REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTERR/W-0 R/W-1 R/W-0 R/W-0 R (1) R-0 R/W-0 R/W-0

IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0

bit 7 bit 0

bit 7 IDLEN: Idle Enable bit1 = Device enters Idle mode on SLEEP instruction0 = Device enters Sleep mode on SLEEP instruction

bit 6-4 IRCF2:IRCF0: Internal Oscillator Frequency Select bits111 = 8 MHz (INTOSC drives clock directly)110 = 4 MHz101 = 2 MHz100 = 1 MHz (3) 011 = 500 kHz010 = 250 kHz001 = 125 kHz000 = 31 kHz (from either INTOSC/256 or INTRC directly) (2)

bit 3 OSTS: Oscillator Start-up Time-out Status bit (1)

1 = Oscillator start-up time-out timer has expired; primary oscillator is running0 = Oscillator start-up time-out timer is running; primary oscillator is not readybit 2 IOFS: INTOSC Frequency Stable bit

1 = INTOSC frequency is stable and the frequency is provided by one of the RC modes0 = INTOSC frequency is not stable

bit 1-0 SCS1:SCS0: System Clock Select bits1x = Internal oscillator block01 = Timer1 oscillator00 = Primary oscillator

Note 1: Depends on state of the IESO Configuration bit.

2: Source selected by the INTSRC bit (OSCTUNE), see text.

3: Default output frequency of INTOSC on Reset.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as 0

-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown

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3.0 POWER MANAGED MODESPIC18F2585/2680/4585/4680 devices offer a total ofseven operating modes for more efficient powermanagement. These modes provide a variety ofoptions for selective power conservation in applicationswhere resources may be limited (i.e., battery-powered

devices).There are three categories of power managed modes:

Run modes Idle modes Sleep mode

These categories define which portions of the deviceare clocked and sometimes, what speed. The Run andIdle modes may use any of the three available clocksources (primary, secondary or internal oscillatorblock); the Sleep mode does not use a clock source.

The power managed modes include several powersaving features offered on previous PIC devices. One

is the clock switching feature, offered in other PIC18devices, allowing the controller to use the Timer1oscillator in place of the primary oscillator. Alsoincluded is the Sleep mode, offered by all PIC devices,where all device clocks are stopped.

3.1 Selecting Power Managed Modes

Selecting a power managed mode requires twodecisions: if the CPU is to be clocked or not and theselection of a clock source. The IDLEN bit(OSCCON) controls CPU clocking, while theSCS1:SCS0 bits (OSCCON) select the clocksource. The individual modes, bit settings, clock sources

and affected modules are summarized in Table 3-1 .

3.1.1 CLOCK SOURCESThe SCS1:SCS0 bits allow the selection of one of threeclock sources for power managed modes. They are:

the primary clock, as defined by theFOSC3:FOSC0 Configuration bits

the secondary clock (the Timer1 oscillator)

the internal oscillator block (for RC modes)

3.1.2 ENTERING POWER MANAGEDMODES

Switching from one power managed mode to anotherbegins by loading the OSCCON register. TheSCS1:SCS0 bits select the clock source and determinewhich Run or Idle mode is to be used. Changing thesebits causes an immediate switch to the new clocksource, assuming that it is running. The switch mayalso be subject to clock transition delays. These arediscussed in Section 3.1.3 Clock Transitions AndStatus Indicators and subsequent sections.

Entry to the Power Managed Idle or Sleep modes istriggered by the execution of a SLEEP instruction. Theactual mode that results depends on the status of theIDLEN bit.

Depending on the current mode and the mode beingswitched to, a change to a power managed mode doesnot always require setting all of these bits. Manytransitions may be done by changing the oscillatorselect bits, or changing the IDLEN bit, prior to issuing aSLEEP instruction. If the IDLEN bit is alreadyconfigured correctly, it may only be necessary toperform a SLEEP instruction to switch to the desiredmode.

TABLE 3-1: POWER MANAGED MODES

ModeOSCCON Bits Module Clocking

Available Clock and Oscillator SourceIDLEN (1) SCS1:SCS0 CPU Peripherals

Sleep 0 N/A Off Off None All clocks are disabledPRI_RUN N/A 00 Clocked Clocked Primary LP, XT, HS, HSPLL, RC, EC, INTRC (2):

This is the normal full power execution mode.

SEC_RUN N/A 01 Clocked Clocked Secondary Timer1 OscillatorRC_RUN N/A 1x Clocked Clocked Internal Oscillator Block (2)

PRI_IDLE 1 00 Off Clocked Primary LP, XT, HS, HSPLL, RC, ECSEC_IDLE 1 01 Off Clocked Secondary Timer1 OscillatorRC_IDLE 1 1x Off Clocked Internal Oscillator Block (2)

Note 1: IDLEN reflects its value when the SLEEP instruction is executed.2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source.

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FIGURE 3-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE

FIGURE 3-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)

3.2.3 RC_RUN MODEIn RC_RUN mode, the CPU and peripherals areclocked from the internal oscillator block using theINTOSC multiplexer; the primary clock is shut down.When using the INTRC source, this mode provides thebest power conservation of all the Run modes, whilestill executing code. It works well for user applicationswhich are not highly timing sensitive or do not requirehigh-speed clocks at all times.

If the primary clock source is the internal oscillatorblock (either INTRC or INTOSC), there are no distin-

guishable differences between PRI_RUN andRC_RUN modes during execution. However, a clockswitch delay will occur during entry to and exit fromRC_RUN mode. Therefore, if the primary clock sourceis the internal oscillator block, the use of RC_RUNmode is not recommended.

This mode is entered by setting SCS1 to 1. Althoughit is ignored, it is recommended that SCS0 also becleared; this is to maintain software compatibility withfuture devices. When the clock source is switched tothe INTOSC multiplexer (see Figure 3-3 ), the primaryoscillator is shut down and the OSTS bit is cleared. TheIRCF bits may be modified at any time to immediatelychange the clock speed.

Q4Q3Q2

OSC1

Peripheral

Program

Q1

T1OSI

Q1

Counter

Clock

CPUClock

PC + 2PC

1 2 3 n-1 n

Clock Transition

Q4Q3Q2 Q1 Q3Q2

PC + 4

Q1 Q3 Q4

OSC1

Peripheral

Program PC

T1OSI

PLL Clock

Q1

PC + 4

Q2

Output

Q3 Q4 Q1

CPU Clock

PC + 2

Clock

Counter

Q2 Q2 Q3

Note 1: TOST = 1024 T OSC ; TPLL = 2 ms (approx). These intervals are not shown to scale.

SCS1:SCS0 bits changed

TOST (1) TPLL(1)1 2 n-1 n

Clock

OSTS bit set

Transition

Note: Caution should be used when modifying asingle IRCF bit. If V DD is less than 3V, it ispossible to select a higher clock speedthan is supported by the low V DD.Improper device operation may result ifthe V DD /F OSC specifications are violated.

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3.4.1 PRI_IDLE MODEThis mode is unique among the three Low-Power Idlemodes, in that it does not disable the primary deviceclock. For timing sensitive applications, this allows forthe fastest resumption of device operation with its moreaccurate primary clock source, since the clock sourcedoes not have to warm up or transition from anotheroscillator.

PRI_IDLE mode is entered from PRI_RUN mode bysetting the IDLEN bit and executing a SLEEP instruc-tion. If the device is in another Run mode, set IDLENfirst, then clear the SCS bits and execute SLEEP.Although the CPU is disabled, the peripherals continueto be clocked from the primary clock source specifiedby the FOSC3:FOSC0 Configuration bits. The OSTSbit remains set (see Figure 3-7 ).

When a wake event occurs, the CPU is clocked from theprimary clock source. A delay of interval T CSD isrequired between the wake event and when codeexecution starts. This is required to allow the CPU tobecome ready to execute instructions. After thewake-up, the OSTS bit remains set. The IDLEN andSCS bits are not affected by the wake-up (seeFigure 3-8 ).

3.4.2 SEC_IDLE MODEIn SEC_IDLE mode, the CPU is disabled but theperipherals continue to be clocked from the Timer1oscillator. This mode is entered from SEC_RUN by set-ting the IDLEN bit and executing a SLEEP instruction. Ifthe device is in another Run mode, set the IDLEN bitfirst, then set the SCS1:SCS0 bits to 01 and executeSLEEP. When the clock source is switched to theTimer1 oscillator, the primary oscillator is shut down,the OSTS bit is cleared and the T1RUN bit is set.

When a wake event occurs, the peripherals continue tobe clocked from the Timer1 oscillator. After an interval ofTCSD following the wake event, the CPU beginsexecuting code being clocked by the Timer1 oscillator.The IDLEN and SCS bits are not affected by thewake-up; the Timer1 oscillator continues to run (seeFigure 3-8 ).

FIGURE 3-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE

FIGURE 3-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE

Note: The Timer1 oscillator should already berunning prior to entering SEC_IDLE mode.If the T1OSCEN bit is not set when theSLEEP instruction is executed, the SLEEPinstruction will be ignored and entry toSEC_IDLE mode will not occur. If theTimer1 oscillator is enabled but not yet run-ning, peripheral clocks will be delayed untilthe oscillator has started. In such situations,initial oscillator operation is far from stableand unpredictable operation may result.

Q1

Peripheral

Program PC PC + 2

OSC1

Q3 Q4 Q1

CPU Clock

Clock

Counter

Q2

OSC1

Peripheral

Program PC

CPU Clock

Q1 Q3 Q4

Clock

Counter

Q2

Wake Event

TCSD

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3.4.3 RC_IDLE MODEIn RC_IDLE mode, the CPU is disabled but the periph-erals continue to be clocked from the internal oscillatorblock using the INTOSC multiplexer. This mode allowsfor controllable power conservation during Idle periods.

From RC_RUN, this mode is entered by setting the

IDLEN bit and executing a SLEEP instruction. If thedevice is in another Run mode, first set IDLEN, then setthe SCS1 bit and execute SLEEP. Although its value isignored, it is recommended that SCS0 also be cleared;this is to maintain software compatibility with futuredevices. The INTOSC multiplexer may be used toselect a higher clock frequency, by modifying the IRCFbits, before executing the SLEEP instruction. When theclock source is switched to the INTOSC multiplexer, theprimary oscillator is shut down and the OSTS bit iscleared.

If the IRCF bits are set to any non-zero value or theINTSRC bit is set, the INTOSC output is enabled. TheIOFS bit becomes set, after the INTOSC outputbecomes stable, after an interval of T IOBST(parameter 39 , Table 27-10 ). Clocks to the peripheralscontinue while the INTOSC source stabilizes. If theIRCF bits were previously at a non-zero value, orINTSRC was set before the SLEEP instruction wasexecuted and the INTOSC source was already stable,the IOFS bit will remain set. If the IRCF bits andINTSRC are all clear, the INTOSC output will not beenabled, the IOFS bit will remain clear and there will beno indication of the current clock source.

When a wake event occurs, the peripherals continue tobe clocked from the INTOSC multiplexer. After a delayof TCSD following the wake event, the CPU begins

executing code being clocked by the INTOSC multi-plexer. The IDLEN and SCS bits are not affected by thewake-up. The INTRC source will continue to run ifeither the WDT or the Fail-Safe Clock Monitor isenabled.

3.5 Exiting Idle and Sleep Modes

An exit from Sleep mode or any of the Idle modes istriggered by an interrupt, a Reset or a WDT time-out.This section discusses the triggers that cause exitsfrom power managed modes. The clocking subsystemactions are discussed in each of the power managedmodes (see Section 3.2 Run Modes , Section 3.3

Sleep Mode and Section 3.4 Idle Modes ).3.5.1 EXIT BY INTERRUPTAny of the available interrupt sources can cause thedevice to exit from an Idle mode or the Sleep mode toa Run mode. To enable this functionality, an interruptsource must be enabled by setting its enable bit in oneof the INTCON or PIE registers. The exit sequence isinitiated when the corresponding interrupt flag bit is set.

On all exits from Idle or Sleep modes by interrupt, codeexecution branches to the interrupt vector if theGIE/GIEH bit (INTCON) is set. Otherwise, codeexecution continues or resumes without branching(see Section 9.0 Interrupts ).

A fixed delay of interval T CSD following the wake eventis required when leaving Sleep and Idle modes. Thisdelay is required for the CPU to prepare for execution.Instruction execution resumes on the first clock cyclefollowing this delay.

3.5.2 EXIT BY WDT TIME-OUTA WDT time-out will cause different actions dependingon which power managed mode the device is in whenthe time-out occurs.

If the device is not executing code (all Idle modes andSleep mode), the time-out will result in an exit from thepower managed mode (see Section 3.2 Run Modesand Section 3.3 Sleep Mode ). If the device isexecuting code (all Run modes), the time-out will result

in a WDT Reset (see Section 24.2 Watchdog Timer(WDT) ).

The WDT timer and postscaler are cleared by execut-ing a SLEEP or CLRWDTinstruction, the loss of acurrently selected clock source (if the Fail-Safe ClockMonitor is enabled) and modifying the IRCF bits in theOSCCON register if the internal oscillator block is thedevice clock source.

3.5.3 EXIT BY RESETNormally, the device is held in Reset by the OscillatorStart-up Timer (OST) until the primary clock becomesready. At that time, the OSTS bit is set and the device

begins executing code. If the internal oscillator block isthe new clock source, the IOFS bit is set instead.

The exit delay time from Reset to the start of codeexecution depends on both the clock sources beforeand after the wake-up and the type of oscillator if thenew clock source is the primary clock. Exit delays aresummarized in Table 3-2 .

Code execution can begin before the primary clockbecomes ready. If either the Two-Speed Start-up (seeSection 24.3 Two-Speed Start-up ) or Fail-SafeClock Monitor (see Section 24.4 Fail-Safe Clock Monitor ) is enabled, the device may begin executionas soon as the Reset source has cleared. Execution is

clocked by the INTOSC multiplexer driven by theinternal oscillator block. Execution is clocked by theinternal oscillator block until either the primary clockbecomes ready or a power managed mode is enteredbefore the primary clock becomes ready; the primaryclock is then shut down.

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3.5.4 EXIT WITHOUT AN OSCILLATORSTART-UP DELAY

Certain exits from power managed modes do notinvoke the OST at all. There are two cases:

PRI_IDLE mode where the primary clock sourceis not stopped; and

the primary clock source is not any of the LP, XT,HS or HSPLL modes.

In these instances, the primary clock source eitherdoes not require an oscillator start-up delay, since it isalready running (PRI_IDLE), or normally does notrequire an oscillator start-up delay (RC, EC and INTIOOscillator modes). However, a fixed delay of intervalTCSD following the wake event is still required whenleaving Sleep and Idle modes to allow the CPU to pre-

pare for execution. Instruction execution resumes onthe first clock cycle following this delay.

TABLE 3-2: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE(BY CLOCK SOURCES)

Clock SourceBefore Wake-up

Clock SourceAfter Wake-up Exit Delay

Clock Ready StatusBit (OSCCON)

Primary Device Clock(PRI_IDLE mode)

LP, XT, HS

TCSD (2)OSTSHSPLL

EC, RC

INTRC (1)

INTOSC (3) IOFS

T1OSC or INTRC (1)

LP, XT, HS T OST (4)

OSTSHSPLL T OST + t rc(4)

EC, RCTCSD (2)

INTRC (1) INTOSC (2) TIOBST (5) IOFS

INTOSC (3)



EC, RCTCSD (2)

INTRC (1)

INTOSC(2)

None IOFS

None(Sleep mode)



EC, RCTCSD (2)

INTRC (1)

INTOSC (2) TIOBST (5) IOFS

Note 1: In this instance, refers specifically to the 31 kHz INTRC clock source.2: TCSD (parameter 38 ) is a required delay when waking from Sleep and all Idle modes and runs concurrently

with any other required delays (see Section 3.4 Idle Modes ).3: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.4: TOST is the Oscillator Start-up Timer (parameter 32 ). t rc is the PLL Lock-out Timer (parameter F12 ); it is

also designated as T PLL.5: Execution continues during T IOBST (parameter 39 ), the INTOSC stabilization period.

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REGISTER 4-1: RCON: RESET CONTROL REGISTERR/W-0 R/W-1 (1) U-0 R/W-1 R-1 R-1 R/W-0 (2) R/W-0

IPEN SBOREN RI TO PD POR BOR

bit 7 bit 0

bit 7 IPEN: Interrupt Priority Enable bit1 = Enable priority levels on interrupts0 = Disable priority levels on interrupts (16CXXX Compatibility mode)

bit 6 SBOREN: BOR Software Enable bit (1)

If BOREN1:BOREN0 = 01 :1 = BOR is enabled0 = BOR is disabledIf BOREN1:BOREN0 = 00 , 10 or 11 :Bit is disabled and read as 0.

bit 5 Unimplemented: Read as 0bit 4 RI: RESET Instruction Flag bit

1 = The RESET instruction was not executed (set by firmware only)0 = The RESET instruction was executed causing a device Reset (must be set in software after

a Brown-out Reset occurs)bit 3 TO: Watchdog Time-out Flag bit

1 = Set by power-up, CLRWDTinstruction or SLEEP instruction0 = A WDT time-out occurred

bit 2 PD: Power-down Detection Flag bit1 = Set by power-up or by the CLRWDTinstruction0 = Set by execution of the SLEEP instruction

bit 1 POR: Power-on Reset Status bit (2)

1 = A Power-on Reset has not occurred (set by firmware only)0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR: Brown-out Reset Status bit1 = A Brown-out Reset has not occurred (set by firmware only)0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Note 1: If SBOREN is enabled, its Reset state is 1; otherwise, it is 0.

2: The actual Reset value of POR is determined by the type of device Reset. See thenotes following this register and Section 4.6 Reset State of Registers foradditional information.

Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as 0

-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown

Note 1: It is recommended that the POR bit be set after a Power-on Reset has beendetected so that subsequent Power-on Resets may be detected.

2: Brown-out Reset is said to have occurred when BOR is 0 and POR is 1 (assumingthat POR was set to 1 by software immediately after POR).

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FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO V DD , VDD RISE > T PWRT )

FIGURE 4-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO V DD)

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

0V 1V

5V

TPWRT

TOST

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

PLL TIME-OUT

TPLL

Note: TOST = 1024 clock cycles.TPLL 2 ms max. First three stages of the PWRT timer.

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CCPR1H 2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuuCCPR1L 2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuuCCP1CON 2585 2680 4585 4680 --00 0000 --00 0000 --uu uuuuECCPR1H 2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuuECCPR1L 2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuuECCP1CON 2585 2680 4585 4680 0000 0000 0000 0000 uuuu uuuuBAUDCON 2585 2680 4585 4680 01-0 0-00 01-0 0-00 --uu uuuuECCP1DEL 2585 2680 4585 4680 0000 0000 0000 0000 uuuu uuuuECCP1AS 2585 2680 4585 4680 0000 0000 0000 0000 uuuu uuuuCVRCON 2585 2680 4585 4680 0000 0000 0000 0000 uuuu uuuuCMCON 2585 2680 4585 4680 0000 0111 0000 0111 uuuu uuuuTMR3H 2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuuTMR3L 2585 2680 4585 4680 xxxx xxxx uuuu uuuu uuuu uuuuT3CON 2585 2680 4585 4680 0000 0000 uuuu uuuu uuuu uuuuSPBRGH 2585 2680 4585 4680 0000 0000 0000 0000 uuuu uuuuSPBRG 2585 2680 4585 4680 0000 0000 0000 0000 uuuu uuuuRCREG 2585 2680 4585 4680 0000 0000 0000 0000 uuuu uuuuTXREG 2585 2680 4585 4680 0000 0000 0000 0000 uuuu uuuuTXSTA 2585 2680 4585 4680 0000 0010 0000 0010 uuuu uuuuRCSTA 2585 2680 4585 4680 0000 000x 0000 000x uuuu uuuuEEADRH 2585 2680 4585 4680 ---- --00 ---- --00 ---- --uuEEADR 2585 2680 4585 4680 0000 0000 0000 0000 uuuu uuuuEEDATA 2585 2680 4585 4680 0000 0000 0000 0000 uuuu uuuuEECON2 2585 2680 4585 4680 0000 0000 0000 0000 0000 0000EECON1 2585 2680 4585 4680 xx-0 x000 uu-0 u000 uu-0 u000IPR3 2585 2680 4585 4680 1111 1111 1111 1111 uuuu uuuuPIR3 2585 2680 4585 4680 0000 0000 0000 0000 uuuu uuuuPIE3 2585 2680 4585 4680 0000 0000 0000 0000 uuuu uuuuIPR2 2585 2680 4585 4680 11-1 1111 11-1 1111 uu-u uuuu

2585 2680 4585 4680 1--1 111- 1--1 111- u--u uuu-PIR2 2585 2680 4585 4680 00-0 0000 00-0 0000 uu-u uuuu (1)

2585 2680 4585 4680 0--0 000- 0--0 000- u--u uuu- (1)

TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Register Applicable Devices Power-on Reset,Brown-out Reset

MCLR Resets,WDT Reset,

RESET Instruction,Stack Resets

Wake-up via WDTor Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as 0, q = value depends on condition.Shaded cells indicate condi

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PIC18F2585/2680/4585/4680 Data Sheet