PIC_part5_Timer0-2

7/27/2019 PIC_part5_Timer0-2

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Introduction

The Timer0 module has the following features:

8-bit timer/counter

Readable and writable

8-bit software programmable prescaler

Clock source selectable to be external or internal

Interrupt on overflow from FFh to 00h

Edge select for external clock


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OPTION_REG

The OPTION_REG register is a readable and

writable register.

Contains various control bits to configure the

TMR0/WDT prescaler, the External INT Interrupt,

TMR0, and the weak pull-ups on PORTB.


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Simplified block diagram of the Timer0 module


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TIMER MODE

Timer mode is selected by clearing the T0CS bit

(OPTION).

In timer mode, the Timer0 module will increment

every instruction cycle (without prescaler). Writing to the TMR0 register used as a timer, will not

cause the pulse counting to start immediately, but

with two instruction cycles delay.

Accordingly, it is necessary to adjust the value

written to the TMR0 register.


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COUNTER MODE

Counter mode is selected by setting the T0CS bit

(OPTION).

In counter mode, Timer0 will increment either on

every rising or falling edge of the T0CKI pin.

The incrementing edge is determined by the

Timer0 Source Edge Select the T0SE bit

(OPTION). Clearing the T0SE bit selects the rising edge.


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PRESCALER

An 8-bit counter Mutually exclusively shared between the Timer0 module and

the Watchdog Timer.

A prescaler for the Timer0 module, or as a postscaler for theWatchdog Timer.

i.e prescaler assignment for the Timer0 module means thatthere is no postscaler for the Watchdog Timer, and vice-versa.

The prescaler assignment is controlled in software by the PSAcontrol bit (OPTION).

Clearing the PSA bit will assign the prescaler to the Timer0module.

The prescaler is not readable or writable.


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PRESCALER contd..

The PSA and PS2:PS0 bits (OPTION_REG)

determine the prescaler assignment and prescale

ratio.

When prescaler is assigned to the

Timer0 module, all instructions writing to the TMR0

register (e.g., CLRF TMR0, MOVWF TMR0, BSF

TMR0,x....etc.) will clear the prescaler.

When assigned to WDT, a CLRWDT instruction will

clear the prescaler along with the Watchdog Timer..


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TMR0 Interrupt

INTCON

Register

The INTCON

Register is areadable and

writable register

which contains

various enable and

flag bits.


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TMR0 Interrupt

The TMR0 interrupt is generated when the TMR0

register overflows from FFh to 00h.

This overflow sets bit Timer 0 Overflow Interrupt

flag bit, T0IF (INTCON).

The interrupt can be masked by clearing bit T0IE

(INTCON).

Bit T0IF must be cleared in software by theTimer0 module interrupt service routine before

re-enabling this interrupt.


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Timer1- Introduction

16-bit timer/counter

Consists of two 8-bit registers - TMR1H & TMR1L

Both TMR1H & TMR1L are readable & writable

An interrupt occurs when the timer value rollsover from FFFFh to 0000h

Interrupt flag bit TMR1IF (PIR1)

Interrupt is enabled/disabled by setting/clearingTMR1 interrupt enable bit TMR1IE (PIE1)


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Timer1 Prescaler

The prescaler counter is cleared on writes to the

TMR1H or TMR1L registers.


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Timer1 can operate in one of three modes:

As a synchronous timer

As a synchronous counter

As an asynchronous counter

The operating mode is determined by clock select bit,TMR1CS (T1CON), and the synchronization bit,T1SYNC

Timer mode: Timer-1 increments every instruction cycle

Counter mode: increments on every rising edge of externalclock input

Timer1 can be turned on and off using the TMR1ON control

bit (T1CON).


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T1CON: Timer1 Control Register


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Timer1 Block Diagram


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TIMER1 contd.

Timer1 has the capability to operate off an

external crystal.

When the Timer1 oscillator is enabled

(T1OSCEN is set), the T1OSI and T1OSO pinsbecome inputs. That is, their corresponding TRIS

values are ignored.


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Clear Timer 1 Clock Source Select bit, TMR1CS(T1CON)

Input clock to timer = Fosc./4

The synchronize control bit, T1SYNC(T1CON), has no effect since the internal

clock is always synchronized.

Timer-1 operation in timer mode


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Timer-1 operation in synchronous counter mode

Select the counter mode by setting the TMR1CS

In this mode the timer increments on every rising edge ofclock input depending upon whether TIOSCEN is set orcleared .

T1OSCEN is set( enabled) => Timer increments on every

rising edge of clock input on pin RC1/T1OSI/CCP2 T1OSCEN is cleared => Timer increments on every rising

edge of clock input on pin RC0/T1OSO/T1CKI

If T1SYNC cleared,

external clock input synchronised with internal phase clock.

Synchronisation done after prescaler stage as prescaler is an asyncripple counter

Wont work during SLEEP as the synchronisation circuit is shut off.


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Timer-1 operation in asynchronous counter

mode

T1SYNC set => external clock input is not synchronized with

the internal phase clocks.

Timer continues to increment asynchronous to internal phase

clock. Timer continue run during SLEEP, can generate interrupt-on-

overflow which will wake up the processor.

Since the counter can operate in sleep, Timer1 can be used to

implement a true real-time clock.


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Introduction Timer 2 is an 8-bit timer

Has a prescaler & a postscaler and a period register

The 8 bit register of Timer2 is called TMR2.

Timer2 also has a period register called PR2

PR2 register can be set to a fixed value Timer 2 will increment from 00h until it matches the

value in PR2.

When TMR2 matches that of PR2 , an equal signal will

raise the TMR2IF flag and reset TMR2 to 00h

PR2 is a readable and writable register.

The PR2 register is initialized to FFh upon RESET.


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Timer2 Block Diagram

The postscaler counts the number of times that the TMR2 register matched

the PR2 register.This can be useful in reducing the overhead of the interrupt service routine

on the CPU performance.


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Introduction The clock source for Timer 2 is Fosc/4 with the options of

both prescaler and postscaler

The input clock (FOSC/4) has a prescale option of 1:1, 1:4,

or 1:16, selected by control bits T2CKPS1:T2CKPS0

(T2CON).

It cannot be used as a counter

The match output of TMR2 goes through a 4-bit postscaler

to generate a TMR2 interrupt ( TMR2IF) in PIR1.

Timer2 can be shut-off by clearing control bit TMR2ON

(T2CON), to minimize power consumption.


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T2CON: TIMER2 CONTROL

REGISTER


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Timer2 Prescaler and Postscaler

The prescaler and postscaler counters are

cleared when any of the following occurs:

a write to the TMR2 register

a write to the T2CON register

any device RESET (POR, MCLR Reset, WDT

Reset, or BOR)

TMR2 is not cleared when T2CON is written.


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THANK YOU

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PIC_part5_Timer0-2