Pixel power R&D in SpainF. Arteche

Phase II daysPhase 2 pixel electronics meeting

CERN - May 2015

OUTLINE

• 1. Introduction • 2. Spanish R&D for powering

–Implementation–Schedule and tasks

• 3. AIDA2020 – EMC facility –Support for pixel

• 4. Conclusions

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1. Introduction • New chip technology will force to design and develop

a complex power supply distribution system for pixel phase II– Huge power / high current demanded by each power

channel due to chip technology (250 nm → 65 nm)• 16 kW – 9 kW at 1.1V – 15 kA – 8kA

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1. Introduction • Powering pixel phase II is a challenging project

– Low mass & noise– Power dissipation aspects– Reliable systems ( high granularity)

• Design aspects :– On chip power generation – EMC/Grounding– Safety/protection aspects ( HV and LV lines)– Power cabling & services (noise coupling & mass)

• All these issues should be addressed at the same time– System level analysis

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• There are two different approaches to perform system studies:– Bottom to Top – System level studies at the end of the R&D

• Theoretical analysis : They can be started • Practical studies : It is necessary to wait till some prototype

components exists.– 3 or more years of waiting time

– Top – Bottom – At the same time than R&D at component level - Preferred option.

• They can start now.– These studies do not require final components.

• Component and system studies run in parallel• We can gain insight to critical aspects of the system quite early

1. Introduction

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• The project proposal plans to build two flexible prototypes of one /several power groups pixel phase II in order to study the impact of system aspects (topology and granularity ) on: – Noise distribution (cables & electronics)– Grounding topology / configuration – Transient issues (protections)

• They can be evaluated at the same time – Power, material budget and noise (EMC) issues

• Table making decision

• Final goal - To participate in the construction of the power supply system of CMS pixel phase II.– It will be part of Spanish contribution to CMS

2. Spanish R&D for powering

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• Two / Three topologies may be studied:– Based on serial powering (2):

• In Module / Across Module– Based on hybrid topologies (Serial + DC-DC)

• Common to serial (70% ) and DC-DC option (30%)• Preliminary analysis soon – (Go or no go)

• We have decided to focused most of our efforts on the study of serial powering topology.– It seems very good option but still too many open questions at

system level (pass from 1 A to 4 A or 14A)– Noise studies at system level for DC-DC have been already

done during previous years.• R&D CMS project focuses on EMC on DC-DC systems – 2009-2013• Several papers & Tracker phase II meeting contributions (2009-2013)

2. Spanish R&D for powering

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• The idea is to analyze / measure several EMC parameters for these configurations :– Conducted noise level

• At the entrance on each module• In the modules• Through cables (coupling among bundles)

– Radiated noise level• Cable level • Module level • Group level.

– Transients - Level & propagation

2. Spanish R&D for powering

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• Theses activities will help a lot to study :– HF grounding

• Several board designs (different grounding connections)– Which is the best place to ground the system (input or center)?

• Evaluation of different topologies (in module / on module) from the point of view of noise

– Which topology is more robust to noise? Which emits less noise?

– Cable bundles – Noise distribution• Impact at system level based on real measurement.

– It is important for neighboring systems

– Transients studies (protections ….)• Specially important for serial powering option (levels..)

2. Spanish R&D for powering

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• These prototypes will be based on the preferred proposed topologies defined by CMS pixel power working group.– The layout / voltages will be as similar as possible to the

ones defined by the group • The more realistic the better conclusions.

• These power units will be built with:– Set of resistance (emulated electronics power consump.)– Commercial power units. – One or two sensors and FEE from previous experiments or

Alibava systems.• They will be used to inject noise and to measure noise.

2.1 Spanish R&D for powering: Implementation

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• It will be a set of passive resistance • Connected in serial

(in mod /per mod)• Several modules can be prepared

in order to study grounding options

It becomes a resistor

• One of these passive loads will be substituted by an old FEE & sensor. It would act as a noise probe, not

as a sensor A very sensitive sensor would

be preferred.

2.1 Spanish R&D for powering: Implementation

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2.2 Spanish R&D for powering: Schedule and Tasks

• The project is planned in 4 WP:– WP1: Analysis of Hybrid topology– WP2: Design and development of pixel power system:

• Simulation unit of pixel power unit• Design and development of Dummy and active units.• Full system integrations (primary PS and cables)

– WP3: Noise studies in prototype• Noise emissions• Noise susceptibility of different grounding configurations• Transients

– WP4: Noise distribution in cable bundles• Noise measurements • Cable bundle model based on MTL

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2.2 Spanish R&D for powering: Schedule and Tasks

• The schedule is planned as:– WP1: Analysis of Hybrid topology

• Summer 2015– WP2: Design and development of pixel power system

• Summer 2016– WP3: Noise studies in prototype

• Summer 2017 / End 2017– WP4: Noise distribution in cable bundles

• End 2017

• The project development will be very dynamic.– Close work with electronic designers in order to anticipate system

problems → improve designs.– We will try to have as many studies as possible in order to give

valuable information to be included in the TDR planned for 2017.13 of 16

Phase 2 pixel electronics meetingCERN - May 2015

3. AIDA 2020 – EMC facility • A new EU Project has started recently – AIDA2020• ITAINNOVA is one of the partners

– Transnational access facility for Electromagnetic Compatibility tests

• These tests may be used to define in any electronic device installed in HEP experiment:– EM noise emission and immunity level & transients

• These tests are very good for:– Grounding topologies evaluation– FEE designs (robust designs against EM noise)

• It can be used to test small components, but mid-scale prototypes can be tested too.

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3. AIDA 2020 – EMC facility • Belle II SVD EMC test - Mid scale prototypes

CMS pixel electronics phase II community may use the facility to evaluate designsExpenses are covered by EU

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• Spanish R&D for powering has been presented.• It is focused mainly on system aspects of serial powering

topology based on:– Real measurements on system prototypes– Power systems simulations

• Power simulations - Transients & Noise simulations – Cable bundles.

• The study plans to build flexible system prototypes.– During the analysis, component prototypes can be added

• Very flexible option– Study other possible options

• All these studies can be done in three years. – A lot of system information may be obtained when component R&D

designs are ready for integration• Even for the TDR – planned for 2017 ??

– Exchange of information to get global solution

4. Conclusions

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