© 2002 by Triscend Corporation. All rights reserved. www.triscend.com

Triscend Part Number TCH405-0002-001

®

Designing with Synplify

November 2002 Version 1.9Abstract Triscend supports the use of the Synplify FPGA Synthesis tool for the creation of designs to place into the Configurable System Logic (CSL) portion of a Triscend device.

Contents Introduction................................................................................................................................................2 System Requirements...............................................................................................................................2 Before You Begin ......................................................................................................................................2 Getting Started ..........................................................................................................................................3 Creating an EDIF Netlist in Synplify ..........................................................................................................3 Instantiating Exported Modules in VHDL and Verilog Designs.................................................................4 Frequently Asked Questions .....................................................................................................................5

1. Unable to Access the Synplify License .............................................................................................5 2. Unable to Access Triscend Devices..................................................................................................5 3. Triscend Target Device is Not Listed ................................................................................................5 4. Instantiation Libraries for Black Boxes ..............................................................................................5 5. Instantiating Modules With Attributes ................................................................................................6 6. Pre-defined Constants.......................................................................................................................8 7. Why do I get this message - 860 Error: primitive view:PrimLib.z(prim) not handled yet...................8 8. FastChip Prints an ERROR for LATCHCS, LATCHC, LATCHS, or DFFCSMACRO in a Netlist .....9 9. Synplify produces a Dr. Watson exception or "corrupted memory bin" message.............................9 10. Synplify does not display the design graphically.............................................................................9 11. ConnectedPinNotInEquation warning printed when importing Synplify EDIF netlists ....................9

Known Bugs ............................................................................................................................................11 1. Synplify 6.x: Missing Clock Inversion ..............................................................................................11 2. Synplify 6.x: Inferred ROMs.............................................................................................................12 3. Synplify 7.0.2 and below: Index 0 is OUT of Range........................................................................15

2 TCH405-0002-001

Introduction Synplify, version 6.1.3 or later, can be used to create designs for the CSL portion of Triscend devices. Support for Triscend parts is built into versions of this tool as of version 6.1. Designs are created in the VHDL or Verilog HDL languages and synthesized by this tool into netlists of the EDIF 2.0.0 format. These netlists can then be imported into FastChip as modules, which can then be used as design elements in FastChip.

System Requirements In order to synthesize designs, you need the following items:

• Synplify/Synplify Pro version 6.1.3 or later (7.0.2 or higher recommended). This is the version of the Synplify tool that supports Triscend. An evaluation copy can be downloaded from the Synplicity web site http://www.synplicity.com/ .

• The Triscend FastChip Development System version 2.1.1 or later:

Designers can import the EDIF files exported by Synplify into FastChip. Once imported, your designs become Imported types in FastChip and can be instantiated in designs.

You may also need one or more of these optional files:

• [FastChip Dir]/data/libraries/Synthesis/TriscendDefines.v or .vhd

These files contain definitions of constants which may be applied to the ports of primitives instantiated in your design.

• [FastChip Dir]/data/libraries/Synthesis/TriscendVBB.v or TriscendVBBSynplify.vhd

These are instantiation libraries for Triscend primitives and macros which are not included in the default libraries shipped with the Synplify product. The default Synplify instantiation libraries triscend.v and triscend.vhd contain primitives that are inferred, and are found in the directory [Synplify Dir]/synplify/lib/triscend/triscend.v or triscend.vhd.

Before You Begin Before creating a new design in Synplify, first review some of the Triscend documents found in the Docs directory of the FastChip software installation. The Documentation Guide provides an overview of available documents. Particularly useful for synthesis users are the following documents:

• Synthesis_Design_Guide.pdf

• Using_Soft_Modules_in_EDA_Tools.pdf

• Triscend_Primitives.pdf

For complete information on using Synplify, refer to the Synplify User's Guide.

3 TCH405-0002-001

Getting Started Follow these steps to begin using Synplify:

1. Open Synplify or Synplify Pro.

2. Create a new project (if this is the first time you are importing your design).

3. Add your input VHDL or Verilog designs to the project. Verilog source files are found in the “verilog” folder and VHDL files in the “vhdl” folder. Add instantiation source files containing module interfaces for black boxes ahead of your source, followed by intermediate level modules, with your top-level module added last. There is an instantiation library in the Synplify installation under synplify\lib\triscend for some Triscend primitives, but you may also create your own file.

4. When all the VHDL and Verilog files comprising your design have been read in, select the Project pull down menu from the main menu bar and choose “Implementation Options.”

5. In the Options for Implementation window, select the Device tab and choose your Triscend device family as the Technology, as well as the Part, Speed and Package for the device you want to target. If you do not see the exact combination for your device, select the closest configuration.

There are some options to consider.

• The “Disable I/O Insertion” option must be selected. (In the current version of the tool, this is checked by default.) Otherwise, the tool inserts pads on all dangling ports. Triscend highly recommends hand-instantiating I/O primitives on ports instead of allowing the synthesis tool to perform this function.

• Other implementation options are common to all vendors supported by Synplify; consult the Synplify User’s Guide for more information.

Click on OK to set the implementation options.

6. Synthesize your design by clicking Run in the main window.

Creating an EDIF Netlist in Synplify When synthesis is complete, an implementation folder containing your design should appear in the source window of Synplify. For example, a folder named “rev_1” may exist. Open the folder by double-clicking the left mouse button on the folder icon or the “+” icon to the left. Your design is written out as an EDIF netlist by default and you should see a file with the “.edf” extension.

Your design has been exported to EDIF 2.0.0 format. You can specify the EDIF file name, implementation name and directory using the Project->Options for Implementation window and setting options in the “Implementation Results” tab. You can also create optional output files. You can re-synthesize your design after changing these options.

You can now import the design into FastChip, where it appears in the Library Tree under the Imported branch, and can be instantiated as a type in that environment.

During the import process, a design rule check is run on the EDIF design to make sure it is compatible with the internal Triscend tools. If the design rule check fails, you must change your design in Synplify, re-synthesize it, and then re-import your design into FastChip.

4 TCH405-0002-001

Instantiating Exported Modules in VHDL and Verilog Designs You can use models exported from FastChip as modules in user HDL designs. A typical candidate is an imported module in the FastChip library tree (perhaps obtained from another design environment) that the designer wishes to use as a cell type in HDL designs. By right-clicking one of the modules in the library tree, any of the modules can be exported to VHDL or Verilog.

Modules exported for use in this manner must be defined for synthesis as block boxes, or undefined modules, by the appropriate “Don’t touch” statements in HDL code. These statements cause the synthesizer to halt processing at the surface and not attempt to descend below into the contents.

This is typically done by adding comments with embedded synthesis directives to empty module definitions in an instantiation library, and including the library as a source file for implementation. For example, if the module type name is BBOX, the Verilog code is similar to:

module BBOX(I,O) /* synthesis syn_black_box syn_noprune=1 */ ;

input I;

output O;

endmodule

:

more module definitions

:

and the VHDL code is similar to: library ieee;

use ieee.std_logic_1164.all;

library synplify;

use synplify.attributes.all;

package myComponents is

component BBOX port(

I : in STD_ULOGIC;

O : out STD_ULOGIC

);

end component;

attribute syn_black_box of BBOX: component is true;

attribute syn_noprune of BBOX: component is true;

:

more component definitions

:

end myComponents;

If an imported module is exported and instantiated in an HDL design, the resulting EDIF netlist from the synthesized HDL design must be imported into the same FastChip project from which the imported module was obtained.

When importing a design with instantiated modules, the contents are read from the imported modules in a project and flattened into the design. Note that this means if you re-import one of these modules, then other imported designs with instantiated versions of the module must be re-imported as well.

When working with soft modules, the csoc modlib command can be used to create HDL black box and simulation libraries; see the Triscend technical document titled Using_Soft_Modules_with_EDA_Tools.pdf for more information.

5 TCH405-0002-001

Frequently Asked Questions If you have questions about using Synplify to synthesize your design, consult the items below for some of the more common issues experienced by users. The Triscend technical document titled Synthesis_Design_Guide.pdf also contains useful design information.

11.. UUnnaabbllee ttoo AAcccceessss tthhee SSyynnpplliiffyy LLiicceennssee Synplify requires a FlexLM license server for floating licenses or a hardware dongle (plug) for node-locked licenses that plugs into the parallel port of your workstation.

If you have a floating license, set the environment variable LM_LICENSE_FILE to <port>@machine, where <port> is the port number used by the license server to communicate with the client and machine is the name of the license server host.

If the license is node-locked, you will need to connect a license dongle to your parallel port, and install a driver for the dongle and a license file. A common error encountered by dongle users occurs because the driver for the dongle has not been installed.

When updating your license file, be sure that license data copied from email or a file is properly inserted into the license file (typically named license.txt or license.dat). You may need to correct problems due to line breaks inserted by email programs. If license data requires more than one line, make sure there is a back-slash character '\' at the end of each line except the last:

• Example of license data with check-out failure: FEATURE synplify_pc synplctyd 2002.050 14-may-2003 0

9CFA39C576076B8D706B \

VENDOR_STRING=fpga,analyst HOSTID=SKEY=0C53 ck=200

• Example of the same license data without check-out failure (the missing back-slash was added to the first line):

FEATURE synplify_pc synplctyd 2002.050 14-may-2003 0 \

9CFA39C576076B8D706B \

VENDOR_STRING=fpga,analyst HOSTID=SKEY=0C53 ck=200

22.. UUnnaabbllee ttoo AAcccceessss TTrriisscceenndd DDeevviicceess Synplify/Synplify Pro 6.1 and up support Triscend devices. Make sure you have the correct version of the Synplify software, as well as the license for the Triscend mapper.

33.. TTrriisscceenndd TTaarrggeett DDeevviiccee iiss NNoott LLiisstteedd When targeting Triscend devices in synthesis tools, you may find that the part you wish to select is not listed. This occurs because there may be a time lag between the release of libraries by synthesis tool vendors and FastChip.

To target a part that is not listed, select any Triscend device family, speed grade and part. Although timing values will differ, all device families support the same set of primitive modules in the configurable system logic (CSL). The synthesized netlist can be imported into any FastChip project, and during the Bind process a timing report of the actual mapped design will be produced.

44.. IInnssttaannttiiaattiioonn LLiibbrraarriieess ffoorr BBllaacckk BBooxxeess When instantiating Triscend primitives and macros, or any user module, as a block box in your HDL design, you will need a black box definition which is used to declare the module name and port interface for Synplify. You may create your own Verilog or VHDL black box interfaces or use pre-defined instantiation libraries.

6 TCH405-0002-001

Synplify includes instantiation libraries triscend.v and triscend.vhd in the directory [Synplify_Dir]/synplify/lib/triscend. It contains Triscend primitives which are inferred or instantiated by the Synplify tool--for example, pad cells. The VHDL package name is component.

Triscend includes instantiation libraries TriscendVBB.v and TriscendVBBSynplify.vhd in the directory [FastChip_DIR]/data/libraries/Synthesis (Note: TriscendVBB.vhd is for use with FPGA Express and results in warnings when used with Synplify). These libraries are complementary to those included with Synplify; the modules in the file do not overlap. The VHDL package name is TCOMPONENTS, which is the same as the Triscend simulation library.

To use these libraries, simply add them as a source file to be compiled.

55.. IInnssttaannttiiaattiinngg MMoodduulleess WWiitthh AAttttrriibbuutteess Synplify supports mechanisms for specifying attributes embedded in comments for Verilog or using the VHDL attribute mechanism for an instantiated module.

The syn_props synthesis attribute is used to pass vendor-specific attributes through to the EDIF netlist as a property for processing by FastChip software and is not used by Synplify. The FastChip EDIF reader processes these properties and attaches them to the imported netlist.

Other synthesis attributes are read by Synplify, but are not read by FastChip. The syn_black_box attribute is an example.

Here are some general guidelines for instantiating modules.

• Triscend bus ports, for example, the SIM port on CSI bus primitives SIDESIM port on sideband primitives, need to be connected if you simulate your RTL or post-synthesis design. Otherwise, you may leave them unconnected (during FastChip netlist import, these ports are connected automatically for you). Do not insert pads automatically for the SIM or SIDESIM ports.

• The symbolic name associated with a selector primitive, for example SELECTRANGE, is defined as the name of the input port of the top-level module connected to the SYMBOLIC port. The SYMBOLIC port of instantiated selector primitives should be connected to a top-level input.

• Instantiating pads within FastChip gives you much flexibility in assigning pin numbers and electrical characteristics in a graphical environment. If you choose instead to instantiate pads in your synthesized netlist, be sure to connect the NAME port of the pad primitives to a port of the top-level module. Automatic insertion of pads during synthesis is not recommended.

• Modules with INITV ports on the simulation model can be instantiated using an attribute. In the netlist to be synthesized, instantiate the module with a syn_props attribute, which can be used to define the INITV value.

In Verilog netlists, Synplify uses comments beginning with the keyword “synthesis” to define synthesis attributes; separate multiple synthesis attributes with spaces. VHDL attributes are used in those netlists to define synthesis attributes; use the library “synplify” and package “attributes”. Some examples are:

• VHDL

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

library synplify;

use synplify.attributes.all;

:

architecture TEST of MyExample is

:

7 TCH405-0002-001

attribute syn_props: string;

attribute syn_props of myPad1: label is "HYSTERESIS=TRUE";

begin

:

myPad1: PAD port map( ... );

:

end TEST;

• Verilog

PAD myPad1( ... ) // synthesis syn_props="HYSTERESIS=TRUE"

Within the syn_props attribute value (which is enclosed in double quotes), separate multiple FastChip attributes with commas. For example:

• VHDL

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

library synplify;

use synplify.attributes.all;

:

architecture TEST of MyExample is

:

attribute syn_props: string;

attribute syn_props of myPad2: label is "HYSTERESIS=FALSE, BUSMINDER=PULLUP";

begin

:

myPad2: PAD_IN port map( ... );

:

end TEST;

• Verilog

PAD_IN myPad2( ... ) // synthesis syn_props="HYSTERESIS=FALSE, BUSMINDER=PULLUP"

Pad modules instantiated in HDL netlists are likely candidates for specifying FastChip attributes. Attribute names are not case sensitive. Supported pad attributes include:

Attribute Value

Name <pad_name>

BusMinder NONE, PULLUP, PULLDOWN, FOLLOWER

IsInputLowPower TRUE, FALSE (inputs)

8 TCH405-0002-001

IsClamped TRUE, FALSE (inputs, A7 only)

Hysteresis TRUE, FALSE (inputs)

Drive WEAK, STRONG, PULLDOWN, FOLLOWER (outputs)

SlewRate SLOW, FAST (outputs, A7 only)

IsOutputLowPower TRUE, FALSE (outputs)

66.. PPrree--ddeeffiinneedd CCoonnssttaannttss When instantiating Triscend primitives, you may save time by using libraries of pre-defined constants included with FastChip. The files TriscendDefines.v and TriscendDefines.vhd in the directory [FastChip_Dir]/data/libraries/Synthesis contain useful constants. The VHDL package name is TRISCEND_DEFINES.

77.. WWhhyy ddoo II ggeett tthhiiss mmeessssaaggee -- 886600 EErrrroorr:: pprriimmiittiivvee vviieeww::PPrriimmLLiibb..zz((pprriimm)) nnoott hhaannddlleedd yyeett When synthesizing a design with Synplify, the last module of the last source file is selected as the top level module, unless otherwise specified. One way to do this in the Synplify GUI is to click and drag the top-level source file to move it after the other files (move it vertically on the screen), or make sure that it is added as the last source file.

For example, if the last file compiled were the instantiation library TriscendVBB.v, you might get the error below (assuming WAITCTRL is the last module in that file):

$ Start of Compile

#Wed Mar 21 22:28:27 2001

Synplicity Verilog Compiler, version 6.1.3, Build 077R, built Nov 27 2000

Copyright (C) 1994-2000, Synplicity Inc. All Rights Reserved

@I::"c:\my documents\triscend\data\source\top.v"

@I::"c:\my documents\triscend\data\source\TriscendVBB.v"

Verilog syntax check successful!

Compiler output is up to date. No re-compile necessary

Selecting top level module WAITCTRL

Synthesizing module WAITCTRL

@END

Process took 0.38 seconds realtime, 0.38 seconds cputime

Synplicity Triscend Technology Mapper, version 6.1.0, Build 068R, built

Oct 23 2000

Copyright (C) 2000, Synplicity Inc. All Rights Reserved

List of partitions to map:

view:work.WAITCTRL(verilog)

\\synnac\syn\george\nt\syn610\src\mappers\triscend\trmap.c:860 Error:

primitive view:PrimLib.z(prim) not handled yet

Process took 0.33 seconds realtime, 0.33 seconds cputime

You should make your top level module the last one compiled. TriscendVBB.v is compiled last, and the last module in it is being treated as the top level module. If you move TriscendVBB.v ahead of the other source files, this message should go away (or at least a different message will be observed).

9 TCH405-0002-001

88.. FFaassttCChhiipp PPrriinnttss aann EERRRROORR ffoorr LLAATTCCHHCCSS,, LLAATTCCHHCC,, LLAATTCCHHSS,, oorr DDFFFFCCSSMMAACCRROO iinn aa NNeettlliisstt The Triscend configurable system logic (CSL) does not support latches with asynchronous clear or set pins, nor does it support a D-type flip-flop with both a clear and a set pin. Synplify assumes these primitives are available and may infer them in your design:

• LATCHCS - latch with asynchronous clear and set pins

• LATCHC - latch with asynchronous clear pin

• LATCHS - latch with asynchronous set pin

• DFFCSMACRO - D-type flip-flop with asynchronous clear and set pins

Designs containing these elements cannot be imported by FastChip. If your design contains any of these elements, you should modify your HDL code and re-synthesize your design. Also, the CSL architecture does not support true transparent latches, and it is recommended that synthesized designs containing the LATCH primitive be re-implemented without latches if possible.

If you are using VHDL, conditional signal assignments will result in the inference of latches. For example, q <= d when clk = '1' else q. If you have a process block with an "if", a latch could be inferred:

if (clk = '1') then q <= d.

In "case" statements with "when" statements where signals are not always assigned a value, a latch may result.

Synplify generates a warning message if unsupported flip-flops or latches are inferred: @W|Found flip-flop with both clear and set; requires an implementation model for Triscend place and route.

@W|Found latch with clear and/or set; requires an implementation model for Triscend place and route.

99.. SSyynnpplliiffyy pprroodduucceess aa DDrr.. WWaattssoonn eexxcceeppttiioonn oorr ""ccoorrrruupptteedd mmeemmoorryy bbiinn"" mmeessssaaggee On rare occasions during logic mapping Synplify may experience an application exception, e.g. a Windows Dr. Watson error, or detect an error condition, e.g. the <design>.srr report file contains a "corrupted memory bin" message.

These types of errors are difficult to diagnose, but a possible workaround involves setting an environment variable which causes Synplify to use a different memory allocation scheme. It should not cause any differences in the results.

Set the environment variable SYNPLIFY_SAVEMEM to a value of 1 and re-run the design. You will need to launch Synplify again after setting the environment variable. If this does not solve the problem, try running the design with FSM Compiler/Resource sharing turned on and off.

If the problem persists, contact Synplicity technical support.

1100.. SSyynnpplliiffyy ddooeess nnoott ddiissppllaayy tthhee ddeessiiggnn ggrraapphhiiccaallllyy The Synplify HDL Analyst option must be purchased to view a user's design graphically. It supports a number of views of the design, from RTL to vendor implementation.

This option must be purchased directly from Synplicity; Triscend does not sell this option and it is not included with the standard Synplify product.

1111.. CCoonnnneecctteeddPPiinnNNoottIInnEEqquuaattiioonn wwaarrnniinngg pprriinntteedd wwhheenn iimmppoorrttiinngg SSyynnpplliiffyy EEDDIIFF nneettlliissttss When importing an EDIF netlist synthesized by Synplify, a ConnectedPinNotInEquation warning similar to the one may be displayed:

10 TCH405-0002-001

WARNING: Import Command: ConnectedPinNotInEquation: The pin

'fifo_ctrl_N_216_i.i[3]' of item 'fifo_ctrl_N_216_i' is

connected but is not a parameter of its equation:

'( 2)|( 0)|(~ 1)'.

This message is displayed if an input of a look-up table (LUT) cell is connected, but the input is not used in the equation that defines the functionality of the LUT. In the example above, input 3 is connected but not used.

Synplify will connected unused inputs in the synthesized netlist to a net. LUT inputs that are connected but not used are flagged during import. If you examine the netlist and determine this is the case, the warning can be safely ignored.

This issue will be addressed in future releases of FastChip (enable the user to control the display of messages) and Synplify (LUT inputs connected to ground but not specified in a LUT equation are ignored by FastChip).

11 TCH405-0002-001

Known Bugs If you experience problems using Synplify to synthesize your design or in importing designs into FastChip, consult the list of known bugs below.

11.. SSyynnpplliiffyy 66..xx:: MMiissssiinngg CClloocckk IInnvveerrssiioonn The Synplify mapper for Triscend devices has a known problem with using an inverted clock, or the falling clock edge, from synthesis using Synplify versions 6.3 and earlier. The inversion is missing in the synthesized netlist.

This issue is being tracked by Synplicity as Synplify bug 31674, scheduled to be fixed in Synplify release 7.0, which is productional in the 4th quarter of 2001. A work-around is to explicitly create an inverted signal and apply the syn_keep attribute to the net to prevent it from being optimized. The resulting EDIF netlist contains an inverter that is merged into the flip-flop by FastChip.

An example is shown below.

Consider the following VHDL code snippet, which creates two flip-flops after synthesis. One flip-flop, called ‘q_rising’, is clocked on the rising or positive clock edge. The other flip-flop, called ‘q_falling’, is clocked on the falling or negative clock edge.

architecture example of clk_inversion_example is

begin

process(clk)

begin

if (rising_edge(clk)) then

q_rising <= d;

end if;

if (falling_edge(clk)) then

q_falling <= d;

end if;

end process;

end example;

Synplify’s Technology Viewer shows a clock bubble into the clock on ‘q_falling’ flip-flop, which is the expected behavior.

However, the EDIF netlist file created by Synplify version 6.3 or earlier does not include the inverted clock in the resulting netlist. Consequently, the design fails to operate as expected when imported into FastChip and implemented on a Triscend Configurable System-on-Chip (CSoC) device.

Fortunately, there is a simple work-around using a Synplicity synthesis attribute called ‘syn_keep’. To use this attribute, add the Synplicity library to the top your VHDL source file.

library synplify;

use synplify.attributes.all;

Then, create a new signal for the inverted clock, called ‘clk_inv’ in this example. Placing a ‘syn_keep’ attribute on this signal prevents the Synplify optimizer from attempting to merge the inverted clock into the flip-flop.

Finally, instead of clocking the ‘q_falling’ flip-flop on the falling edge of ‘clk’, clock the flip-flop on the rising edge of the inverted clock ‘clk_inv’.

architecture fixed_example of clk_inversion_example is

12 TCH405-0002-001

-- signal created to explicitly invert 'clk' input

signal clk_inv : std_logic;

-- this special Synplicty attribute prevents 'clk_inv' from

-- being optimized away

attribute syn_keep of clk_inv : signal is true;

begin

-- invert 'clk'

clk_inv <= not(clk);

process(clk, clk_inv)

begin

if (rising_edge(clk)) then

q_rising <= d;

end if;

-- instead of clocking on the falling edge

-- of 'clk', clock on the rising edge of the

-- inverted 'clk' signal

if (rising_edge(clk_inv)) then

q_falling <= d;

end if;

end process;

end fixed_example;

Viewing the synthesized design, note the explicit inverter on the ‘clk’ signal entering the clock input on the ‘q_falling’ flip-flop. This inverter correctly appears in the EDIF file created by Synplify and works correctly when the logic is implemented on a Triscend CSoC device.

During Bind, FastChip is smart enough to merge the inverter into the Configurable System Logic (CSL) flip-flop using the optional clock inversion allowed on each cell, resulting in optimal timing and routing.

22.. SSyynnpplliiffyy 66..xx:: IInnffeerrrreedd RROOMMss The ROM support for Triscend devices has the following known problems with Synplify versions 6.3 and earlier: 1) inferred ROMs are missing the prefix “#B” in the INITV property of the ROM instantiated in the EDIF netlist, and 2) ‘X’ default values for inferred ROMs are not mapped to a logic 0 or 1.

This issue is being tracked by Synplicity and is scheduled to be fixed in Synplify release 7.0, which is productional in the 4th quarter of 2001. Synplify 7.0 contains corrections for both of the issues described above, and also outputs the INITV property in the EDIF netlist using a hexadecimal format which is easier to read. Two work-arounds are described below.

For use with Synplify 6.x only, you may obtain an updated ROM generator file rombin.vhd from the Triscend Support Center and install this file as rom.vhd in the Synplify software installation (back up your original rom.vhd file): <Synplify_root>\synplify\lib\triscend\gen_e5\rom.vhd. Run Synplify again to synthesize your design and this new rom.vhd file will be used automatically when ROMs are inferred by the Synplify Triscend mapper.

13 TCH405-0002-001

Alternatively, the following manual work-arounds may be used.

1. In the EDIF netlist, if the INITV property for inferred ROMs is missing the prefix "#B", for example (instance U0 (viewRef prim (cellRef ROM32X1 (libraryRef Triscend)))

(property INITV (string "00001000010000000001001111110000"))

)

correct this by inserting "#B" in the binary string using a text editor: (instance U0 (viewRef prim (cellRef ROM32X1 (libraryRef Triscend)))

(property INITV (string "#B00001000010000000001001111110000"))

)

2. Default values for inferred ROMs which are specified as 'X' are not mapped to a known logic value of 0 or 1. For example, a "default" clause of 'X' in a Verilog "case" statement inferred as a ROM results in INITV properties in the EDIF netlist with 'X' logic values, for example

(instance U0 (viewRef prim (cellRef ROM32X1 (libraryRef Triscend)))

(property INITV (string "X0001000010000000001001111110000"))

)

To correct this, change the default in your HDL source code for ROMs to logic '0' (or change 'X' to '0' in the ROM INITV property in the resulting EDIF netlist). Remember to insert "#B" in the binary string using a text editor to correct the ROM INITV property in the EDIF netlist.

(instance U0 (viewRef prim (cellRef ROM32X1 (libraryRef Triscend)))

(property INITV (string "#B00001000010000000001001111110000"))

)

An example of Verilog code inferred as a ROM is included below: module myrom(z, a) ;

output [3:0] z;

input [6:0] a;

reg [3:0] z ;

always @(a) begin

case (a[6:0])

7'b0000000: z = 4'ha;

7'b0000010: z = 4'b0011;

7'b0000100: z = 4'b1110;

7'b0000101: z = 4'b0111;

7'b0000110: z = 4'b0101;

7'b0000111: z = 4'b0100;

7'b0001000: z = 4'b0111;

7'b0001001: z = 4'b1101;

7'b0001010: z = 4'b1011;

7'b0001011: z = 4'b1010;

7'b0001100: z = 4'b1100;

7'b0010101: z = 4'b1011;

7'b0010110: z = 4'b1111;

7'b0010111: z = 4'b1001;

7'b0011000: z = 4'b1011;

14 TCH405-0002-001

7'b0011001: z = 4'b1001;

7'b0011010: z = 4'b1011;

7'b0011011: z = 4'b1101;

7'b0011100: z = 4'b1011;

7'b0011101: z = 4'b1011;

7'b0011110: z = 4'b1010;

7'b0011111: z = 4'b1011;

7'b0100000: z = 4'b0010;

7'b0100001: z = 4'b1001;

7'b0100010: z = 4'b0101;

7'b0100011: z = 4'b0100;

7'b1001000: z = 4'b1110;

7'b1001001: z = 4'b0100;

7'b1001010: z = 4'b1001;

7'b1001011: z = 4'b0101;

7'b1001100: z = 4'b0000;

7'b1001101: z = 4'b1001;

7'b1001110: z = 4'b0110;

7'b1001111: z = 4'b1001;

7'b1010000: z = 4'b1011;

7'b1010001: z = 4'b1010;

7'b1010010: z = 4'b1000;

7'b1010011: z = 4'b1010;

7'b1010100: z = 4'b0101;

7'b1010101: z = 4'b1001;

7'b1010110: z = 4'b0100;

7'b1010111: z = 4'b1101;

7'b1011000: z = 4'b1110;

7'b1011001: z = 4'b1101;

7'b1011010: z = 4'b0101;

7'b1011011: z = 4'b0110;

7'b1011100: z = 4'b1011;

default : z = 4’b0000; // default to logic 0

// original default clause which is not handled properly

// default: z = 4'bxxxx;

endcase

end

endmodule

15 TCH405-0002-001

33.. SSyynnpplliiffyy 77..00..22 aanndd bbeellooww:: IInnddeexx 00 iiss OOUUTT ooff RRaannggee When inferring ROMs with Synplify version 7.0.2 and earlier, an "index 0 is out of range" error message is printed if the word data at address 0 is not defined (Synplify bug #43808).

To work around this problem, explicitly define the word data for ROM address 0. You may also contact the Triscend Support Center to obtain a patch. The problem is corrected in later versions of Synplify.

® Triscend Corporation

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