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l Edward A. Lee l 10/13/11
l 1
Portable Real-Time Code from PTIDES Models Patricia Derler, John Eidson, Edward A. Lee, Slobodan Matic, Christos Stergiou, Michael Zimmer UC Berkeley Invited Talk Workshop on Time Analysis and Model-Based Design, from Functional Models to Distributed Deployments (TiMoBD) ESWeek Taipei, Taiwan, Oct. 9, 2011
Lee, et al. Berkeley 2
The Problem we are addressing
For cyber-physical systems, programs do not adequately specify behavior. When interactions with physical processes are central, the temporal dynamics of software is a critical part of its behavior. Today, temporal dynamics emerges from an implementation of the system, rather than being part of the model and/or program(s) specifying the system. As a consequence, systems are brittle and non-portable.
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Lee, et al. Berkeley 3
Platform independent model of functional and
timing behavior Code Generation to multiple target platforms
2x10
-10
0
10
20
30
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Reserve Velocity (red), Target Velocity (green) and Tracking Error
Time in seconds
Velo
city
m/s
2x10
0.10
0.15
0.20
0.25
0.30
1.997 1.998 1.999 2.000 2.001 2.002 2.003 2.004 2.005 2.006
Contact (red), Top Dead Center (green), Cut (blue) and Arm (black)
Time in seconds
Even
ts
Simulation
Same I/O behavior w.r.t. value and timing
e.g.: Renesas 7216 Demonstration Kit
e.g.: XMOS development board with 4
XCores.
Our Goal: Determinate timing at sensors and actuators
Lee, et al. Berkeley 4
Success on a test case: Flying Paster
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-0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 Time (ms)
topDeadCenter armContact tapeDetector contact cut
-3x10
0.05
0.10
0.15
0.20
0.25
0.30
-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
Contact (red), Top Dead Center (green), Cut (blue) and Arm (black)
Time in seconds
Even
ts
Timing given by simulation of the model
Timing measured by oscilloscope on a Renesas board.
Timing measured by software instrumentation on an XMOS board.
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Lee, et al. Berkeley 5
Problems that complicate analysis of system behavior:
Structure of a Cyber-Physical System
Messages from different sources interleave
nondeterministically Sensors may be locked out for an indeterminate
amount of time
Plat
Variability of execution times affects results
(not just WCET) Interrupt-driven I/O disrupts timing
Platforms’ measurements of time differ
A fault in a remote component may disrupt a
critical local activity
A fault in a remote component may go undetected for a long time
Etc…
Lee, et al. Berkeley 6
Our Programming Model
PTIDES: Programming Temporally Integrated Distributed Embedded Systems Based on a determinate discrete-event (DE) model of computation (MoC), originally developed for simulation.
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Lee, et al. Berkeley 7
Ptides: First step: Time-stamped messages.
Messages carry time stamps that define their
interleaving
Lee, et al. Berkeley 8
Ptides: Second step: Network time synchronization
GPS, NTP, IEEE 1588, time-triggered busses, etc., all provide some form of common time base. These are becoming fairly common.
Assume bounded clock error
Assume bounded clock error e
Assume bounded clock error e
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Lee, et al. Berkeley 9
Ptides: Third step: Bind time stamps to real time at sensors and actuators
Input time stamps are ≥ real time
Input time stamps are ≥ real time
Output time stamps are ≤ real time
Output time stamps are ≤ real time Messages are
processed in time-stamp order.
Clock synchronization gives global meaning to
time stamps
Lee, et al. Berkeley 10
Global latencies between sensors and actuators become controllable, which enables analysis of system dynamics.
Ptides: Fourth step: Specify latencies in the model
Model includes manipulations of time stamps, which control
latencies between sensors and actors
Actuators may be designed to interpret input time stamps as the time at which to
take action. Feedback through the physical world
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Lee, et al. Berkeley 11
Ptides: Fifth step Safe-to-process analysis (ensures determinacy) Safe-to-process analysis guarantees that the generated code obeys time-stamp semantics (events are processed in time-stamp order), given some assumptions.
Assume bounded network delay d
Assume bounded clock error
Assume bounded clock error e
An earliest event with time stamp t here can be safely merged when real time exceeds t + s + d + e – d2
Assume bounded clock error e
Assume bounded sensor delay s
Application specification of
latency d2
Lee, et al. Berkeley 12
Ptides Schedulability Analysis Determine whether deadlines can be met
Schedulability analysis incorporates computation times to determine whether we can guarantee that deadlines are met.
Deadline for delivery of event with time stamp t
here is t – c3 – d2
Deadline for delivery here is t
Assume bounded computation time c1
Assume bounded computation time c3
Assume bounded computation time c2
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Lee, et al. Berkeley 13
PtidyOS: A lightweight microkernel supporting Ptides semantics
PtidyOS runs on ¢ Arm (Luminary Micro) ¢ Renesas ¢ XMOS Occupies about 16 kbytes of memory.
Luminary Micro 8962
An interesting property of PtidyOS is that despite being highly concurrent, preemptive, and EDF-based, it does not require threads. A single stack is sufficient!
The name “PtidyOS” is a bow to TinyOS, which is a similar style of runtime kernel.
Renesas 7216 Demonstration Kit
XMOS development board with 4
XCores.
Lee, et al. Berkeley 14
Workflow Structure
HW Platform Software Component
Library
Ptides Model Code Generator
PtidyOS
Code
Plant Model
Network Model
HW in the Loop
Simulator
Causality Analysis
Program Analysis
Schedulability Analysis
Analysis
Mixed Simulator
Ptolemy II Ptides domain
Ptolemy II Discrete-event, Continuous, and Wireless domains
e.g. Luminary Micro 8962 IEEE 1588 Network
time protocol
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Lee, et al. Berkeley 15
A Typical Cyber-Physical System Printing Press
• Applica(on aspects • local (control) • distributed (coordina(on) • global (modes)
• Ethernet network • Synchronous, Time-‐Triggered • IEEE 1588 (me-‐sync protocol
• High-‐speed, high precision • Speed: 1 inch/ms (~100km/hr) • Precision: 0.01 inch
-‐> Time accuracy: 10us Bosch-‐Rexroth
15
Lee, et al. Berkeley 16 Source: http://offsetpressman.blogspot.com/2011/03/how-flying-paster-works.html
Example – Flying Paster
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Source: hNp://offsetpressman.blogspot.com/2011/03/how-‐flying-‐paster-‐works.html
Flying Paster
Lee, et al. Berkeley 18
Printing Press – Model in Ptolemy II See talk Thursday by Patricia Derler at workshop on Model-Based Design with a Focus on Extra-Functional Properties
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Plant model +
Distributed Controllers
5 Siemens CKI Project Review Patricia Derler
Printing Press – Model in Ptolemy II See talk Thursday by Patricia Derler at workshop on Model-Based Design with a Focus on Extra-Functional Properties
Lee, et al. Berkeley 20
Printing Press – Model in Ptolemy II See talk Thursday by Patricia Derler at workshop on Model-Based Design with a Focus on Extra-Functional Properties
l Edward A. Lee l 10/13/11
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Lee, et al. Berkeley 21
Platform independent model of functional and
timing behavior Code Generation to multiple target platforms
2x10
-10
0
10
20
30
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Reserve Velocity (red), Target Velocity (green) and Tracking Error
Time in seconds
Velo
city
m/s
2x10
0.10
0.15
0.20
0.25
0.30
1.997 1.998 1.999 2.000 2.001 2.002 2.003 2.004 2.005 2.006
Contact (red), Top Dead Center (green), Cut (blue) and Arm (black)
Time in seconds
Even
ts
Simulation
Same I/O behavior w.r.t. value and timing
e.g.: Renesas 7216 Demonstration Kit
e.g.: XMOS development board with 4
XCores.
Determinate timing at sensors and actuators
Lee, et al. Berkeley 22
Platform independent model of functional and
timing behavior Code Generation to multiple target platforms
2x10
-10
0
10
20
30
0.0 0.5 1.0 1.5 2.0 2.5 3.0
Reserve Velocity (red), Target Velocity (green) and Tracking Error
Time in seconds
Velo
city
m/s
2x10
0.10
0.15
0.20
0.25
0.30
1.997 1.998 1.999 2.000 2.001 2.002 2.003 2.004 2.005 2.006
Contact (red), Top Dead Center (green), Cut (blue) and Arm (black)
Time in seconds
Even
ts
Simulation
Same I/O behavior w.r.t. value and timing
e.g.: Renesas 7216 Demonstration Kit
e.g.: XMOS development board with 4
XCores.
Determinate timing at sensors and actuators
XMOS Predictable timing Multiple cores No analog I/O No FPU No hardware clock
Renesas PHY chip for accurate timestamping of inputs, Analog I/O
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Lee, et al. Berkeley 23
Renesas vs. XMOS: Measured I/O timing
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-0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 Time (ms)
topDeadCenter armContact tapeDetector contact cut
-3x10
0.05
0.10
0.15
0.20
0.25
0.30
-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
Contact (red), Top Dead Center (green), Cut (blue) and Arm (black)
Time in seconds
Even
tsSimulation
Renesas
XMOS
Lee, et al. Berkeley 24
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-0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 Time (ms)
topDeadCenter armContact tapeDetector contact cut
-3x10
0.05
0.10
0.15
0.20
0.25
0.30
-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
Contact (red), Top Dead Center (green), Cut (blue) and Arm (black)
Time in seconds
Even
tsSimulation
Renesas
XMOS
input input output
Renesas vs. XMOS: I/O timing
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Lee, et al. Berkeley 25
Renesas vs. XMOS: Busy vs. Idle Time
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-0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 Time (ms)
topDeadCenter armContact tapeDetector contact cut
-3x10
0.05
0.10
0.15
0.20
0.25
0.30
-0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
Contact (red), Top Dead Center (green), Cut (blue) and Arm (black)
Time in seconds
Even
tsSimulation
Renesas
XMOS
Lee, et al. Berkeley 26
Ptides Publications ¢ Y. Zhao, J. Liu, E. A. Lee, “A Programming Model for Time-Synchronized
Distributed Real-Time Systems,” RTAS 2007.
¢ T. H. Feng and E. A. Lee, “Real-Time Distributed Discrete-Event Execution with Fault Tolerance,” RTAS 2008.
¢ P. Derler, E. A. Lee, and S. Matic, “Simulation and implementation of the ptides programming model,” DS-RT 2008.
¢ J. Zou, S. Matic, E. A. Lee, T. H. Feng, and P. Derler, “Execution strategies for Ptides, a programming model for distributed embedded systems,” RTAS 2009.
¢ J. Zou, J. Auerbach, D. F. Bacon, E. A. Lee, “PTIDES on Flexible Task Graph: Real-Time Embedded System Building from Theory to Practice,” LCTES 2009.
¢ J. C. Eidson, E. A. Lee, S. Matic, S. A. Seshia and J. Zou, “Time-centric Models For Designing Embedded Cyber-physical Systems,” ACES-MB 2010.
¢ J. C. Eidson, E. A. Lee, S. Matic, S. A. Seshia, and J. Zou, Distributed Real-Time Software for Cyber-Physical Systems, To appear in Proceedings of the IEEE special issue on CPS, December, 2011.
http://chess.eecs.berkeley.edu/ptides/
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Lee, et al. Berkeley 27
Conclusions
Today, timing behavior is a property only of realizations of software systems.
Tomorrow, timing behavior will be a semantic property of programs and models.
Raffaello Sanzio da Urbino – The Athens School
Overview References: • Lee. Computing needs time. CACM, 52(5):70–79, 2009 • Derler, Lee, Sangiovanni-Vincentelli, Modeling Cyber-Physical Systems, To appear in Proc. of the IEEE December, 2011.