Computer Harware Design

Register Transfer and Microoperation

Postgraduate Course

Electrical Engineering Department

College of Engineering

University of Salahaddin

February 2015

Register Transfer Level (RTL)

A digital system is a sequential logic system constructed with flip-flops and gates.

Because the number of states would be prohibitively large, digital systems are

designed using a modular approach instead of state table.

Digital modules are best defined by a set of registers and the operations that are

performed on the binary information stored in them.

A digital system is represented at the register transfer level (RTL) when it is

specified by the following three components:

1. The set of register in the system

2. The operations that are performed on the data stored in the register.

3. The control that supervises the sequence of operations in the system.

The type of operations most often encountered in digital systems can be classified

into four categories:

1. Transfer operations

2. Arithmetic operations

3. Logic operations

4. Shift operations

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Register Transfer Level (RTL) Cont.

The internal hardware organization of a digital computer is best defined by

specifying

The set of registers it contains and their functions

The sequence of microoperations performed on the binary information stored

The control that initiates the sequence of microoperations

Use symbols, rather than words, to specify the sequence of microoperations

The symbolic notation used is called a register transfer language

A programming language is a procedure for writing symbols to specify a given

computational process

Define symbols for various types of microoperations and describe associated

hardware that can implement the microoperations

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Register Transfer Operations

Computer registers are designated by capital letters (sometimes followed by

numerals) to denote the function of the register:

o R1: processor register

o MAR: Memory Address Register (holds an address for a memory unit)

o PC: Program Counter

o IR: Instruction Register

o SR: Status Register

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Register Transfer Operations Cont.

The individual flip-flops in an n-bit register are numbered in sequence from 0 to n-1

(from the right position toward the left position)

Other ways of drawing the block diagram of a register;

Computer Hardware Design EED at University of Salahaddin

A block diagram of a register

Register R1 Showing individual bits

7 6 5 4 3 2 1 0R1

PC

Numbering of bits

Partitioned into two parts

15 0

PC(H) PC(L)

07815

Lower byteUpper byte

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Register Transfer Operations Cont.

Information transfer from one register to another is described by a replacement operator:

R2 ← R1

This statement implies that the hardware is available

• Transfer of the content of register R1 into register R2

• The transfer happens in one clock cycle

• The content of the R1 (source) does not change

• The content of the R2 (destination) will be lost and replaced by the new data

transferred from R1

• We are assuming that the circuits are available from the outputs of the source

register to the inputs of the destination register, and that the destination register

has a parallel load capability

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Register Transfer Operations Cont.

Conditional transfer occurs only under a control condition

Representation of a (conditional) transfer

P: R2 ← R1

which can be written as

If (P = 1) then (R2 ← R1)

• where P is a control function that can be either 0 or 1

• The content of R1 is transferred into R2 only if P is 1

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Register Transfer Operations Cont.

Hardware implementation of a controlled transfer: P: R2 ← R1

It is assumed that all transfers occur during a clock edge transition

All microoperations written on a single line are to be executed at the same time

T: R2 ← R1 , R1 ← R2

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t t+1

Clock

Load

Transfer occurs here

Synchronized

with the clock

Block diagram:

Timing diagram

n

Clock

R1

R2Control

CircuitLoadP

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Basic Symbols for Register Transfers

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VHDL Symbols for Register Transfers

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Microoperations

A microoperation is an elementary operation performed on data stored in

registers or in memory.

The microoperations most often encountered in digital systems are of four

types:

1. Transfer microoperations, which transfer binary data from one register

to another.

2. Arithmetic microoperations, which perform arithmetic on data in

registers.

3. Logic microoperations, which perform bit manipulation on data in

registers.

4. Shift microoperations, which shift data in registers.

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Arithmetic Microoperations

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Note

• Multiplication and division are not listed in Table . Multiplication can be representedby the symbol * and division by /.

• These two operations are not included in the basic set of arithmetic microoperationsbecause they are assumed to be implemented by sequences of basic microoperations.

• In contrast, multiplication can be considered as a microoperation if implemented by acombinational circuit.

• In such a case, the result is transferred into a destination register at the clock edge afterall signals have propagated through the entire combinational circuit.

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Arithmetic Microoperations Cont.

There is a direct relationship between the statements written in register transfer notation and the registers and digital functions required for their implementation.

To illustrate, consider the following two statements:

Control variable K1 activates an operation to add or subtract.

If, at the same time, control variable X is equal to 0, then XK1 = 1, and the contents of R2 are added to the contents of Rl.

If X is equal to 1, then XK1 = 1, and the contents of R2 are subtracted from the contents of Rl.

Note that the two control conditions are Boolean functions and reduce to 0 when K1= 0, a condition that inhibits the execution of both operations simultaneously.

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An n-Bit Adder - Subtractor

• An n-bit adder-subtractor receivesits input data from registers R1 andR2.

• The sum or difference is applied tothe inputs of R1.

• The Select input S of the adder-subtractor selects the operation inthe circuit.

• When S = 0, the two inputs areadded, and when S = 1, R2 issubtracted from R1.

• Applying the control variable X tothe S input activates the requiredoperation.

• The output of the adder-subtractoris loaded into R1 on any positiveclock edge at which 𝑿K1 = 1 or XK1

= 1.

• This is simplified to just Ki, since

• Thus, the control variable X selectsthe operation, and the controlvariable K1 loads the result into R1.

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Logic Microoperations

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Logic Microoperations Cont.

Consider

• The + between K1 and K2 is an OR operation between two variables in a control

condition.

• The + between R2 and R3 specifies an add microoperation.

• The OR microoperation is designated by the symbol between registers R5 and R6.

• The logic microoperations can be easily implemented with a group of gates, one for

each bit position.

The NOT of a register of n bits is obtained with n NOT gates in parallel.

The AND microoperation is obtained using a group of n AND gates, each receiving a

pair of corresponding inputs from the two source registers.

The outputs of the AND gates are applied to the corresponding inputs of the destination

register.

The OR and exclusive-OR microoperations require a similar arrangement of gates.

The AND microoperation can be used for clearing one or more bits in a register to 0.

• The Boolean equations X · 0 = 0 and X · 1 = X dictate that, when ANDed with 0, a

binary variable X produces a 0, but when ANDed with 1, the variable remains

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Logic Microoperations Cont.

A given bit or group of bits in a register can be cleared to 0 if ANDed with 0.

Consider the following example:

A given bit or group of bits in a register can be set to 1 if ORed with 1.

Consider the following example:

By XORing a bit or group of bits in register R1 with 1s in selected positions in R2, it ispossible to complement the bits in the selected positions in R1.

Consider the following example:

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Shift Microoperations

Shift microoperations are used for lateral movement of data.

The contents of a source register can be shifted either right or left.

A left shift is toward the most significant bit, and a right shift is toward the least

significant bit. Shift microoperations are used in the serial transfer of data.

They are also used for manipulating the contents of registers in arithmetic, logical,

and control operations.

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Mutliplexer-Based Transfers

There are occasions when a register receives data from two or more different sources atdifferent times.

Consider the following conditional statement having an if-then-else :

The conditional statement may be broken into two parts using the following controlconditions:

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Mutliplexer-Based Transfers Cont.

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Generalization of Multiplexer Selection for n Sources

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Multiplexer and Bus-Based Transfers

A typical digital system has many registers.

Paths must be provided to transfer data from one register to another.

The amount of logic and the number of interconnections may be excessive if each

register has its own dedicated set of multiplexers.

A more efficient scheme for transferring data between registers is a system that uses a

shared transfer path called a bus.

A bus is characterized by a set of common lines, with each line driven by selection logic.

Control signals for the logic select a single source and one or more destinations on any

clock cycle for which a transfer occurs.

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Multiplexer and Bus-Based Transfers Cont.

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Three-State Bus

A bus can be constructed with the three-state buffers instead of multiplexers.

This has the potential for additional reductions in the number of connections.

But why use three-state buffers instead of a multiplexer, particularly for implementing

buses?

The reason is that many three-state buffer outputs can be connected together to form a

bit line of a bus, and this bus is implemented using only one level of logic gates.

On the other hand, in a multiplexer, such a large number of sources means a high fan-

in OR, which requires multiple levels of OR gates, introducing more logic and

increasing delay.

In contrast, three-state buffers provide a practical way to construct fast buses with

many sources, so they are often preferred in such cases.

More important is the fact that signals can travel in two directions on a three-state bus.

Thus, the three-state bus can use the same interconnection to carry signals into and out

of a logic circuit.

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Three-State Bus: Multiplexer vs. Three-State Buses

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Algorithm State Machines (ASM)

The logic design of a digital system can be divided into two distinct parts:

1. Design of the digital circuits that perform the data processing operations.

2. Design of the control circuits that determines the sequence in which the

various actions are performed.

The relationship between two parts is shown as follows:

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Algorithm State Machines (ASM) Cont.

A flowchart is a convenient way to specify the sequence of procedural steps and

decision paths for an algorithm.

A special flowchart called an algorithmic state machine (ASM) chart describes

the sequence of events as well as the timing relationship between the states of a

sequential controller and the events that occur while going from one state to the

next.

ASM contains three basic elements: State box, Decision box, and Condition box.

State box indicates as FSM state; box also indicates operation to be performed.

Binary code and state name also included.

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Algorithm State Machines (ASM) Cont.

Decision Box:

Describes the impact of input on control system

Contains two exit paths which indicate result of

condition

More complicated conditions possible

Implemented in hardware with a magnitude

comparator

Conditional Box

Indicates assignments following a decision box

Generally indicates data transfer

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Algorithm State Machines (ASM) Cont.

ASM Block:

The ASM block is a structure consisting of one state box and all the decision and

conditional boxes connected to its exit path.

The ASM chart is very similar to a state diagram. It is convenient to convert the

chart into a state diagram and use sequential circuit procedures to design the control

logic.

ASM Block State Diagram

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Algorithm State Machines: Timing Consideration

The major difference between a conventional flow chart and an ASM chart is in

interpreting the time relationship among the various operations.

An ASM chart considers the entire block as one unit. All the operations that are

specified within the block must occur in synchronism during the edge transition of

the same clock pulse.

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Algorithm State Machines: Example – Odd Parity Checker

Assert output whenever input bit stream has odd # of 1's

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Algorithm State Machines: Example – Odd Parity Checker Cont.

Assert output whenever input bit stream has odd # of 1's

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Algorithm State Machines: Example – ASM Equivalent to Mealy Machine

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Algorithm State Machines: Example – ASM Equivalent to Moore Machine

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End of Lecture 8!

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