Power-aware design method for class A switched-current wave filters

Power-aware design method for class A switched-current wave filters

R. Wilcock and B.M. Al-Hashimi

Abstract: Power consumption is addressed in switched-current filters, designed using the wave filtertechnique and class A memory cells. It has been demonstrated that power consumption can bereduced through the proposed two-stage bias and signal current scaling method, whilst ensuring nodegradation in filter total harmonic distortion. Two full transistor-level filter case studies using0.6mm 3.3V BSim3v3 CMOS foundry models are given to demonstrate the method, withadditional simulation results for filters of different types and orders showing power savings as highas 16.6%. One case study has been fabricated, with measured silicon results confirming powersavings using the proposed method.

1 Introduction

In the last decade, considerable interest has been shown inthe switched-current (SI) approach, a current-modesampled analogue data technique requiring only transistors.Compatible with mainstream low-voltage digital processes,switched-current circuits are indicated to surpass theperformance of switched-capacitor equivalents in the nextfive years [1]. Low power consumption plays a key role inmodern consumer electronics, and this paper investigatespower consumption in SI filters, designed using the wavefilter technique and class A memory cells. Class A circuitsrely on a bias current to prevent devices leaving saturationduring negative signal swings and the power dissipated in adesign is therefore proportional to the sum of every branchcurrent in a design. We present a two-stage bias and signalscaling method which appropriately assigns bias currentsand signal levels to ensure that power is kept at a minimumwithout increasing the filter’s total harmonic distortion(THD). This is in contrast to previous methods whichassume a uniform bias current [2, 3].

2 Wave filter design

In this Section we provide a review of wave filter design toan extent required by later Sections. The reader is referredto [2–4] for more details. The wave filter approach is analternative to integrator filter design and has been foundparticularly suitable for SI implementations, offering regularlayouts and simple design procedures [2, 5]. Wave filtersemulate the behaviour of passive lossless filters bytransforming inductors and capacitors into one-portelements defined by an incident signal, a reflected signaland a port resistance [4]. Parallel and series adaptors are

used to connect these one-port elements. Figure 1 shows anexample of a third-order LC ladder prototype with the waveequivalent.

Adaptors are defined by port resistances and coefficients,with these relating to the sample period and normalisedvalues used in the passive reference filter. Equations (1), (2)and (3) can be used to derive the port coefficients gj in eachadaptor, where Rj and Gj are the port resistances andconductances, respectively. Note that the coefficients mustsum to two in any single adaptor.

Series adaptor:

gj ¼2Rj

R0 þ R1 þ R2ð1Þ

Parallel adaptor:

gj ¼2Gj

G0 þ G1 þ G2ð2Þ

All adaptors:

X2j¼0

gij ¼ 2 ð3Þ

In order to investigate the power consumed in the designedfilter, we now consider transistor-level implementations ofthe wave blocks. Figure 2 shows the circuit level structuresused to implement series and parallel adaptors [6] andpositive and negative delay cells, the latter consisting of thehigh accuracy S2I memory cell [7]. The delay cell design is ofgreatest importance in the wave filter design flow and it isat this step that the delay cell bias current J is chosen soas to support a given sample frequency SNR andmaximum input signal imax [8]. The total quiescent powerconsumption of a wave filter is shown in (4) as theproduct of the supply voltage and the bias currentcontributions from the four wave blocks shown in Fig. 2.Note that the three branches implementing adaptorcoefficients only consume 2JVdd due to (3). It should benoted that although we recognise that the relatively newclass AB technique [9] offers low power at the memory celllevel, the motivation of this paper is to decrease power

The authors are with the Electronic Systems Design Group, School ofElectronics and Computer Science, University of Southampton, Highfield,Southampton SO17 1BJ, UK

r IEE, 2004

IEE Proceedings online no. 20040254

doi:10.1049/ip-cds:20040254

Paper first received 17th July and in revised form 20th October 2003

IEE Proc.-Circuits Devices Syst., Vol. 151, No. 1, February 2004 1

consumption in filters designed with class A memorycells.

power ¼ JVddð18S þ 12P þ 2Dp þ 4DnÞ ð4Þ

where S and P are the total number of series and paralleladaptors, Dp and Dn are the total number of positive andnegative delay cells used, J is the bias current and Vdd is thesupply voltage.

3 Proposed power-aware design method

Section 3.1 investigates the spread of signal levels in wavefilters and how this is addressed with existing techniques.Section 3.2 then details the proposed power-aware two-stage bias and signal scaling method. Section 3.3 considersnoise in the context of the proposed approach. Finally,Section 3.4 considers how to integrate the proposed methodinto the design flow for wave filters.

Iin

−Z−1

Z−1 Z−1

0

Iout

γ00

γ01

γ02 γ00

γ01

γ12γ30

γ31

γ32

Z−1

γ 20

γ 21

γ 22

Ri

L1C

1 C3

Ro

C2

Vout

Vin

a b

parallel parallel

para

llel

series

negativedelay cell

positivedelay cells

positivedelay cell

Fig. 1 Third-order passive prototype and wave equivalent structure

wave structure transistor structure power

R0

R1

R2γ0

γ1

γ2

A0

B0

A1B1

A2

B2

parallel adaptor

1 1 γ0: : 1 1 γ1: : 1 1 γ2: : 1 1: : 1 1:

A0 A1 A2

B2B1B0

R0

R1

R2γ0

γ1γ2

A0

B0

A1B1

A2

B2

γ0

γ1

γ2

series adaptor

1 1 1: : 1 1 1: : 1 1 1: : 1 γ0: : γ1 γ2:

A0 A1 A2

B0 B1 B2

1 1: 1 1: 1 1:

18JVdd

2JVdd

4JVdd

Z−1A B

positive delay cell

φ1a

φ1bφ1 φ2 φ1

φ2a

A B

Vb

−Z−1A B

negative delay cell

φ1a

φ1a

φ1bφ1

φ2a

φ2a

φ2b

φ2b

φ2 φ1

φ2aφ1a

VbVb

A B

1 1:

12JVdd J = bias

Vdd = supply

Fig. 2 Transistor-level structures and power consumptions of the wave building blocks

2 IEE Proc.-Circuits Devices Syst., Vol. 151, No. 1, February 2004

3.1 Signal levels in wave filtersWhere internal signal levels within a large design varysignificantly, these are referred to as nonhomogeneous [2].Unfortunately, nonhomogeneous signal levels within wavefilters can lead to the dynamic range of some blocks beingexceeded. In order to maintain the designed performance, itis essential to investigate such possible sources of distortion.The nature of wave designs makes it difficult to derivemathematical relationships between the input signal and anarbitrary internal node, and consequently we believe it is farmore practical to model the circuit either behaviourally orwith ideal components and then use a suitable switchedsimulator to derive the frequency response. Extensivelibraries of behavioural and ideal models have beendeveloped for this purpose [10].

To illustrate block level distortion, a fifth-order Cheby-shev SI wave filter was designed and is shown in Fig. 3, withtwo internal node responses. It is clear from these responsesthat some nodes exhibit a substantial amount of gain fromthe input, often in the form of a peak at the band edgefrequency. Using a uniform bias current of J, and with imax

as the input signal, any gain to an internal node will result inthe signal at that point exceeding imax and thus alsoexceeding the dynamic range of that current mirror.Without addressing these issues the performance of thefilter would be unlikely to meet its expected values. In aclass A design there are two ways to deal with this problem,either increase the bias current for the current mirrors wherethe signal peaks are large, or decrease the signal values.Previous wave filter publications appear to have simply

identified those blocks whose dynamic range are beingexceeded and introduced circuitry and scaling to preventdistortion at these points only [2, 3].

3.2 Two-stage scaling methodThe proposed power-aware scaling method consists of twostages. Stage one involves scaling current mirror bias levels,and stage two involves scaling delay cell signal levels. Bothof these changes can be made independently of one anotherand without affecting the rest of the filter. The procedurestarts after the wave filter coefficients have been calculatedand the first task is to determine the peak input signal levelipeak to all delay cells and adaptor current mirrors. Tofacilitate this, a periodic AC analysis of the circuit is runusing the Affirmat switched simulator, SpectreRF, inCadence Design Framework II and behavioural or idealmodels. If a unity input is chosen for this simulation thenthe peak magnitudes on the frequency response are in factthe peak input signal levels ipeak. We now discuss the twostages in detail.Stage 1: Current mirror bias scaling: As shown in Fig. 4,every current mirror block in the adaptors has its biascurrent J scaled to a new value J0, which just supports thepeak input signal value ipeak found from the frequencyresponse for that block. Not only does this preventdistortion in this block, but it also lowers power consump-tion by scaling down bias levels where the signals theysupport are small. The transistor-level current mirrorarchitecture is the popular high compliance cascodestructure, and as an example the first current mirror from

mag

f

J

response of inputnode of one of thecurrent mirrors in

the second adaptor

mag

f

J

Iin

γ00

γ01

γ02

Z−1

γ10

γ11

γ12

−Z−1

γ20

γ21

γ22

Z−1

γ30

γ31

γ32

−Z−1

γ40

γ41

γ42

Z−1

0

Iout

response of inputnode of one of thecurrent mirrors inthe last adaptor

Fig. 3 Example fifth-order Chebyshev filter which would suffer from block level distortion

i in r

esp

on

se

f

J

Ipeak

ipeak smaller thannominal bias J :power wasted

bias scaled so J ′just supports ipeak

i in r

esp

on

se

f

J

J ′

before after

J ′ iout1iout2i in

J ′ J ′J iout1iout2

J J

iin

Fig. 4 Bias scaling in stage 1, before and after proposed method


the parallel adaptor of Fig. 2 is shown to transistor levelin Fig. 5. The bias currents in all current mirrors canbe altered easily by scaling all the transistor widths. Notethat the branch ratios are not changed in stage 1, justthe bias current and hence the maximum supported signalcurrent. A scaling factor S is calculated using (5),then transistor widths in the current mirror are scaledaccording to (6).

S ¼ ipeakifilter

ð5Þ

Wnew ¼ S:Wold ð6Þwhere ipeak is the peak input signal value to the currentmirror, ifilter is the AC input current to the entire filter andWold and Wnew are the old and new width dimensions forthe current mirror being scaled.Stage 2: Delay cell signal scaling: Unlike the current mirrorbias scaling in stage 1, the delay cell bias current cannot bechanged without significantly affecting the performance ofthe cell, so a different approach is taken in stage 2. Instead,as shown in Fig. 6, the signal values in the delay cells arescaled such that the peak input signal ipeak through these

will always be the designed maximum value, and hence justsupported by the nominal bias current J. No extra scalingblocks are required to achieve this and instead the newdimensions are implemented in any output branches ofcurrent mirrors connected to the input of the delay cell andany input branches of current mirrors connected to theoutput of the delay cell. The scaling factor S is againcalculated using (5) and the necessary branches then havetheir transistor widths altered as follows:

Wnew ¼ Wold

Sð7Þ

These changes must not affect the rest of the filter and assuch the signal levels everywhere other than the delay celland adjoining current mirror branches should remain thesame. An example situation is shown in Fig. 7 and (8)–(10)show the current mirror and delay cell ratios an and aD,respectively. It is clear from (11) that if we multiply thesefrom the first altered mirror to the last then the result isunity, and as such the scaling in stage 2 does not affect therest of the filter.

a1 ¼ a2 ¼1=S1

¼ 1

Sð8Þ

aD ¼ 1 ð9Þ

a3 ¼1

1=S¼ S ð10Þ

atot ¼ a1 � aD � a3 ¼1

S:1:S ¼ 1 ð11Þ

By appropriately assigning bias currents and signal levels,stages 1 and 2 ensure that signal levels never exceed theirbiasing. Furthermore, unlike methods where a uniform biascurrent is assumed, the power consumption of the filter isreduced by lowering bias currents where possible. Note thatit is only the current mirror branches in the adaptors whichare scaled at all. The delay cells are left as they are, thusensuring correct memory cell operation.

1 1 γ0: :

Iout1IinIout2

Pbias

PCbias

NCbias

Fig. 5 Example full transistor-level current mirror used in theadaptor blocks

before after

i in r

esp

on

se

f

J

Ipeak

ipeak greater than

nominal bias J :

signal distorts

signal scaled so

ipeak is just below J

i in′ r

esp

on

se

f

J

iout

Vb Vb

iin

iout

Vb Vb

iin′

Fig. 6 Signal scaling in stage 2, before and after proposed method

Vb Vb

currentmirror 1

currentmirror 2

delaycell

currentmirror 3

1 : 1/S 1 : 1/S 1 : 1 1/S : 1

scale any currentmirror branch

connected to adelay cell to 1/S

Iin2Iin1 Iout

�1 �2 �D �3

Fig. 7 Current mirrors either side of delay cells are scaled to prevent distortion


3.3 Noise considerationsIn the context of class A SI wave filters, the two mainsources of noise are thermal and 1/f, which are the first andsecond terms in (12), respectively [11].

i2d ¼ 4kT2

3gm

� �Df þ K

IDfDf ð12Þ

Where i2d is the small signal noise, k is Boltzmann’sconstant, T is temperature, Df is bandwidth, K is a constantfor a given device and f is the frequency. The thermal noiseterm includes transconductance gm as a factor, which isproportional to the device drain current ID. The secondterm includes ID explicitly, and as such the total small signalnoise is proportional to the quiescent bias level of thetransistor. Therefore, at the block level, if we increasebias currents, large signals will be less distorted but noisewill increase, leading to a trade-off between large-signallinearity and small-signal noise. However, the proposedmethodology only increases bias currents where absolutelynecessary, and in fact the power savings achieved imply thatthe filter’s average bias current is reduced, and hencethe noise should also be lower. In terms of the entire filter,the proposed method therefore improves large-signallinearity by scaling signals and bias currents wherenecessary, but due to the general reduction in power, andhence average bias current, the small-signal noise should bereduced.

3.4 Power-aware design flowWe now consider how to incorporate the proposed methodinto a power-aware design flow for switched-current wavefilters. Once the basic wave structure has been designed [3],scaling factors have to be calculated for every branch ofevery current mirror in each adaptor block. There are threecomponents to the final scaling factor. The first representsthe alterations made during stage 1, the second imple-ments the changes made during stage 2 and the lastimplements the calculated adaptor coefficients gij. Thesethree components are represented with multidimensionalarrays, and the index of the array elements uniquelyidentifies every current mirror branch; i is the adaptornumber, j the current mirror number in the adaptor and kthe branch in that current mirror. These scaling componentsare now discussed in detail:Aijk – Peak signal values are read from the magnituderesponse of the input of all the current mirrors as describedin stage 1 of Section 3.2. These values are practicallyobtained by connecting an AC source of value unity to theinput of the wave filter and using a switched simulator toplot the response of the current mirror inputs. This arrayAijk is then filled with the resulting scaling factors as foundfrom (5).Dijk – Peak signal values for the delay cells are obtainedin exactly the same manner as for the current mirrors.The structure of the filter is then considered and allcurrent mirror branches, be they outputs or inputs,which are connected to the input or output of a delaycell, are identified. These positions in Dijk are then filledwith the inverse of the delay cell scale value as describedin stage 2 of Section 3.2. The rest of the array isunity-filled.Yijk – The adaptor coefficient values gij are implemented inthe correct positions of this array Yijk, reflecting the relevantbranches of the current mirrors in the adaptor blocks ofFig. 2. The rest of the array is unity-filled.

The entire set of scaling factors Sijk encompassing biasand signal scaling and wave coefficients are then given by

(13) as the product of the contributions from the abovearrays. Given a set of nominal current mirror dimensions,the new widths for all the branches in the entire wave filtercan be calculated from (14).

Sijk ¼ AijkDijkYijk ð13Þ

Wnew;ijk ¼ SijkWold;ijk ð14Þ

The resulting power-aware switched-current wave filterdesign flow is shown in Fig. 8. Our own in-house tool,AutoSIF [10, 12], created to enable rapid development of SIfilter and other popular IP cores, has recently had itsfunctionality extended to incorporate the power-awaresteps. The tool is written in SKILLs and is integrated intoCadence Design Framework II.

4 Results

In order to validate the proposed method, numerousexample filters have been designed and the method appliedto ascertain the resulting improvements in performance andpower. Our in-house tool, AutoSIF [10, 12], was employedextensively for the design of these example filters. Two casestudies were taken to real transistor level, using 0.6mm 3.3VBSim3v3 CMOS foundry models. The filters chosen were athird-order elliptic and fifth-order Chebyshev lowpass filterof specifications given in Table 1 and wave structures givenin Figs. 9a and 9b, respectively. The transistor-levelstructure for the elliptic filter case study is shown inFig. 10. Note that all current mirrors are actually of thehigh compliance cascode type, as shown in Fig. 5. Adaptorcoefficients and nominal transistor dimensions for thecurrent mirrors and S2I memory cell are shown in Table 2for the elliptic case study. Transistor-level current mirrorand delay cell structures are shown in Fig. 11.

In order to quantify the extent to which internal blocksare distorting, a spectrum of the filter output signal to agiven input signal can be used to calculate a THD figure.Clearly, distortion increases as signal levels increase andtransistors begin to leave the saturation region. In ourfilters, the worst case normal working distortion wouldtherefore arise when the input signal is at its maximumvalue imax. Therefore, calculating the THD with themaximum input signal of imax gives us a good metric to

design reference filter

switched AC simulations usingbehavioural/ideal models

derive wave structure and calculateadaptor coeffcients

Yijk Aijk Dijk

scale nominal current mirror dimensions by Sijkto define full transistor level filter

Fig. 8 Power-aware switched-current wave filter design flow


compare the extent to which internal blocks are exceedingtheir dynamic range.

The wave filter structures were derived from their passivereference prototypes and adaptor coefficients calculated [3].Initial simulations were run, having not scaled any parts ofthe filter and with a signal input equal to imax, so as todemonstrate the resulting worst case distortion. Table 3shows the first five harmonic levels for the two filters andthe total harmonic distortion calculated from the first seven(harmonics higher than this are insignificant). Despite thisbeing a worst case measurement, the high THD levels of

around 6% clearly indicate that without any scaling someof the internal nodes are exceeding their dynamic range withthe maximum designed input imax. To illustrate thenonhomogeneous signal levels in the filters, internal noderesponses at points X, Y and Z of the transistor-level ellipticfilter of Fig. 10 are shown in Fig. 12. The response at pointsX and Y show that the bias value is being exceeded at somefrequencies, and response Y in particular demonstrates thatsome current mirrors would be running at very distortedlevels for the entirety of the passband. The response at pointZ demonstrates how some bias values exceed the signalvalues they support, as is discussed in Section 3.2.

All internal signal levels for the filters were thendetermined as described in Section 3.2 and the signal andbias levels in the filter scaled only where distortion occurs, asin [2]. A quiescent power reading was taken and then thefull proposed method was used, which should not onlyprevent block level distortion but also save power byreducing bias currents where the signals they support aresmall. A second quiescent power reading was then takenand the saving in power calculated. Results shown inTable 4 are from these simulations. It is clear that usingscaling has greatly reduced the distortion in both cases,

Table 1: Specifications for the case study filters

Elliptic Chebyshev

Filter order Third Filter order Fifth

Stopband attenuation 430dB Attenuation at 3fc 460dB

Passband ripple 0.177dB Ripple 0.5dB

fc to fs ratio 1:10 fc to fs ratio 1:10

Maximum input imax 75mA Maximum input imax 75mA

Iin

−Z−1

Z−1 Z−1

0

Iout

γ00

γ01

γ02 γ00

γ11

γ12γ30

γ31

γ32

Z−1

γ 20

γ 21

γ 22

Iin

γ00

γ01

γ02

Z−1

γ10

γ11

γ12

−Z−1

γ20

γ21

γ22

Z−1

γ30

γ31

γ32

−Z−1

γ40

γ41

γ42

Z−1

0

Iout

D0

D1

D3

D2

A0 A1 A3

A2

b

a

Fig. 9 Structures of the elliptic (a) and Chebyshev (b) case studies

node X node Z

nodeY

Iin Iout

0

Fig. 10 Transistor-level circuit for the third-order elliptic filter


showing that this is therefore an essential part of the wavefilter design process. However, the results also clearly showthat by using the proposed method it is possible to not onlyprevent block level distortion, to at least the same extent assimple scaling, but also to save power as part of this process.For the two case studies, the power savings are 16.6%for the Third-order elliptic filter and 6.1% for the fifth-order Chebyshev filter. In order to validate the noise

considerations of Section 3.3 a periodic noise analysis, usingSpectreRF, was run for both case studies and the integralnoise spectrums plotted. As can be seen in Fig. 13, noise isreduced in line with the general reduction in power, with thetotal reductions in RMS noise being 14.7% and 9.7% forthe elliptic and Chebyshev case study, respectively.

The elliptic case study has been taken to layout and wasrecently fabricated. Detailed measured results and char-acterisation is the subject of a further publication. However,initial results show the measured power for the filter coreplus structures for test purposes is 22.2mW. The extrastructures consume a total of 1.9mW (found throughsimulation), and hence the measured consumption of thefilter alone is 20.3mW, which compares well with thesimulated results of Table 4. A die photograph is shown inFig. 14.

To investigate the potential benefits of the methodfurther, a larger range of filter orders were designed and thepower savings determined. The filters were first scaled onlyto prevent distortion, and then scaled using the proposedtwo-stage method, including reducing bias currents wherethe signal levels are small. Table 5 shows the power savingsfor different filter types and orders when compared to usingbasic scaling and uniform bias currents as in [2, 3]. Thesesavings can be as much as 16.6%, as verified through theelliptic filter case study. The figures show that power savingsincrease as the filter order decreases. Through extensive

Table 2: Transistor dimensions and coefficient values for the elliptic case study

Adaptor coefficients Current mirror (mm) S2I memory cell (mm)

g01, g02, g03 0.275, 1.225, 0.500 PMOS 120/5 M1 130/24

g11, g12, g13 0.527, 0.973, 0.500 PCAS 120/1.5 M2 220/14

g21, g22, g23 1.000, 0.648, 0.352 NCAS 40/1.5 M3, M5, M7 9/0.6

g31, g32, g33 0.520, 1.208, 0.272 NMOS 40/5 M4, M6 1.6/0.6

M1

M2

M3

M4

M5

M6

Vb

M7φ 1a

φ1b

φ1a

φ 1 φ2

a

b

Iin

Pbias

PCbias

NCbias

PMOS

PCAS

NCAS

NMOS

Iout1

Fig. 11 S2I memory cell and nominal current mirror structurea S2I memory cellb Nominal current mirror structure

Table 3: Harmonic levels and worst case THD with noscaling and maximum input signal

Elliptic Chebyshev

Second harmonic �50.8dB Second harmonic �27.4dB

Third harmonic �24.3dB Third harmonic �27.1dB

Fourth harmonic �55.4dB Fourth harmonic �40.1dB

Fifth harmonic �43.9dB Fifth harmonic �51.4dB

THD 6.13% THD 6.21%

3.0

2.0

1.0

0.00.0 15K 30K

mag

nitu

de

3.0

2.0

1.0

0.0

mag

nitu

de

bias level

bias level

: reponse at node 'X'

: reponse at node 'Y'

frequency, Hz

0.0 15K 30K

frequency, Hz

3.0

2.0

1.0

0.0

mag

nitu

de bias level

: reponse at node 'Z'

0.0 15K 30K

frequency, Hz

Fig. 12 Internal responses of typical nodes X, Y and Z of theelliptic filter


simulations it was observed that the greatest power savingsoccurred at the beginning and end of the wave filterstructure, mostly in the first and last adaptor. As filter orderincreases, the filter structure naturally becomes larger and sothese savings become smaller relative to the overall filterpower consumption. In any case as was shown in Section4.1, the savings are in addition to the usual goal ofpreventing distortion.

5 Conclusions

In this paper we have addressed power consumption in SIfilters, designed using the wave filter approach and class Amemory cells. A two-stage bias and signal scaling methodhas been proposed which not only resolves block leveldistortion issues, thus improving filter THD but, unlike [2],addresses power consumption as part of this process. Thispower-aware method achieves power savings by taking intoaccount maximum signal levels when assigning biascurrents. It has been demonstrated that the proposedmethod achieves its goal of reduced power consumption byas much as 16.6%, with these savings validated throughsimulation and, in particular, two case studies using 0.6mm3.3V BSim3v3 CMOS foundry models. Silicon resultsfurther support these findings. We believe that the proposedmethod is a very useful contribution to the area of class Aswitched-current design where power consumption is anissue.

6 Acknowledgments

The authors would like to thank EPSRC for partiallysponsoring this work, under grant number GR/N31900.

7 References

1 Hughes, J.B., Worapishet, A., and Toumazou, C.: ‘Switched-capacitors versus switched-currents: a theoretical comparison’.Proc. IEEE Int. Symp. on Circuits and systems, 2000, Vol. II,pp. 409–412

2 Yufera, A., Rueda, A., and Huertas, J.L.: ‘Programmable switchedcurrent wave analog filters’, IEEE J. Solid-State Circuits, 1994, 29,pp. 927–935

3 Jonsson, B., and Eriksson, S.: ‘A low voltage wave SI filterimplementation using improved delay elements’. Proc. IEEE Int.Symp. on Circuits and systems, 1994, Vol. 5, pp. 305–308

4 Fettweis, A.: ‘Wave digital filters: theory and practice’, Proc. IEEE,1986, 74, pp. 270–327

5 Lancaster, J.D., Al-Hashimi, B.M., andMoniri, M.: ‘Efficient SI waveelliptic filters based on direct and inverse Bruton transformations’,IEE Proc., Circuits Devices Syst., 1999, 146, pp. 235–241

6 Jonsson, B., and Eriksson, S.: ‘Current-mode N-port adaptors forwave SI filters’, Electron. Lett., 1993, 29, pp. 925–926

Table 4: Savings in power are found in both case studies with no loss in performance

Elliptic Chebyshev

Method Basic scaling [2] Proposed method Basic scaling [2] Proposed method

THD 2.5% 1.6% 1.38% 1.32%

Power 24.5mW 20.4mW 48.8mW 45.8mW

Power saving 16.6% 6.1%

b

a

√�N

PS

D, A

0.0

10n

20n

30n

√�N

PS

D, A

21.3 nA23.6 nA

13.9 nA16.3 nA

basic scaling

basic scaling

proposed method

proposed method

frequency, Hz30K15K0.0

frequency, Hz30K15K0.0

0.0

5.0n

10n

15n

20n

Fig. 13 Noise characteristics of the elliptic (a) and Chebyshev (b)case studies

Fig. 14 Photo of fabricated elliptic filter, employing proposedpower-aware scaling method

Table 5: Power savings for a number of example filters

Filter type Filter Order Power saving (%)

Chebyshev 3 14.3

Chebyshev 5 6.1

Chebyshev 7 3.9

Chebyshev 9 2.6

Elliptic 3 16.6

Elliptic 5 7.8

Elliptic 7 4.8

Elliptic 9 2.4


7 Hughes, J.B., and Moulding, K.W.: ‘S2I: A two-step approach toswitched currents’, Proc. IEEE Int. Symp. on Circuits and systems,1993, pp. 1235–1238

8 Hughes, J.B.: ‘Top-down design of a switched-current video filter’,IEE Proc., Circuits Devices Syst., 2000, 147, pp. 73–81

9 Battersby, N.C., and Toumazou, C.: ‘Class AB switched-currentmemory for analogue sampled data systems’, Electron. Lett., 1991, 27,pp. 873–875

10 Wilcock, R., and Al-Hashimi, B.M.: ‘A CAD methodology forswitched current analog IP cores’. Proc. IEEE Conf. on Emergingtechnologies and factory automation, 2003, Vol. 1. pp. 434–437

11 Gray, P., Hurst, P., Lewis, S., and Meyer, R.: ‘Analysis and design ofanalog integrated circuits’ (John Wiley & Sons Inc., 2001)

12 Wilcock, R., Al-Hashimi, B.M.: ‘AutoSIF, a CAD tool forswitched-current IP cores’. http://www.ecs.soton.ac.uk/Brw01r/pages/research.php


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Power-aware design method for class A switched-current wave filters